diff --git a/.gitmodules b/.gitmodules index 1587bd6c..a8a1fb84 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,6 @@ [submodule "mavis"] path = mavis - url = https://github.com/sparcians/mavis.git + url = git@github.com:sparcians/mavis [submodule "stf_lib"] path = stf_lib url = https://github.com/sparcians/stf_lib.git diff --git a/CMakeLists.txt b/CMakeLists.txt index 381d3552..b106725b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -35,6 +35,7 @@ include_directories(${SPARTA_INCLUDE_DIRS}) # Set up STF library set (STF_LIB_BASE ${PROJECT_SOURCE_DIR}/stf_lib) set (DISABLE_STF_DOXYGEN ON) +set (DISABLE_STF_TESTS ON) if (CMAKE_BUILD_TYPE MATCHES "^[Rr]elease") set (FULL_LTO true) diff --git a/arches/big_core.yaml b/arches/big_core.yaml index 13713658..37566b97 100644 --- a/arches/big_core.yaml +++ b/arches/big_core.yaml @@ -11,6 +11,7 @@ top.cpu.core0: rename.params.num_to_rename: 8 rename.params.num_integer_renames: 64 rename.params.num_float_renames: 64 + rename.params.num_vector_renames: 64 dispatch.params.num_to_dispatch: 8 rob.params.num_to_retire: 8 dcache.params: @@ -32,7 +33,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], # exe6 ["float", "f2i"], # exe7 ["br"], # exe8 - ["br"] # exe9 + ["br"], # exe9 + ["vint", "vset", "vdiv", "vmul"] ] # this is used to set how many units per queue # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive @@ -47,25 +49,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], # iq1 -> exe2, exe3 ["4", "5"], # iq2 -> exe4, exe5 ["6", "7"], # iq3 -> exe6, exe7 - ["8", "9"] # iq4 -> exe8, exe9 + ["8", "9"], # iq4 -> exe8, exe9 + ["10"] # iq5 -> exe10 ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/arches/isa_json/gen_uarch_rv64v_json.py b/arches/isa_json/gen_uarch_rv64v_json.py new file mode 100755 index 00000000..e6ef18a6 --- /dev/null +++ b/arches/isa_json/gen_uarch_rv64v_json.py @@ -0,0 +1,222 @@ +#!/usr/bin/env python + +import os +import json + +MAVIS = os.environ.get('MAVIS', "../../mavis/") +JSON = os.environ.get('JSON', "olympia_uarch_rv64v.json") + +SUPPORTED_INSTS = { +# Vector Config Setting Instructions + "vsetvli" : {"pipe" : "vset", "latency" : 1}, + "vsetvl" : {"pipe" : "vset", "latency" : 1}, + "vsetivli" : {"pipe" : "vset", "latency" : 1}, + +# TODO: Vector Loads and Stores: Vector Unit-Stride Instructions +# TODO: Vector Loads and Stores: Vector Strided Instructions +# TODO: Vector Loads and Stores: Vector Indexed Instructions +# TODO: Vector Loads and Stores: Unit-stride Fault-Only-First Loads +# TODO: Vector Loads and Stores: Vector Load/Store Segment Instructions +# TODO: Vector Loads and Stores: Vector Load/Store Whole Register Instructions + +# Vector Integer Arithmetic Instructions: Vector Single-Width Integer Add and Subtract + "vadd.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vadd.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vadd.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsub.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsub.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vrsub.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vrsub.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Widening Integer Add/Subtract + "vwaddu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwaddu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsubu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsubu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwadd.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwadd.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsub.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsub.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwaddu.wv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwaddu.wx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsubu.wv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsubu.wx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwadd.wv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwadd.wx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsub.wv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsub.wx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + +# TODO: Vector Integer Arithmetic Instructions: Vector Integer Extension +# TODO: Vector Integer Arithmetic Instructions: Vector Integer Add-with-Carry/Subtract-with-Borrow Instructions +# Vector Integer Arithmetic Instructions: Vector Bitwise Logical Instructions + "vand.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vand.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vand.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vor.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vor.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vor.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vxor.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vxor.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vxor.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# TODO: Vector Integer Arithmetic Instructions: Vector Single-Width Shift Instructions +# TODO: Vector Integer Arithmetic Instructions: Vector Narrowing Integer Right Shift Instructions +# Vector Integer Arithmetic Instructions: Vector Integer Compare Instructions + "vmseq.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmseq.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmseq.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsne.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsne.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsne.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsltu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsltu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmslt.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmslt.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsleu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsleu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsleu.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsle.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsle.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsle.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsgtu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsgtu.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsgt.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsgt.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Integer Min/Max Instructions + "vminu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vminu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmin.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmin.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmaxu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmaxu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmax.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmax.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Single-Width Integer Multiply Instructions + "vmul.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmul.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulhu.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulhu.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulh.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulh.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulhsu.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulhsu.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + +# Vector Integer Arithmetic Instructions: Vector Integer Divide Instructions + "vdiv.vv" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vdiv.vx" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vdivu.vv" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vdivu.vx" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vremu.vv" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vremu.vx" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vrem.vv" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vrem.vx" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + +# Vector Integer Arithmetic Instructions: Vector Widening Integer Multiply Instructions + "vwmul.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + "vwmul.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + "vwmulu.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + "vwmulu.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + "vwmulsu.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + "vwmulsu.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + +# TODO: Vector Integer Arithmetic Instructions: Vector Single-Width Integer Multiply-Add Instructions +# TODO: Vector Integer Arithmetic Instructions: Vector Widening Integer Multiply-Add Instructions +# TODO: Vector Integer Arithmetic Instructions: Vector Integer Merge Instructions +# TODO: Vector Integer Arithmetic Instructions: Vector Integer Move Instructions +# TODO: Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Saturating Add and Subtract +# TODO: Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Averaging Add and Subtract +# Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Fractional Multiply with Rounding and Saturation + "vsmul.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vsmul.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + +# TODO: Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Scaling Shift Instructions +# TODO: Vector Fixed-Point Arithmetic Instructions: Vector Narrowing Fixed-Point Clip Instructions +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Exception Flags +# TODO: Vector Floating-Point Instructions: Vector Single-Width Floating-Point Add/Subtract Instructions +# TODO: Vector Floating-Point Instructions: Vector Widening Floating-Point Add/Subtract Instructions +# TODO: Vector Floating-Point Instructions: Vector Single-Width Floating-Point Multiply/Divide Instructions +# TODO: Vector Floating-Point Instructions: Vector Widening Floating-Point Multiply +# TODO: Vector Floating-Point Instructions: Vector Single-Width Floating-Point Fused Multiply-Add Instructions +# TODO: Vector Floating-Point Instructions: Vector Widening Floating-Point Fused Multiply-Add Instructions +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Square-Root Instruction +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Reciprocal Square-Root Estimate Instruction +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Reciprocal Estimate Instruction +# TODO: Vector Floating-Point Instructions: Vector Floating-Point MIN/MAX Instructions +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Sign-Injection Instructions +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Compare Instructions +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Classify Instruction +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Merge Instruction +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Move Instruction +# TODO: Vector Floating-Point Instructions: Single-Width Floating-Point/Integer Type-Convert Instructions +# TODO: Vector Floating-Point Instructions: Widening Floating-Point/Integer Type-Convert Instructions +# TODO: Vector Floating-Point Instructions: Narrowing Floating-Point/Integer Type-Convert Instructions +# TODO: Vector Reduction Operations: Vector Single-Width Integer Reduction Instructions +# TODO: Vector Reduction Operations: Vector Widening Integer Reduction Instructions +# TODO: Vector Reduction Operations: Vector Single-Width Floating-Point Reduction Instructions +# TODO: Vector Reduction Operations: Vector Widening Floating-Point Reduction Instructions +# Vector Mask Instructions: Vector Mask-Register Logical Instructions + "vmandn.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmand.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmor.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmxor.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmorn.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmnand.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmnor.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmxnor.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + +# TODO: Vector Mask Instructions: Vector count population in mask vcpop.m +# TODO: Vector Mask Instructions: vfirst nd-rst-set mask bit +# TODO: Vector Mask Instructions: vmsbf.m set-before-rst mask bit +# TODO: Vector Mask Instructions: vmsif.m set-including-rst mask bit +# TODO: Vector Mask Instructions: vmsof.m set-only-rst mask bit +# TODO: Vector Mask Instructions: Vector Iota Instruction +# TODO: Vector Mask Instructions: Vector Element Index Instruction +# TODO: Vector Permutation Instructions: Integer Scalar Move Instructions +# TODO: Vector Permutation Instructions: Floating-Point Scalar Move Instructions +# TODO: Vector Permutation Instructions: Vector Slide Instructions +# TODO: Vector Permutation Instructions: Vector Register Gather Instructions +# TODO: Vector Permutation Instructions: Vector Compress Instruction +# TODO: Vector Permutation Instructions: Whole Vector Register Move +} + +# Get a list of all vector insts from Mavis +mavis_rv64v_json = [] +with open(MAVIS+"json/isa_rv64v.json", "r") as f: + mavis_rv64v_json.extend(json.load(f)) +with open(MAVIS+"json/isa_rv64vf.json", "r") as f: + mavis_rv64v_json.extend(json.load(f)) + +# Sort alphabetically by mnemonic +mavis_rv64v_json.sort(key=lambda opcode: opcode["mnemonic"]) + +# Construct the uarch json +uarch_json = [] +for opcode in mavis_rv64v_json: + mnemonic = opcode["mnemonic"] + + # Assume inst is unsupported + opcode_entry = { + "mnemonic" : mnemonic, + "pipe" : "?", + "uop_gen" : "NONE", + "latency" : 0 + } + + # If it is supported, get the pipe and latency + if mnemonic in SUPPORTED_INSTS.keys(): + opcode_entry["mnemonic"] = mnemonic + opcode_entry["pipe"] = SUPPORTED_INSTS[mnemonic]["pipe"] + if(SUPPORTED_INSTS[mnemonic].get("uop_gen")): + opcode_entry["uop_gen"] = SUPPORTED_INSTS[mnemonic]["uop_gen"] + opcode_entry["pipe"] = SUPPORTED_INSTS[mnemonic]["pipe"] + opcode_entry["latency"] = SUPPORTED_INSTS[mnemonic]["latency"] + + uarch_json.append(opcode_entry) + +# Write the json to the file +with open(JSON, "w") as f: + print("Writing rv64v uarch json to "+JSON) + json.dump(uarch_json, f, indent=4) + diff --git a/arches/isa_json/olympia_uarch_rv64v.json b/arches/isa_json/olympia_uarch_rv64v.json new file mode 100644 index 00000000..e49847c5 --- /dev/null +++ b/arches/isa_json/olympia_uarch_rv64v.json @@ -0,0 +1,2228 @@ +[ + { + "mnemonic": "vaadd.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vaadd.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vaaddu.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vaaddu.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vadc.vim", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vadc.vvm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vadc.vxm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vadd.vi", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vadd.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vadd.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vand.vi", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vand.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vand.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vasub.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vasub.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vasubu.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vasubu.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vcompress.vm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vdiv.vv", + "pipe": "vdiv", + "uop_gen": "ARITH", + "latency": 23 + }, + { + "mnemonic": "vdiv.vx", + "pipe": "vdiv", + "uop_gen": "ARITH", + "latency": 23 + }, + { + "mnemonic": "vdivu.vv", + "pipe": "vdiv", + "uop_gen": "ARITH", + "latency": 23 + }, + { + "mnemonic": "vdivu.vx", + "pipe": "vdiv", + "uop_gen": "ARITH", + "latency": 23 + }, + { + "mnemonic": "vfadd.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfadd.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfclass.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfcvt.f.x.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfcvt.f.xu.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfcvt.rtz.x.f.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfcvt.rtz.xu.f.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfcvt.x.f.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfcvt.xu.f.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfdiv.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfdiv.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfdot.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfirst.m", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmacc.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmacc.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmadd.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmadd.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmax.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmax.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmerge.vfm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmin.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmin.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmsac.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmsac.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmsub.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmsub.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmul.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmul.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmv.f.s", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmv.s.f", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfmv.v.f", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfncvt.f.f.w", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfncvt.f.x.w", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfncvt.f.xu.w", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfncvt.rod.f.f.w", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfncvt.rtz.x.f.w", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfncvt.rtz.xu.f.w", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfncvt.x.f.w", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfncvt.xu.f.w", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfnmacc.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfnmacc.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfnmadd.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfnmadd.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfnmsac.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfnmsac.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfnmsub.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfnmsub.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfrdiv.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfrec7.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfredmax.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfredmin.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfredosum.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfredusum.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfrsqrt7.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfrsub.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfsgnj.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfsgnj.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfsgnjn.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfsgnjn.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfsgnjx.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfsgnjx.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfslide1down.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfslide1up.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfsqrt.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfsub.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfsub.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwadd.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwadd.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwadd.wf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwadd.wv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwcvt.f.f.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwcvt.f.x.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwcvt.f.xu.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwcvt.rtz.x.f.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwcvt.rtz.xu.f.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwcvt.x.f.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwcvt.xu.f.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwmacc.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwmacc.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwmsac.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwmsac.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwmul.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwmul.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwnmacc.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwnmacc.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwnmsac.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwnmsac.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwredosum.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwredusum.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwsub.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwsub.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwsub.wf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vfwsub.wv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vid.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "viota.m", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl1re16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl1re32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl1re64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl1re8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl2re16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl2re32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl2re64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl2re8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl4re16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl4re32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl4re64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl4re8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl8re16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl8re32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl8re64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vl8re8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vle16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vle16ff.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vle32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vle32ff.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vle64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vle64ff.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vle8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vle8ff.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vlm.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vloxei16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vloxei32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vloxei64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vloxei8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vlse16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vlse32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vlse64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vlse8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vluxei16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vluxei32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vluxei64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vluxei8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmacc.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmacc.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmadc.vim", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmadc.vvm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmadc.vxm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmadd.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmadd.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmand.mm", + "pipe": "vmask", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vmandn.mm", + "pipe": "vmask", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vmax.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vmax.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vmaxu.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vmaxu.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vmerge.vim", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmerge.vvm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmerge.vxm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmfeq.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmfeq.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmfge.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmfgt.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmfle.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmfle.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmflt.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmflt.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmfne.vf", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmfne.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmin.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vmin.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vminu.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vminu.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vmnand.mm", + "pipe": "vmask", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vmnor.mm", + "pipe": "vmask", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vmor.mm", + "pipe": "vmask", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vmorn.mm", + "pipe": "vmask", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vmsbc.vvm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmsbc.vxm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmsbf.m", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmseq.vi", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmseq.vv", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmseq.vx", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsgt.vi", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsgt.vx", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsgtu.vi", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsgtu.vx", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsif.m", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmsle.vi", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsle.vv", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsle.vx", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsleu.vi", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsleu.vv", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsleu.vx", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmslt.vv", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmslt.vx", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsltu.vv", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsltu.vx", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsne.vi", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsne.vv", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsne.vx", + "pipe": "vint", + "uop_gen": "ARITH_SINGLE_DEST", + "latency": 1 + }, + { + "mnemonic": "vmsof.m", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmul.vv", + "pipe": "vmul", + "uop_gen": "ARITH", + "latency": 3 + }, + { + "mnemonic": "vmul.vx", + "pipe": "vmul", + "uop_gen": "ARITH", + "latency": 3 + }, + { + "mnemonic": "vmulh.vv", + "pipe": "vmul", + "uop_gen": "ARITH", + "latency": 3 + }, + { + "mnemonic": "vmulh.vx", + "pipe": "vmul", + "uop_gen": "ARITH", + "latency": 3 + }, + { + "mnemonic": "vmulhsu.vv", + "pipe": "vmul", + "uop_gen": "ARITH", + "latency": 3 + }, + { + "mnemonic": "vmulhsu.vx", + "pipe": "vmul", + "uop_gen": "ARITH", + "latency": 3 + }, + { + "mnemonic": "vmulhu.vv", + "pipe": "vmul", + "uop_gen": "ARITH", + "latency": 3 + }, + { + "mnemonic": "vmulhu.vx", + "pipe": "vmul", + "uop_gen": "ARITH", + "latency": 3 + }, + { + "mnemonic": "vmv.s.x", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmv.v.i", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmv.v.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmv.v.x", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmv.x.s", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmv1r.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmv2r.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmv4r.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmv8r.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vmxnor.mm", + "pipe": "vmask", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vmxor.mm", + "pipe": "vmask", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vnclip.wi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnclip.wv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnclip.wx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnclipu.wi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnclipu.wv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnclipu.wx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnmsac.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnmsac.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnmsub.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnmsub.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnsra.wi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnsra.wv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnsra.wx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnsrl.wi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnsrl.wv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vnsrl.wx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vor.vi", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vor.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vor.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vpopc.m", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vredand.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vredmax.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vredmaxu.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vredmin.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vredminu.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vredor.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vredsum.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vredxor.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vrem.vv", + "pipe": "vdiv", + "uop_gen": "ARITH", + "latency": 23 + }, + { + "mnemonic": "vrem.vx", + "pipe": "vdiv", + "uop_gen": "ARITH", + "latency": 23 + }, + { + "mnemonic": "vremu.vv", + "pipe": "vdiv", + "uop_gen": "ARITH", + "latency": 23 + }, + { + "mnemonic": "vremu.vx", + "pipe": "vdiv", + "uop_gen": "ARITH", + "latency": 23 + }, + { + "mnemonic": "vrgather.vi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vrgather.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vrgather.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vrgatherei16.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vrsub.vi", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vrsub.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vs1r.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vs2r.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vs4r.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vs8r.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsadd.vi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsadd.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsadd.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsaddu.vi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsaddu.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsaddu.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsbc.vvm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsbc.vxm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vse16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vse32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vse64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vse8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsetivli", + "pipe": "vset", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vsetvl", + "pipe": "vset", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vsetvli", + "pipe": "vset", + "uop_gen": "NONE", + "latency": 1 + }, + { + "mnemonic": "vsext.vf2", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsext.vf4", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsext.vf8", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vslide1down.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vslide1up.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vslidedown.vi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vslidedown.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vslideup.vi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vslideup.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsll.vi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsll.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsll.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsm.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsmul.vv", + "pipe": "vmul", + "uop_gen": "ARITH", + "latency": 3 + }, + { + "mnemonic": "vsmul.vx", + "pipe": "vmul", + "uop_gen": "ARITH", + "latency": 3 + }, + { + "mnemonic": "vsoxei16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsoxei32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsoxei64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsoxei8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsra.vi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsra.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsra.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsrl.vi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsrl.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsrl.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsse16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsse32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsse64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsse8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vssra.vi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vssra.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vssra.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vssrl.vi", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vssrl.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vssrl.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vssub.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vssub.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vssubu.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vssubu.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsub.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vsub.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vsuxei16.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsuxei32.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsuxei64.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vsuxei8.v", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vwadd.vv", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwadd.vx", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwadd.wv", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwadd.wx", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwaddu.vv", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwaddu.vx", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwaddu.wv", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwaddu.wx", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwmacc.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vwmacc.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vwmaccsu.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vwmaccsu.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vwmaccu.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vwmaccu.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vwmaccus.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vwmul.vv", + "pipe": "vmul", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 3 + }, + { + "mnemonic": "vwmul.vx", + "pipe": "vmul", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 3 + }, + { + "mnemonic": "vwmulsu.vv", + "pipe": "vmul", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 3 + }, + { + "mnemonic": "vwmulsu.vx", + "pipe": "vmul", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 3 + }, + { + "mnemonic": "vwmulu.vv", + "pipe": "vmul", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 3 + }, + { + "mnemonic": "vwmulu.vx", + "pipe": "vmul", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 3 + }, + { + "mnemonic": "vwredsum.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vwredsumu.vs", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vwsub.vv", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwsub.vx", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwsub.wv", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwsub.wx", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwsubu.vv", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwsubu.vx", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwsubu.wv", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vwsubu.wx", + "pipe": "vint", + "uop_gen": "ARITH_WIDE_DEST", + "latency": 1 + }, + { + "mnemonic": "vxor.vi", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vxor.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vxor.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vzext.vf2", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vzext.vf4", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vzext.vf8", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + } +] \ No newline at end of file diff --git a/arches/medium_core.yaml b/arches/medium_core.yaml index 5a6cc06d..661f8e47 100644 --- a/arches/medium_core.yaml +++ b/arches/medium_core.yaml @@ -26,7 +26,8 @@ top.cpu.core0.extension.core_extensions: ["int"], # exe2 ["float", "faddsub", "fmac"], # exe3 ["float", "f2i"], # exe4 - ["br"] # exe5 + ["br"], # exe5 + ["vint", "vset", "vdiv", "vmul"] # exe6 ] # this is used to set how many units per queue @@ -40,7 +41,8 @@ top.cpu.core0.extension.core_extensions: ["0"], # iq0 -> exe0 ["1", "2"], # iq1 -> exe1, exe2 ["3", "4"], # iq2 -> exe3, exe4 - ["5"] # iq3 -> exe5 + ["5"], # iq3 -> exe5 + ["6"] ] top.cpu.core0.rename.scoreboards: @@ -48,16 +50,26 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] diff --git a/arches/small_core.yaml b/arches/small_core.yaml index 7b2b3802..67cb94db 100644 --- a/arches/small_core.yaml +++ b/arches/small_core.yaml @@ -20,7 +20,8 @@ top.cpu.core0.extension.core_extensions: [ ["sys", "int", "mul", "i2f", "cmov", "div"], # exe0 ["float", "faddsub", "fmac", "f2i"], # exe1 - ["br"] # exe2 + ["br"], # exe2 + ["vint", "vset", "vdiv", "vmul"] # exe3 ] # this is used to set how many units per queue # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive @@ -32,7 +33,8 @@ top.cpu.core0.extension.core_extensions: [ ["0"], # iq0 -> exe0 ["1"], # iq1 -> exe1 - ["2"] # iq2 -> exe2 + ["2"], # iq2 -> exe2 + ["3"], # iq3 -> exe3 ] top.cpu.core0.rename.scoreboards: @@ -40,14 +42,23 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] diff --git a/core/CMakeLists.txt b/core/CMakeLists.txt index 0b2daaac..32743498 100644 --- a/core/CMakeLists.txt +++ b/core/CMakeLists.txt @@ -5,6 +5,7 @@ add_library(core SimpleBranchPred.cpp Fetch.cpp Decode.cpp + VectorUopGenerator.cpp Rename.cpp Dispatch.cpp Dispatcher.cpp diff --git a/core/CPUFactories.hpp b/core/CPUFactories.hpp index bf0799d5..1a875ea9 100644 --- a/core/CPUFactories.hpp +++ b/core/CPUFactories.hpp @@ -7,6 +7,7 @@ #include "Core.hpp" #include "Fetch.hpp" #include "Decode.hpp" +#include "VectorUopGenerator.hpp" #include "Rename.hpp" #include "Dispatch.hpp" #include "Execute.hpp" @@ -47,6 +48,10 @@ namespace olympia{ sparta::ResourceFactory decode_rf; + //! \brief Resource Factory to build a VectorUopGenerator + sparta::ResourceFactory vec_uop_gen_rf; + //! \brief Resource Factory to build a Rename Unit RenameFactory rename_rf; @@ -56,7 +61,6 @@ namespace olympia{ //! \brief Resource Factory to build a Execute Unit ExecuteFactory execute_rf; - //! \brief Resource Factory to build a MMU Unit sparta::ResourceFactory dcache_rf; diff --git a/core/CPUTopology.cpp b/core/CPUTopology.cpp index 67447e14..d8fdb0a1 100644 --- a/core/CPUTopology.cpp +++ b/core/CPUTopology.cpp @@ -43,6 +43,14 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ sparta::TreeNode::GROUP_IDX_NONE, &factories->decode_rf }, + { + "vec_uop_gen", + "cpu.core*.decode", + "Vector Uop Generator", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + &factories->vec_uop_gen_rf + }, { "rename", "cpu.core*", @@ -381,8 +389,15 @@ void olympia::CoreTopologySimple::bindTree(sparta::RootTreeNode* root_node) pipe_target_end = stoi(iq[1]); } pipe_target_end++; + const std::string vset_in_decode = + core_node + ".decode." + "ports.in_vset_inst"; for (int pipe_idx = pipe_target_start; pipe_idx < pipe_target_end; ++pipe_idx) { + // check to ensure no duplicate pipe definitions + std::set unique_pipe_def_check(pipelines[pipe_idx].begin(), pipelines[pipe_idx].end()); + sparta_assert(unique_pipe_def_check.size() == pipelines[pipe_idx].size(), + "Duplicate pipe definitions, double check yaml file") + std::string unit_name = "exe" + std::to_string(pipe_idx); if (exe_pipe_rename.size() > 0) { @@ -395,6 +410,16 @@ void olympia::CoreTopologySimple::bindTree(sparta::RootTreeNode* root_node) const std::string exe_pipe_out = core_node + ".execute." + unit_name + ".ports.out_execute_pipe"; bind_ports(exe_pipe_in, exe_pipe_out); + + for(uint32_t i = 0; i < pipelines[pipe_idx].size(); ++i){ + if(pipelines[pipe_idx][i] == "vset"){ + // only bind execute pipe -> decode port for an issue queue if it has a vset pipe + const std::string exe_vset_out = + core_node + ".execute." + unit_name + ".ports.out_vset"; + bind_ports(vset_in_decode, exe_vset_out); + break; // break after we find a vset in pipeline def + } + } } const std::string exe_flush_in = diff --git a/core/CoreTypes.hpp b/core/CoreTypes.hpp index facd808f..4e37db57 100644 --- a/core/CoreTypes.hpp +++ b/core/CoreTypes.hpp @@ -9,29 +9,21 @@ namespace olympia::core_types using RegisterBitMask = sparta::Scoreboard::RegisterBitMask; //! Register file types - enum RegFile : uint8_t { + enum RegFile : uint8_t + { RF_INTEGER, RF_FLOAT, + RF_VECTOR, RF_INVALID, N_REGFILES = RF_INVALID }; - static inline const char * const regfile_names[] = { - "integer", - "float" - }; - - static inline const char * const issue_queue_types[] = { - "alu", - "fpu", - "br" - }; + static inline const char* const regfile_names[] = {"integer", "float", "vector"}; inline std::ostream & operator<<(std::ostream & os, const RegFile & rf) { - sparta_assert(rf < RegFile::RF_INVALID, - "RF index off into the weeds " << rf); + sparta_assert(rf < RegFile::RF_INVALID, "RF index off into the weeds " << rf); os << regfile_names[rf]; return os; } -} +} // namespace olympia::core_types diff --git a/core/CoreUtils.hpp b/core/CoreUtils.hpp index e4e0521b..00e33a90 100644 --- a/core/CoreUtils.hpp +++ b/core/CoreUtils.hpp @@ -28,7 +28,8 @@ namespace olympia::coreutils {mavis::InstMetaData::OperandTypes::DOUBLE, core_types::RegFile::RF_FLOAT}, {mavis::InstMetaData::OperandTypes::WORD, core_types::RegFile::RF_INTEGER}, {mavis::InstMetaData::OperandTypes::LONG, core_types::RegFile::RF_INTEGER}, - {mavis::InstMetaData::OperandTypes::QUAD, core_types::RegFile::RF_INTEGER}}; + {mavis::InstMetaData::OperandTypes::QUAD, core_types::RegFile::RF_INTEGER}, + {mavis::InstMetaData::OperandTypes::VECTOR, core_types::RegFile::RF_VECTOR}}; if (auto match = mavis_optype_to_regfile.find(reg.operand_type); match != mavis_optype_to_regfile.end()) { diff --git a/core/Decode.cpp b/core/Decode.cpp index e730a1fd..e9072fc0 100644 --- a/core/Decode.cpp +++ b/core/Decode.cpp @@ -1,11 +1,11 @@ // -*- C++ -*- #include "Decode.hpp" +#include "VectorUopGenerator.hpp" #include "fsl_api/FusionTypes.h" #include "sparta/events/StartupEvent.hpp" #include "sparta/utils/LogUtils.hpp" - #include #include @@ -19,7 +19,7 @@ namespace olympia sparta::Unit(node), fetch_queue_("FetchQueue", p->fetch_queue_size, node->getClock(), &unit_stat_set_), - + uop_queue_("UOpQueue", p->uop_queue_size, node->getClock(), &unit_stat_set_), fusion_num_fuse_instructions_(&unit_stat_set_, "fusion_num_fuse_instructions", "The number of custom instructions created by fusion", sparta::Counter::COUNT_NORMAL), @@ -33,8 +33,8 @@ namespace olympia sparta::Counter::COUNT_LATEST), fusion_num_groups_utilized_(&unit_stat_set_, "fusion_num_groups_utilized", - "Incremented on first use of a fusion group", - sparta::Counter::COUNT_LATEST), + "Incremented on first use of a fusion group", + sparta::Counter::COUNT_LATEST), fusion_pred_cycles_saved_(&unit_stat_set_, "fusion_pred_cycles_saved", "Optimistic prediction of the cycles saved by fusion", @@ -60,12 +60,31 @@ namespace olympia CREATE_SPARTA_HANDLER_WITH_DATA(Decode, receiveUopQueueCredits_, uint32_t)); in_reorder_flush_.registerConsumerHandler( CREATE_SPARTA_HANDLER_WITH_DATA(Decode, handleFlush_, FlushManager::FlushingCriteria)); + in_vset_inst_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Decode, process_vset_, InstPtr)); sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(Decode, sendInitialCredits_)); + + VCSRs_.setVCSRs(p->init_vl, p->init_sew, p->init_lmul, p->init_vta); } // Send fetch the initial credit count - void Decode::sendInitialCredits_() { fetch_queue_credits_outp_.send(fetch_queue_.capacity()); } + void Decode::sendInitialCredits_() + { + fetch_queue_credits_outp_.send(fetch_queue_.capacity()); + + // setting MavisIDs for vsetvl and vsetivli + mavis_facade_ = getMavis(getContainer()); + mavis_vsetvl_uid_ = mavis_facade_->lookupInstructionUniqueID("vsetvl"); + mavis_vsetivli_uid_ = mavis_facade_->lookupInstructionUniqueID("vsetivli"); + mavis_vsetvli_uid_ = mavis_facade_->lookupInstructionUniqueID("vsetvli"); + + // Get pointer to the vector uop generator + sparta::TreeNode * root_node = getContainer()->getRoot(); + vec_uop_gen_ = \ + root_node->getChild("cpu.core0.decode.vec_uop_gen")->getResourceAs(); + vec_uop_gen_->setMavis(mavis_facade_); + } // ------------------------------------------------------------------- // ------------------------------------------------------------------- @@ -73,7 +92,7 @@ namespace olympia { if (fusion_enable_) { - fuser_ = std::make_unique(fusion_group_definitions_); + fuser_ = std::make_unique(fusion_group_definitions_); hcache_ = fusion::HCache(FusionGroupType::jenkins_1aat); fusion_num_groups_defined_ = fuser_->getFusionGroupContainer().size(); } @@ -112,25 +131,69 @@ namespace olympia } } + void Decode::updateVcsrs_(const InstPtr & inst) + { + VCSRs_.setVCSRs(inst->getVL(), inst->getSEW(), inst->getLMUL(), inst->getVTA()); + + const uint64_t uid = inst->getOpCodeInfo()->getInstructionUniqueID(); + if ((uid == mavis_vsetvli_uid_) && inst->hasZeroRegSource()) + { + // If rs1 is x0 and rd is x0 then the vl is unchanged (assuming it is legal) + VCSRs_.vl = inst->hasZeroRegDest() ? std::min(VCSRs_.vl, VCSRs_.vlmax) + : VCSRs_.vlmax; + } + + ILOG("Processing vset{i}vl{i} instruction: " << inst); + ILOG(" LMUL: " << VCSRs_.lmul); + ILOG(" SEW: " << VCSRs_.sew); + ILOG(" VTA: " << VCSRs_.vta); + ILOG(" VLMAX: " << VCSRs_.vlmax); + ILOG(" VL: " << VCSRs_.vl); + + // Check validity of vector config + sparta_assert(VCSRs_.lmul <= 8, + "LMUL (" << VCSRs_.lmul << ") cannot be greater than " << 8); + sparta_assert(VCSRs_.vl <= VCSRs_.vlmax, + "VL (" << VCSRs_.vl << ") cannot be greater than VLMAX ("<< VCSRs_.vlmax << ")"); + } + + // process vset settings being forward from execution pipe + // for set instructions that depend on register + void Decode::process_vset_(const InstPtr & inst) + { + updateVcsrs_(inst); + + // if rs1 != 0, VL = x[rs1], so we assume there's an STF field for VL + if (waiting_on_vset_) + { + // schedule decode, because we've been stalled on vset + waiting_on_vset_ = false; + ev_decode_insts_event_.schedule(sparta::Clock::Cycle(0)); + } + } + // Handle incoming flush void Decode::handleFlush_(const FlushManager::FlushingCriteria & criteria) { ILOG("Got a flush call for " << criteria); fetch_queue_credits_outp_.send(fetch_queue_.size()); fetch_queue_.clear(); + + // Reset the vector uop generator + vec_uop_gen_->handleFlush(criteria); } // Decode instructions void Decode::decodeInsts_() { - uint32_t num_decode = std::min(uop_queue_credits_, fetch_queue_.size()); - num_decode = std::min(num_decode, num_to_decode_); + uint32_t num_to_decode = std::min(uop_queue_credits_, fetch_queue_.size() + uop_queue_.size()); + num_to_decode = std::min(num_to_decode, num_to_decode_); // buffer to maximize the chances of a group match limited // by max allowed latency, bounded by max group size if (fusion_enable_) { - if (num_decode < fusion_max_group_size_ && latency_count_ < fusion_max_latency_) + if (num_to_decode < fusion_max_group_size_ && latency_count_ < fusion_max_latency_) { ++latency_count_; return; @@ -139,72 +202,150 @@ namespace olympia latency_count_ = 0; - if (num_decode > 0) - { - InstGroupPtr insts = - sparta::allocate_sparta_shared_pointer(instgroup_allocator); + // For fusion + InstUidListType uids; - InstUidListType uids; - // Send instructions on their way to rename - for (uint32_t i = 0; i < num_decode; ++i) + // Send instructions on their way to rename + InstGroupPtr insts = + sparta::allocate_sparta_shared_pointer(instgroup_allocator); + // if we have a waiting on vset followed by more instructions, we decode + // vset and stall anything else + while ((insts->size() < num_to_decode) && !waiting_on_vset_) + { + if (uop_queue_.size() > 0) { - const auto & inst = fetch_queue_.read(0); + const auto & inst = uop_queue_.read(0); insts->emplace_back(inst); inst->setStatus(Inst::Status::DECODED); + ILOG("From UOp Queue Decoded: " << inst); + uop_queue_.pop(); + } + else if (fetch_queue_.size() > 0) + { + sparta_assert(fetch_queue_.size() > 0, + "Cannot read from the fetch queue because it is empty!"); + auto & inst = fetch_queue_.read(0); + + // for vector instructions, we block on vset and do not allow any other + // processing of instructions until the vset is resolved optimizations could be + // to allow scalar operations to move forward until a subsequent vector + // instruction is detected or do vset prediction + + // vsetvl always block + // vsetvli only blocks if rs1 is not x0 + // vsetivli never blocks + const uint64_t uid = inst->getOpCodeInfo()->getInstructionUniqueID(); + if ((uid == mavis_vsetivli_uid_) || + ((uid == mavis_vsetvli_uid_) && inst->hasZeroRegSource())) + { + updateVcsrs_(inst); + } + else if (uid == mavis_vsetvli_uid_ || uid == mavis_vsetvl_uid_) + { + // block for vsetvl or vsetvli when rs1 of vsetvli is NOT 0 + waiting_on_vset_ = true; + // need to indicate we want a signal sent back at execute + inst->setBlockingVSET(true); + ILOG("Decode stalled, Waiting on vset that has register dependency: " << inst) + } + else + { + if (!inst->isVset() && inst->isVector()) + { + // set LMUL, VSET, VL, VTA for any other vector instructions + inst->setVCSRs(&VCSRs_); + } + } + + ILOG("Decoded: " << inst); + insts->emplace_back(inst); + inst->setStatus(Inst::Status::DECODED); + + // Handle vector uop generation + if (inst->isVector() && !inst->isVset()) + { + // If LMUL > 1, fracture instruction into UOps + ILOG("Vector uop gen: " << inst); + vec_uop_gen_->setInst(inst); + + while(vec_uop_gen_->getNumUopsRemaining() >= 1) + { + const InstPtr uop = vec_uop_gen_->generateUop(); + if (insts->size() < num_to_decode_) + { + insts->emplace_back(uop); + uop->setStatus(Inst::Status::DECODED); + } + else + { + ILOG("Not enough decode credits to process UOp, " + "appending to the uop queue: " << uop); + uop_queue_.push(uop); + } + } + } if (fusion_enable_) { uids.push_back(inst->getMavisUid()); } - ILOG("Decoded: " << inst); - + // Remove from Fetch Queue fetch_queue_.pop(); } + else + { + // Uop queue and fetch queue are both empty, nothing left to decode + break; + } + } - if (fusion_enable_) + if (fusion_enable_) + { + MatchInfoListType matches; + uint32_t max_itrs = 0; + FusionGroupContainerType & container = fuser_->getFusionGroupContainer(); + do { - MatchInfoListType matches; - uint32_t max_itrs = 0; - FusionGroupContainerType & container = fuser_->getFusionGroupContainer(); - do - { - matchFusionGroups_(matches, insts, uids, container); - processMatches_(matches, insts, uids); - // Future feature whereIsEgon(insts,numGhosts); - ++max_itrs; - } while (matches.size() > 0 && max_itrs < fusion_match_max_tries_); + matchFusionGroups_(matches, insts, uids, container); + processMatches_(matches, insts, uids); + // Future feature whereIsEgon(insts,numGhosts); + ++max_itrs; + } while (matches.size() > 0 && max_itrs < fusion_match_max_tries_); - if (max_itrs >= fusion_match_max_tries_) - { - throw sparta::SpartaException("Fusion group match watch dog exceeded."); - } + if (max_itrs >= fusion_match_max_tries_) + { + throw sparta::SpartaException("Fusion group match watch dog exceeded."); } // Debug statement - if (fusion_debug_ && fusion_enable_) + if (fusion_debug_) + { infoInsts_(cout, insts); - // Send decoded instructions to rename - uop_queue_outp_.send(insts); + } + } - // TODO: whereisegon() would remove the ghosts, - // Commented out for now, in practice insts - // would be smaller due to the fused ops - // uint32_t unfusedInstsSize = insts->size(); + // Send decoded instructions to rename + sparta_assert(insts->size() <= num_to_decode_, + "Instruction group grew too large! " << insts); + uop_queue_outp_.send(insts); - // Decrement internal Uop Queue credits - sparta_assert(uop_queue_credits_ >= insts->size(), - "Attempt to decrement d0q credits below what is available"); + // TODO: whereisegon() would remove the ghosts, + // Commented out for now, in practice insts + // would be smaller due to the fused ops + // uint32_t unfusedInstsSize = insts->size(); - uop_queue_credits_ -= insts->size(); + // Decrement internal Uop Queue credits + sparta_assert(uop_queue_credits_ >= insts->size(), + "Attempt to decrement d0q credits below what is available"); + uop_queue_credits_ -= insts->size(); - // Send credits back to Fetch to get more instructions - fetch_queue_credits_outp_.send(insts->size()); - } + // Send credits back to Fetch to get more instructions + fetch_queue_credits_outp_.send(insts->size()); // If we still have credits to send instructions as well as // instructions in the queue, schedule another decode session - if (uop_queue_credits_ > 0 && fetch_queue_.size() > 0) + if (uop_queue_credits_ > 0 && (fetch_queue_.size() + uop_queue_.size()) > 0) { ev_decode_insts_event_.schedule(1); } diff --git a/core/Decode.hpp b/core/Decode.hpp index 0ca443bf..209d30bf 100644 --- a/core/Decode.hpp +++ b/core/Decode.hpp @@ -5,6 +5,7 @@ #include "CoreTypes.hpp" #include "FlushManager.hpp" #include "InstGroup.hpp" +#include "MavisUnit.hpp" #include "fsl_api/FieldExtractor.h" #include "fsl_api/Fusion.h" @@ -27,7 +28,7 @@ namespace olympia { - + class VectorUopGenerator; /** * @file Decode.h * @brief Decode instructions from Fetch and send them on @@ -75,6 +76,9 @@ namespace olympia //! \brief depth of the input instruction buffer PARAMETER(uint32_t, fetch_queue_size, 10, "Size of the fetch queue") + //! \brief depth of UOp Queue + PARAMETER(uint32_t, uop_queue_size, 8, "Size of the UOp queue") + //! \brief enable fusion operations //! //! master enable, when false fusion_* parmeters have no effect @@ -91,8 +95,7 @@ namespace olympia //! //! \see fusion_enable_register_ for the encoding //! in the yaml to choose a transform my name - PARAMETER(uint32_t, fusion_enable_register, - std::numeric_limits::max(), + PARAMETER(uint32_t, fusion_enable_register, std::numeric_limits::max(), "bit-wise fusion group enable") //! \brief max acceptable latency created by gathering uops @@ -111,7 +114,7 @@ namespace olympia //! Used with fusion_max_latency to gather instructions for //! possible fusion. If number of decode is >= fusion group size //! there is no need to continue to gather instructions. - PARAMETER(uint32_t, fusion_max_group_size, 4, "max fusion group isze") + PARAMETER(uint32_t, fusion_max_group_size, 4, "max fusion group size") //! \brief ... PARAMETER(std::string, fusion_summary_report, "fusion_summary.txt", @@ -120,6 +123,18 @@ namespace olympia //! \brief ... PARAMETER(FileNameListType, fusion_group_definitions, {}, "Lists of fusion group UID json files") + + //! LMUL + PARAMETER(uint32_t, init_lmul, 1, "effective length") + + //! Element width in bits + PARAMETER(uint32_t, init_sew, 8, "element width") + + //! Vector length, number of elements + PARAMETER(uint32_t, init_vl, 128, "vector length") + + //! Vector tail agnostic, default is undisturbed + PARAMETER(bool, init_vta, 0, "vector tail agnostic") }; /** @@ -136,10 +151,15 @@ namespace olympia private: // The internal instruction queue InstQueue fetch_queue_; + InstQueue uop_queue_; + + // Vector uop generator + VectorUopGenerator * vec_uop_gen_ = nullptr; // Port listening to the fetch queue appends - Note the 1 cycle delay sparta::DataInPort fetch_queue_write_in_{&unit_port_set_, "in_fetch_queue_write", 1}; + sparta::DataInPort in_vset_inst_{&unit_port_set_, "in_vset_inst", 1}; sparta::DataOutPort fetch_queue_credits_outp_{&unit_port_set_, "out_fetch_queue_credits"}; @@ -313,16 +333,32 @@ namespace olympia //! \brief the fusion group definition files, JSON or (future) FSL const std::vector fusion_group_definitions_; + Inst::VCSRs VCSRs_; + + MavisType* mavis_facade_; + + uint32_t mavis_vsetvl_uid_; + uint32_t mavis_vsetivli_uid_; + uint32_t mavis_vsetvli_uid_; + + bool waiting_on_vset_; + + // Helper method to update VCSRs + void updateVcsrs_(const InstPtr &); + ////////////////////////////////////////////////////////////////////// // Decoder callbacks void sendInitialCredits_(); void fetchBufferAppended_(const InstGroupPtr &); void receiveUopQueueCredits_(const uint32_t &); + void process_vset_(const InstPtr &); void decodeInsts_(); void handleFlush_(const FlushManager::FlushingCriteria & criteria); uint32_t uop_queue_credits_ = 0; + friend class DecodeTester; }; + class DecodeTester; //! \brief the fusion functor/function objects //! @@ -339,5 +375,4 @@ namespace olympia return false; } }; - } // namespace olympia diff --git a/core/Dispatch.cpp b/core/Dispatch.cpp index 1b27498c..74ce4a14 100644 --- a/core/Dispatch.cpp +++ b/core/Dispatch.cpp @@ -211,7 +211,7 @@ namespace olympia InstGroupPtr insts_dispatched = sparta::allocate_sparta_shared_pointer(instgroup_allocator); - ; + bool keep_dispatching = true; for (uint32_t i = 0; (i < num_dispatch) && keep_dispatching; ++i) { diff --git a/core/Dispatch.hpp b/core/Dispatch.hpp index 78ff2fa1..1f94c0f9 100644 --- a/core/Dispatch.hpp +++ b/core/Dispatch.hpp @@ -123,30 +123,24 @@ namespace olympia /////////////////////////////////////////////////////////////////////// // Stall counters - enum StallReason + enum StallReason : uint16_t { - CMOV_BUSY = InstArchInfo::TargetPipe::CMOV, // Could not send any or all instructions -- - // CMOV busy - DIV_BUSY = - InstArchInfo::TargetPipe::DIV, // Could not send any or all instructions -- DIV busy - FADDSUB_BUSY = InstArchInfo::TargetPipe::FADDSUB, // Could not send any or all - // instructions -- FADDSUB busy - FLOAT_BUSY = InstArchInfo::TargetPipe::FLOAT, // Could not send any or all instructions - // -- FLOAT busy - FMAC_BUSY = InstArchInfo::TargetPipe::FMAC, // Could not send any or all instructions -- - // FMAC busy - I2F_BUSY = - InstArchInfo::TargetPipe::I2F, // Could not send any or all instructions -- I2F busy - F2I_BUSY = - InstArchInfo::TargetPipe::F2I, // Could not send any or all instructions -- F2I busy - INT_BUSY = - InstArchInfo::TargetPipe::INT, // Could not send any or all instructions -- INT busy - LSU_BUSY = - InstArchInfo::TargetPipe::LSU, // Could not send any or all instructions -- LSU busy - MUL_BUSY = - InstArchInfo::TargetPipe::MUL, // Could not send any or all instructions -- MUL busy - BR_BUSY = - InstArchInfo::TargetPipe::BR, // Could not send any or all instructions -- MUL busy + BR_BUSY = InstArchInfo::TargetPipe::BR, + CMOV_BUSY = InstArchInfo::TargetPipe::CMOV, + DIV_BUSY = InstArchInfo::TargetPipe::DIV, + FADDSUB_BUSY = InstArchInfo::TargetPipe::FADDSUB, + FLOAT_BUSY = InstArchInfo::TargetPipe::FLOAT, + FMAC_BUSY = InstArchInfo::TargetPipe::FMAC, + I2F_BUSY = InstArchInfo::TargetPipe::I2F, + F2I_BUSY = InstArchInfo::TargetPipe::F2I, + INT_BUSY = InstArchInfo::TargetPipe::INT, + LSU_BUSY = InstArchInfo::TargetPipe::LSU, + MUL_BUSY = InstArchInfo::TargetPipe::MUL, + VINT_BUSY = InstArchInfo::TargetPipe::VINT, + VMASK_BUSY = InstArchInfo::TargetPipe::VMASK, + VMUL_BUSY = InstArchInfo::TargetPipe::VMUL, + VDIV_BUSY = InstArchInfo::TargetPipe::VDIV, + VSET_BUSY = InstArchInfo::TargetPipe::VSET, NO_ROB_CREDITS = InstArchInfo::TargetPipe::SYS, // No credits from the ROB NOT_STALLED, // Made forward progress (dispatched all instructions or no instructions) N_STALL_REASONS @@ -180,6 +174,16 @@ namespace olympia sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_br_busy", "BR busy", sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vint_busy", "VINT busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vmask_busy", "VMASK busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vmul_busy", "VMUL busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vdiv_busy", "VDIV busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vset_busy", "VSET busy", + sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_sys_busy", "No credits from ROB", sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", @@ -209,6 +213,16 @@ namespace olympia sparta::Counter::COUNT_NORMAL), sparta::Counter(getStatisticSet(), "count_br_insts", "Total BR insts", sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vint_insts", "Total VINT insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vmask_insts", "Total VMASK insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vmul_insts", "Total VMUL insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vdiv_insts", "Total VDIV insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vset_insts", "Total VSET insts", + sparta::Counter::COUNT_NORMAL), sparta::Counter(getStatisticSet(), "count_sys_insts", "Total SYS insts", sparta::Counter::COUNT_NORMAL)}}; @@ -262,51 +276,23 @@ namespace olympia inline std::ostream & operator<<(std::ostream & os, const Dispatch::StallReason & stall) { - switch (stall) + if (stall == Dispatch::StallReason::NOT_STALLED) { - case Dispatch::StallReason::NOT_STALLED: os << "NOT_STALLED"; - break; - case Dispatch::StallReason::NO_ROB_CREDITS: + } + else if (stall == Dispatch::StallReason::NO_ROB_CREDITS) + { os << "NO_ROB_CREDITS"; - break; - case Dispatch::StallReason::LSU_BUSY: - os << "LSU_BUSY"; - break; - case Dispatch::StallReason::CMOV_BUSY: - os << "CMOV_BUSY"; - break; - case Dispatch::StallReason::DIV_BUSY: - os << "DIV_BUSY"; - break; - case Dispatch::StallReason::FADDSUB_BUSY: - os << "FADDSUB_BUSY"; - break; - case Dispatch::StallReason::FLOAT_BUSY: - os << "FLOAT_BUSY"; - break; - case Dispatch::StallReason::FMAC_BUSY: - os << "FMAC_BUSY"; - break; - case Dispatch::StallReason::I2F_BUSY: - os << "I2F_BUSY"; - break; - case Dispatch::StallReason::F2I_BUSY: - os << "F2I_BUSY"; - break; - case Dispatch::StallReason::INT_BUSY: - os << "INT_BUSY"; - break; - case Dispatch::StallReason::MUL_BUSY: - os << "MUL_BUSY"; - break; - case Dispatch::StallReason::BR_BUSY: - os << "BR_BUSY"; - break; - case Dispatch::StallReason::N_STALL_REASONS: + } + else if (stall != Dispatch::StallReason::N_STALL_REASONS) + { + os << InstArchInfo::execution_pipe_string_map.at((InstArchInfo::TargetPipe)stall) << "_BUSY"; + } + else + { sparta_assert(false, "How'd we get here?"); } return os; } -} // namespace olympia \ No newline at end of file +} // namespace olympia diff --git a/core/ExecutePipe.cpp b/core/ExecutePipe.cpp index 22d801eb..dc7932ad 100644 --- a/core/ExecutePipe.cpp +++ b/core/ExecutePipe.cpp @@ -15,6 +15,7 @@ namespace olympia execute_time_(p->execute_time), enable_random_misprediction_(p->enable_random_misprediction && p->contains_branch_unit), issue_queue_name_(p->iq_name), + valu_adder_num_(p->valu_adder_num), collected_inst_(node, node->getName()) { p->enable_random_misprediction.ignore(); @@ -30,7 +31,6 @@ namespace olympia void ExecutePipe::setupExecutePipe_() { // Setup scoreboard view upon register file - std::vector reg_files = {core_types::RF_INTEGER, core_types::RF_FLOAT}; // if we ever move to multicore, we only want to have resources look for // scoreboard in their cpu if we're running a test where we only have // top.rename or top.issue_queue, then we can just use the root @@ -41,7 +41,7 @@ namespace olympia { cpu_node = getContainer()->getRoot(); } - for (const auto rf : reg_files) + for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) { // alu0, alu1 name is based on exe names, point to issue_queue name instead scoreboard_views_[rf].reset( @@ -53,12 +53,60 @@ namespace olympia // change to insertInst void ExecutePipe::insertInst(const InstPtr & ex_inst) { - sparta_assert_context( - unit_busy_ == false, - "ExecutePipe is receiving a new instruction when it's already busy!!"); - ex_inst->setStatus(Inst::Status::SCHEDULED); - const uint32_t exe_time = - ignore_inst_execute_time_ ? execute_time_ : ex_inst->getExecuteTime(); + if (num_passes_needed_ == 0) + { + ex_inst->setStatus(Inst::Status::SCHEDULED); + // we only need to check if unit_busy_ if instruction doesn't have multiple passes + // if it does need multiple passes, we need to keep unit_busy_ blocked so no instruction + // can get dispatched before the next pass begins + sparta_assert_context( + unit_busy_ == false, + "ExecutePipe is receiving a new instruction when it's already busy!!"); + } + + // Get instruction latency + uint32_t exe_time = ignore_inst_execute_time_ ? execute_time_ : ex_inst->getExecuteTime(); + + if (!ex_inst->isVset() && ex_inst->isVector()) + { + // have to factor in vlen, sew, valu length to calculate how many passes are needed + // i.e if VL = 256 and SEW = 8, but our VALU only has 8 64 bit adders, it will take 4 + // passes to execute the entire instruction if we have an 8 bit number, the 64 bit adder + // will truncate, but we have each adder support the largest SEW possible + if (ex_inst->getPipe() == InstArchInfo::TargetPipe::VINT) + { + // First time seeing this uop, determine number of passes needed + if (num_passes_needed_ == 0) + { + // The number of non-tail elements in the uop is used to determine how many + // passes are needed + const uint32_t num_elems_per_uop = ex_inst->getVLMAX() / ex_inst->getLMUL(); + const uint32_t num_elems_remaining = ex_inst->getVL() - (num_elems_per_uop * (ex_inst->getUOpID() - 1)); + const uint32_t vl = std::min(num_elems_per_uop, num_elems_remaining); + const uint32_t num_passes = std::ceil(vl / valu_adder_num_); + if (num_passes > 1) + { + // only care about cases with multiple passes + num_passes_needed_ = num_passes; + curr_num_pass_ = 1; + ILOG("Inst " << ex_inst << " needs " << num_passes_needed_ + << " before completing the instruction, beginning pass: " + << curr_num_pass_); + } + } + else + { + curr_num_pass_++; + sparta_assert(curr_num_pass_ <= num_passes_needed_, + "Instruction with multiple passes incremented for more than the " + "total number of passes needed for instruction: " + << ex_inst) + ILOG("Inst: " + << ex_inst << " beginning it's pass number: " << curr_num_pass_ + << " of the total required passes needed: " << num_passes_needed_); + } + } + } collected_inst_.collectWithDuration(ex_inst, exe_time); ILOG("Executing: " << ex_inst << " for " << exe_time + getClock()->currentCycle()); sparta_assert(exe_time != 0); @@ -70,31 +118,52 @@ namespace olympia // Called by the scheduler, scheduled by complete_inst_. void ExecutePipe::executeInst_(const InstPtr & ex_inst) { - ILOG("Executed inst: " << ex_inst); - auto reg_file = ex_inst->getRenameData().getDestination().rf; - if (reg_file != core_types::RegFile::RF_INVALID) + if (num_passes_needed_ != 0 && curr_num_pass_ < num_passes_needed_) { - const auto & dest_bits = ex_inst->getDestRegisterBitMask(reg_file); - scoreboard_views_[reg_file]->setReady(dest_bits); + issue_inst_.preparePayload(ex_inst)->schedule(sparta::Clock::Cycle(0)); } - - if (enable_random_misprediction_) + else { - if (ex_inst->isBranch() && (std::rand() % 20) == 0) + if (num_passes_needed_ != 0) { - ILOG("Randomly injecting a mispredicted branch: " << ex_inst); - ex_inst->setMispredicted(); + // reseting counters once vector instruction needing more than 1 pass + curr_num_pass_ = 0; + num_passes_needed_ = 0; + } + ILOG("Executed inst: " << ex_inst); + if (ex_inst->isVset() && ex_inst->isBlockingVSET()) + { + // sending back VSET CSRs + ILOG("Forwarding VSET CSRs back to decode, LMUL: " + << ex_inst->getLMUL() << " SEW: " << ex_inst->getSEW() + << " VTA: " << ex_inst->getVTA() << " VL: " << ex_inst->getVL()); + out_vset_.send(ex_inst); + } + auto reg_file = ex_inst->getRenameData().getDestination().rf; + if (reg_file != core_types::RegFile::RF_INVALID) + { + const auto & dest_bits = ex_inst->getDestRegisterBitMask(reg_file); + scoreboard_views_[reg_file]->setReady(dest_bits); } - } - // We're not busy anymore - unit_busy_ = false; + if (enable_random_misprediction_) + { + if (ex_inst->isBranch() && (std::rand() % 20) == 0) + { + ILOG("Randomly injecting a mispredicted branch: " << ex_inst); + ex_inst->setMispredicted(); + } + } + + // We're not busy anymore + unit_busy_ = false; - // Count the instruction as completely executed - ++total_insts_executed_; + // Count the instruction as completely executed + ++total_insts_executed_; - // Schedule completion - complete_inst_.preparePayload(ex_inst)->schedule(1); + // Schedule completion + complete_inst_.preparePayload(ex_inst)->schedule(1); + } } // Called by the scheduler, scheduled by complete_inst_. diff --git a/core/ExecutePipe.hpp b/core/ExecutePipe.hpp index 5a2b95a3..1a281454 100644 --- a/core/ExecutePipe.hpp +++ b/core/ExecutePipe.hpp @@ -50,6 +50,8 @@ namespace olympia PARAMETER(uint32_t, execute_time, 1, "Time for execution") PARAMETER(bool, enable_random_misprediction, false, "test mode to inject random branch mispredictions") + PARAMETER(uint32_t, valu_adder_num, 8, + "VALU Number of Adders") // # of 64 bit adders, so 8 64 bit adders = 512 bits HIDDEN_PARAMETER(bool, contains_branch_unit, false, "Does this exe pipe contain a branch unit") HIDDEN_PARAMETER(std::string, iq_name, "", "issue queue name for scoreboard view") @@ -82,6 +84,7 @@ namespace olympia sparta::DataOutPort out_scheduler_credits_{&unit_port_set_, "out_scheduler_credits"}; sparta::DataOutPort out_execute_pipe_{&unit_port_set_, "out_execute_pipe"}; + sparta::DataOutPort out_vset_{&unit_port_set_, "out_vset"}; sparta::DataInPort in_reorder_flush_{ &unit_port_set_, "in_reorder_flush", sparta::SchedulingPhase::Flush, 1}; @@ -97,9 +100,11 @@ namespace olympia const uint32_t execute_time_; const bool enable_random_misprediction_; const std::string issue_queue_name_; - + uint32_t valu_adder_num_; + uint32_t num_passes_needed_ = 0; + uint32_t curr_num_pass_ = 0; // Events used to issue, execute and complete the instruction - sparta::UniqueEvent<> issue_inst_{ + sparta::PayloadEvent issue_inst_{ &unit_event_set_, getName() + "_insert_inst", CREATE_SPARTA_HANDLER_WITH_DATA(ExecutePipe, insertInst, InstPtr)}; sparta::PayloadEvent execute_inst_{ diff --git a/core/Fetch.cpp b/core/Fetch.cpp index 0629111f..3c27deb1 100644 --- a/core/Fetch.cpp +++ b/core/Fetch.cpp @@ -15,26 +15,24 @@ namespace olympia { - const char * Fetch::name = "fetch"; + const char* Fetch::name = "fetch"; - Fetch::Fetch(sparta::TreeNode * node, - const FetchParameterSet * p) : + Fetch::Fetch(sparta::TreeNode* node, const FetchParameterSet* p) : sparta::Unit(node), num_insts_to_fetch_(p->num_to_fetch), skip_nonuser_mode_(p->skip_nonuser_mode), my_clk_(getClock()) { - in_fetch_queue_credits_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveFetchQueueCredits_, uint32_t)); + in_fetch_queue_credits_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveFetchQueueCredits_, uint32_t)); - in_fetch_flush_redirect_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, flushFetch_, FlushManager::FlushingCriteria)); + in_fetch_flush_redirect_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, flushFetch_, FlushManager::FlushingCriteria)); - fetch_inst_event_.reset(new sparta::SingleCycleUniqueEvent<>(&unit_event_set_, "fetch_random", - CREATE_SPARTA_HANDLER(Fetch, fetchInstruction_))); + fetch_inst_event_.reset(new sparta::SingleCycleUniqueEvent<>( + &unit_event_set_, "fetch_random", CREATE_SPARTA_HANDLER(Fetch, fetchInstruction_))); // Schedule a single event to start reading from a trace file sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(Fetch, initialize_)); - } Fetch::~Fetch() {} @@ -42,12 +40,11 @@ namespace olympia void Fetch::initialize_() { // Get the CPU Node - auto cpu_node = getContainer()->getParent()->getParent(); - auto extension = sparta::notNull(cpu_node->getExtension("simulation_configuration")); - auto workload = extension->getParameters()->getParameter("workload"); - inst_generator_ = InstGenerator::createGenerator(getMavis(getContainer()), - workload->getValueAsString(), - skip_nonuser_mode_); + auto cpu_node = getContainer()->getParent()->getParent(); + auto extension = sparta::notNull(cpu_node->getExtension("simulation_configuration")); + auto workload = extension->getParameters()->getParameter("workload"); + inst_generator_ = InstGenerator::createGenerator( + getMavis(getContainer()), workload->getValueAsString(), skip_nonuser_mode_); fetch_inst_event_->schedule(1); } @@ -57,57 +54,65 @@ namespace olympia const uint32_t upper = std::min(credits_inst_queue_, num_insts_to_fetch_); // Nothing to send. Don't need to schedule this again. - if(upper == 0) { return; } + if (upper == 0) + { + return; + } - InstGroupPtr insts_to_send = sparta::allocate_sparta_shared_pointer(instgroup_allocator); - for(uint32_t i = 0; i < upper; ++i) + InstGroupPtr insts_to_send = + sparta::allocate_sparta_shared_pointer(instgroup_allocator); + for (uint32_t i = 0; i < upper; ++i) { InstPtr ex_inst = inst_generator_->getNextInst(my_clk_); - if(SPARTA_EXPECT_TRUE(nullptr != ex_inst)) + if (SPARTA_EXPECT_TRUE(nullptr != ex_inst)) { ex_inst->setSpeculative(speculative_path_); insts_to_send->emplace_back(ex_inst); - ILOG("Sending: " << ex_inst << " down the pipe"); } - else { + else + { break; } } - if(false == insts_to_send->empty()) + if (false == insts_to_send->empty()) { out_fetch_queue_write_.send(insts_to_send); - credits_inst_queue_ -= static_cast (insts_to_send->size()); + credits_inst_queue_ -= static_cast(insts_to_send->size()); - if((credits_inst_queue_ > 0) && (false == inst_generator_->isDone())) { + if ((credits_inst_queue_ > 0) && (false == inst_generator_->isDone())) + { fetch_inst_event_->schedule(1); } - if(SPARTA_EXPECT_FALSE(info_logger_)) { + if (SPARTA_EXPECT_FALSE(info_logger_)) + { info_logger_ << "Fetch: send num_inst=" << insts_to_send->size() << " instructions, remaining credit=" << credits_inst_queue_; } } - else if(SPARTA_EXPECT_FALSE(info_logger_)) { + else if (SPARTA_EXPECT_FALSE(info_logger_)) + { info_logger_ << "Fetch: no instructions from trace"; } } // Called when decode has room - void Fetch::receiveFetchQueueCredits_(const uint32_t & dat) { + void Fetch::receiveFetchQueueCredits_(const uint32_t & dat) + { credits_inst_queue_ += dat; - ILOG("Fetch: receive num_decode_credits=" << dat - << ", total decode_credits=" << credits_inst_queue_); + ILOG("Fetch: receive num_decode_credits=" << dat << ", total decode_credits=" + << credits_inst_queue_); // Schedule a fetch event this cycle fetch_inst_event_->schedule(sparta::Clock::Cycle(0)); } // Called from FlushManager via in_fetch_flush_redirect_port - void Fetch::flushFetch_(const FlushManager::FlushingCriteria &criteria) + void Fetch::flushFetch_(const FlushManager::FlushingCriteria & criteria) { ILOG("Fetch: received flush " << criteria); @@ -130,4 +135,4 @@ namespace olympia // speculative_path_ = false; } -} +} // namespace olympia diff --git a/core/Fetch.hpp b/core/Fetch.hpp index 1538bb17..3087a2a6 100644 --- a/core/Fetch.hpp +++ b/core/Fetch.hpp @@ -125,6 +125,9 @@ namespace olympia // Receive flush from FlushManager void flushFetch_(const FlushManager::FlushingCriteria &); + // Recieve vset instruction and set waiting_on_vset_ flag + void process_vset_(const InstPtr &); + // Are we fetching a speculative path? bool speculative_path_ = false; }; diff --git a/core/Inst.cpp b/core/Inst.cpp index dfb4ce95..f80248c1 100644 --- a/core/Inst.cpp +++ b/core/Inst.cpp @@ -68,11 +68,18 @@ namespace olympia is_condbranch_(opcode_info_->isInstType(mavis::OpcodeInfo::InstructionTypes::CONDITIONAL)), is_call_(isCallInstruction(opcode_info)), is_csr_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::CSR)), + is_vector_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::VECTOR)), is_return_(isReturnInstruction(opcode_info)), status_state_(Status::FETCHED) { sparta_assert(inst_arch_info_ != nullptr, "Mavis decoded the instruction, but Olympia has no uarch data for it: " << getDisasm() << " " << std::hex << " opc: 0x" << getOpCode()); + + // Check that instruction is supported + sparta_assert(getPipe() != InstArchInfo::TargetPipe::UNKNOWN, + "Unknown target pipe (execution) for " << getMnemonic()); + sparta_assert(getExecuteTime() != 0, + "Unknown execution time (latency) for " << getMnemonic()); } } // namespace olympia diff --git a/core/Inst.hpp b/core/Inst.hpp index 9ece3435..3cb04ce5 100644 --- a/core/Inst.hpp +++ b/core/Inst.hpp @@ -74,6 +74,33 @@ namespace olympia Reg data_reg_; }; + static const uint32_t VLEN = 1024; // vector register default bit size + + // Vector CSRs + struct VCSRs + { + uint32_t vl = 16; // vector length + uint32_t sew = 8; // set element width + uint32_t lmul = 1; // effective length + bool vta = false; // vector tail agnostic, false = undisturbed, true = agnostic + + uint32_t vlmax_formula() { return (VLEN / sew) * lmul; } + + void setVCSRs(uint32_t input_vl, + uint32_t input_sew, + uint32_t input_lmul, + uint32_t input_vta) + { + vl = input_vl; + sew = input_sew; + lmul = input_lmul; + vta = input_vta; + vlmax = vlmax_formula(); + } + + uint32_t vlmax = vlmax_formula(); + }; + // Used by Mavis using PtrType = sparta::SpartaSharedPointer; @@ -93,7 +120,7 @@ namespace olympia COMPLETED, RETIRED, FLUSHED, - UNMOD, //no extended status + UNMOD, // no extended status FUSED, FUSION_GHOST, __LAST @@ -132,52 +159,30 @@ namespace olympia } } - const Status & getStatus() const - { - return status_state_; - } + const Status & getStatus() const { return status_state_; } - bool getCompletedStatus() const - { - return getStatus() == olympia::Inst::Status::COMPLETED; - } + bool getCompletedStatus() const { return getStatus() == olympia::Inst::Status::COMPLETED; } - bool getFlushedStatus() const - { - return getStatus() == olympia::Inst::Status::FLUSHED; - } + bool getFlushedStatus() const { return getStatus() == olympia::Inst::Status::FLUSHED; } - void setMispredicted() - { - is_mispredicted_ = true; - } + void setMispredicted() { is_mispredicted_ = true; } // Is this branch instruction mispredicted? - bool isMispredicted() const - { - return is_mispredicted_; - } + bool isMispredicted() const { return is_mispredicted_; } - const Status & getExtendedStatus() const - { - return extended_status_state_; - } + const Status & getExtendedStatus() const { return extended_status_state_; } void setExtendedStatus(Status status) { - sparta_assert( - extended_status_state_ == Inst::Status::UNMOD - || extended_status_state_ == Inst::Status::FUSED - || extended_status_state_ == Inst::Status::FUSION_GHOST, - "Attempt to set unknown extended status : " - << status << " " << *this); + sparta_assert(extended_status_state_ == Inst::Status::UNMOD + || extended_status_state_ == Inst::Status::FUSED + || extended_status_state_ == Inst::Status::FUSION_GHOST, + "Attempt to set unknown extended status : " << status << " " << *this); extended_status_state_ = status; } - InstArchInfo::TargetPipe getPipe() const - { - return inst_arch_info_->getTargetPipe(); } + InstArchInfo::TargetPipe getPipe() const { return inst_arch_info_->getTargetPipe(); } // ROB handling -- mark this instruction as the oldest in the machine void setOldest(bool oldest, sparta::Scheduleable* rob_retire_event) @@ -200,6 +205,25 @@ namespace olympia uint64_t getUniqueID() const { return unique_id_; } + // Set the instruction's UOp ID. This ID is incremented based + // off of number of Uops. The UOp instructions will all have the same + // UID, but different UOp IDs. + void setUOpID(uint64_t uopid) { uopid_ = uopid; } + + // Set the instruction's UOp ID. This ID is incremented based + // off of number of Uops. The UOp instructions will all have the same + // UID, but different UOp IDs. + uint64_t getUOpID() const { return uopid_.isValid() ? uopid_.getValue() : 0; } + + bool hasUOps() const { return uopid_.isValid() && uopid_.getValue() == 0; } + + // UOpIDs start at 1, because we use 0 as default UOpID on initialization + bool isUOp() const { return uopid_.isValid() && uopid_ > 0; } + + void setBlockingVSET(bool is_blocking_vset) { is_blocking_vset_ = is_blocking_vset; } + + bool isBlockingVSET() const { return is_blocking_vset_; } + // Set the instruction's Program ID. This ID is specific to // an instruction's retire pointer. The same instruction in a // trace will have the same program ID (as compared to @@ -208,19 +232,13 @@ namespace olympia uint64_t getProgramID() const { return program_id_; } - //A fused operation will modify the program_id_increment_ based on - //the number of instructions fused. A-B-C-D -> fA incr becomes 4 - //This is planned, but not currently used. - void setProgramIDIncrement(uint64_t incr) - { - program_id_increment_ = incr; - } + // A fused operation will modify the program_id_increment_ based on + // the number of instructions fused. A-B-C-D -> fA incr becomes 4 + // This is planned, but not currently used. + void setProgramIDIncrement(uint64_t incr) { program_id_increment_ = incr; } - //This is planned, but not currently used. - uint64_t getProgramIDIncrement() const - { - return program_id_increment_; - } + // This is planned, but not currently used. + uint64_t getProgramIDIncrement() const { return program_id_increment_; } // Set the instruction's PC void setPC(sparta::memory::addr_t inst_pc) { inst_pc_ = inst_pc; } @@ -229,13 +247,55 @@ namespace olympia // Set the instruction's target PC (branch target or load/store target) void setTargetVAddr(sparta::memory::addr_t target_vaddr) { target_vaddr_ = target_vaddr; } - sparta::memory::addr_t getTargetVAddr() const { return target_vaddr_; } + void setVCSRs(const VCSRs * input_VCSRs) + { + VCSRs_ = *input_VCSRs; + } + + const VCSRs * getVCSRs() const { return &VCSRs_; } + + // Set lmul from vset (vsetivli, vsetvli) + void setLMUL(uint32_t lmul) + { + VCSRs_.lmul = lmul; + VCSRs_.vlmax = VCSRs_.vlmax_formula(); + } + + // Set sew from vset (vsetivli, vsetvli) + void setSEW(uint32_t sew) + { + VCSRs_.sew = sew; + VCSRs_.vlmax = VCSRs_.vlmax_formula(); + } + + // Set VL from vset (vsetivli, vsetvli) + void setVL(uint32_t vl) { VCSRs_.vl = vl; } + + // Set VTA (vector tail agnostic) + // vta = true means agnostic, set destination values to 1's or maintain original + // vta = false means undisturbed, maintain original destination values + void setVTA(bool vta) { VCSRs_.vta = vta; } + + uint32_t getSEW() const { return VCSRs_.sew; } + uint32_t getLMUL() const { return VCSRs_.lmul; } + uint32_t getVL() const { return VCSRs_.vl; } + uint32_t getVTA() const { return VCSRs_.vta; } + uint32_t getVLMAX() const { return VCSRs_.vlmax; } + + void setTail(bool has_tail) { has_tail_ = has_tail; } + bool hasTail() const { return has_tail_; } + + void setUOpParent(sparta::SpartaWeakPointer & parent_uop) + { + parent_uop_ = parent_uop; + } + sparta::SpartaWeakPointer getUOpParent() { return parent_uop_; } + // Branch instruction was taken (always set for JAL/JALR) void setTakenBranch(bool taken) { is_taken_branch_ = taken; } - // TBD -- add branch prediction void setSpeculative(bool spec) { is_speculative_ = spec; } @@ -247,7 +307,9 @@ namespace olympia uint32_t getOpCode() const { return static_cast(opcode_info_->getOpcode()); } mavis::InstructionUniqueID getMavisUid() const - { return opcode_info_->getInstructionUniqueID(); } + { + return opcode_info_->getInstructionUniqueID(); + } // Operand information using OpInfoList = mavis::DecodedInstructionInfo::OpInfoList; @@ -257,8 +319,28 @@ namespace olympia return opcode_info_->getSourceOpInfoList(); } + uint64_t getImmediate() const { return opcode_info_->getImmediate(); } + const OpInfoList & getDestOpInfoList() const { return opcode_info_->getDestOpInfoList(); } + bool hasZeroRegSource() const + { + return std::any_of(getSourceOpInfoList().begin(), getSourceOpInfoList().end(), + [](const mavis::OperandInfo::Element & elem) + { + return elem.field_value == 0; + }); + } + + bool hasZeroRegDest() const + { + return std::any_of(getDestOpInfoList().begin(), getDestOpInfoList().end(), + [](const mavis::OperandInfo::Element & elem) + { + return elem.field_value == 0; + }); + } + // Static instruction information bool isStoreInst() const { return is_store_; } @@ -266,6 +348,8 @@ namespace olympia uint32_t getExecuteTime() const { return inst_arch_info_->getExecutionTime(); } + InstArchInfo::UopGenType getUopGenType() const { return inst_arch_info_->getUopGenType(); } + uint64_t getRAdr() const { return target_vaddr_ | 0x8000000; } // faked bool isSpeculative() const { return is_speculative_; } @@ -284,6 +368,10 @@ namespace olympia bool isReturn() const { return is_return_; } + bool isVset() const { return inst_arch_info_->isVset(); } + + bool isVector() const { return is_vector_; } + // Rename information core_types::RegisterBitMask & getSrcRegisterBitMask(const core_types::RegFile rf) { @@ -322,38 +410,40 @@ namespace olympia const RenameData & getRenameData() const { return rename_data; } + mavis::OpcodeInfo::PtrType getOpCodeInfo() { return opcode_info_; } + // Duplicates stream operator but does not change EXPECT logs std::string info() { std::string rStatus = "DONTCARE"; std::string eStatus = "UNKNOWN"; - if(getExtendedStatus() == Inst::Status::UNMOD) { - eStatus = "UNMOD"; - } else if(getExtendedStatus() == Inst::Status::FUSED) { - eStatus = "FUSED"; - } else if(getExtendedStatus() == Inst::Status::FUSION_GHOST) { - eStatus = "GHOST"; + if (getExtendedStatus() == Inst::Status::UNMOD) + { + eStatus = "UNMOD"; } - + else if (getExtendedStatus() == Inst::Status::FUSED) + { + eStatus = "FUSED"; + } + else if (getExtendedStatus() == Inst::Status::FUSION_GHOST) + { + eStatus = "GHOST"; + } + std::stringstream ss; - ss << "uid: " << std::dec //<< std::hex << std::setfill('0') - << getUniqueID() - << " pid: " << std::dec //<< std::hex << std::setfill('0') - << getProgramID() - << " mav: 0x" << std::hex << std::setw(2) << std::setfill('0') - << getMavisUid() - << " inc: " << std::dec - << getProgramIDIncrement() - << " pc: 0x" << std::hex << std::setw(8) << std::setfill('0') - << getPC() - << " " << std::setw(10) << std::setfill(' ') << rStatus - << " " << std::setw(12) << std::setfill(' ') << eStatus - << " '" << getDisasm() << "'"; + ss << "uid: " << std::dec //<< std::hex << std::setfill('0') + << getUniqueID() << " pid: " << std::dec //<< std::hex << std::setfill('0') + << getProgramID() << " mav: 0x" << std::hex << std::setw(2) << std::setfill('0') + << getMavisUid() << " inc: " << std::dec << getProgramIDIncrement() << " pc: 0x" + << std::hex << std::setw(8) << std::setfill('0') << getPC() << " " << std::setw(10) + << std::setfill(' ') << rStatus << " " << std::setw(12) << std::setfill(' ') + << eStatus << " '" << getDisasm() << "'"; return ss.str(); } + private: mavis::OpcodeInfo::PtrType opcode_info_; InstArchInfo::PtrType inst_arch_info_; @@ -362,8 +452,9 @@ namespace olympia sparta::memory::addr_t target_vaddr_ = 0; // Instruction's Target PC (for branches, loads/stores) bool is_oldest_ = false; - uint64_t unique_id_ = 0; // Supplied by Fetch - uint64_t program_id_ = 0; // Supplied by a trace Reader or execution backend + uint64_t unique_id_ = 0; // Supplied by Fetch + uint64_t program_id_ = 0; // Supplied by a trace Reader or execution backend + sparta::utils::ValidValue uopid_; // Set in decode uint64_t program_id_increment_ = 1; bool is_speculative_ = false; // Is this instruction soon to be flushed? const bool is_store_; @@ -372,8 +463,18 @@ namespace olympia const bool is_condbranch_; const bool is_call_; const bool is_csr_; + const bool is_vector_; const bool is_return_; + VCSRs VCSRs_; + bool has_tail_ = false; // Does this vector uop have a tail? + + // blocking vset is a vset that needs to read a value from a register value. A blocking vset + // can't be resolved until after execution, so we need to block on it due to UOp fracturing + bool is_blocking_vset_ = false; + + sparta::SpartaWeakPointer parent_uop_; + // Did this instruction mispredict? bool is_mispredicted_ = false; bool is_taken_branch_ = false; @@ -392,7 +493,7 @@ namespace olympia RegisterBitMaskArray dest_reg_bit_masks_; RegisterBitMaskArray store_data_mask_; RenameData rename_data; - static const std::unordered_map status2String; + static const std::unordered_map status2String; }; using InstPtr = Inst::PtrType; @@ -426,15 +527,15 @@ namespace olympia case Inst::Status::FLUSHED: os << "FLUSHED"; break; - //Used in extended_status_state as default case + // Used in extended_status_state as default case case Inst::Status::UNMOD: os << "UNMOD"; break; - //The new opcode/instruction as a result of fusion + // The new opcode/instruction as a result of fusion case Inst::Status::FUSED: os << "FUSED"; break; - //The opcodes/instruction no longer present due to fusion + // The opcodes/instruction no longer present due to fusion case Inst::Status::FUSION_GHOST: os << "FUSION_GHOST"; break; @@ -444,21 +545,24 @@ namespace olympia return os; } - // Expect log info system uses simple diff + // Expect log info system uses simple diff // - any changes here will break EXPECT inline std::ostream & operator<<(std::ostream & os, const Inst & inst) { os << "uid: " << inst.getUniqueID() << " " << std::setw(10) << inst.getStatus() << " " - << std::hex << inst.getPC() << std::dec << " pid: " << inst.getProgramID() << " '" - << inst.getDisasm() << "' "; + << std::hex << inst.getPC() << std::dec << " pid: " << inst.getProgramID() + << " uopid: " << inst.getUOpID() << " '" << inst.getDisasm() << "' "; return os; } inline std::ostream & operator<<(std::ostream & os, const InstPtr & inst) { - if(inst) { + if (inst) + { os << *inst; - } else { + } + else + { os << "nullptr"; } return os; diff --git a/core/InstArchInfo.cpp b/core/InstArchInfo.cpp index 8ceb3d9a..95b5e7b1 100644 --- a/core/InstArchInfo.cpp +++ b/core/InstArchInfo.cpp @@ -6,12 +6,53 @@ namespace olympia { const InstArchInfo::TargetPipeMap InstArchInfo::execution_pipe_map = { - {"br", InstArchInfo::TargetPipe::BR}, {"cmov", InstArchInfo::TargetPipe::CMOV}, - {"div", InstArchInfo::TargetPipe::DIV}, {"faddsub", InstArchInfo::TargetPipe::FADDSUB}, - {"float", InstArchInfo::TargetPipe::FLOAT}, {"fmac", InstArchInfo::TargetPipe::FMAC}, - {"i2f", InstArchInfo::TargetPipe::I2F}, {"f2i", InstArchInfo::TargetPipe::F2I}, - {"int", InstArchInfo::TargetPipe::INT}, {"lsu", InstArchInfo::TargetPipe::LSU}, - {"mul", InstArchInfo::TargetPipe::MUL}, {"sys", InstArchInfo::TargetPipe::SYS}}; + {"br", InstArchInfo::TargetPipe::BR}, + {"cmov", InstArchInfo::TargetPipe::CMOV}, + {"div", InstArchInfo::TargetPipe::DIV}, + {"faddsub", InstArchInfo::TargetPipe::FADDSUB}, + {"float", InstArchInfo::TargetPipe::FLOAT}, + {"fmac", InstArchInfo::TargetPipe::FMAC}, + {"i2f", InstArchInfo::TargetPipe::I2F}, + {"f2i", InstArchInfo::TargetPipe::F2I}, + {"int", InstArchInfo::TargetPipe::INT}, + {"lsu", InstArchInfo::TargetPipe::LSU}, + {"mul", InstArchInfo::TargetPipe::MUL}, + {"vint", InstArchInfo::TargetPipe::VINT}, + {"vmask", InstArchInfo::TargetPipe::VMASK}, + {"vset", InstArchInfo::TargetPipe::VSET}, + {"vmul", InstArchInfo::TargetPipe::VMUL}, + {"vdiv", InstArchInfo::TargetPipe::VDIV}, + {"sys", InstArchInfo::TargetPipe::SYS}, + {"?", InstArchInfo::TargetPipe::UNKNOWN} + }; + + const InstArchInfo::TargetPipeStringMap InstArchInfo::execution_pipe_string_map = { + {InstArchInfo::TargetPipe::BR, "BR"}, + {InstArchInfo::TargetPipe::CMOV, "CMOV"}, + {InstArchInfo::TargetPipe::DIV, "DIV"}, + {InstArchInfo::TargetPipe::FADDSUB, "FADDSUB"}, + {InstArchInfo::TargetPipe::FLOAT, "FLOAT"}, + {InstArchInfo::TargetPipe::FMAC, "FMAC"}, + {InstArchInfo::TargetPipe::I2F, "I2F"}, + {InstArchInfo::TargetPipe::F2I, "F2I"}, + {InstArchInfo::TargetPipe::INT, "INT"}, + {InstArchInfo::TargetPipe::LSU, "LSU"}, + {InstArchInfo::TargetPipe::MUL, "MUL"}, + {InstArchInfo::TargetPipe::VINT, "VINT"}, + {InstArchInfo::TargetPipe::VMASK, "VMASK"}, + {InstArchInfo::TargetPipe::VSET, "VSET"}, + {InstArchInfo::TargetPipe::VMUL, "VMUL"}, + {InstArchInfo::TargetPipe::VDIV, "VDIV"}, + {InstArchInfo::TargetPipe::SYS, "SYS"}, + {InstArchInfo::TargetPipe::UNKNOWN, "?"} + }; + + const InstArchInfo::UopGenMap InstArchInfo::uop_gen_type_map = { + {"ARITH", InstArchInfo::UopGenType::ARITH}, + {"ARITH_SINGLE_DEST", InstArchInfo::UopGenType::ARITH_SINGLE_DEST}, + {"ARITH_WIDE_DEST", InstArchInfo::UopGenType::ARITH_WIDE_DEST}, + {"NONE", InstArchInfo::UopGenType::NONE} + }; void InstArchInfo::update(const nlohmann::json & jobj) { @@ -24,17 +65,24 @@ namespace olympia << jobj["mnemonic"].get()); tgt_pipe_ = itr->second; } - sparta_assert(tgt_pipe_ != TargetPipe::UNKNOWN, "Unknown target pipe (execution) for " - << jobj["mnemonic"].get()); if (jobj.find("latency") != jobj.end()) { execute_time_ = jobj["latency"].get(); } - sparta_assert(execute_time_ != 0, "Unknown execution time (latency) for " - << jobj["mnemonic"].get()); + + if (jobj.find("uop_gen") != jobj.end()) + { + auto uop_gen_name = jobj["uop_gen"].get(); + const auto itr = uop_gen_type_map.find(uop_gen_name); + sparta_assert(itr != uop_gen_type_map.end(), + "Unknown uop gen: " << uop_gen_name << " for inst: " + << jobj["mnemonic"].get()); + uop_gen_ = itr->second; + } is_load_store_ = (tgt_pipe_ == TargetPipe::LSU); + is_vset_ = {tgt_pipe_ == TargetPipe::VSET}; } } // namespace olympia diff --git a/core/InstArchInfo.hpp b/core/InstArchInfo.hpp index 7f2b57ed..bbf7f8fc 100644 --- a/core/InstArchInfo.hpp +++ b/core/InstArchInfo.hpp @@ -35,7 +35,7 @@ namespace olympia public: using PtrType = sparta::SpartaSharedPointer; - enum TargetPipe : std::uint16_t + enum TargetPipe : uint16_t { BR, CMOV, @@ -48,6 +48,11 @@ namespace olympia INT, LSU, MUL, + VINT, + VMASK, + VMUL, + VDIV, + VSET, SYS, UNKNOWN }; @@ -57,6 +62,23 @@ namespace olympia using TargetPipeMap = std::map; static const TargetPipeMap execution_pipe_map; + using TargetPipeStringMap = std::map; + static const TargetPipeStringMap execution_pipe_string_map; + + enum class UopGenType + { + ARITH, + ARITH_SINGLE_DEST, + ARITH_WIDE_DEST, + NONE, + UNKNOWN + }; + + static constexpr uint32_t N_UOP_GEN_TYPES = static_cast(UopGenType::NONE); + + using UopGenMap = std::map; + static const UopGenMap uop_gen_type_map; + // Called by Mavis during its initialization explicit InstArchInfo(const nlohmann::json & jobj) { update(jobj); } @@ -70,57 +92,31 @@ namespace olympia //! Return the execution time (latency) of the instruction uint32_t getExecutionTime() const { return execute_time_; } + //! Return the vector uop generator type + UopGenType getUopGenType() const { return uop_gen_; } + //! Is this instruction a load/store type? bool isLoadStore() const { return is_load_store_; } + //! Is this instruction a vset instruction type + bool isVset() const { return is_vset_; } + private: TargetPipe tgt_pipe_ = TargetPipe::UNKNOWN; uint32_t execute_time_ = 0; + UopGenType uop_gen_ = UopGenType::UNKNOWN; bool is_load_store_ = false; + bool is_vset_ = false; }; inline std::ostream & operator<<(std::ostream & os, const InstArchInfo::TargetPipe & pipe) { - switch (pipe) + if (pipe != InstArchInfo::TargetPipe::UNKNOWN) + { + os << InstArchInfo::execution_pipe_string_map.at(pipe); + } + else { - case InstArchInfo::TargetPipe::BR: - os << "BR"; - break; - case InstArchInfo::TargetPipe::CMOV: - os << "CMOV"; - break; - case InstArchInfo::TargetPipe::DIV: - os << "DIV"; - break; - case InstArchInfo::TargetPipe::FADDSUB: - os << "FADDSUB"; - break; - case InstArchInfo::TargetPipe::FLOAT: - os << "FLOAT"; - break; - case InstArchInfo::TargetPipe::FMAC: - os << "FMAC"; - break; - case InstArchInfo::TargetPipe::I2F: - os << "I2F"; - break; - case InstArchInfo::TargetPipe::F2I: - os << "F2I"; - break; - case InstArchInfo::TargetPipe::INT: - os << "INT"; - break; - case InstArchInfo::TargetPipe::LSU: - os << "LSU"; - break; - case InstArchInfo::TargetPipe::MUL: - os << "MUL"; - break; - case InstArchInfo::TargetPipe::SYS: - os << "SYS"; - break; - - case InstArchInfo::TargetPipe::UNKNOWN: throw sparta::SpartaException("Got UNKNOWN/NONE target pipe."); } return os; diff --git a/core/InstGenerator.cpp b/core/InstGenerator.cpp index c68c9e15..7c01d09c 100644 --- a/core/InstGenerator.cpp +++ b/core/InstGenerator.cpp @@ -1,45 +1,52 @@ #include "InstGenerator.hpp" -#include "json.hpp" // From Mavis +#include "json.hpp" // From Mavis #include "mavis/Mavis.h" namespace olympia { - std::unique_ptr InstGenerator::createGenerator(MavisType * mavis_facade, + std::unique_ptr InstGenerator::createGenerator(MavisType* mavis_facade, const std::string & filename, const bool skip_nonuser_mode) { const std::string json_ext = "json"; - if((filename.size() > json_ext.size()) && filename.substr(filename.size()-json_ext.size()) == json_ext) { + if ((filename.size() > json_ext.size()) + && filename.substr(filename.size() - json_ext.size()) == json_ext) + { std::cout << "olympia: JSON file input detected" << std::endl; return std::unique_ptr(new JSONInstGenerator(mavis_facade, filename)); } - const std::string stf_ext = "stf"; // Should cover both zstf and stf - if((filename.size() > stf_ext.size()) && filename.substr(filename.size()-stf_ext.size()) == stf_ext) { + const std::string stf_ext = "stf"; // Should cover both zstf and stf + if ((filename.size() > stf_ext.size()) + && filename.substr(filename.size() - stf_ext.size()) == stf_ext) + { std::cout << "olympia: STF file input detected" << std::endl; - return std::unique_ptr(new TraceInstGenerator(mavis_facade, filename, skip_nonuser_mode)); + return std::unique_ptr( + new TraceInstGenerator(mavis_facade, filename, skip_nonuser_mode)); } // Dunno what it is... sparta_assert(false, "Unknown file extension for '" << filename - << "'. Expected .json or .[z]stf"); + << "'. Expected .json or .[z]stf"); return nullptr; } //////////////////////////////////////////////////////////////////////////////// // JSON Inst Generator - JSONInstGenerator::JSONInstGenerator(MavisType * mavis_facade, - const std::string & filename) : + JSONInstGenerator::JSONInstGenerator(MavisType* mavis_facade, const std::string & filename) : InstGenerator(mavis_facade) { std::ifstream fs; std::ios_base::iostate exceptionMask = fs.exceptions() | std::ios::failbit; fs.exceptions(exceptionMask); - try { + try + { fs.open(filename); - } catch (const std::ifstream::failure &e) { + } + catch (const std::ifstream::failure & e) + { throw sparta::SpartaException("ERROR: Issues opening ") << filename << ": " << e.what(); } @@ -48,9 +55,7 @@ namespace olympia n_insts_ = jobj_->size(); } - bool JSONInstGenerator::isDone() const { - return (curr_inst_index_ >= n_insts_); - } + bool JSONInstGenerator::isDone() const { return (curr_inst_index_ >= n_insts_); } void JSONInstGenerator::reset(const InstPtr & inst_ptr, const bool skip = false) { @@ -63,58 +68,97 @@ namespace olympia } } - InstPtr JSONInstGenerator::getNextInst(const sparta::Clock * clk) + InstPtr JSONInstGenerator::getNextInst(const sparta::Clock* clk) { - if(SPARTA_EXPECT_FALSE(isDone())) { + if (SPARTA_EXPECT_FALSE(isDone())) + { return nullptr; } // Get the JSON record at the current index nlohmann::json jinst = jobj_->at(curr_inst_index_); - if (jinst.find("mnemonic") == jinst.end()) { + if (jinst.find("mnemonic") == jinst.end()) + { throw sparta::SpartaException() << "Missing mnemonic at " << curr_inst_index_; } const std::string mnemonic = jinst["mnemonic"]; - auto addElement = [&jinst] (mavis::OperandInfo & operands, - const std::string & key, - const mavis::InstMetaData::OperandFieldID operand_field_id, - const mavis::InstMetaData::OperandTypes operand_type) { - if(jinst.find(key) != jinst.end()) { - operands.addElement(operand_field_id, - operand_type, - jinst[key].get()); - } - }; + auto addElement = [&jinst](mavis::OperandInfo & operands, const std::string & key, + const mavis::InstMetaData::OperandFieldID operand_field_id, + const mavis::InstMetaData::OperandTypes operand_type) + { + if (jinst.find(key) != jinst.end()) + { + operands.addElement(operand_field_id, operand_type, jinst[key].get()); + } + }; mavis::OperandInfo srcs; - addElement(srcs, "rs1", mavis::InstMetaData::OperandFieldID::RS1, mavis::InstMetaData::OperandTypes::LONG); - addElement(srcs, "fs1", mavis::InstMetaData::OperandFieldID::RS1, mavis::InstMetaData::OperandTypes::DOUBLE); - addElement(srcs, "rs2", mavis::InstMetaData::OperandFieldID::RS2, mavis::InstMetaData::OperandTypes::LONG); - addElement(srcs, "fs2", mavis::InstMetaData::OperandFieldID::RS2, mavis::InstMetaData::OperandTypes::DOUBLE); + addElement(srcs, "rs1", mavis::InstMetaData::OperandFieldID::RS1, + mavis::InstMetaData::OperandTypes::LONG); + addElement(srcs, "fs1", mavis::InstMetaData::OperandFieldID::RS1, + mavis::InstMetaData::OperandTypes::DOUBLE); + addElement(srcs, "rs2", mavis::InstMetaData::OperandFieldID::RS2, + mavis::InstMetaData::OperandTypes::LONG); + addElement(srcs, "fs2", mavis::InstMetaData::OperandFieldID::RS2, + mavis::InstMetaData::OperandTypes::DOUBLE); + addElement(srcs, "vs1", mavis::InstMetaData::OperandFieldID::RS1, + mavis::InstMetaData::OperandTypes::VECTOR); + addElement(srcs, "vs2", mavis::InstMetaData::OperandFieldID::RS2, + mavis::InstMetaData::OperandTypes::VECTOR); mavis::OperandInfo dests; - addElement(dests, "rd", mavis::InstMetaData::OperandFieldID::RD, mavis::InstMetaData::OperandTypes::LONG); - addElement(dests, "fd", mavis::InstMetaData::OperandFieldID::RD, mavis::InstMetaData::OperandTypes::DOUBLE); + addElement(dests, "rd", mavis::InstMetaData::OperandFieldID::RD, + mavis::InstMetaData::OperandTypes::LONG); + addElement(dests, "fd", mavis::InstMetaData::OperandFieldID::RD, + mavis::InstMetaData::OperandTypes::DOUBLE); + addElement(dests, "vd", mavis::InstMetaData::OperandFieldID::RD, + mavis::InstMetaData::OperandTypes::VECTOR); InstPtr inst; - if(jinst.find("imm") != jinst.end()) { + if (jinst.find("imm") != jinst.end()) + { const uint64_t imm = jinst["imm"].get(); mavis::ExtractorDirectOpInfoList ex_info(mnemonic, srcs, dests, imm); inst = mavis_facade_->makeInstDirectly(ex_info, clk); } - else { + else + { mavis::ExtractorDirectOpInfoList ex_info(mnemonic, srcs, dests); inst = mavis_facade_->makeInstDirectly(ex_info, clk); } - if (jinst.find("vaddr") != jinst.end()) { + if (jinst.find("vaddr") != jinst.end()) + { uint64_t vaddr = std::strtoull(jinst["vaddr"].get().c_str(), nullptr, 0); inst->setTargetVAddr(vaddr); } + if (jinst.find("vtype") != jinst.end()) + { + // immediate, so decode from hex + uint64_t vtype = std::strtoull(jinst["vtype"].get().c_str(), nullptr, 0); + std::string binaryString = std::bitset<32>(vtype).to_string(); + uint32_t sew = std::pow(2, std::stoi(binaryString.substr(26, 3), nullptr, 2)) * 8; + uint32_t lmul = std::pow(2, std::stoi(binaryString.substr(29, 3), nullptr, 2)); + inst->setLMUL(lmul); + inst->setSEW(sew); + } - if (jinst.find("taken") != jinst.end()) { + if (jinst.find("vta") != jinst.end()) + { + const bool vta = jinst["vta"].get() > 0 ? true: false; + inst->setVTA(vta); + } + + if (jinst.find("vl") != jinst.end()) + { + const uint64_t vl = jinst["vl"].get(); + inst->setVL(vl); + } + + if (jinst.find("taken") != jinst.end()) + { const bool taken = jinst["taken"].get(); inst->setTakenBranch(taken); } @@ -124,13 +168,11 @@ namespace olympia inst->setProgramID(program_id_++); ++curr_inst_index_; return inst; - } //////////////////////////////////////////////////////////////////////////////// // STF Inst Generator - TraceInstGenerator::TraceInstGenerator(MavisType * mavis_facade, - const std::string & filename, + TraceInstGenerator::TraceInstGenerator(MavisType* mavis_facade, const std::string & filename, const bool skip_nonuser_mode) : InstGenerator(mavis_facade) { @@ -138,9 +180,12 @@ namespace olympia std::ios_base::iostate exceptionMask = fs.exceptions() | std::ios::failbit; fs.exceptions(exceptionMask); - try { + try + { fs.open(filename); - } catch (const std::ifstream::failure &e) { + } + catch (const std::ifstream::failure & e) + { throw sparta::SpartaException("ERROR: Issues opening ") << filename << ": " << e.what(); } @@ -151,19 +196,14 @@ namespace olympia // value. Required for traces that stay in machine mode the entire // time constexpr bool FILTER_MODE_CHANGE_EVENTS = true; - constexpr size_t BUFFER_SIZE = 4096; - reader_.reset(new stf::STFInstReader(filename, - skip_nonuser_mode, - CHECK_FOR_STF_PTE, - FILTER_MODE_CHANGE_EVENTS, - BUFFER_SIZE)); + constexpr size_t BUFFER_SIZE = 4096; + reader_.reset(new stf::STFInstReader(filename, skip_nonuser_mode, CHECK_FOR_STF_PTE, + FILTER_MODE_CHANGE_EVENTS, BUFFER_SIZE)); next_it_ = reader_->begin(); } - bool TraceInstGenerator::isDone() const { - return next_it_ == reader_->end(); - } + bool TraceInstGenerator::isDone() const { return next_it_ == reader_->end(); } void TraceInstGenerator::reset(const InstPtr & inst_ptr, const bool skip = false) { @@ -176,32 +216,32 @@ namespace olympia } } - InstPtr TraceInstGenerator::getNextInst(const sparta::Clock * clk) + InstPtr TraceInstGenerator::getNextInst(const sparta::Clock* clk) { - if(SPARTA_EXPECT_FALSE(isDone())) { + if (SPARTA_EXPECT_FALSE(isDone())) + { return nullptr; } mavis::Opcode opcode = next_it_->opcode(); - try { + try + { InstPtr inst = mavis_facade_->makeInst(opcode, clk); inst->setPC(next_it_->pc()); inst->setUniqueID(++unique_id_); inst->setProgramID(program_id_++); inst->setRewindIterator(next_it_); - if (const auto& mem_accesses = next_it_->getMemoryAccesses(); !mem_accesses.empty()) + if (const auto & mem_accesses = next_it_->getMemoryAccesses(); !mem_accesses.empty()) { using VectorAddrType = std::vector; VectorAddrType addrs; std::for_each(next_it_->getMemoryAccesses().begin(), next_it_->getMemoryAccesses().end(), - [&addrs] (const auto & ma) { - addrs.emplace_back(ma.getAddress()); - }); + [&addrs](const auto & ma) { addrs.emplace_back(ma.getAddress()); }); inst->setTargetVAddr(addrs.front()); - //For misaligns, more than 1 address is provided - //inst->setVAddrVector(std::move(addrs)); + // For misaligns, more than 1 address is provided + // inst->setVAddrVector(std::move(addrs)); } if (next_it_->isBranch()) { @@ -211,15 +251,14 @@ namespace olympia ++next_it_; return inst; } - catch(std::exception & excpt) { - std::cerr << "ERROR: Mavis failed decoding: 0x" - << std::hex << opcode << " for STF It PC: 0x" - << next_it_->pc() << " STFID: " << std::dec - << next_it_->index() << " err: " - << excpt.what() << std::endl; + catch (std::exception & excpt) + { + std::cerr << "ERROR: Mavis failed decoding: 0x" << std::hex << opcode + << " for STF It PC: 0x" << next_it_->pc() << " STFID: " << std::dec + << next_it_->index() << " err: " << excpt.what() << std::endl; throw; } return nullptr; } -} +} // namespace olympia diff --git a/core/IssueQueue.cpp b/core/IssueQueue.cpp index cbc817ad..91345b2a 100644 --- a/core/IssueQueue.cpp +++ b/core/IssueQueue.cpp @@ -35,8 +35,7 @@ namespace olympia { cpu_node = getContainer()->getRoot(); } - std::vector reg_files = {core_types::RF_INTEGER, core_types::RF_FLOAT}; - for (const auto rf : reg_files) + for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) { scoreboard_views_[rf].reset(new sparta::ScoreboardView( getContainer()->getName(), core_types::regfile_names[rf], cpu_node)); @@ -98,33 +97,43 @@ namespace olympia void IssueQueue::handleOperandIssueCheck_(const InstPtr & ex_inst) { - // FIXME: Now every source operand should be ready - auto reg_file = core_types::RegFile::RF_INTEGER; const auto srcs = ex_inst->getRenameData().getSourceList(); - if (srcs.size() > 0) + uint32_t ready = 0; + for(const auto & src : srcs) { - reg_file = srcs[0].rf; + // vector-scalar operations have 1 vector src and 1 scalar src that + // need to be checked, so can't assume the register files are the + // same for every source + auto reg_file = src.rf; + const auto & src_bits = ex_inst->getSrcRegisterBitMask(reg_file); + if (scoreboard_views_[reg_file]->isSet(src_bits)) + { + ready++; + } + else + { + // temporary fix for clearCallbacks not working + scoreboard_views_[reg_file]->registerReadyCallback(src_bits, ex_inst->getUniqueID(), + [this, ex_inst](const sparta::Scoreboard::RegisterBitMask &) + { this->handleOperandIssueCheck_(ex_inst); }); + ILOG("Instruction NOT ready: " << ex_inst + << " Bits needed:" << sparta::printBitSet(src_bits) + << " rf: " << reg_file); + // we break to prevent multiple callbacks from being sent out + break; + } } - const auto & src_bits = ex_inst->getSrcRegisterBitMask(reg_file); - if (scoreboard_views_[reg_file]->isSet(src_bits)) + + // we wait till the final callback comes back and checks in the case where both RF are ready at the same time + if(ready == srcs.size()) { - // Insert at the end if we are doing in order issue or if the scheduler is - // empty + // all register file types are ready ILOG("Sending to issue queue " << ex_inst); // will insert based on if in_order_issue_ is set // if it is, will be first in first out, if not it'll be by age, so by UniqueID (UID) ready_queue_.insert(ex_inst); ev_issue_ready_inst_.schedule(sparta::Clock::Cycle(0)); } - else - { - scoreboard_views_[reg_file]->registerReadyCallback( - src_bits, ex_inst->getUniqueID(), - [this, ex_inst](const sparta::Scoreboard::RegisterBitMask &) - { this->handleOperandIssueCheck_(ex_inst); }); - ILOG("Instruction NOT ready: " << ex_inst - << " Bits needed:" << sparta::printBitSet(src_bits)); - } } void IssueQueue::readyExeUnit_(const uint32_t & readyExe) @@ -243,4 +252,4 @@ namespace olympia } sparta_assert(false, "Attempt to complete instruction no longer exiting in issue queue!"); } -} // namespace olympia \ No newline at end of file +} // namespace olympia diff --git a/core/LSU.cpp b/core/LSU.cpp index 31735c04..edc45eeb 100644 --- a/core/LSU.cpp +++ b/core/LSU.cpp @@ -150,14 +150,16 @@ namespace olympia void LSU::setupScoreboard_() { // Setup scoreboard view upon register file - std::vector reg_files = {core_types::RF_INTEGER, core_types::RF_FLOAT}; - // if we ever move to multicore, we only want to have resources look for scoreboard in their cpu - // if we're running a test where we only have top.rename or top.issue_queue, then we can just use the root + // if we ever move to multicore, we only want to have resources look for scoreboard in their + // cpu if we're running a test where we only have top.rename or top.issue_queue, then we can + // just use the root auto cpu_node = getContainer()->findAncestorByName("core.*"); - if(cpu_node == nullptr){ + if (cpu_node == nullptr) + { cpu_node = getContainer()->getRoot(); } - for (const auto rf : reg_files) + for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; + ++rf) // for (const auto rf : reg_files) { scoreboard_views_[rf].reset(new sparta::ScoreboardView( getContainer()->getName(), core_types::regfile_names[rf], cpu_node)); @@ -756,9 +758,8 @@ namespace olympia flushReadyQueue_(criteria); // Cancel replay events - auto flush = [&criteria](const LoadStoreInstInfoPtr & ldst_info_ptr) -> bool { - return criteria.includedInFlush(ldst_info_ptr->getInstPtr()); - }; + auto flush = [&criteria](const LoadStoreInstInfoPtr & ldst_info_ptr) -> bool + { return criteria.includedInFlush(ldst_info_ptr->getInstPtr()); }; uev_append_ready_.cancelIf(flush); uev_replay_ready_.cancelIf(flush); @@ -1175,9 +1176,8 @@ namespace olympia { const InstPtr & inst_ptr = mem_access_info_ptr->getInstPtr(); - sparta_assert( - inst_ptr->getFlushedStatus() == false, - "Attempt to rehandle cache lookup for flushed instruction!"); + sparta_assert(inst_ptr->getFlushedStatus() == false, + "Attempt to rehandle cache lookup for flushed instruction!"); const LoadStoreInstIterator & iter = mem_access_info_ptr->getIssueQueueIterator(); sparta_assert( @@ -1242,17 +1242,20 @@ namespace olympia uint32_t credits_to_send = 0; auto iter = ldst_inst_queue_.begin(); - while (iter != ldst_inst_queue_.end()) { + while (iter != ldst_inst_queue_.end()) + { auto inst_ptr = (*iter)->getInstPtr(); auto delete_iter = iter++; - if (criteria.includedInFlush(inst_ptr)) { + if (criteria.includedInFlush(inst_ptr)) + { ldst_inst_queue_.erase(delete_iter); // Clear any scoreboard callback - std::vector reg_files = {core_types::RF_INTEGER, core_types::RF_FLOAT}; - for(const auto rf : reg_files) + std::vector reg_files = {core_types::RF_INTEGER, + core_types::RF_FLOAT}; + for (const auto rf : reg_files) { scoreboard_views_[rf]->clearCallbacks(inst_ptr->getUniqueID()); } @@ -1278,18 +1281,21 @@ namespace olympia void LSU::flushLSPipeline_(const FlushCriteria & criteria) { uint32_t stage_id = 0; - for (auto iter = ldst_pipeline_.begin(); iter != ldst_pipeline_.end(); iter++, stage_id++) { + for (auto iter = ldst_pipeline_.begin(); iter != ldst_pipeline_.end(); iter++, stage_id++) + { // If the pipe stage is already invalid, no need to criteria - if (!iter.isValid()) { + if (!iter.isValid()) + { continue; } auto inst_ptr = (*iter)->getInstPtr(); - if (criteria.includedInFlush(inst_ptr)) { + if (criteria.includedInFlush(inst_ptr)) + { ldst_pipeline_.flushStage(iter); ILOG("Flush Pipeline Stage[" << stage_id - << "], Instruction ID: " << inst_ptr->getUniqueID()); + << "], Instruction ID: " << inst_ptr->getUniqueID()); } } } @@ -1297,12 +1303,14 @@ namespace olympia void LSU::flushReadyQueue_(const FlushCriteria & criteria) { auto iter = ready_queue_.begin(); - while (iter != ready_queue_.end()) { + while (iter != ready_queue_.end()) + { auto inst_ptr = (*iter)->getInstPtr(); auto delete_iter = iter++; - if (criteria.includedInFlush(inst_ptr)) { + if (criteria.includedInFlush(inst_ptr)) + { ready_queue_.erase(delete_iter); ILOG("Flushing from ready queue - Instruction ID: " << inst_ptr->getUniqueID()); } @@ -1312,12 +1320,14 @@ namespace olympia void LSU::flushReplayBuffer_(const FlushCriteria & criteria) { auto iter = replay_buffer_.begin(); - while (iter != replay_buffer_.end()) { + while (iter != replay_buffer_.end()) + { auto inst_ptr = (*iter)->getInstPtr(); auto delete_iter = iter++; - if (criteria.includedInFlush(inst_ptr)) { + if (criteria.includedInFlush(inst_ptr)) + { replay_buffer_.erase(delete_iter); ILOG("Flushing from replay buffer - Instruction ID: " << inst_ptr->getUniqueID()); } diff --git a/core/MavisUnit.cpp b/core/MavisUnit.cpp index 96b19288..90ef92e5 100644 --- a/core/MavisUnit.cpp +++ b/core/MavisUnit.cpp @@ -27,7 +27,9 @@ namespace olympia isa_file_path + "/isa_rv64zicsr.json", isa_file_path + "/isa_rv64c.json", isa_file_path + "/isa_rv64cf.json", - isa_file_path + "/isa_rv64cd.json"}; + isa_file_path + "/isa_rv64cd.json", + isa_file_path + "/isa_rv64v.json", + isa_file_path + "/isa_rv64vf.json"}; return isa_files; } @@ -36,7 +38,8 @@ namespace olympia { std::vector uarch_files = {uarch_file_path + "/olympia_uarch_rv64g.json", uarch_file_path + "/olympia_uarch_rv64c.json", - uarch_file_path + "/olympia_uarch_rv64b.json"}; + uarch_file_path + "/olympia_uarch_rv64b.json", + uarch_file_path + "/olympia_uarch_rv64v.json"}; if(false == std::string(p->uarch_overrides_json).empty()) { uarch_files.emplace_back(p->uarch_overrides_json); diff --git a/core/ROB.cpp b/core/ROB.cpp index e7a77438..a262b136 100644 --- a/core/ROB.cpp +++ b/core/ROB.cpp @@ -1,6 +1,5 @@ // -*- C++ -*- - #include #include "ROB.hpp" @@ -12,20 +11,17 @@ namespace olympia { const char ROB::name[] = "rob"; - ROB::ROB(sparta::TreeNode * node, - const ROBParameterSet * p) : + ROB::ROB(sparta::TreeNode* node, const ROBParameterSet* p) : sparta::Unit(node), - stat_ipc_(&unit_stat_set_, - "ipc", - "Instructions retired per cycle", - &unit_stat_set_, + stat_ipc_(&unit_stat_set_, "ipc", "Instructions retired per cycle", &unit_stat_set_, "total_number_retired/cycles"), - num_retired_(&unit_stat_set_, - "total_number_retired", + num_retired_(&unit_stat_set_, "total_number_retired", "The total number of instructions retired by this core", sparta::Counter::COUNT_NORMAL), - num_flushes_(&unit_stat_set_, - "total_number_of_flushes", + num_uops_retired_(&unit_stat_set_, "total_uops_retired", + "The total number of uops retired by this core", + sparta::Counter::COUNT_NORMAL), + num_flushes_(&unit_stat_set_, "total_number_of_flushes", "The total number of flushes performed by the ROB", sparta::Counter::COUNT_NORMAL), overall_ipc_si_(&stat_ipc_), @@ -34,8 +30,7 @@ namespace olympia num_to_retire_(p->num_to_retire), num_insts_to_retire_(p->num_insts_to_retire), retire_heartbeat_(p->retire_heartbeat), - reorder_buffer_("ReorderBuffer", p->retire_queue_depth, - node->getClock(), &unit_stat_set_) + reorder_buffer_("ReorderBuffer", p->retire_queue_depth, node->getClock(), &unit_stat_set_) { // Set a cycle delay on the retire, just for kicks ev_retire_.setDelay(1); @@ -43,30 +38,27 @@ namespace olympia // Set up the reorder buffer to support pipeline collection. reorder_buffer_.enableCollection(node); - in_reorder_buffer_write_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(ROB, robAppended_, InstGroup)); + in_reorder_buffer_write_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(ROB, robAppended_, InstGroup)); - in_reorder_flush_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(ROB, handleFlush_, - FlushManager::FlushingCriteria)); + in_reorder_flush_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(ROB, handleFlush_, FlushManager::FlushingCriteria)); // Do not allow this event to keep simulation alive ev_ensure_forward_progress_.setContinuing(false); // Notify other components when ROB stops the simulation rob_stopped_notif_source_.reset(new sparta::NotificationSource( - this->getContainer(), - "rob_stopped_notif_channel", - "ROB terminated simulation channel", - "rob_stopped_notif_channel" - )); + this->getContainer(), "rob_stopped_notif_channel", "ROB terminated simulation channel", + "rob_stopped_notif_channel")); // Send initial credits to anyone that cares. Probably Dispatch. sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(ROB, sendInitialCredits_)); } /// Destroy! - ROB::~ROB() { + ROB::~ROB() + { // Logging can be done from destructors in the correct simulator setup ILOG("ROB is destructing now, but you can still see this message"); } @@ -80,8 +72,10 @@ namespace olympia // An illustration of the use of the callback -- instead of // getting a reference, you can pull the data from the port // directly, albeit inefficient and superfluous here... - void ROB::robAppended_(const InstGroup &) { - for(auto & i : *in_reorder_buffer_write_.pullData()) { + void ROB::robAppended_(const InstGroup &) + { + for (auto & i : *in_reorder_buffer_write_.pullData()) + { reorder_buffer_.push(i); ILOG("retire appended: " << i); } @@ -119,7 +113,8 @@ namespace olympia void ROB::retireInstructions_() { // ROB is expecting a flush (back to itself) - if(expect_flush_) { + if (expect_flush_) + { return; } @@ -128,55 +123,64 @@ namespace olympia ILOG("num to retire: " << num_to_retire); uint32_t retired_this_cycle = 0; - for(uint32_t i = 0; i < num_to_retire; ++i) + for (uint32_t i = 0; i < num_to_retire; ++i) { auto ex_inst_ptr = reorder_buffer_.access(0); sparta_assert(nullptr != ex_inst_ptr); auto & ex_inst = *ex_inst_ptr; sparta_assert(ex_inst.isSpeculative() == false, "Uh, oh! A speculative instruction is being retired: " << ex_inst); - if(ex_inst.getStatus() == Inst::Status::COMPLETED) + + if (ex_inst.getStatus() == Inst::Status::COMPLETED) { // UPDATE: ex_inst.setStatus(Inst::Status::RETIRED); - if (ex_inst.isStoreInst()) { + if (ex_inst.isStoreInst()) + { out_rob_retire_ack_.send(ex_inst_ptr); } // sending retired instruction to rename out_rob_retire_ack_rename_.send(ex_inst_ptr); - ++num_retired_; - ++retired_this_cycle; - reorder_buffer_.pop(); + // All instructions count as 1 uop + ++num_uops_retired_; + if (ex_inst_ptr->getUOpID() == 0) + { + ++num_retired_; + ++retired_this_cycle; + + // Use the program ID to verify that the program order has been maintained. + sparta_assert(ex_inst.getProgramID() == expected_program_id_, + "\nUnexpected program ID when retiring instruction" << + "\n(suggests wrong program order)" << + "\n expected: " << expected_program_id_ << + "\n received: " << ex_inst.getProgramID() << + "\n UID: " << ex_inst_ptr->getMavisUid() << + "\n incr: " << ex_inst_ptr->getProgramIDIncrement() << + "\n inst " << ex_inst); + + // The fused op records the number of insts that + // were eliminated and adjusts the progID as needed + expected_program_id_ += ex_inst.getProgramIDIncrement(); + } + reorder_buffer_.pop(); ILOG("retiring " << ex_inst); retire_event_.collect(*ex_inst_ptr); + last_inst_retired_ = ex_inst_ptr; - // Use the program ID to verify that the program order has been maintained. - sparta_assert(ex_inst.getProgramID() == expected_program_id_, - "\nUnexpected program ID when retiring instruction" - << "\n(suggests wrong program order)" - << "\n expected: " << expected_program_id_ - << "\n received: " << ex_inst.getProgramID() - << "\n UID: " << ex_inst_ptr->getMavisUid() - << "\n incr: " << ex_inst_ptr->getProgramIDIncrement() - << "\n inst "<currentCycle() + if (SPARTA_EXPECT_FALSE((num_retired_ % retire_heartbeat_) == 0)) + { + std::cout << "olympia: Retired " << num_retired_.get() << " instructions in " + << getClock()->currentCycle() << " cycles. Period IPC: " << period_ipc_si_.getValue() - << " overall IPC: " << overall_ipc_si_.getValue() - << std::endl; + << " overall IPC: " << overall_ipc_si_.getValue() << std::endl; period_ipc_si_.start(); } // Will be true if the user provides a -i option - if (SPARTA_EXPECT_FALSE((num_retired_ == num_insts_to_retire_))) { + if (SPARTA_EXPECT_FALSE((num_retired_ == num_insts_to_retire_))) + { rob_stopped_simulation_ = true; rob_stopped_notif_source_->postNotification(true); getScheduler()->stopRunning(); @@ -184,47 +188,54 @@ namespace olympia } // Is this a misprdicted branch requiring a refetch? - if(ex_inst.isMispredicted()) { - FlushManager::FlushingCriteria criteria - (FlushManager::FlushCause::MISPREDICTION, ex_inst_ptr); + if (ex_inst.isMispredicted()) + { + FlushManager::FlushingCriteria criteria(FlushManager::FlushCause::MISPREDICTION, + ex_inst_ptr); out_retire_flush_.send(criteria); expect_flush_ = true; break; } // This is rare for the example - if(SPARTA_EXPECT_FALSE(ex_inst.getPipe() == InstArchInfo::TargetPipe::SYS)) + if (SPARTA_EXPECT_FALSE(ex_inst.getPipe() == InstArchInfo::TargetPipe::SYS)) { retireSysInst_(ex_inst_ptr); } } - else { + else + { break; } } - if(false == reorder_buffer_.empty()) { + if (false == reorder_buffer_.empty()) + { const auto & oldest_inst = reorder_buffer_.front(); - if(oldest_inst->getStatus() == Inst::Status::COMPLETED) { + if (oldest_inst->getStatus() == Inst::Status::COMPLETED) + { ILOG("oldest is marked completed: " << oldest_inst); ev_retire_.schedule(); } - else if(false == oldest_inst->isMarkedOldest()) { + else if (false == oldest_inst->isMarkedOldest()) + { ILOG("set oldest: " << oldest_inst); oldest_inst->setOldest(true, &ev_retire_); } } - if(retired_this_cycle != 0) { + if (retired_this_cycle != 0) + { out_reorder_buffer_credits_.send(retired_this_cycle); last_retirement_ = getClock()->currentCycle(); } } - void ROB::dumpDebugContent_(std::ostream& output) const + void ROB::dumpDebugContent_(std::ostream & output) const { output << "ROB Contents" << std::endl; - for(const auto & entry : reorder_buffer_) { + for (const auto & entry : reorder_buffer_) + { output << '\t' << entry << std::endl; } } @@ -232,19 +243,24 @@ namespace olympia // Make sure the pipeline is making forward progress void ROB::checkForwardProgress_() { - if(getClock()->currentCycle() - last_retirement_ >= retire_timeout_interval_) + if (getClock()->currentCycle() - last_retirement_ >= retire_timeout_interval_) { sparta::SpartaException e; - e << "Been a while since we've retired an instruction. Is the pipe stalled indefinitely?"; - e << " currentCycle: " << getClock()->currentCycle(); + e << "Been a while since we've retired an instruction. Is the pipe stalled " + "indefinitely?"; + e << " currentCycle: " << getClock()->currentCycle(); throw e; } ev_ensure_forward_progress_.schedule(retire_timeout_interval_); } - void ROB::onStartingTeardown_() { - if ((reorder_buffer_.size() > 0) && (false == rob_stopped_simulation_)) { - std::cerr << "WARNING! Simulation is ending, but the ROB didn't stop it. Lock up situation?" << std::endl; + void ROB::onStartingTeardown_() + { + if ((reorder_buffer_.size() > 0) && (false == rob_stopped_simulation_)) + { + std::cerr + << "WARNING! Simulation is ending, but the ROB didn't stop it. Lock up situation?" + << std::endl; dumpDebugContent_(std::cerr); } } @@ -271,4 +287,3 @@ namespace olympia } } - diff --git a/core/ROB.hpp b/core/ROB.hpp index fcb7895d..23ab29ec 100644 --- a/core/ROB.hpp +++ b/core/ROB.hpp @@ -72,11 +72,12 @@ namespace olympia private: // Stats and counters - sparta::StatisticDef stat_ipc_; // A simple expression to calculate IPC - sparta::Counter num_retired_; // Running counter of number instructions retired - sparta::Counter num_flushes_; // Number of flushes - sparta::StatisticInstance overall_ipc_si_; // An overall IPC statistic instance starting at time == 0 - sparta::StatisticInstance period_ipc_si_; // An IPC counter for the period between retirement heartbeats + sparta::StatisticDef stat_ipc_; // A simple expression to calculate IPC + sparta::Counter num_retired_; // Running counter of number of instructions retired + sparta::Counter num_uops_retired_; // Running counter of the number of uops retired + sparta::Counter num_flushes_; // Number of flushes + sparta::StatisticInstance overall_ipc_si_; // An overall IPC statistic instance starting at time == 0 + sparta::StatisticInstance period_ipc_si_; // An IPC counter for the period between retirement heartbeats // Parameter constants const sparta::Clock::Cycle retire_timeout_interval_; @@ -118,6 +119,9 @@ namespace olympia // For correlation activities sparta::pevents::PeventCollector retire_event_{"RETIRE", getContainer(), getClock()}; + // Last inst retired for testing + InstPtr last_inst_retired_ = nullptr; + // A nice checker to make sure forward progress is being made // Note that in the ROB constructor, this event is set as non-continuing sparta::Clock::Cycle last_retirement_ = 0; // Last retirement cycle for checking stalled retire @@ -136,5 +140,9 @@ namespace olympia void retireSysInst_(InstPtr & ); + // Friend class used in retire testing + friend class ROBTester; }; + + class ROBTester; } diff --git a/core/Rename.cpp b/core/Rename.cpp index 4dcc2c8d..897b1cbd 100644 --- a/core/Rename.cpp +++ b/core/Rename.cpp @@ -16,76 +16,84 @@ namespace olympia { const char Rename::name[] = "rename"; - Rename::Rename(sparta::TreeNode * node, - const RenameParameterSet * p) : + Rename::Rename(sparta::TreeNode* node, const RenameParameterSet* p) : sparta::Unit(node), - uop_queue_("rename_uop_queue", p->rename_queue_depth, - node->getClock(), getStatisticSet()), + uop_queue_("rename_uop_queue", p->rename_queue_depth, node->getClock(), getStatisticSet()), num_to_rename_per_cycle_(p->num_to_rename), rename_histogram_(*getStatisticSet(), "rename_histogram", "Rename Stage Histogram", - [&p]() { std::vector v(p->num_to_rename+1); std::iota(v.begin(), v.end(), 0); return v; }()) + [&p]() + { + std::vector v(p->num_to_rename + 1); + std::iota(v.begin(), v.end(), 0); + return v; + }()) { uop_queue_.enableCollection(node); // The path into the Rename block // - Instructions are received on the Uop Queue Append port // - Credits arrive on the dispatch queue credits port - in_uop_queue_append_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Rename, decodedInstructions_, InstGroupPtr)); - in_dispatch_queue_credits_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Rename, creditsDispatchQueue_, uint32_t)); - in_reorder_flush_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Rename, handleFlush_, FlushManager::FlushingCriteria)); - in_rename_retire_ack_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(Rename, getAckFromROB_, InstPtr)); + in_uop_queue_append_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Rename, decodedInstructions_, InstGroupPtr)); + in_dispatch_queue_credits_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Rename, creditsDispatchQueue_, uint32_t)); + in_reorder_flush_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Rename, handleFlush_, FlushManager::FlushingCriteria)); + in_rename_retire_ack_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Rename, getAckFromROB_, InstPtr)); sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(Rename, setupRename_)); - auto setup_map = [this] (core_types::RegFile reg_file, const uint32_t num_renames) { - const uint32_t num_regs = 32; // default risc-v ARF count - sparta_assert(num_regs < num_renames); // ensure we have more renames than 32 because first 32 renames are allocated at the beginning - // initialize the first 32 Float (31 for INT) regs, i.e x1 -> PRF1 - - // for x0 for RF_INTEGER, we don't want to set a PRF for it because x0 is hardwired to 0 - uint32_t i = 0; - if (reg_file == core_types::RegFile::RF_INTEGER){ - reference_counter_[reg_file].push_back(0); - freelist_[reg_file].push(0); - i = 1; - } - for(; i < num_regs; i++){ - map_table_[reg_file][i] = i; - // for the first 32 Float (31 INT) registers, we mark their reference_counters 1, as they are the - // current "valid" PRF for that ARF - reference_counter_[reg_file].push_back(1); - } - for(uint32_t j = num_regs; j < num_renames; ++j) { - freelist_[reg_file].push(j); - reference_counter_[reg_file].push_back(0); - } - }; + auto setup_map = [this](core_types::RegFile reg_file, const uint32_t num_renames) + { + const uint32_t num_regs = 32; // default risc-v ARF count + sparta_assert(num_regs + < num_renames); // ensure we have more renames than 32 because first 32 + // renames are allocated at the beginning + // initialize the first 32 Float (31 for INT) regs, i.e x1 -> PRF1 + + // for x0 for RF_INTEGER, we don't want to set a PRF for it because x0 is hardwired to 0 + uint32_t i = 0; + if (reg_file == core_types::RegFile::RF_INTEGER) + { + reference_counter_[reg_file].push_back(0); + freelist_[reg_file].push(0); + i = 1; + } + for (; i < num_regs; i++) + { + map_table_[reg_file][i] = i; + // for the first 32 Float (31 INT) registers, we mark their reference_counters 1, as + // they are the current "valid" PRF for that ARF + reference_counter_[reg_file].push_back(1); + } + for (uint32_t j = num_regs; j < num_renames; ++j) + { + freelist_[reg_file].push(j); + reference_counter_[reg_file].push_back(0); + } + }; setup_map(core_types::RegFile::RF_INTEGER, p->num_integer_renames); - setup_map(core_types::RegFile::RF_FLOAT, p->num_float_renames); + setup_map(core_types::RegFile::RF_FLOAT, p->num_float_renames); + setup_map(core_types::RegFile::RF_VECTOR, p->num_vector_renames); - static_assert(core_types::RegFile::N_REGFILES == 2, "New RF type added, but Rename not updated"); + static_assert(core_types::RegFile::N_REGFILES == 3, + "New RF type added, but Rename not updated"); } // Using the Rename factory, create the Scoreboards void RenameFactory::onConfiguring(sparta::ResourceTreeNode* node) { - sparta::TreeNode * sb_tn = nullptr; - sb_tns_.emplace_back(sb_tn = - new sparta::TreeNode(node, "scoreboards", "Scoreboards used by Rename")); + sparta::TreeNode* sb_tn = nullptr; + sb_tns_.emplace_back( + sb_tn = new sparta::TreeNode(node, "scoreboards", "Scoreboards used by Rename")); // Set up the Scoreboard resources - for(uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) + for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) { const auto rf_name = core_types::regfile_names[rf]; - sb_tns_.emplace_back(new sparta::ResourceTreeNode(sb_tn, - rf_name, - sparta::TreeNode::GROUP_NAME_NONE, - sparta::TreeNode::GROUP_IDX_NONE, - rf_name + std::string(" Scoreboard"), - &sb_facts_[rf])); + sb_tns_.emplace_back(new sparta::ResourceTreeNode( + sb_tn, rf_name, sparta::TreeNode::GROUP_NAME_NONE, sparta::TreeNode::GROUP_IDX_NONE, + rf_name + std::string(" Scoreboard"), &sb_facts_[rf])); } } @@ -94,7 +102,8 @@ namespace olympia // Set up scoreboards auto sbs_tn = getContainer()->getChild("scoreboards"); sparta_assert(sbs_tn != nullptr, "Expected to find 'scoreboards' node in Rename, got none"); - for(uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) { + for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) + { // Get scoreboard resources auto sb_tn = sbs_tn->getChild(core_types::regfile_names[rf]); scoreboards_[rf] = sb_tn->getResourceAs(); @@ -102,12 +111,14 @@ namespace olympia // Initialize 32 scoreboard resources, // all ready. uint32_t reg = 0; - if(rf == core_types::RegFile::RF_INTEGER){ + if (rf == core_types::RegFile::RF_INTEGER) + { reg = 1; } constexpr uint32_t num_regs = 32; core_types::RegisterBitMask bits; - for(; reg < num_regs; ++reg) { + for (; reg < num_regs; ++reg) + { bits.set(reg); } scoreboards_[rf]->set(bits); @@ -122,29 +133,33 @@ namespace olympia sparta_assert(in_dispatch_queue_credits_.dataReceived()); credits_dispatch_ += credits; - if (uop_queue_.size() > 0) { + if (uop_queue_.size() > 0) + { ev_schedule_rename_.schedule(); } } + void Rename::getAckFromROB_(const InstPtr & inst_ptr) { sparta_assert(inst_ptr->getStatus() == Inst::Status::RETIRED, - "Get ROB Ack, but the inst hasn't retired yet!"); + "Get ROB Ack, but the inst hasn't retired yet!"); auto const & dests = inst_ptr->getDestOpInfoList(); - if(dests.size() > 0) + if (dests.size() > 0) { sparta_assert(dests.size() == 1); // we should only have one destination const auto dest = dests[0]; - const auto rf = olympia::coreutils::determineRegisterFile(dest); + const auto rf = olympia::coreutils::determineRegisterFile(dest); const auto num = dest.field_value; const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); if (!is_x0) { auto const & original_dest = inst_ptr->getRenameData().getOriginalDestination(); --reference_counter_[original_dest.rf][original_dest.val]; - // free previous PRF mapping if no references from srcs, there should be a new dest mapping for the ARF -> PRF - // so we know it's free to be pushed to freelist if it has no other src references - if(reference_counter_[original_dest.rf][original_dest.val] <= 0){ + // free previous PRF mapping if no references from srcs, there should be a new dest + // mapping for the ARF -> PRF so we know it's free to be pushed to freelist if it + // has no other src references + if (reference_counter_[original_dest.rf][original_dest.val] <= 0) + { freelist_[original_dest.rf].push(original_dest.val); } } @@ -152,24 +167,31 @@ namespace olympia const auto & srcs = inst_ptr->getRenameData().getSourceList(); // decrement reference to data register - if(inst_ptr->isLoadStoreInst()){ + if (inst_ptr->isLoadStoreInst()) + { const auto & data_reg = inst_ptr->getRenameData().getDataReg(); - if(data_reg.field_id == mavis::InstMetaData::OperandFieldID::RS2 && data_reg.is_x0 != true){ + if (data_reg.field_id == mavis::InstMetaData::OperandFieldID::RS2 + && data_reg.is_x0 != true) + { --reference_counter_[data_reg.rf][data_reg.val]; - if(reference_counter_[data_reg.rf][data_reg.val] <= 0){ - // freeing data register value, because it's not in the source list, so won't get caught below + if (reference_counter_[data_reg.rf][data_reg.val] <= 0) + { + // freeing data register value, because it's not in the source list, so won't + // get caught below freelist_[data_reg.rf].push(data_reg.val); } } } // freeing references to PRF - for(const auto & src: srcs){ + for (const auto & src : srcs) + { --reference_counter_[src.rf][src.val]; - if(reference_counter_[src.rf][src.val] <= 0){ - // freeing a register in the case where it still has references and has already been retired - // we wait until the last reference is retired to then free the prf - // any "valid" PRF that is the true mapping of an ARF will have a reference_counter of at least 1, - // and thus shouldn't be retired + if (reference_counter_[src.rf][src.val] <= 0) + { + // freeing a register in the case where it still has references and has already been + // retired we wait until the last reference is retired to then free the prf any + // "valid" PRF that is the true mapping of an ARF will have a reference_counter of + // at least 1, and thus shouldn't be retired freelist_[src.rf].push(src.val); } } @@ -177,20 +199,42 @@ namespace olympia if (SPARTA_EXPECT_TRUE(!inst_queue_.empty())) { const auto & oldest_inst = inst_queue_.front(); - sparta_assert(oldest_inst->getUniqueID() == inst_ptr->getUniqueID(), "ROB and rename inst_queue out of sync"); + if (!oldest_inst->hasUOps() && !oldest_inst->isUOp()) + { + // if instructions aren't UOp and oldest instruction doesn't have UOps + sparta_assert(oldest_inst->getUniqueID() == inst_ptr->getUniqueID(), + "ROB and rename inst_queue out of sync"); + } + inst_queue_.pop_front(); + + // pop all UOps from inst_queue_ to relaign ROB and rename inst_queue + if (inst_ptr->hasUOps()) + { + while (inst_queue_.empty() == false) + { + if (inst_ptr->getUOpID() == inst_queue_.front()->getUOpID()) + { + inst_queue_.pop_front(); + } + else + { + break; + } + } + } } else { sparta_assert(false, "ROB and rename inst_queue out of sync"); } - if(credits_dispatch_ > 0 && (uop_queue_.size() > 0)){ + if (credits_dispatch_ > 0 && (uop_queue_.size() > 0)) + { ev_schedule_rename_.schedule(); } ILOG("Retired instruction: " << inst_ptr); } - // Handle incoming flush void Rename::handleFlush_(const FlushManager::FlushingCriteria & criteria) { @@ -209,18 +253,20 @@ namespace olympia for (const auto & dest : dests) { // restore rename table following a flush - const auto rf = olympia::coreutils::determineRegisterFile(dest); + const auto rf = olympia::coreutils::determineRegisterFile(dest); const auto num = dest.field_value; const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); if (!is_x0) { - auto const & original_dest = inst_ptr->getRenameData().getOriginalDestination(); + auto const & original_dest = + inst_ptr->getRenameData().getOriginalDestination(); map_table_[rf][num] = original_dest.val; // free renamed PRF mapping when reference counter reaches zero auto const & renamed_dest = inst_ptr->getRenameData().getDestination(); --reference_counter_[renamed_dest.rf][renamed_dest.val]; - if(reference_counter_[renamed_dest.rf][renamed_dest.val] <= 0){ + if (reference_counter_[renamed_dest.rf][renamed_dest.val] <= 0) + { freelist_[renamed_dest.rf].push(renamed_dest.val); } } @@ -228,24 +274,31 @@ namespace olympia const auto & srcs = inst_ptr->getRenameData().getSourceList(); // decrement reference to data register - if(inst_ptr->isLoadStoreInst()){ + if (inst_ptr->isLoadStoreInst()) + { const auto & data_reg = inst_ptr->getRenameData().getDataReg(); - if(data_reg.field_id == mavis::InstMetaData::OperandFieldID::RS2 && data_reg.is_x0 != true){ + if (data_reg.field_id == mavis::InstMetaData::OperandFieldID::RS2 + && data_reg.is_x0 != true) + { --reference_counter_[data_reg.rf][data_reg.val]; - if(reference_counter_[data_reg.rf][data_reg.val] <= 0){ - // freeing data register value, because it's not in the source list, so won't get caught below + if (reference_counter_[data_reg.rf][data_reg.val] <= 0) + { + // freeing data register value, because it's not in the source list, so + // won't get caught below freelist_[data_reg.rf].push(data_reg.val); } } } // freeing references to PRF - for(const auto & src: srcs){ + for (const auto & src : srcs) + { --reference_counter_[src.rf][src.val]; - if(reference_counter_[src.rf][src.val] <= 0){ - // freeing a register in the case where it still has references and has already been retired - // we wait until the last reference is retired to then free the prf - // any "valid" PRF that is the true mapping of an ARF will have a reference_counter of at least 1, - // and thus shouldn't be retired + if (reference_counter_[src.rf][src.val] <= 0) + { + // freeing a register in the case where it still has references and has + // already been retired we wait until the last reference is retired to then + // free the prf any "valid" PRF that is the true mapping of an ARF will have + // a reference_counter of at least 1, and thus shouldn't be retired freelist_[src.rf].push(src.val); } } @@ -266,20 +319,24 @@ namespace olympia sparta_assert(in_uop_queue_append_.dataReceived()); RegCountData current_counts; - if(!uop_queue_regcount_data_.empty()){ + if (!uop_queue_regcount_data_.empty()) + { // if we have entries, use the most recent entered instruction counts current_counts = uop_queue_regcount_data_.back(); } - for(auto & i : *insts) { + for (auto & i : *insts) + { // create an index count for each instruction entered const auto & dests = i->getDestOpInfoList(); - if(dests.size() > 0){ + if (dests.size() > 0) + { sparta_assert(dests.size() == 1); // we should only have one destination const auto rf = olympia::coreutils::determineRegisterFile(dests[0]); const auto num = dests[0].field_value; const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); // if dest is x0, we don't need to count it towards cumulative register count - if(!is_x0){ + if (!is_x0) + { current_counts.cumulative_reg_counts[rf]++; } } @@ -287,10 +344,12 @@ namespace olympia uop_queue_regcount_data_.push_back(current_counts); } - if(credits_dispatch_ > 0) { + if (credits_dispatch_ > 0) + { ev_schedule_rename_.schedule(); } } + void Rename::scheduleRenaming_() { current_stall_ = StallReason::NOT_STALLED; @@ -298,25 +357,31 @@ namespace olympia // If we have credits from dispatch, schedule a rename session this cycle uint32_t num_rename = std::min(uop_queue_.size(), num_to_rename_per_cycle_); num_rename = std::min(credits_dispatch_, num_rename); - if(credits_dispatch_ > 0) + if (credits_dispatch_ > 0) { RegCountData count_subtract; bool enough_rename = false; - for(uint32_t i = num_rename; i > 0 ; --i) + for (uint32_t i = num_rename; i > 0; --i) { - if(enough_rename){ + if (enough_rename) + { // once we know the number we can rename // pop everything below it uop_queue_regcount_data_.pop_front(); } - else{ + else + { uint32_t enough_freelists = 0; - for(int j = 0; j < core_types::RegFile::N_REGFILES; ++j){ - if(uop_queue_regcount_data_[i-1].cumulative_reg_counts[j] <= freelist_[j].size()){ + for (int j = 0; j < core_types::RegFile::N_REGFILES; ++j) + { + if (uop_queue_regcount_data_[i - 1].cumulative_reg_counts[j] + <= freelist_[j].size()) + { enough_freelists++; } } - if(enough_freelists == core_types::RegFile::N_REGFILES){ + if (enough_freelists == core_types::RegFile::N_REGFILES) + { // we are good to process all instructions from this index num_to_rename_ = i; enough_rename = true; @@ -324,12 +389,13 @@ namespace olympia } } // decrement the rest of the entries in the uop_queue_reg_count_data_ accordingly - if(enough_rename) + if (enough_rename) { count_subtract = uop_queue_regcount_data_.front(); uop_queue_regcount_data_.pop_front(); - for(uint32_t i = 0; i < uop_queue_regcount_data_.size(); ++i){ - for(uint32_t j = 0; j < core_types::RegFile::N_REGFILES; ++j) + for (uint32_t i = 0; i < uop_queue_regcount_data_.size(); ++i) + { + for (uint32_t j = 0; j < core_types::RegFile::N_REGFILES; ++j) { uop_queue_regcount_data_[i].cumulative_reg_counts[j] -= count_subtract.cumulative_reg_counts[j]; @@ -337,27 +403,31 @@ namespace olympia } ev_rename_insts_.schedule(); } - else{ + else + { current_stall_ = StallReason::NO_RENAMES; num_to_rename_ = 0; } } - else{ + else + { current_stall_ = StallReason::NO_DISPATCH_CREDITS; num_to_rename_ = 0; } ILOG("current stall: " << current_stall_); - rename_histogram_.addValue((int) num_to_rename_); + rename_histogram_.addValue((int)num_to_rename_); } + void Rename::renameInstructions_() { - if(num_to_rename_ > 0) + if (num_to_rename_ > 0) { // Pick instructions from uop queue to rename - InstGroupPtr insts = sparta::allocate_sparta_shared_pointer(instgroup_allocator); + InstGroupPtr insts = + sparta::allocate_sparta_shared_pointer(instgroup_allocator); - for(uint32_t i = 0; i < num_to_rename_; ++i) + for (uint32_t i = 0; i < num_to_rename_; ++i) { // Pick the oldest const auto & renaming_inst = uop_queue_.read(0); @@ -366,51 +436,58 @@ namespace olympia const auto & srcs = renaming_inst->getSourceOpInfoList(); const auto & dests = renaming_inst->getDestOpInfoList(); - for(const auto & src : srcs) + for (const auto & src : srcs) { - const auto rf = olympia::coreutils::determineRegisterFile(src); + const auto rf = olympia::coreutils::determineRegisterFile(src); const auto num = src.field_value; // we check if src is RF_INTEGER x0, if so, we skip rename const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); - if (is_x0) { - // if x0 is a data operand for LSU op, we need to set it in DataReg when we check in LSU - // so we can still check the scoreboard, which will always return back ready for x0 - if(src.field_id == mavis::InstMetaData::OperandFieldID::RS2){ - renaming_inst->getRenameData().setDataReg({num, rf, src.field_id, is_x0}); + if (is_x0) + { + // if x0 is a data operand for LSU op, we need to set it in DataReg when we + // check in LSU so we can still check the scoreboard, which will always + // return back ready for x0 + if (src.field_id == mavis::InstMetaData::OperandFieldID::RS2) + { + renaming_inst->getRenameData().setDataReg( + {num, rf, src.field_id, is_x0}); } continue; } // we check for load/store separately because address operand // is always integer - else if(renaming_inst->isLoadStoreInst()) { + else if (renaming_inst->isLoadStoreInst()) + { // check for data operand existing based on RS2 existence // store data register info separately - if(src.field_id == mavis::InstMetaData::OperandFieldID::RS2) { + if (src.field_id == mavis::InstMetaData::OperandFieldID::RS2) + { auto & bitmask = renaming_inst->getDataRegisterBitMask(rf); const uint32_t prf = map_table_[rf][num]; reference_counter_[rf][prf]++; - renaming_inst->getRenameData().setDataReg({prf, rf, src.field_id, is_x0}); + renaming_inst->getRenameData().setDataReg( + {prf, rf, src.field_id, is_x0}); bitmask.set(prf); - ILOG("\tsetup store data register bit mask " - << sparta::printBitSet(bitmask) - << " for '" << rf << "' scoreboard"); + ILOG("\tsetup store data register bit mask " << sparta::printBitSet( + bitmask) << " for '" << rf << "' scoreboard"); } - else { + else + { // address is always INTEGER - const auto addr_rf = core_types::RF_INTEGER; + const auto addr_rf = core_types::RF_INTEGER; auto & bitmask = renaming_inst->getSrcRegisterBitMask(addr_rf); const uint32_t prf = map_table_[addr_rf][num]; reference_counter_[addr_rf][prf]++; renaming_inst->getRenameData().setSource({prf, addr_rf, src.field_id}); bitmask.set(prf); - ILOG("\tsetup source register bit mask " - << sparta::printBitSet(bitmask) - << " for '" << addr_rf << "' scoreboard"); + ILOG("\tsetup source register bit mask " << sparta::printBitSet( + bitmask) << " for '" << addr_rf << "' scoreboard"); } } - else { + else + { auto & bitmask = renaming_inst->getSrcRegisterBitMask(rf); const uint32_t prf = map_table_[rf][num]; reference_counter_[rf][prf]++; @@ -418,37 +495,63 @@ namespace olympia bitmask.set(prf); ILOG("\tsetup source register bit mask " - << sparta::printBitSet(bitmask) - << " for '" << rf << "' scoreboard"); + << sparta::printBitSet(bitmask) << " for '" << rf << "' scoreboard"); } } - for(const auto & dest : dests) + for (const auto & dest : dests) { - const auto rf = olympia::coreutils::determineRegisterFile(dest); + const auto rf = olympia::coreutils::determineRegisterFile(dest); const auto num = dest.field_value; - if (num == 0 && rf == core_types::RF_INTEGER) { + if (num == 0 && rf == core_types::RF_INTEGER) + { continue; } - else{ + else + { + if (renaming_inst->isVector() && !renaming_inst->isVset() + && !renaming_inst->getVTA() && renaming_inst->hasTail()) + { + // if vector instruction is undisturbed and has a mask or tail, so vta = + // false, we need to set the original destination as a source as well + // need to set before destination rename, because we need the original + // destination + + // TODO: Once we implement masks, add logic to check if vta is false and + // mask is being applied, then we need the original destination because + // if we always add 3rd source for undisturbed, then we're adding extra + // dependency, slowing the pipeline down + + // we set for source bitmask because we need to wait for previous + // destination to be written to before reading (RAW) hazard + auto & bitmask = renaming_inst->getSrcRegisterBitMask(rf); + const uint32_t prf = map_table_[rf][num]; + reference_counter_[rf][prf]++; + renaming_inst->getRenameData().setSource({prf, rf, dest.field_id}); + bitmask.set(prf); + + ILOG("\tsetup vector undisturbed source register bit mask " + << sparta::printBitSet(bitmask) << " for '" << rf + << "' scoreboard"); + } auto & bitmask = renaming_inst->getDestRegisterBitMask(rf); const uint32_t prf = freelist_[rf].front(); freelist_[rf].pop(); - renaming_inst->getRenameData().setOriginalDestination({map_table_[rf][num], rf, dest.field_id}); + renaming_inst->getRenameData().setOriginalDestination( + {map_table_[rf][num], rf, dest.field_id}); renaming_inst->getRenameData().setDestination({prf, rf, dest.field_id}); map_table_[rf][num] = prf; // we increase reference_counter_ for destinations to mark them as "valid", // so the PRF in the reference_counter_ should have a value of 1 - // once a PRF reference_counter goes to 0, we know that the PRF isn't the "valid" - // PRF for that ARF anymore and there are no sources referring to it + // once a PRF reference_counter goes to 0, we know that the PRF isn't the + // "valid" PRF for that ARF anymore and there are no sources referring to it // so we can push it to freelist reference_counter_[rf][prf]++; bitmask.set(prf); // clear scoreboard for the PRF we are allocating scoreboards_[rf]->clearBits(bitmask); ILOG("\tsetup destination register bit mask " - << sparta::printBitSet(bitmask) - << " for '" << rf << "' scoreboard"); + << sparta::printBitSet(bitmask) << " for '" << rf << "' scoreboard"); } } // Remove it from uop queue @@ -465,8 +568,9 @@ namespace olympia out_uop_queue_credits_.send(num_to_rename_); num_to_rename_ = 0; } - if (credits_dispatch_ > 0 && (uop_queue_.size() > 0)) { + if (credits_dispatch_ > 0 && (uop_queue_.size() > 0)) + { ev_schedule_rename_.schedule(1); } } -} \ No newline at end of file +} // namespace olympia diff --git a/core/Rename.hpp b/core/Rename.hpp index 5f31eed3..c5e7165d 100644 --- a/core/Rename.hpp +++ b/core/Rename.hpp @@ -1,6 +1,5 @@ // -*- C++ -*- - #pragma once #include @@ -16,7 +15,6 @@ #include "sparta/statistics/Histogram.hpp" #include "sparta/statistics/BasicHistogram.hpp" - #include "CoreTypes.hpp" #include "FlushManager.hpp" #include "InstGroup.hpp" @@ -35,19 +33,18 @@ namespace olympia */ class Rename : public sparta::Unit { - public: + public: //! \brief Parameters for Rename model class RenameParameterSet : public sparta::ParameterSet { - public: - RenameParameterSet(sparta::TreeNode* n) : - sparta::ParameterSet(n) - { } + public: + RenameParameterSet(sparta::TreeNode* n) : sparta::ParameterSet(n) {} - PARAMETER(uint32_t, num_to_rename, 4, "Number of instructions to rename") + PARAMETER(uint32_t, num_to_rename, 4, "Number of instructions to rename") PARAMETER(uint32_t, rename_queue_depth, 10, "Number of instructions queued for rename") PARAMETER(uint32_t, num_integer_renames, 128, "Number of integer renames") - PARAMETER(uint32_t, num_float_renames, 128, "Number of float renames") + PARAMETER(uint32_t, num_float_renames, 128, "Number of float renames") + PARAMETER(uint32_t, num_vector_renames, 48, "Number of vector renames") }; /** @@ -56,29 +53,32 @@ namespace olympia * @param node The node that represents (has a pointer to) the Rename * @param p The Rename's parameter set */ - Rename(sparta::TreeNode * node, - const RenameParameterSet * p); + Rename(sparta::TreeNode* node, const RenameParameterSet* p); //! \brief Name of this resource. Required by sparta::UnitFactory static const char name[]; - private: - InstQueue uop_queue_; - sparta::DataInPort in_uop_queue_append_ {&unit_port_set_, "in_uop_queue_append", 1}; - sparta::DataOutPort out_uop_queue_credits_ {&unit_port_set_, "out_uop_queue_credits"}; - sparta::DataOutPort out_dispatch_queue_write_ {&unit_port_set_, "out_dispatch_queue_write"}; - sparta::DataInPort in_dispatch_queue_credits_ {&unit_port_set_, "in_dispatch_queue_credits", - sparta::SchedulingPhase::Tick, 0}; - sparta::DataInPort in_rename_retire_ack_ {&unit_port_set_, "in_rename_retire_ack", 1}; + private: + InstQueue uop_queue_; + sparta::DataInPort in_uop_queue_append_{&unit_port_set_, + "in_uop_queue_append", 1}; + sparta::DataOutPort out_uop_queue_credits_{&unit_port_set_, + "out_uop_queue_credits"}; + sparta::DataOutPort out_dispatch_queue_write_{&unit_port_set_, + "out_dispatch_queue_write"}; + sparta::DataInPort in_dispatch_queue_credits_{ + &unit_port_set_, "in_dispatch_queue_credits", sparta::SchedulingPhase::Tick, 0}; + sparta::DataInPort in_rename_retire_ack_{&unit_port_set_, "in_rename_retire_ack", + 1}; // For flush - sparta::DataInPort in_reorder_flush_ - {&unit_port_set_, "in_reorder_flush", sparta::SchedulingPhase::Flush, 1}; + sparta::DataInPort in_reorder_flush_{ + &unit_port_set_, "in_reorder_flush", sparta::SchedulingPhase::Flush, 1}; - sparta::UniqueEvent<> ev_rename_insts_ {&unit_event_set_, "rename_insts", - CREATE_SPARTA_HANDLER(Rename, renameInstructions_)}; - sparta::UniqueEvent<> ev_schedule_rename_ {&unit_event_set_, "schedule_rename", - CREATE_SPARTA_HANDLER(Rename, scheduleRenaming_)}; + sparta::UniqueEvent<> ev_rename_insts_{&unit_event_set_, "rename_insts", + CREATE_SPARTA_HANDLER(Rename, renameInstructions_)}; + sparta::UniqueEvent<> ev_schedule_rename_{&unit_event_set_, "schedule_rename", + CREATE_SPARTA_HANDLER(Rename, scheduleRenaming_)}; const uint32_t num_to_rename_per_cycle_; uint32_t num_to_rename_ = 0; @@ -96,21 +96,24 @@ namespace olympia std::array, core_types::N_REGFILES> reference_counter_; // list of free PRF that are available to map std::queue freelist_[core_types::N_REGFILES]; + // used to track current number of each type of RF instruction at each // given index in the uop_queue_ - struct RegCountData{ + struct RegCountData + { uint32_t cumulative_reg_counts[core_types::RegFile::N_REGFILES] = {0}; }; + std::deque uop_queue_regcount_data_; // Used to track inflight instructions for the purpose of recovering // the rename data structures std::deque inst_queue_; - /////////////////////////////////////////////////////////////////////// // Stall counters - enum StallReason { + enum StallReason + { NO_DECODE_INSTS, // No insts from Decode NO_DISPATCH_CREDITS, // No credits from Dispatch NO_RENAMES, // Out of renames @@ -121,24 +124,20 @@ namespace olympia }; StallReason current_stall_ = NO_DECODE_INSTS; - friend std::ostream&operator<<(std::ostream &, const StallReason &); + friend std::ostream & operator<<(std::ostream &, const StallReason &); // Counters -- this is only supported in C++11 -- uses // Counter's move semantics - std::array stall_counters_{{ - sparta::CycleCounter(getStatisticSet(), "stall_no_decode_insts", - "No Decode Insts", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_no_dispatch_credits", - "No Dispatch Credits", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_no_renames", - "No Renames", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", - "Rename not stalled, all instructions renamed", - sparta::Counter::COUNT_NORMAL, getClock()) - }}; + std::array stall_counters_{ + {sparta::CycleCounter(getStatisticSet(), "stall_no_decode_insts", "No Decode Insts", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_no_dispatch_credits", + "No Dispatch Credits", sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_no_renames", "No Renames", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", + "Rename not stalled, all instructions renamed", + sparta::Counter::COUNT_NORMAL, getClock())}}; //! Rename setup void setupRename_(); @@ -163,27 +162,26 @@ namespace olympia // Friend class used in rename testing friend class RenameTester; - }; - inline std::ostream&operator<<(std::ostream &os, const Rename::StallReason & stall) + inline std::ostream & operator<<(std::ostream & os, const Rename::StallReason & stall) { - switch(stall) + switch (stall) { - case Rename::StallReason::NO_DECODE_INSTS: - os << "NO_DECODE_INSTS"; - break; - case Rename::StallReason::NO_DISPATCH_CREDITS: - os << "NO_DISPATCH_CREDITS"; - break; - case Rename::StallReason::NO_RENAMES: - os << "NO_RENAMES"; - break; - case Rename::StallReason::NOT_STALLED: - os << "NOT_STALLED"; - break; - case Rename::StallReason::N_STALL_REASONS: - sparta_assert(false, "How'd we get here?"); + case Rename::StallReason::NO_DECODE_INSTS: + os << "NO_DECODE_INSTS"; + break; + case Rename::StallReason::NO_DISPATCH_CREDITS: + os << "NO_DISPATCH_CREDITS"; + break; + case Rename::StallReason::NO_RENAMES: + os << "NO_RENAMES"; + break; + case Rename::StallReason::NOT_STALLED: + os << "NOT_STALLED"; + break; + case Rename::StallReason::N_STALL_REASONS: + sparta_assert(false, "How'd we get here?"); } return os; } @@ -191,16 +189,16 @@ namespace olympia //! Rename's factory class. Don't create Rename without it class RenameFactory : public sparta::ResourceFactory { - public: + public: void onConfiguring(sparta::ResourceTreeNode* node) override; - private: + private: using ScoreboardTreeNodes = std::vector>; - using ScoreboardFactories = std::array , - core_types::RegFile::N_REGFILES>; + using ScoreboardFactories = std::array< + sparta::ResourceFactory, + core_types::RegFile::N_REGFILES>; ScoreboardFactories sb_facts_; ScoreboardTreeNodes sb_tns_; }; class RenameTester; -} +} // namespace olympia diff --git a/core/VectorUopGenerator.cpp b/core/VectorUopGenerator.cpp new file mode 100644 index 00000000..cde59823 --- /dev/null +++ b/core/VectorUopGenerator.cpp @@ -0,0 +1,186 @@ +#include "VectorUopGenerator.hpp" +#include "mavis/Mavis.h" +#include "sparta/utils/LogUtils.hpp" + +namespace olympia +{ + constexpr char VectorUopGenerator::name[]; + + VectorUopGenerator::VectorUopGenerator(sparta::TreeNode* node, const VectorUopGeneratorParameterSet* p) : + sparta::Unit(node) + { + // Vector arithmetic uop generator, increment all src and dest register numbers + // For a "vadd.vv v12, v4,v8" with an LMUL of 4: + // Uop 1: vadd.vv v12, v4, v8 + // Uop 2: vadd.vv v13, v5, v9 + // Uop 3: vadd.vv v14, v6, v10 + // Uop 4: vadd.vv v15, v7, v11 + { + constexpr bool SINGLE_DEST = false; + constexpr bool WIDE_DEST = false; + uop_gen_function_map_.emplace(InstArchInfo::UopGenType::ARITH, + &VectorUopGenerator::generateArithUop); + } + + // Vector arithmetic single dest uop generator, only increment all src register numbers + // For a "vmseq.vv v12, v4,v8" with an LMUL of 4: + // Uop 1: vadd.vv v12, v4, v8 + // Uop 2: vadd.vv v12, v5, v9 + // Uop 3: vadd.vv v12, v6, v10 + // Uop 4: vadd.vv v12, v7, v11 + { + constexpr bool SINGLE_DEST = true; + constexpr bool WIDE_DEST = false; + uop_gen_function_map_.emplace(InstArchInfo::UopGenType::ARITH_SINGLE_DEST, + &VectorUopGenerator::generateArithUop); + } + + // Vector arithmetic wide dest uop generator, only increment src register numbers for even uops + // For a "vwmul.vv v12, v4, v8" with an LMUL of 4: + // Uop 1: vwmul.vv v12, v4, v8 + // Uop 2: vwmul.vv v13, v4, v8 + // Uop 3: vwmul.vv v14, v6, v10 + // Uop 4: vwmul.vv v15, v6, v10 + // Uop 5: vwmul.vv v16, v8, v12 + // Uop 6: vwmul.vv v17, v8, v12 + // Uop 7: vwmul.vv v18, v10, v14 + // Uop 8: vwmul.vv v19, v10, v14 + { + constexpr bool SINGLE_DEST = false; + constexpr bool WIDE_DEST = true; + uop_gen_function_map_.emplace(InstArchInfo::UopGenType::ARITH_WIDE_DEST, + &VectorUopGenerator::generateArithUop); + } + } + + void VectorUopGenerator::setInst(const InstPtr & inst) + { + sparta_assert(current_inst_ == nullptr, + "Cannot start generating uops for a new vector instruction, " + "current instruction has not finished: " << current_inst_); + + const auto uop_gen_type = inst->getUopGenType(); + sparta_assert(uop_gen_type != InstArchInfo::UopGenType::UNKNOWN, + "Inst: " << current_inst_ << " uop gen type is unknown"); + + if(uop_gen_type != InstArchInfo::UopGenType::NONE) + { + // Number of vector elements processed by each uop + const Inst::VCSRs * current_vcsrs = inst->getVCSRs(); + const uint64_t num_elems_per_uop = Inst::VLEN / current_vcsrs->sew; + // TODO: For now, generate uops for all elements even if there is a tail + num_uops_to_generate_ = std::ceil(current_vcsrs->vlmax / num_elems_per_uop); + + if(uop_gen_type == InstArchInfo::UopGenType::ARITH_WIDE_DEST) + { + // TODO: Add parameter to support dual dests + num_uops_to_generate_ *= 2; + } + } + + if(num_uops_to_generate_ > 1) + { + // Original instruction will act as the first UOp + inst->setUOpID(0); // set UOpID() + current_inst_ = inst; + ILOG("Inst: " << current_inst_ << " is being split into " + << num_uops_to_generate_ << " UOPs"); + } + else + { + ILOG("Inst: " << inst << " does not need to generate uops"); + } + + // Inst counts as the first uop + --num_uops_to_generate_; + } + + const InstPtr VectorUopGenerator::generateUop() + { + const auto uop_gen_type = current_inst_->getUopGenType(); + sparta_assert(uop_gen_type <= InstArchInfo::UopGenType::NONE, + "Inst: " << current_inst_ << " uop gen type is unknown"); + + // Generate uop + auto uop_gen_func = uop_gen_function_map_.at(uop_gen_type); + const InstPtr uop = uop_gen_func(this); + ++num_uops_generated_; + + // setting UOp instructions to have the same UID and PID as parent instruction + uop->setUniqueID(current_inst_->getUniqueID()); + uop->setProgramID(current_inst_->getProgramID()); + + const Inst::VCSRs * current_vcsrs = current_inst_->getVCSRs(); + uop->setVCSRs(current_vcsrs); + uop->setUOpID(num_uops_generated_); + + // Set weak pointer to parent vector instruction (first uop) + sparta::SpartaWeakPointer parent_weak_ptr = current_inst_; + uop->setUOpParent(parent_weak_ptr); + + // Handle last uop + if(num_uops_generated_ == num_uops_to_generate_) + { + const uint32_t num_elems = current_vcsrs->vl / current_vcsrs->sew; + uop->setTail(num_elems < current_vcsrs->vlmax); + + reset_(); + } + + ILOG("Generated uop: " << uop); + + return uop; + } + + template + const InstPtr VectorUopGenerator::generateArithUop() + { + // Increment source and destination register values + auto srcs = current_inst_->getSourceOpInfoList(); + for (auto & src : srcs) + { + // Do not increment scalar sources for transfer instructions + if (src.operand_type != mavis::InstMetaData::OperandTypes::VECTOR) + { + continue; + } + + if constexpr (WIDE_DEST == true) + { + // Only increment source values for even uops + src.field_value += (num_uops_generated_ % 2) ? num_uops_generated_ - 1 + : num_uops_generated_; + } + else + { + src.field_value += num_uops_generated_; + } + } + + auto dests = current_inst_->getDestOpInfoList(); + if constexpr (SINGLE_DEST == false) + { + for (auto & dest : dests) + { + dest.field_value += num_uops_generated_; + } + } + + // Create uop + mavis::ExtractorDirectOpInfoList ex_info(current_inst_->getMnemonic(), + srcs, + dests, + current_inst_->getImmediate()); + InstPtr uop = mavis_facade_->makeInstDirectly(ex_info, getClock()); + + return uop; + } + + void VectorUopGenerator::handleFlush(const FlushManager::FlushingCriteria & flush_criteria) + { + if(current_inst_ && flush_criteria.includedInFlush(current_inst_)) + { + reset_(); + } + } +} // namespace olympia diff --git a/core/VectorUopGenerator.hpp b/core/VectorUopGenerator.hpp new file mode 100644 index 00000000..f7de669d --- /dev/null +++ b/core/VectorUopGenerator.hpp @@ -0,0 +1,80 @@ +// -*- C++ -*- +//! \file VectorUopGenerator.hpp +#pragma once + +#include "sparta/simulation/Unit.hpp" +#include "sparta/simulation/TreeNode.hpp" +#include "sparta/simulation/ParameterSet.hpp" + +#include "Inst.hpp" +#include "FlushManager.hpp" +#include "MavisUnit.hpp" + +namespace olympia +{ + + /** + * @file VectorUopGenerator.hpp + * @brief TODO + */ + class VectorUopGenerator : public sparta::Unit + { + public: + //! \brief Parameters for VectorUopGenerator model + class VectorUopGeneratorParameterSet : public sparta::ParameterSet + { + public: + VectorUopGeneratorParameterSet(sparta::TreeNode* n) : sparta::ParameterSet(n) {} + + //! \brief Generate uops for widening vector instructions with two dests + //PARAMETER(bool, widening_dual_dest, false, + // "Generate uops for widening vector instructions with two dests") + }; + + /** + * @brief Constructor for VectorUopGenerator + * + * @param node The node that represents (has a pointer to) the VectorUopGenerator + * @param p The VectorUopGenerator's parameter set + */ + VectorUopGenerator(sparta::TreeNode* node, const VectorUopGeneratorParameterSet* p); + + //! \brief Name of this resource. Required by sparta::UnitFactory + static constexpr char name[] = "vec_uop_gen"; + + void setMavis(MavisType * mavis) { mavis_facade_ = mavis; } + + void setInst(const InstPtr & inst); + + const InstPtr generateUop(); + + template + const InstPtr generateArithUop(); + + uint64_t getNumUopsRemaining() const { return num_uops_to_generate_; } + + void handleFlush(const FlushManager::FlushingCriteria &); + + private: + MavisType * mavis_facade_; + + //typedef std::function FUNC; + typedef std::function UopGenFunctionType; + typedef std::map UopGenFunctionMapType; + UopGenFunctionMapType uop_gen_function_map_; + + // TODO: Use Sparta ValidValue + InstPtr current_inst_ = nullptr; + //UopGenFunctionMapType::iterator current_uop_gen_function_; + + uint64_t num_uops_generated_ = 0; + uint64_t num_uops_to_generate_ = 0; + + void reset_() + { + current_inst_ = nullptr; + num_uops_generated_ = 0; + num_uops_to_generate_ = 0; + } + }; +} // namespace olympia diff --git a/stf_lib b/stf_lib index 69d48b1b..b874cc0c 160000 --- a/stf_lib +++ b/stf_lib @@ -1 +1 @@ -Subproject commit 69d48b1bab14a410c859aa3591b4eb175323ec98 +Subproject commit b874cc0c8dc6a7e95fe00c2f9cd8e4504270d395 diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 82e365e1..e4364e7a 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -33,4 +33,5 @@ add_subdirectory(core/rename) add_subdirectory(core/lsu) add_subdirectory(core/issue_queue) add_subdirectory(core/branch_pred) +add_subdirectory(core/vector) add_subdirectory(fusion) diff --git a/test/core/dispatch/expected_output/big_core.out.EXPECTED b/test/core/dispatch/expected_output/big_core.out.EXPECTED index 037a35d2..5f049f20 100644 --- a/test/core/dispatch/expected_output/big_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:28 2024 -#Elapsed: 0.017899s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.003678s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -17,6 +17,10 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq5 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 @@ -27,6 +31,7 @@ {0000000000 00000000 top.execute.exe7 info} ExecutePipe: ExecutePipe construct: #7 {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 +{0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -41,21 +46,23 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -63,182 +70,182 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid: 2 RENAMED 0 pid: 0 'add 6,4,5' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to iq2 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq2 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' Bits needed:[0,3] -{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' Bits needed:[5,32] +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 4 RENAMED 0 pid: 0 'add 10,8,9' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid: 5 RENAMED 0 pid: 0 'add 12,10,11' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to iq2 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq2 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' Bits needed:[7,33] -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' Bits needed:[9,34] -{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' Bits needed:[11,35] +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 'add 14,12,13' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 'add 16,14,15' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid: 8 RENAMED 0 pid: 0 'add 18,16,17' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to iq2 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq2 of target type: INT {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' Bits needed:[13,36] -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' Bits needed:[15,37] -{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' Bits needed:[17,38] +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to exe_pipe exe2 -{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe2 +{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 'add 20,18,19' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq0 of target type: INT {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 'add 6,4,5' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 'add 8,6,7' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 4 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add, 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' Bits needed:[19,39] +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add, 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000006 00000006 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to exe_pipe exe4 -{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' for 8 +{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe4 +{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to exe_pipe exe2 -{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe2 +{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to exe_pipe exe4 -{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe4 +{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 7 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to exe_pipe exe2 -{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe2 +{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to exe_pipe exe4 -{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe4 +{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/medium_core.out.EXPECTED b/test/core/dispatch/expected_output/medium_core.out.EXPECTED index bc042b8f..837fbfc3 100644 --- a/test/core/dispatch/expected_output/medium_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:34 2024 -#Elapsed: 0.004375s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.003807s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -16,12 +16,17 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq4 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 {0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.execute.exe4 info} ExecutePipe: ExecutePipe construct: #4 {0000000000 00000000 top.execute.exe5 info} ExecutePipe: ExecutePipe construct: #5 +{0000000000 00000000 top.execute.exe6 info} ExecutePipe: ExecutePipe construct: #6 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -34,21 +39,23 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -56,191 +63,191 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' Bits needed:[0,3] +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 'add 6,4,5' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 3 RENAMED 0 pid: 0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' Bits needed:[5,32] -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' Bits needed:[7,33] +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 'add 10,8,9' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 5 RENAMED 0 pid: 0 'add 12,10,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' Bits needed:[9,34] -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' Bits needed:[11,35] +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to exe_pipe exe1 -{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe1 +{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 'add 14,12,13' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 'add 16,14,15' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to iq1 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq1 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 2 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' Bits needed:[13,36] -{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' Bits needed:[15,37] +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' +{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 'add 18,16,17' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid: 9 RENAMED 0 pid: 0 'add 20,18,19' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to iq1 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq1 of target type: INT {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 'add 6,4,5' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 'add 8,6,7' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 2 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' Bits needed:[17,38] -{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' Bits needed:[19,39] +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to exe_pipe exe1 -{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe1 +{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to exe_pipe exe1 -{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe1 +{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to exe_pipe exe1 -{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe1 +{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to exe_pipe exe1 -{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe1 +{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/small_core.out.EXPECTED b/test/core/dispatch/expected_output/small_core.out.EXPECTED index 4e70d90a..f1f7560a 100644 --- a/test/core/dispatch/expected_output/small_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:37 2024 -#Elapsed: 0.004805s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.003546s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -15,9 +15,14 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq2 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq3 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 +{0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -28,21 +33,23 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -50,218 +57,218 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 0 'add 4,2,3' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' Bits needed:[0,3] +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 'add 6,4,5' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' Bits needed:[5,32] +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to exe_pipe exe0 -{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe0 +{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 'add 8,6,7' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 'add 28,26,27' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(23) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' Bits needed:[7,33] +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(13) PID(0) add -{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' +{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 'add 10,8,9' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' stall: INT_BUSY +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' stall: INT_BUSY {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 'add 30,28,29' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(24) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' Bits needed:[9,34] +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(14) PID(0) add -{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid: 5 RENAMED 0 pid: 0 'add 12,10,11' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to iq0 of target type: INT -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' stall: INT_BUSY +{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq0 of target type: INT +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' stall: INT_BUSY {0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 'add 0,30,31' +{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(25) PID(0) add -{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' Bits needed:[11,35] +{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(15) PID(0) add -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 'add 14,12,13' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' stall: INT_BUSY +{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' stall: INT_BUSY {0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 'add 2,0,1' +{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' Bits needed:[13,36] +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' for 10 +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid: 7 RENAMED 0 pid: 0 'add 16,14,15' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to iq0 of target type: INT -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' stall: INT_BUSY +{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq0 of target type: INT +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' stall: INT_BUSY {0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 'add 4,2,3' +{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000009 00000009 top.decode info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.decode info} Sending group: 0x00000000 UID(27) PID(0) add -{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' Bits needed:[15,37] +{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(17) PID(0) add -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 'add 18,16,17' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to iq0 of target type: INT -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' stall: INT_BUSY +{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq0 of target type: INT +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' stall: INT_BUSY {0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 'add 6,4,5' +{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' Bits needed:[17,38] +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' for 12 +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000011 00000011 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 'add 20,18,19' -{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to iq0 of target type: INT +{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq0 of target type: INT {0000000011 00000011 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 'add 8,6,7' +{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000011 00000011 top.decode info} inCredits: Got credits from dut: 1 {0000000011 00000011 top.decode info} Sending group: 0x00000000 UID(29) PID(0) add -{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' Bits needed:[19,39] +{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000012 00000012 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(19) PID(0) add {0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to exe_pipe exe0 -{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe0 +{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to exe_pipe exe0 -{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe0 +{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' diff --git a/test/core/dispatch/test_cores/test_big_core.yaml b/test/core/dispatch/test_cores/test_big_core.yaml index 56fcd1c5..4119f823 100644 --- a/test/core/dispatch/test_cores/test_big_core.yaml +++ b/test/core/dispatch/test_cores/test_big_core.yaml @@ -13,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/dispatch/test_cores/test_medium_core.yaml b/test/core/dispatch/test_cores/test_medium_core.yaml index fe70dec9..a723a59e 100644 --- a/test/core/dispatch/test_cores/test_medium_core.yaml +++ b/test/core/dispatch/test_cores/test_medium_core.yaml @@ -1,6 +1,9 @@ + # -# Set up the pipeline for a 3-wide machine +# Set up the pipeline for a 2-wide machine # +#top.cpu: +# dispatch.num_to_dispatch: 2 top.extension.core_extensions: pipelines: @@ -10,14 +13,16 @@ top.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.rename.scoreboards: @@ -25,16 +30,26 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/dispatch/test_cores/test_small_core.yaml b/test/core/dispatch/test_cores/test_small_core.yaml index b154fa01..0d993d95 100644 --- a/test/core/dispatch/test_cores/test_small_core.yaml +++ b/test/core/dispatch/test_cores/test_small_core.yaml @@ -7,13 +7,15 @@ top.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.rename.scoreboards: @@ -21,14 +23,23 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/issue_queue/test_cores/test_big_core.yaml b/test/core/issue_queue/test_cores/test_big_core.yaml index ec35e30b..4119f823 100644 --- a/test/core/issue_queue/test_cores/test_big_core.yaml +++ b/test/core/issue_queue/test_cores/test_big_core.yaml @@ -13,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/issue_queue/test_cores/test_big_core_full.yaml b/test/core/issue_queue/test_cores/test_big_core_full.yaml index 66c1ec15..18315cad 100644 --- a/test/core/issue_queue/test_cores/test_big_core_full.yaml +++ b/test/core/issue_queue/test_cores/test_big_core_full.yaml @@ -13,7 +13,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/l2cache/expected_output/hit_case.out.EXPECTED b/test/core/l2cache/expected_output/hit_case.out.EXPECTED index abf3ec67..619d9ce5 100644 --- a/test/core/l2cache/expected_output/hit_case.out.EXPECTED +++ b/test/core/l2cache/expected_output/hit_case.out.EXPECTED @@ -3,16 +3,16 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Jan 27 08:59:40 2024 -#Elapsed: 0.004092s +#Start: Thursday Thu May 30 21:50:32 2024 +#Elapsed: 0.012536s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 {0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received {0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested {0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! @@ -28,16 +28,16 @@ {0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,21 +48,21 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Requested -{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Requested +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received +{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Requested +{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Requested {0000000051 00000051 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000051 00000051 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000051 00000051 top.l2cache info} getReqFromICache_: Request received from ICache on the port @@ -77,15 +77,15 @@ {0000000053 00000053 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000053 00000053 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000053 00000053 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000061 00000061 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000062 00000062 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Received -{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received +{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000063 00000063 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000063 00000063 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Received +{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received diff --git a/test/core/l2cache/expected_output/single_access.out.EXPECTED b/test/core/l2cache/expected_output/single_access.out.EXPECTED index bf6d8619..5af68b58 100644 --- a/test/core/l2cache/expected_output/single_access.out.EXPECTED +++ b/test/core/l2cache/expected_output/single_access.out.EXPECTED @@ -3,16 +3,16 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Jan 27 08:59:40 2024 -#Elapsed: 0.003294s +#Start: Thursday Thu May 30 21:50:19 2024 +#Elapsed: 0.015993s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 {0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received {0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested {0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! @@ -28,16 +28,16 @@ {0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received diff --git a/test/core/lsu/test_cores/test_big_core.yaml b/test/core/lsu/test_cores/test_big_core.yaml index e83682c6..4119f823 100644 --- a/test/core/lsu/test_cores/test_big_core.yaml +++ b/test/core/lsu/test_cores/test_big_core.yaml @@ -1,10 +1,6 @@ - # -# Set up the pipeline for a 2-wide machine +# Set up the pipeline for a 8-wide machine # -#top.cpu: -# dispatch.num_to_dispatch: 2 - top.extension.core_extensions: pipelines: [ @@ -17,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -25,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/lsu/test_cores/test_big_core_small_rename.yaml b/test/core/lsu/test_cores/test_big_core_small_rename.yaml index c0642231..bf1aaf72 100644 --- a/test/core/lsu/test_cores/test_big_core_small_rename.yaml +++ b/test/core/lsu/test_cores/test_big_core_small_rename.yaml @@ -4,10 +4,13 @@ # #top.cpu: # dispatch.num_to_dispatch: 2 - top: +top: rename.params.num_integer_renames: 34 rename.params.num_float_renames: 34 +# +# Set up the pipeline for a 8-wide machine +# top.extension.core_extensions: pipelines: [ @@ -20,7 +23,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -28,25 +32,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_medium_core.yaml b/test/core/lsu/test_cores/test_medium_core.yaml index 979835d6..a723a59e 100644 --- a/test/core/lsu/test_cores/test_medium_core.yaml +++ b/test/core/lsu/test_cores/test_medium_core.yaml @@ -13,14 +13,16 @@ top.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.rename.scoreboards: @@ -28,16 +30,26 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_medium_core_full.yaml b/test/core/lsu/test_cores/test_medium_core_full.yaml index a5d0ae4a..36e40fe3 100644 --- a/test/core/lsu/test_cores/test_medium_core_full.yaml +++ b/test/core/lsu/test_cores/test_medium_core_full.yaml @@ -21,14 +21,16 @@ top.cpu.core0.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.cpu.core0.rename.scoreboards: @@ -36,16 +38,26 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_small_core.yaml b/test/core/lsu/test_cores/test_small_core.yaml index 2704eaf3..0d993d95 100644 --- a/test/core/lsu/test_cores/test_small_core.yaml +++ b/test/core/lsu/test_cores/test_small_core.yaml @@ -1,22 +1,21 @@ - # # Set up the pipeline for a 2-wide machine # -#top.cpu: -# dispatch.num_to_dispatch: 2 top.extension.core_extensions: pipelines: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.rename.scoreboards: @@ -24,14 +23,23 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_small_core_full.yaml b/test/core/lsu/test_cores/test_small_core_full.yaml index da6e5864..6ff1c99c 100644 --- a/test/core/lsu/test_cores/test_small_core_full.yaml +++ b/test/core/lsu/test_cores/test_small_core_full.yaml @@ -23,13 +23,15 @@ top.cpu.core0.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.cpu.core0.rename.scoreboards: @@ -37,14 +39,23 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] diff --git a/test/core/rename/expected_output/big_core.out.EXPECTED b/test/core/rename/expected_output/big_core.out.EXPECTED index 4af48d33..f954c737 100644 --- a/test/core/rename/expected_output/big_core.out.EXPECTED +++ b/test/core/rename/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:40:26 2024 -#Elapsed: 0.012103s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.003622s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -17,6 +17,10 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq5 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 @@ -27,6 +31,7 @@ {0000000000 00000000 top.execute.exe7 info} ExecutePipe: ExecutePipe construct: #7 {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 +{0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -41,10 +46,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -52,43 +59,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED index 98fa8906..395d3a52 100644 --- a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED +++ b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:59 2024 -#Elapsed: 0.005573s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.00475s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -17,6 +17,10 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq5 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 @@ -27,6 +31,7 @@ {0000000000 00000000 top.execute.exe7 info} ExecutePipe: ExecutePipe construct: #7 {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 +{0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -41,10 +46,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -52,39 +59,39 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NO_RENAMES diff --git a/test/core/rename/expected_output/medium_core.out.EXPECTED b/test/core/rename/expected_output/medium_core.out.EXPECTED index e0bf8a0f..5eb25f2f 100644 --- a/test/core/rename/expected_output/medium_core.out.EXPECTED +++ b/test/core/rename/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:39:26 2024 -#Elapsed: 0.013707s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.004244s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -16,12 +16,17 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq4 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 {0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.execute.exe4 info} ExecutePipe: ExecutePipe construct: #4 {0000000000 00000000 top.execute.exe5 info} ExecutePipe: ExecutePipe construct: #5 +{0000000000 00000000 top.execute.exe6 info} ExecutePipe: ExecutePipe construct: #6 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -34,10 +39,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -45,43 +52,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/small_core.out.EXPECTED b/test/core/rename/expected_output/small_core.out.EXPECTED index 0d97e3a5..37d343de 100644 --- a/test/core/rename/expected_output/small_core.out.EXPECTED +++ b/test/core/rename/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:39:15 2024 -#Elapsed: 0.019968s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.004802s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -15,9 +15,14 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq2 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq3 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 +{0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -28,10 +33,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -39,43 +46,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/test_cores/test_big_core.yaml b/test/core/rename/test_cores/test_big_core.yaml index ec35e30b..4119f823 100644 --- a/test/core/rename/test_cores/test_big_core.yaml +++ b/test/core/rename/test_cores/test_big_core.yaml @@ -13,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/rename/test_cores/test_big_core_full.yaml b/test/core/rename/test_cores/test_big_core_full.yaml index 66c1ec15..18315cad 100644 --- a/test/core/rename/test_cores/test_big_core_full.yaml +++ b/test/core/rename/test_cores/test_big_core_full.yaml @@ -13,7 +13,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/rename/test_cores/test_big_core_small_rename.yaml b/test/core/rename/test_cores/test_big_core_small_rename.yaml index dcbcfb37..bf1aaf72 100644 --- a/test/core/rename/test_cores/test_big_core_small_rename.yaml +++ b/test/core/rename/test_cores/test_big_core_small_rename.yaml @@ -23,7 +23,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -31,25 +32,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_big_core_small_rename_full.yaml b/test/core/rename/test_cores/test_big_core_small_rename_full.yaml index 07581a69..9423dee8 100644 --- a/test/core/rename/test_cores/test_big_core_small_rename_full.yaml +++ b/test/core/rename/test_cores/test_big_core_small_rename_full.yaml @@ -23,7 +23,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -31,25 +32,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_medium_core.yaml b/test/core/rename/test_cores/test_medium_core.yaml index 979835d6..a723a59e 100644 --- a/test/core/rename/test_cores/test_medium_core.yaml +++ b/test/core/rename/test_cores/test_medium_core.yaml @@ -13,14 +13,16 @@ top.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.rename.scoreboards: @@ -28,16 +30,26 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_medium_core_full.yaml b/test/core/rename/test_cores/test_medium_core_full.yaml index 85f39c74..36e40fe3 100644 --- a/test/core/rename/test_cores/test_medium_core_full.yaml +++ b/test/core/rename/test_cores/test_medium_core_full.yaml @@ -21,14 +21,16 @@ top.cpu.core0.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.cpu.core0.rename.scoreboards: @@ -36,16 +38,26 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_small_core.yaml b/test/core/rename/test_cores/test_small_core.yaml index b154fa01..0d993d95 100644 --- a/test/core/rename/test_cores/test_small_core.yaml +++ b/test/core/rename/test_cores/test_small_core.yaml @@ -7,13 +7,15 @@ top.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.rename.scoreboards: @@ -21,14 +23,23 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_small_core_full.yaml b/test/core/rename/test_cores/test_small_core_full.yaml index 20feb903..927db2d4 100644 --- a/test/core/rename/test_cores/test_small_core_full.yaml +++ b/test/core/rename/test_cores/test_small_core_full.yaml @@ -20,13 +20,15 @@ top.cpu.core0.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.cpu.core0.rename.scoreboards: @@ -34,14 +36,23 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/vector/CMakeLists.txt b/test/core/vector/CMakeLists.txt new file mode 100644 index 00000000..8fc04eb4 --- /dev/null +++ b/test/core/vector/CMakeLists.txt @@ -0,0 +1,31 @@ +project(Vector_test) + +add_executable(Vector_test Vector_test.cpp ${SIM_BASE}/sim/OlympiaSim.cpp) +target_link_libraries(Vector_test core common_test ${STF_LINK_LIBS} mavis SPARTA::sparta) + +file(CREATE_LINK ${SIM_BASE}/mavis/json ${CMAKE_CURRENT_BINARY_DIR}/mavis_isa_files SYMBOLIC) +file(CREATE_LINK ${SIM_BASE}/arches ${CMAKE_CURRENT_BINARY_DIR}/arches SYMBOLIC) + +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/test_cores ${CMAKE_CURRENT_BINARY_DIR}/test_cores SYMBOLIC) + +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetivli_vaddvv_e8m4.json ${CMAKE_CURRENT_BINARY_DIR}/vsetivli_vaddvv_e8m4.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetvli_vaddvv_e32m1ta.json ${CMAKE_CURRENT_BINARY_DIR}/vsetvli_vaddvv_e32m1ta.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetvl_vaddvv_e64m1ta.json ${CMAKE_CURRENT_BINARY_DIR}/vsetvl_vaddvv_e64m1ta.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetivli_vaddvv_tail_e8m8ta.json ${CMAKE_CURRENT_BINARY_DIR}/vsetivli_vaddvv_tail_e8m8ta.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/multiple_vset.json ${CMAKE_CURRENT_BINARY_DIR}/multiple_vset.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vmulvx_e8m4.json ${CMAKE_CURRENT_BINARY_DIR}/vmulvx_e8m4.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vwmulvv_e8m4.json ${CMAKE_CURRENT_BINARY_DIR}/vwmulvv_e8m4.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vmseqvv_e8m4.json ${CMAKE_CURRENT_BINARY_DIR}/vmseqvv_e8m4.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vrgather.json ${CMAKE_CURRENT_BINARY_DIR}/vrgather.json SYMBOLIC) + + + +sparta_named_test(Vector_test_vsetivli Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vsetivli_vaddvv_e8m4.json) +sparta_named_test(Vector_test_vsetvli Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vsetvli_vaddvv_e32m1ta.json) +sparta_named_test(Vector_test_vsetvl Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vsetvl_vaddvv_e64m1ta.json) +sparta_named_test(Vector_test_vsetivli_tail Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vsetivli_vaddvv_tail_e8m8ta.json) +sparta_named_test(Vector_test_multiple_vset Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file multiple_vset.json) +sparta_named_test(Vector_test_vmulvx Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vmulvx_e8m4.json) +sparta_named_test(Vector_test_vmulvv Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vwmulvv_e8m4.json) +sparta_named_test(Vector_test_vmseqvv Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vmseqvv_e8m4.json) +sparta_named_test(Vector_unsupported_test Vector_test big_core.out -c test_cores/test_big_core_full_8_decode.yaml --input-file vrgather.json) diff --git a/test/core/vector/Vector_test.cpp b/test/core/vector/Vector_test.cpp new file mode 100644 index 00000000..2248db6d --- /dev/null +++ b/test/core/vector/Vector_test.cpp @@ -0,0 +1,317 @@ + +#include "CPUFactory.hpp" +#include "CoreUtils.hpp" +#include "Dispatch.hpp" +#include "MavisUnit.hpp" +#include "OlympiaAllocators.hpp" +#include "OlympiaSim.hpp" +#include "IssueQueue.hpp" +#include "test/core/dispatch/Dispatch_test.hpp" + +#include "sparta/app/CommandLineSimulator.hpp" +#include "sparta/app/Simulation.hpp" +#include "sparta/events/UniqueEvent.hpp" +#include "sparta/kernel/Scheduler.hpp" +#include "sparta/report/Report.hpp" +#include "sparta/resources/Buffer.hpp" +#include "sparta/simulation/ClockManager.hpp" +#include "sparta/sparta.hpp" +#include "sparta/statistics/StatisticSet.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/SpartaTester.hpp" + +#include +#include +#include +#include +#include +TEST_INIT + +//////////////////////////////////////////////////////////////////////////////// +// Set up the Mavis decoder globally for the testing +olympia::InstAllocator inst_allocator(2000, 1000); + +const char USAGE[] = "Usage:\n" + " \n" + "\n"; + +sparta::app::DefaultValues DEFAULTS; + +class olympia::DecodeTester +{ +public: + DecodeTester(olympia::Decode * decode) : + decode_(decode) + {} + + void test_waiting_on_vset() + { + EXPECT_TRUE(decode_->waiting_on_vset_ == true); + } + + void test_waiting_on_vset(const bool expected_val) + { + EXPECT_TRUE(decode_->waiting_on_vset_ == expected_val); + } + + void test_vl(const uint32_t expected_vl) + { + EXPECT_TRUE(decode_->VCSRs_.vl == expected_vl); + } + + void test_sew(const uint32_t expected_sew) + { + EXPECT_TRUE(decode_->VCSRs_.sew == expected_sew); + } + + void test_lmul(const uint32_t expected_lmul) + { + EXPECT_TRUE(decode_->VCSRs_.lmul == expected_lmul); + } + + void test_vlmax(const uint32_t expected_vlmax) + { + EXPECT_TRUE(decode_->VCSRs_.vlmax == expected_vlmax); + } + + void test_vta(const bool expected_vta) + { + EXPECT_TRUE(decode_->VCSRs_.vta == expected_vta); + } + +private: + olympia::Decode * decode_; +}; + +class olympia::ROBTester +{ +public: + ROBTester(olympia::ROB * rob) : + rob_(rob) + {} + + void test_num_insts_retired(const uint64_t expected_num_insts_retired) + { + EXPECT_TRUE(rob_->num_retired_ == expected_num_insts_retired); + } + + void test_num_uops_retired(const uint64_t expected_num_uops_retired) + { + EXPECT_TRUE(rob_->num_uops_retired_ == expected_num_uops_retired); + } + + void test_last_inst_has_tail(const bool expected_tail) + { + EXPECT_TRUE(rob_->last_inst_retired_ != nullptr); + EXPECT_TRUE(rob_->last_inst_retired_->hasTail() == expected_tail); + } + +private: + olympia::ROB * rob_; +}; + +void runTests(int argc, char **argv) + { + DEFAULTS.auto_summary_default = "off"; + std::vector datafiles; + std::string input_file; + bool enable_vector; + + sparta::app::CommandLineSimulator cls(USAGE, DEFAULTS); + auto &app_opts = cls.getApplicationOptions(); + app_opts.add_options()("output_file", + sparta::app::named_value>( + "output_file", &datafiles), + "Specifies the output file")( + "input-file", + sparta::app::named_value("INPUT_FILE", &input_file) + ->default_value(""), + "Provide a JSON instruction stream", + "Provide a JSON file with instructions to run through Execute")( + "enable_vector", + sparta::app::named_value("enable_vector", &enable_vector) + ->default_value(false), + "Enable the experimental vector pipelines"); + + po::positional_options_description &pos_opts = cls.getPositionalOptions(); + pos_opts.add("output_file", -1); // example, look for the at the end + + int err_code = 0; + if (!cls.parse(argc, argv, err_code)) + { + sparta_assert(false, + "Command line parsing failed"); // Any errors already printed to cerr + } + + sparta_assert(false == datafiles.empty(), + "Need an output file as the last argument of the test"); + + uint64_t ilimit = 0; + uint32_t num_cores = 1; + bool show_factories = false; + sparta::Scheduler scheduler; + OlympiaSim sim("simple", scheduler, + num_cores, // cores + input_file, ilimit, show_factories); + sparta::RootTreeNode *root_node = sim.getRoot(); + cls.populateSimulation(&sim); + + olympia::Decode *my_decode = \ + root_node->getChild("cpu.core0.decode")->getResourceAs(); + olympia::DecodeTester decode_tester {my_decode}; + + olympia::ROB *my_rob = \ + root_node->getChild("cpu.core0.rob")->getResourceAs(); + olympia::ROBTester rob_tester {my_rob}; + + if (input_file.find("vsetivli_vaddvv.json") != std::string::npos) + { + // Test Decode (defaults) + decode_tester.test_lmul(1); + decode_tester.test_vl(128); + decode_tester.test_vta(false); + decode_tester.test_sew(8); + decode_tester.test_vlmax(128); + + cls.runSimulator(&sim); + + // Test after vsetivli + decode_tester.test_waiting_on_vset(false); + decode_tester.test_lmul(4); + decode_tester.test_vl(512); + decode_tester.test_vta(false); + decode_tester.test_sew(8); + decode_tester.test_vlmax(512); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vset + 4 vadd.vv uops + rob_tester.test_num_uops_retired(5); + rob_tester.test_last_inst_has_tail(false); + } + else if(input_file.find("vsetvli_vaddvv.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Decode + decode_tester.test_waiting_on_vset(false); + decode_tester.test_lmul(1); + decode_tester.test_vl(32); + decode_tester.test_vta(true); + decode_tester.test_sew(32); + decode_tester.test_vlmax(32); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vset + 1 vadd.vv uop + rob_tester.test_num_uops_retired(2); + rob_tester.test_last_inst_has_tail(false); + } + else if(input_file.find("vsetvl_vaddvv.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Decode + decode_tester.test_waiting_on_vset(false); + decode_tester.test_lmul(1); + decode_tester.test_vl(16); + decode_tester.test_vta(true); + decode_tester.test_sew(64); + decode_tester.test_vlmax(16); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vset + 1 vadd.vv uop + rob_tester.test_num_uops_retired(2); + rob_tester.test_last_inst_has_tail(false); + } + else if(input_file.find("vsetivli_vaddvv_tail.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Decode + decode_tester.test_lmul(8); + decode_tester.test_vl(900); + decode_tester.test_vta(false); + decode_tester.test_sew(8); + decode_tester.test_vlmax(1024); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vset + 8 vadd.vv uop + rob_tester.test_num_uops_retired(9); + rob_tester.test_last_inst_has_tail(true); + } + else if(input_file.find("multiple_vset.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Decode (last vset) + decode_tester.test_waiting_on_vset(false); + decode_tester.test_lmul(8); + decode_tester.test_vl(1024); + decode_tester.test_vta(false); + decode_tester.test_sew(8); + decode_tester.test_vlmax(1024); + + // Test Retire + rob_tester.test_num_insts_retired(6); + // vset + 2 vadd.vv + vset + 4 vadd.vv uop + vset + 8 vadd.vv + rob_tester.test_num_uops_retired(17); + } + else if(input_file.find("vmulvx.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Retire + rob_tester.test_num_insts_retired(3); + // vadd + 4 vmul.vx uop + rob_tester.test_num_uops_retired(6); + rob_tester.test_last_inst_has_tail(false); + + // TODO: Test source values for all uops + } + else if(input_file.find("vwmulvv.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vadd + 8 vwmul.vv uop + rob_tester.test_num_uops_retired(9); + rob_tester.test_last_inst_has_tail(false); + + // TODO: Test destination values for all uops + } + else if(input_file.find("vmseqvv.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vadd + 4 vmseq.vv uops + rob_tester.test_num_uops_retired(5); + rob_tester.test_last_inst_has_tail(false); + + // TODO: Test destination values for all uops + } + else if(input_file.find("vrgather.json") != std::string::npos) + { + // Unsupported vector instructions are expected to make the simulator to throw + bool sparta_exception_fired = false; + try { + cls.runSimulator(&sim); + } catch (const sparta::SpartaException& ex) { + sparta_exception_fired = true; + } + EXPECT_TRUE(sparta_exception_fired); + } +} + +int main(int argc, char **argv) + { + runTests(argc, argv); + + REPORT_ERROR; + return (int)ERROR_CODE; +} diff --git a/test/core/vector/multiple_vset.json b/test/core/vector/multiple_vset.json new file mode 100644 index 00000000..db44dbef --- /dev/null +++ b/test/core/vector/multiple_vset.json @@ -0,0 +1,44 @@ +[ + { + "mnemonic": "vsetvli", + "rs1": 0, + "vtype": "0x1", + "rd": 1, + "vl": 512, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 8, + "vs2": 10, + "vd": 12 + }, + { + "mnemonic": "vsetvli", + "rs1": 0, + "vtype": "0x2", + "rd": 1, + "vl": 512, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 8, + "vs2": 12, + "vd": 16 + }, + { + "mnemonic": "vsetvli", + "rs1": 2, + "vtype": "0x3", + "rd": 1, + "vl": 1024, + "vta": 0 + }, + { + "mnemonic": "vadd.vv", + "vs1": 8, + "vs2": 16, + "vd": 24 + } +] diff --git a/test/core/vector/test_cores/test_big_core_full.yaml b/test/core/vector/test_cores/test_big_core_full.yaml new file mode 100644 index 00000000..2ea2b8d1 --- /dev/null +++ b/test/core/vector/test_cores/test_big_core_full.yaml @@ -0,0 +1,69 @@ +# +# Set up the pipeline for a 8-wide machine +# +top.cpu.core0: + fetch.params.num_to_fetch: 8 + decode.params.num_to_decode: 3 + rename.params.num_integer_renames: 64 + rename.params.num_float_renames: 64 + rename.params.num_vector_renames: 64 + dispatch.params.num_to_dispatch: 8 + rob.params.num_to_retire: 8 + dcache.params: + l1_size_kb: 64 + +top.cpu.core0.extension.core_extensions: + pipelines: + [ + ["int"], # alu0 + ["int", "div"], # alu1 + ["int", "mul"], + ["int", "mul", "i2f", "cmov"], + ["int"], + ["int"], + ["float", "faddsub", "fmac"], + ["float", "f2i"], + ["br"], + ["br"], + ["vint", "vset", "vdiv", "vmul"] + ] + issue_queue_to_pipe_map: + [ + ["0", "1"], + ["2", "3"], + ["4", "5"], + ["6", "7"], + ["8", "9"], + ["10"] + ] +top.cpu.core0.rename.scoreboards: + # From + # | + # V + integer.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + float.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/vector/test_cores/test_big_core_full_8_decode.yaml b/test/core/vector/test_cores/test_big_core_full_8_decode.yaml new file mode 100644 index 00000000..26363cfd --- /dev/null +++ b/test/core/vector/test_cores/test_big_core_full_8_decode.yaml @@ -0,0 +1,69 @@ +# +# Set up the pipeline for a 8-wide machine +# +top.cpu.core0: + fetch.params.num_to_fetch: 8 + decode.params.num_to_decode: 8 + rename.params.num_integer_renames: 64 + rename.params.num_float_renames: 64 + rename.params.num_vector_renames: 64 + dispatch.params.num_to_dispatch: 8 + rob.params.num_to_retire: 8 + dcache.params: + l1_size_kb: 64 + +top.cpu.core0.extension.core_extensions: + pipelines: + [ + ["int"], # alu0 + ["int", "div"], # alu1 + ["int", "mul"], + ["int", "mul", "i2f", "cmov"], + ["int"], + ["int"], + ["float", "faddsub", "fmac"], + ["float", "f2i"], + ["br"], + ["br"], + ["vint", "vset", "vdiv", "vmul"] + ] + issue_queue_to_pipe_map: + [ + ["0", "1"], + ["2", "3"], + ["4", "5"], + ["6", "7"], + ["8", "9"], + ["10"] + ] +top.cpu.core0.rename.scoreboards: + # From + # | + # V + integer.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + float.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/vector/vmseqvv_e8m4.json b/test/core/vector/vmseqvv_e8m4.json new file mode 100644 index 00000000..c8651d58 --- /dev/null +++ b/test/core/vector/vmseqvv_e8m4.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 512, + "vta": 0 + }, + { + "mnemonic": "vmseq.vv", + "vd": 12, + "vs2": 8, + "vs1": 4 + } +] diff --git a/test/core/vector/vmulvx_e8m4.json b/test/core/vector/vmulvx_e8m4.json new file mode 100644 index 00000000..c6f97e61 --- /dev/null +++ b/test/core/vector/vmulvx_e8m4.json @@ -0,0 +1,22 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 512, + "vta": 0 + }, + { + "mnemonic": "add", + "rs1": 1, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "vmul.vx", + "vd": 5, + "vs2": 4, + "rs1": 3 + } +] diff --git a/test/core/vector/vrgather.json b/test/core/vector/vrgather.json new file mode 100644 index 00000000..6d67a00d --- /dev/null +++ b/test/core/vector/vrgather.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetvl", + "rs1": 0, + "vtype": "0x18", + "rd": 1, + "vl": 512, + "vta": 1 + }, + { + "mnemonic": "vrgather.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] diff --git a/test/core/vector/vsetivli_vaddvv_e8m4.json b/test/core/vector/vsetivli_vaddvv_e8m4.json new file mode 100644 index 00000000..dde1a6ba --- /dev/null +++ b/test/core/vector/vsetivli_vaddvv_e8m4.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 512, + "vta": 0 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] diff --git a/test/core/vector/vsetivli_vaddvv_tail_e8m8ta.json b/test/core/vector/vsetivli_vaddvv_tail_e8m8ta.json new file mode 100644 index 00000000..6855a96f --- /dev/null +++ b/test/core/vector/vsetivli_vaddvv_tail_e8m8ta.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x3", + "vl": 900, + "vta": 0 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] diff --git a/test/core/vector/vsetvl_vaddvv_e64m1ta.json b/test/core/vector/vsetvl_vaddvv_e64m1ta.json new file mode 100644 index 00000000..22e5a95d --- /dev/null +++ b/test/core/vector/vsetvl_vaddvv_e64m1ta.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetvl", + "rs1": 0, + "vtype": "0x18", + "rd": 1, + "vl": 16, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] diff --git a/test/core/vector/vsetvli_vaddvv_e32m1ta.json b/test/core/vector/vsetvli_vaddvv_e32m1ta.json new file mode 100644 index 00000000..14749801 --- /dev/null +++ b/test/core/vector/vsetvli_vaddvv_e32m1ta.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetvli", + "rs1": 2, + "vtype": "0x10", + "rd": 1, + "vl": 32, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] diff --git a/test/core/vector/vwmulvv_e8m4.json b/test/core/vector/vwmulvv_e8m4.json new file mode 100644 index 00000000..5b094e56 --- /dev/null +++ b/test/core/vector/vwmulvv_e8m4.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 512, + "vta": 0 + }, + { + "mnemonic": "vwmul.vv", + "vd": 12, + "vs2": 8, + "vs1": 4 + } +]