From a8d71b0fd498755d34f7a0d707ae401b7fc37980 Mon Sep 17 00:00:00 2001
From: Ved Shanbhogue <ved@rivosinc.com>
Date: Thu, 12 Sep 2024 19:37:26 -0500
Subject: [PATCH] fix error in reading right sstatus

---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 60f6a89bc7..a5702b852d 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -446,7 +446,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
   // An unexpected trap - a trap when SDT is 1 - traps to M-mode
   if ((state.prv <= PRV_S && bit < max_xlen) &&
       (((vsdeleg >> bit) & 1)  || ((hsdeleg >> bit) & 1))) {
-    reg_t s = curr_virt ? state.nonvirtual_sstatus->read() : state.sstatus->read();
+    reg_t s = curr_virt ? state.sstatus->read() : state.nonvirtual_sstatus->read();
     supv_double_trap = get_field(s, MSTATUS_SDT);
     if (supv_double_trap)
       vsdeleg = hsdeleg = 0;