From 56e020419d482a5b7e74911eb4bba993af2eab31 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 5 Sep 2024 13:43:25 -0700 Subject: [PATCH] Only implement one solution for native triggers. When S-mode is present, use option 1 (disable triggers in M-mode unless MIE is set) from the Debug Spec. When S-mode is not present, use option 2 (implement mte and mpte bits in tcontrol). See discussion in #1777. --- riscv/csr_init.cc | 5 +++-- riscv/triggers.cc | 34 +++++++++++++++++++++++++--------- 2 files changed, 28 insertions(+), 11 deletions(-) diff --git a/riscv/csr_init.cc b/riscv/csr_init.cc index d72c925041..2c2760f97a 100644 --- a/riscv/csr_init.cc +++ b/riscv/csr_init.cc @@ -205,13 +205,14 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa) add_csr(CSR_TDATA2, tdata2 = std::make_shared(proc, CSR_TDATA2)); add_csr(CSR_TDATA3, std::make_shared(proc, CSR_TDATA3)); add_csr(CSR_TINFO, std::make_shared(proc, CSR_TINFO)); - add_csr(CSR_TCONTROL, tcontrol = std::make_shared(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0)); + if (!proc->extension_enabled_const('S')) { + add_csr(CSR_TCONTROL, tcontrol = std::make_shared(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0)); + } } else { add_csr(CSR_TDATA1, std::make_shared(proc, CSR_TDATA1, 0)); add_csr(CSR_TDATA2, tdata2 = std::make_shared(proc, CSR_TDATA2, 0)); add_csr(CSR_TDATA3, std::make_shared(proc, CSR_TDATA3, 0)); add_csr(CSR_TINFO, std::make_shared(proc, CSR_TINFO, 0)); - add_csr(CSR_TCONTROL, tcontrol = std::make_shared(proc, CSR_TCONTROL, 0)); } unsigned scontext_length = (xlen == 32 ? 16 : 32); // debug spec suggests 16-bit for RV32 and 32-bit for RV64 add_supervisor_csr(CSR_SCONTEXT, scontext = std::make_shared(proc, CSR_SCONTEXT, (reg_t(1) << scontext_length) - 1, 0)); diff --git a/riscv/triggers.cc b/riscv/triggers.cc index a93d2b149f..e80fd58327 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -66,7 +66,12 @@ bool trigger_t::common_match(processor_t * const proc, bool use_prev_prv) const auto state = proc->get_state(); auto prv = use_prev_prv ? state->prev_prv : state->prv; auto v = use_prev_prv ? state->prev_v : state->v; - auto m_enabled = get_action() != 0 || (tcontrol_value(state) & CSR_TCONTROL_MTE); + bool m_enabled = get_action() != 0; + if (!m_enabled && proc->extension_enabled('S')) { + m_enabled |= tcontrol_value(state) & CSR_TCONTROL_MTE; + } else { + m_enabled |= state->mstatus->read() & MSTATUS_MIE; + } return (prv < PRV_M || m_enabled) && mode_match(prv, v) && textra_match(proc); } @@ -121,14 +126,25 @@ bool trigger_t::allow_action(processor_t * const proc) const { const state_t *state = proc->get_state(); if (get_action() == ACTION_DEBUG_EXCEPTION) { - const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE; - const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE; - const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE; - const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1; - const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1; - return (state->prv != PRV_M || mstatus_mie) && - (state->prv != PRV_S || state->v || !medeleg_breakpoint || sstatus_sie) && - (state->prv != PRV_S || !state->v || !medeleg_breakpoint || !hedeleg_breakpoint || vsstatus_sie); + if (proc->extension_enabled('S')) { + // The hardware prevents triggers with action=0 from matching or firing + // while in M-mode and while MIE in mstatus is 0. If medeleg [3]=1 then it + // prevents triggers with action=0 from matching or firing while in S-mode + // and while SIE in sstatus is 0. If medeleg [3]=1 and hedeleg [3]=1 then + // it prevents triggers with action=0 from matching or firing while in + // VS-mode and while SIE in vstatus is 0. + const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE; + const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE; + const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE; + const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1; + const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1; + return (state->prv != PRV_M || mstatus_mie) && + (state->prv != PRV_S || state->v || !medeleg_breakpoint || sstatus_sie) && + (state->prv != PRV_S || !state->v || !medeleg_breakpoint || !hedeleg_breakpoint || vsstatus_sie); + } else { + // mte and mpte in tcontrol is implemented. medeleg [3] is hard-wired to 0. + return (state->prv != PRV_M) || (tcontrol_value(state) & CSR_TCONTROL_MTE); + } } return true; }