From 1445760a3d82a7f82d3cf5d0dc8c65ca06a7f3a8 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Tue, 15 Aug 2023 23:18:16 +0530 Subject: [PATCH 1/6] Fix set indexing error. --- riscv_ctg/generator.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index d847f5ec..c52224e6 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -341,9 +341,8 @@ def eval_func(cond): locals()[var] = val return eval(cond) sat_set = set(filter(eval_func,op_comb)) - cond_str += ", ".join([var+"=="+solution[var] for var in cond_vars]+[op_comb[i] for i in sat_set]) + cond_str += ", ".join([var+"=="+solution[var] for var in cond_vars]+list(sat_set)) op_tuple.append(cond_str) - op_comb = op_comb - sat_set problem.reset() solutions.append( tuple(op_tuple) ) From 045fe127fa1c379bf1ebdced88c73a5b1144b539 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Tue, 15 Aug 2023 23:43:09 +0530 Subject: [PATCH 2/6] Fixed K instructions issue with dealing hex integers. --- riscv_ctg/generator.py | 43 ++++++++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 16 deletions(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index c52224e6..035b97d5 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -24,6 +24,12 @@ twos_xlen = lambda x: twos(x,xlen) +def toint(x: str): + if '0x' in x: + return int(x,16) + else: + return int(x) + def get_rm(opcode): if any([x in opcode for x in ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','fmin','fmax', @@ -790,13 +796,13 @@ def eval_inst_coverage(coverpoints,instr): if self.fmt in ['jformat','bformat'] or instr['inst'] in \ ['c.beqz','c.bnez','c.jal','c.j','c.jalr']: var_dict['imm_val'] = \ - (-1 if instr['label'] == '1b' else 1) * int(instr['imm_val']) + (-1 if instr['label'] == '1b' else 1) * toint(instr['imm_val']) else: - var_dict['imm_val'] = int(instr['imm_val']) + var_dict['imm_val'] = toint(instr['imm_val']) elif key == 'rm_val': - var_dict['rm_val'] = int(rm_dict[instr['rm_val']]) + var_dict['rm_val'] = toint(rm_dict[instr['rm_val']]) else: - var_dict[key] = int(instr[key]) + var_dict[key] = toint(instr[key]) for key in self.op_vars: var_dict[key] = instr[key] @@ -1160,7 +1166,7 @@ def correct_val(self,instr_dict): if self.operation: for i in range(len(instr_dict)): for var in self.val_vars: - locals()[var]=int(instr_dict[i][var]) + locals()[var]=toint(instr_dict[i][var]) correctval = eval(self.operation) instr_dict[i]['correctval'] = str(normalise(correctval,instr_dict[i])) else: @@ -1180,28 +1186,33 @@ def reformat_instr(self, instr_dict): # instr_dict is already in the desired format for instructions that perform SIMD operations, or Zpsfoperand instructions in RV32. if 'bit_width' in self.opnode or (self.xlen == 32 and 'p64_profile' in self.opnode): return instr_dict + # Fix all K instructions to be unsigned to output unsigned hex values into the test. Its + # only a cosmetic difference and has no impact on coverage + is_unsigned = any('IZk' in isa for isa in self.opnode['isa']) for i in range(len(instr_dict)): for field in instr_dict[i]: - # if xlen == 32: - # if instr_dict[i]['inst'] in ['sltu', 'sltiu', 'bgeu', 'bltu']: - # size = '>I' - # else: - # size = '>i' - # else: - # if instr_dict[i]['inst'] in ['sltu', 'sltiu', 'bgeu', 'bltu']: - # size = '>Q' - # else: - # size = '>q' + if xlen == 32: + if instr_dict[i]['inst'] in ['sltu', 'sltiu', 'bgeu', 'bltu'] or is_unsigned: + size = '>I' + else: + size = '>i' + else: + if instr_dict[i]['inst'] in ['sltu', 'sltiu', 'bgeu', 'bltu'] or is_unsigned: + size = '>Q' + else: + size = '>q' if 'val' in field and field != 'correctval' and field != 'valaddr_reg' and \ field != 'val_section' and field != 'val_offset' and field != 'rm_val': - value = instr_dict[i][field] + value = (instr_dict[i][field]).strip() + print(value) if '0x' in value: value = '0x' + value[2:].zfill(int(self.xlen/4)) value = struct.unpack(size, bytes.fromhex(value[2:]))[0] else: value = int(value) # value = '0x' + struct.pack(size,value).hex() + print("test",hex(value)) instr_dict[i][field] = hex(value) return instr_dict From 3ac5b48a2237e1a88f603ca84a07278dadbb5a68 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Tue, 15 Aug 2023 23:43:20 +0530 Subject: [PATCH 3/6] =?UTF-8?q?Bump=20version:=200.11.0=20=E2=86=92=200.11?= =?UTF-8?q?.1=20Fixes=20#72?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- riscv_ctg/__init__.py | 2 +- setup.cfg | 2 +- setup.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py index 349aa68e..e0d030a3 100644 --- a/riscv_ctg/__init__.py +++ b/riscv_ctg/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'incorebot@gmail.com' -__version__ = '0.11.0' +__version__ = '0.11.1' diff --git a/setup.cfg b/setup.cfg index 9e839e82..878241cf 100644 --- a/setup.cfg +++ b/setup.cfg @@ -1,5 +1,5 @@ [bumpversion] -current_version = 0.11.0 +current_version = 0.11.1 commit = True tag = True diff --git a/setup.py b/setup.py index a90fdd23..edf39544 100644 --- a/setup.py +++ b/setup.py @@ -26,7 +26,7 @@ def read_requires(): setup( name='riscv_ctg', - version='0.11.0', + version='0.11.1', description="RISC-V CTG", long_description=readme + '\n\n', classifiers=[ From 6c5583572f9379d8ced45be964e316e89a720891 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Tue, 15 Aug 2023 23:57:18 +0530 Subject: [PATCH 4/6] Update changelog. --- CHANGELOG.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 95d2f252..041ac26c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,10 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). +## [0.11.1] - 2023-08-15 +- Fixed hex values handling for K extensions +- Fixed set indexing error during opcomb gen + ## [0.11.0] - 2022-12-11 - Added support for csr_comb test generation From 9b16d7cc1679363e074ebdf152d1ecb8a3a4b910 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Wed, 16 Aug 2023 00:24:01 +0530 Subject: [PATCH 5/6] Fixes #66 --- riscv_ctg/data/fd.yaml | 6 +++--- riscv_ctg/data/imc.yaml | 9 --------- riscv_ctg/data/template.yaml | 25 +------------------------ 3 files changed, 4 insertions(+), 36 deletions(-) diff --git a/riscv_ctg/data/fd.yaml b/riscv_ctg/data/fd.yaml index 63047585..4a6e60ab 100644 --- a/riscv_ctg/data/fd.yaml +++ b/riscv_ctg/data/fd.yaml @@ -1312,7 +1312,7 @@ fcvt.s.wu: val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; fcsr_val: $fcsr*/ TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) - + fcvt.d.w: sig: stride: 2 @@ -1681,7 +1681,7 @@ fcvt.s.l: val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; fcsr_val: $fcsr*/ TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) - + fcvt.s.lu: sig: stride: 2 @@ -1708,4 +1708,4 @@ fcvt.s.lu: val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; fcsr_val: $fcsr*/ TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) - + diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index e71e23d5..571b6273 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -15,7 +15,6 @@ add: rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -36,7 +35,6 @@ sub: rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -58,7 +56,6 @@ addw: rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -79,7 +76,6 @@ subw: rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -100,7 +96,6 @@ and: rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -121,7 +116,6 @@ or: rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -142,7 +136,6 @@ slt: rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -163,7 +156,6 @@ sltu: rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -1455,7 +1447,6 @@ c.nop: rs1_data: "['x0']" rs1_val_data: "[0]" template: |- - // $comment // opcode:$inst; immval:$imm_val TEST_CNOP_OP($inst, $testreg, $imm_val, $swreg, $offset) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index a283d96c..eb5a4218 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -1480,7 +1480,6 @@ clz: rd_op_data: *all_regs rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -1498,7 +1497,6 @@ clzw: rd_op_data: *all_regs rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -1516,7 +1514,6 @@ cpop: rd_op_data: *all_regs rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -1534,7 +1531,6 @@ cpopw: rd_op_data: *all_regs rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -1552,7 +1548,6 @@ ctz: rd_op_data: *all_regs rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -1570,7 +1565,6 @@ ctzw: rd_op_data: *all_regs rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -1590,7 +1584,6 @@ max: rs1_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)' rs2_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -1636,7 +1629,6 @@ maxu: rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -1682,7 +1674,6 @@ min: rs1_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)' rs2_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -1728,7 +1719,6 @@ minu: rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -1755,7 +1745,6 @@ urcrsa16: rs2_h2_val_data: 'gen_usign_dataset(16)' rs2_h3_val_data: 'gen_usign_dataset(16)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -1799,7 +1788,6 @@ orc.b: rd_op_data: *all_regs rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[16909320,33818625,67633410,134283780,72624976414508040,145249888404506625,290483284134592770,576744443617542660]' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -1823,7 +1811,6 @@ orn: rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -1850,7 +1837,6 @@ ukcrsa16: rs2_h2_val_data: 'gen_usign_dataset(16)' rs2_h3_val_data: 'gen_usign_dataset(16)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) @@ -1877,7 +1863,6 @@ stas16: rs2_h2_val_data: 'gen_sign_dataset(16)' rs2_h3_val_data: 'gen_sign_dataset(16)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -1925,7 +1910,6 @@ rev8: rd_op_data: *all_regs rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+gen_bitmanip_dataset(xlen,False)+[16909320,33818625,67633410,134283780,72624976414508040,145249888404506625,290483284134592770,576744443617542660]' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; LI($rs1,$rs1_val) @@ -1953,7 +1937,6 @@ ror: rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -1980,7 +1963,6 @@ urstas16: rs2_h2_val_data: 'gen_usign_dataset(16)' rs2_h3_val_data: 'gen_usign_dataset(16)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) @@ -2007,7 +1989,6 @@ kstas16: rs2_h2_val_data: 'gen_sign_dataset(16)' rs2_h3_val_data: 'gen_sign_dataset(16)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) @@ -2060,7 +2041,7 @@ rori: // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) - + roriw: sig: stride: 1 @@ -2201,7 +2182,6 @@ sext.b: rd_op_data: *all_regs rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -2219,7 +2199,6 @@ sext.h: rd_op_data: *all_regs rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[65408]' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -2314,7 +2293,6 @@ zext.h: rd_op_data: *all_regs rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' template: |- - // $comment // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -2338,7 +2316,6 @@ clmul: rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- - // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) From e41de5ff119a14eaf29d0abcbc2b155246504a73 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Wed, 16 Aug 2023 00:24:53 +0530 Subject: [PATCH 6/6] Update changelog --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 041ac26c..14d689c5 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,6 +5,7 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.htm ## [0.11.1] - 2023-08-15 - Fixed hex values handling for K extensions - Fixed set indexing error during opcomb gen +- Fixed whitespaces on empty lines in yaml template files. ## [0.11.0] - 2022-12-11 - Added support for csr_comb test generation