From 56fb258e52413a82cc379280af8a966871375639 Mon Sep 17 00:00:00 2001 From: Ali Tariq Date: Thu, 22 Jun 2023 19:15:15 +0500 Subject: [PATCH 001/101] Added corner case for dividing most neg number with -1 --- sample_cgfs/dataset.cgf | 1 + 1 file changed, 1 insertion(+) diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index bf0f52e4..8a28d257 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -286,6 +286,7 @@ datasets: 'rs1_val > 0 and rs2_val < 0': 0 'rs1_val < 0 and rs2_val < 0': 0 'rs1_val < 0 and rs2_val > 0': 0 + 'rs1_val == -0x8000000000000000 and rs2_val == -0x01': 0 'rs1_val == rs2_val': 0 'rs1_val != rs2_val': 0 From 650fca7e2d29d6a62a251373de34db37b3431d5e Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Wed, 26 Jul 2023 19:48:00 -0500 Subject: [PATCH 002/101] add paired register support for double xlen instructions in zacas extension --- riscv_ctg/generator.py | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index d847f5ec..5570068b 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -71,7 +71,8 @@ def get_rm(opcode): 'pphrrformat': ['rs1', 'rs2', 'rd'], 'ppbrrformat': ['rs1', 'rs2', 'rd'], 'prrformat': ['rs1', 'rs2', 'rd'], - 'prrrformat': ['rs1', 'rs2', 'rs3', 'rd'] + 'prrrformat': ['rs1', 'rs2', 'rs3', 'rd'], + 'dcasrformat': ['rs1', 'rs2', 'rd'] } ''' Dictionary mapping instruction formats to operands used by those formats ''' @@ -117,7 +118,8 @@ def get_rm(opcode): 'pphrrformat': '["rs1_val"] + simd_val_vars("rs2", xlen, 16)', 'ppbrrformat': '["rs1_val"] + simd_val_vars("rs2", xlen, 8)', 'prrformat': '["rs1_val", "rs2_val"]', - 'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']" + 'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']", + 'dcasrformat': '["rs1_val", "rs2_val"]' } ''' Dictionary mapping instruction formats to operand value variables used by those formats ''' @@ -868,6 +870,14 @@ def eval_inst_coverage(coverpoints,instr): elif 'bit_width' in self.opnode: concat_simd_data(final_instr, self.xlen, self.opnode['bit_width']) + ''' + Zacas introduces double xlen cas operations that need paired source and destination registers + ''' + if any('Zacas' in isa for isa in self.opnode['isa']): + if 'dcas_profile' in self.opnode: + gen_pair_reg_data(final_instr, self.xlen, self.opnode['bit_width'], self.opnode['dcas_profile']) + + return final_instr def valreg(self,instr_dict): @@ -896,6 +906,9 @@ def valreg(self,instr_dict): if self.xlen == 32 and 'p64_profile' in self.opnode: p64_profile = self.opnode['p64_profile'] paired_regs = self.opnode['p64_profile'].count('p') + if 'dcas_profile' in self.opnode: + dcas_profile = self.opnode['dcas_profile'] + paired_regs = self.opnode['dcas_profile'].count('p') regset = e_regset if 'e' in self.base_isa else default_regset total_instr = len(instr_dict) @@ -1016,6 +1029,9 @@ def swreg(self, instr_dict): if self.xlen == 32 and 'p64_profile' in self.opnode: p64_profile = self.opnode['p64_profile'] paired_regs = self.opnode['p64_profile'].count('p') + if 'dcas_profile' in self.opnode: + dcas_profile = self.opnode['dcas_profile'] + paired_regs = self.opnode['dcas_profile'].count('p') regset = e_regset if 'e' in self.base_isa else default_regset total_instr = len(instr_dict) @@ -1102,6 +1118,9 @@ def testreg(self, instr_dict): if self.xlen == 32 and 'p64_profile' in self.opnode: p64_profile = self.opnode['p64_profile'] paired_regs = p64_profile.count('p') + if 'dcas_profile' in self.opnode: + dcas_profile = self.opnode['dcas_profile'] + paired_regs = dcas_profile.count('p') for instr in instr_dict: if 'rs1' in instr and instr['rs1'] in available_reg: @@ -1154,6 +1173,11 @@ def correct_val(self,instr_dict): if len(p64_profile) >= 3 and p64_profile[0]=='p': for i in range(len(instr_dict)): instr_dict[i]['correctval_hi'] = '0' + if 'dcas_profile' in self.opnode: + dcas_profile = self.opnode['dcas_profile'] + if len(dcas_profile) >= 3 and dcas_profile[0]=='p': + for i in range(len(instr_dict)): + instr_dict[i]['correctval_hi'] = '0' if self.fmt in ['caformat','crformat']: normalise = lambda x,y: 0 if y['rs1']=='x0' else x else: @@ -1181,6 +1205,10 @@ def reformat_instr(self, instr_dict): # instr_dict is already in the desired format for instructions that perform SIMD operations, or Zpsfoperand instructions in RV32. if 'bit_width' in self.opnode or (self.xlen == 32 and 'p64_profile' in self.opnode): return instr_dict + if any('Zacas' in isa for isa in self.opnode['isa']): + # instr_dict is already in the desired format for Zacas dcas instructions + if 'bit_width' in self.opnode or 'dcas_profile' in self.opnode: + return instr_dict for i in range(len(instr_dict)): for field in instr_dict[i]: @@ -1259,9 +1287,10 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str): if any('IP' in isa for isa in self.opnode['isa']): code.append("RVTEST_VXSAT_ENABLE()") - if self.xlen == 32 and 'p64_profile' in self.opnode: p64_profile = self.opnode['p64_profile'] + if 'dcas_profile' in self.opnode: + dcas_profile = self.opnode['dcas_profile'] n = 0 is_int_src = any([self.opcode.endswith(x) for x in ['.x','.w','.l','.wu','.lu']]) From cef5d73bd2f619c09f2e4357098f74a73e7013e0 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Wed, 26 Jul 2023 19:48:24 -0500 Subject: [PATCH 003/101] add double xlen cas format --- riscv_ctg/cross_comb.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/cross_comb.py b/riscv_ctg/cross_comb.py index 2b8172f9..25112a26 100644 --- a/riscv_ctg/cross_comb.py +++ b/riscv_ctg/cross_comb.py @@ -51,7 +51,8 @@ 'pphrrformat' : '$instr $rd, $rs1, $rs2', 'ppbrrformat' : '$instr $rd, $rs1, $rs2', 'prrformat' : '$instr ', - 'prrrformat' : '$instr' + 'prrrformat' : '$instr', + 'dcasrformat' : '$instr ' } '''Dictionary to store instruction formats''' @@ -497,4 +498,4 @@ def write_test(self, fprefix, cgf_node, usage_str, cov_label, full_solution): label = cov_label, extension = extension ) - ) \ No newline at end of file + ) From ac2ad67dd89ad3e7615f1ec52ded635c76f06ea4 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Wed, 26 Jul 2023 19:49:03 -0500 Subject: [PATCH 004/101] support paired registers - 64 and 128 bits - for zacas --- riscv_ctg/dsp_function.py | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/riscv_ctg/dsp_function.py b/riscv_ctg/dsp_function.py index 7f892243..4b0f12bd 100644 --- a/riscv_ctg/dsp_function.py +++ b/riscv_ctg/dsp_function.py @@ -175,9 +175,14 @@ def gen_pair_reg_data(instr_dict, xlen, _bit_width, p64_profile): else: bit_width1, bit_width2 = _bit_width, _bit_width - rs1_width = 64 if len(p64_profile) >= 3 and p64_profile[1]=='p' else xlen - rs2_width = 64 if len(p64_profile) >= 3 and p64_profile[2]=='p' else xlen - rd_width = 64 if len(p64_profile) >= 3 and p64_profile[0]=='p' else xlen + if xlen == 32: + rs1_width = 64 if len(p64_profile) >= 3 and p64_profile[1]=='p' else xlen + rs2_width = 64 if len(p64_profile) >= 3 and p64_profile[2]=='p' else xlen + rd_width = 64 if len(p64_profile) >= 3 and p64_profile[0]=='p' else xlen + else: + rs1_width = 128 if len(p64_profile) >= 3 and p64_profile[1]=='p' else xlen + rs2_width = 128 if len(p64_profile) >= 3 and p64_profile[2]=='p' else xlen + rd_width = 128 if len(p64_profile) >= 3 and p64_profile[0]=='p' else xlen for instr in instr_dict: if 'rs1' in instr: From 6cab933acae17a9d58b16494033736f13cc3c62e Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Wed, 26 Jul 2023 19:52:33 -0500 Subject: [PATCH 005/101] add templates for amocas.w, amocas.d (different for for RV32 and RV64), and amocas.d --- riscv_ctg/data/template.yaml | 89 ++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index a283d96c..cd63fb69 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -5,6 +5,7 @@ metadata: all_regs_mx0: &all_regs_mx0 "['x'+str(x) for x in range(1,32 if 'e' not in base_isa else 16)]" c_regs: &c_regs "['x'+str(x) for x in range(8,16)]" pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]" + rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]" aes32dsi: sig: @@ -10341,3 +10342,91 @@ czero.nez: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amocas.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZacas + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + + template: |- + + // $comment + // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset + TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset); + +amocas.d_32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IZacas + bit_width: 64 + dcas_profile: 'pnp' + formattype: 'dcasrformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *rv32rv64pair_regs + rd_op_data: *rv32rv64pair_regs + rs1_val_data: 'gen_sign_dataset(64)' + rs2_val_data: 'gen_sign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; dest($rd, $rd_hi) addr:$rs1; src:($rs2, $rs2_hi); swap_val:($rs2_val, $rs2_val_hi); swreg:$swreg; $offset + TEST_DCAS_OP(amocas.d, $rd, $rd_hi, $rs1, $rs2, $rs2_hi, $rs2_val, $rs2_val_hi, $swreg, $offset); + +amocas.d_64: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZacas + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + + template: |- + + // $comment + // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset + TEST_CAS_OP(amocas.d, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset); + +amocas.q: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZacas + bit_width: 128 + dcas_profile: 'pnp' + formattype: 'dcasrformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *rv32rv64pair_regs + rd_op_data: *rv32rv64pair_regs + rs1_val_data: 'gen_sign_dataset(128)' + rs2_val_data: 'gen_sign_dataset(128)' + + template: |- + + // $comment + // opcode: $inst ; dest($rd, $rd_hi) addr:$rs1; src:($rs2, $rs2_hi); swap_val:($rs2_val, $rs2_val_hi), swreg:$swreg, $offset + TEST_DCAS_OP($inst, $rd, $rd_hi, $rs1, $rs2, $rs2_hi, $rs2_val, $rs2_val_hi, $swreg, $offset); From c1a1233b300afd6f2e101498ac024afe933e9e77 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Wed, 26 Jul 2023 19:57:02 -0500 Subject: [PATCH 006/101] add data generators for zacas --- sample_cgfs/dataset.cgf | 49 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index bf0f52e4..20f1c29c 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -488,3 +488,52 @@ datasets: 'walking_ones("rs2_val", 64, signed=False)': 0 'walking_zeros("rs2_val", 64, signed=False)': 0 'alternate("rs2_val",64, signed=False)': 0 + + rvp128_rs1val_sgn: &rvp128_rs1val_sgn + 'rs1_val == 0': 0 + 'rs1_val == 1': 0 + + rvp128_rs2val_sgn: &rvp128_rs2val_sgn + 'rs2_val == 0': 0 + 'rs2_val == 1': 0 + + rvp128_rs1val_walking_sgn: &rvp128_rs1val_walking_sgn + 'walking_ones("rs1_val", 128)': 0 + 'walking_zeros("rs1_val", 128)': 0 + 'alternate("rs1_val",128)': 0 + + rvp128_rs2val_walking_sgn: &rvp128_rs2val_walking_sgn + 'walking_ones("rs2_val", 128)': 0 + 'walking_zeros("rs2_val", 128)': 0 + 'alternate("rs2_val",128)': 0 + + zacas_op_comb: &zacas_op_comb + 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 + + zacas_dcas_rs1val_sgn: &zacas_dcas_rs1val_sgn + 'rs1_val == 0': 0 + 'rs1_val == 1': 0 + + zacas_dcas_rs2val_sgn: &zacas_dcas_rs2val_sgn + 'rs2_val == 0': 0 + 'rs2_val == 1': 0 + + zacas128_rs1val_walking_sgn: &zacas128_rs1val_walking_sgn + 'walking_ones("rs1_val", 128)': 0 + 'walking_zeros("rs1_val", 128)': 0 + 'alternate("rs1_val",128)': 0 + + zacas128_rs2val_walking_sgn: &zacas128_rs2val_walking_sgn + 'walking_ones("rs2_val", 128)': 0 + 'walking_zeros("rs2_val", 128)': 0 + 'alternate("rs2_val",128)': 0 + + zacas64_rs1val_walking_sgn: &zacas64_rs1val_walking_sgn + 'walking_ones("rs1_val", 64)': 0 + 'walking_zeros("rs1_val", 64)': 0 + 'alternate("rs1_val",64)': 0 + + zacas64_rs2val_walking_sgn: &zacas64_rs2val_walking_sgn + 'walking_ones("rs2_val", 64)': 0 + 'walking_zeros("rs2_val", 64)': 0 + 'alternate("rs2_val",64)': 0 From fcb199607c72527405ae4e18e714504d7088fe59 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Wed, 26 Jul 2023 20:02:37 -0500 Subject: [PATCH 007/101] add zacas cover group files --- sample_cgfs/rv32zacas.cgf | 36 ++++++++++++++++++++++++++ sample_cgfs/rv64zacas.cgf | 54 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 sample_cgfs/rv32zacas.cgf create mode 100644 sample_cgfs/rv64zacas.cgf diff --git a/sample_cgfs/rv32zacas.cgf b/sample_cgfs/rv32zacas.cgf new file mode 100644 index 00000000..6569f3ba --- /dev/null +++ b/sample_cgfs/rv32zacas.cgf @@ -0,0 +1,36 @@ +# cover group format file for Zacas extension +amocas.w: + config: + - check ISA:=regex(.*Zacas.*) + opcode: + amocas.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +amocas.d_32: + config: + - check ISA:=regex(.*Zacas.*) + opcode: + amocas.d_32: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*zacas_dcas_rs1val_sgn, *zacas_dcas_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*zacas64_rs1val_walking_sgn, *zacas64_rs2val_walking_sgn] diff --git a/sample_cgfs/rv64zacas.cgf b/sample_cgfs/rv64zacas.cgf new file mode 100644 index 00000000..4acc4a1e --- /dev/null +++ b/sample_cgfs/rv64zacas.cgf @@ -0,0 +1,54 @@ +# cover group format file for Zacas extension +amocas.w: + config: + - check ISA:=regex(.*Zacas.*) + opcode: + amocas.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +amocas.d_64: + config: + - check ISA:=regex(.*Zacas.*) + opcode: + amocas.d_64: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +amocas.q: + config: + - check ISA:=regex(.*Zacas.*) + opcode: + amocas.q: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*zacas_dcas_rs1val_sgn, *zacas_dcas_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*zacas128_rs1val_walking_sgn, *zacas128_rs2val_walking_sgn] From d5420e075a903442256ae767d1da062c44499741 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Sun, 20 Aug 2023 16:37:15 +0530 Subject: [PATCH 008/101] Updating CONTRIBUTING.rst to capture the new git strategy --- .github/pull_request_template.md | 25 +++++++++++ CHANGELOG.md | 8 ++++ CONTRIBUTING.rst | 71 ++++++++++++++++++++++---------- setup.cfg | 4 -- setup.py | 3 +- 5 files changed, 85 insertions(+), 26 deletions(-) create mode 100644 .github/pull_request_template.md diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md new file mode 100644 index 00000000..6b0e8c95 --- /dev/null +++ b/.github/pull_request_template.md @@ -0,0 +1,25 @@ + + +#DEVELOPMENT PRs SHOULD BE TO DEV BRANCH ONLY + +## Description + +> Provide a detailed description of the changes performed by the PR. + +### Related Issues + +> Please list all the issues related to this PR. Use NA if no issues exist. + +### Update to/for Ratified/Unratified Extensions or to framework + +- [ ] Ratified +- [ ] Unratified +- [ ] Framework + +### List Extensions + +> List the extensions that your PR affects. In case of unratified extensions, please provide a link to the spec draft that was referred to make this PR. + +### Mandatory Checklist: + + - [ ] Make sure to have created a suitable entry in the CHANGELOG.md under `[WIP-DEV]` section. diff --git a/CHANGELOG.md b/CHANGELOG.md index 14d689c5..f540f0b2 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,14 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). +Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. +Only when a release to the main branch is done, the contents of the WIP-DEV are put under a +versioned header while the `WIP-DEV` is left empty + +## [WIP-DEV] +- Updating CONTRIBUTING.rst to capture the new git strategy adopted to follow a monthly release + cadence. + ## [0.11.1] - 2023-08-15 - Fixed hex values handling for K extensions - Fixed set indexing error during opcomb gen diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst index 5e0df16b..391e2711 100644 --- a/CONTRIBUTING.rst +++ b/CONTRIBUTING.rst @@ -2,9 +2,9 @@ .. highlight:: shell -============ -Contributing -============ +====================== +Developer Contribution +====================== Contributions are welcome, and they are greatly appreciated and credit will always be given. @@ -30,15 +30,31 @@ If you are proposing a feature: * Remember that this is a volunteer-driven project, and that contributions are welcome :) +Git Strategy +------------ + +The repo adopts a simple git strategy where all contributions to the repo are made to the ``dev`` +branch (i.e. all Pull-Requests must use ``dev`` as the target branch). On a monthly cadence (decided +and controlled by the SIG-ARCH-TEST members) the ``dev`` branch will be merged to the ``main`` to by +the official maintainers of the repo. This will create an official release capturing all the +development over the month into a single release. + +To implement the above strategy successfully the following needs be followed: + +* Developers: All pull-requests from developers must target the ``dev`` branch and the PR must +contain an entry in the CHANGELOG.md file under `[WIP-DEV]` section. +* Maintainers: When a making a release the maintainers shall assign semantic version number by +updating the CHANGELOG and the respective python files before raising a PR from the `dev` to `main`. + Get Started! ------------ Ready to contribute? Here's how to set up `riscv_ctg` for local development. 1. Fork the `riscv_ctg` repo on GitHub. -2. Clone your fork locally:: +2. Clone your fork locally and checkout the ``dev`` branch:: - $ git clone https://github.com/riscv-software-src/riscv-ctg.git + $ git clone https://github.com/riscv-software-src/riscv-ctg.git -b dev 3. Create an issue and WIP merge request that creates a working branch for you:: @@ -58,33 +74,46 @@ Ready to contribute? Here's how to set up `riscv_ctg` for local development. $ git commit -m "Your detailed description of your changes." $ git push origin name-of-your-bugfix-or-feature -6. Submit a merge request through the GitHub website. +6. Submit a pull-request through the GitHub website. Make sure the pull-request is on the `dev` +branch of the origin repo. + +7. Do not forget to make an entry in the CHANGELOG.md file under the `[WIP-DEV]` section +highlighting the changes you have done. Merge Request Guidelines ----------------------------- +------------------------ Before you submit a merge request, check that it meets these guidelines: -1. The merge request should include tests. +1. The merge request should include tests (if any). 2. If the merge request adds functionality, the docs should be updated. -3. The merge request should work for Python 3.6, 3.7 and 3.8, and for PyPy. - and make sure that the tests pass for all supported Python versions. +3. The target branch must always be the `dev` branch. + + +Versioning (only for maintainers) +--------------------------------- + +When issuing pull requests to the main branch (from dev), a version entry in the CHANGELOG.md is mandatory. The tool adheres to +the [`Semantic Versioning`](https://semver.org/spec/v2.0.0.html) scheme. Following guidelines must +be followed while assigning a new version number : + +- Patch-updates: all doc updates (like typos, more clarification,etc). +- Minor-updates: Fixing bugs in current features, adding new features which do not break current + features or working. Adding new extensions. +- Major-updates: Backward incompatible changes. -Tips ----- +Note: You can have either a patch or minor or major update. +Note: In case of a conflict, the maintainers will decide the final version to be assigned. -To run a subset of tests:: +To update the version of the python package for deployment you can use `bumpversion` (installed +using ``pip install bumpversion``):: - $ pytest tests.test_riscv_ctg +$ bumpversion --no-tag --config-file setup.cfg patch # last arg can be: major or minor or patch +If you don't have bumpversion installed you can manually update the version in the following files: -Deploying ---------- +- change the value of variable ``current_version`` in `./setup.cfg` +- change the value of variable ``__version__`` in `./riscv_ctg/__init__.py` -A reminder for the maintainers on how to deploy. -Make sure all your changes are committed. -Then run:: -$ bumpversion --no-tag --config-file setup.cfg patch # possible: major / minor / patch -$ git push origin name-of-your-branch diff --git a/setup.cfg b/setup.cfg index 878241cf..a9364240 100644 --- a/setup.cfg +++ b/setup.cfg @@ -3,10 +3,6 @@ current_version = 0.11.1 commit = True tag = True -[bumpversion:file:setup.py] -search = version='{current_version}' -replace = version='{new_version}' - [bumpversion:file:riscv_ctg/__init__.py] search = __version__ = '{current_version}' replace = __version__ = '{new_version}' diff --git a/setup.py b/setup.py index edf39544..cfba8937 100644 --- a/setup.py +++ b/setup.py @@ -4,6 +4,7 @@ from setuptools import setup, find_packages import os +import riscv_ctg # Base directory of package here = os.path.abspath(os.path.dirname(__file__)) @@ -26,7 +27,7 @@ def read_requires(): setup( name='riscv_ctg', - version='0.11.1', + version=riscv_ctg.__version__, description="RISC-V CTG", long_description=readme + '\n\n', classifiers=[ From 91393bd5d5b7a40ab672dd65ac3a2293fe38758d Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Fri, 30 Jun 2023 17:23:54 +0500 Subject: [PATCH 009/101] Add cgf file for 32-bit Atomic instructions Signed-off-by: Abdul Wadood --- sample_cgfs/rv32ia.cgf | 161 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 sample_cgfs/rv32ia.cgf diff --git a/sample_cgfs/rv32ia.cgf b/sample_cgfs/rv32ia.cgf new file mode 100644 index 00000000..2ae2cd78 --- /dev/null +++ b/sample_cgfs/rv32ia.cgf @@ -0,0 +1,161 @@ +amoadd.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoadd.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoand.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoand.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoswap.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoswap.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoxor.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoxor.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoor.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoor.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomin.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amomin.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amominu.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amominu.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomax.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amomax.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomaxu.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amomaxu.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] \ No newline at end of file From df9d967659e172ebd8ef890136bdb60002ab9443 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Fri, 30 Jun 2023 17:24:05 +0500 Subject: [PATCH 010/101] Add cgf file for 64-bit Atomic instructions Signed-off-by: Abdul Wadood --- sample_cgfs/rv64ia.cgf | 161 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 sample_cgfs/rv64ia.cgf diff --git a/sample_cgfs/rv64ia.cgf b/sample_cgfs/rv64ia.cgf new file mode 100644 index 00000000..1277ffb7 --- /dev/null +++ b/sample_cgfs/rv64ia.cgf @@ -0,0 +1,161 @@ +amoadd.d: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoadd.d: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoand.d: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoand.d: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoswap.d: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoswap.d: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoxor.d: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoxor.d: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoor.d: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoor.d: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomin.d: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amomin.d: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amominu.d: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amominu.d: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomax.d: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amomax.d: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomaxu.d: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amomaxu.d: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] \ No newline at end of file From 13ac92488fe4bb48e5c928afab37494f0c3c6e70 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Fri, 30 Jun 2023 17:25:54 +0500 Subject: [PATCH 011/101] Add test gen template for 32-bit Atomic instructions Signed-off-by: Abdul Wadood --- riscv_ctg/data/template.yaml | 180 +++++++++++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index eb5a4218..81c515b7 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10318,3 +10318,183 @@ czero.nez: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoadd.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoand.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoswap.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoxor.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoor.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amomin.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amominu.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amomax.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amomaxu.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) From 80aaca28bf88be1a8b5b97365e0f69c91a51b4af Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Fri, 30 Jun 2023 17:26:32 +0500 Subject: [PATCH 012/101] Add test gen template for 64-bit Atomic instructions Signed-off-by: Abdul Wadood --- riscv_ctg/data/template.yaml | 180 +++++++++++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 81c515b7..8ad7ee40 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10498,3 +10498,183 @@ amomaxu.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoadd.d: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoand.d: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoswap.d: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoxor.d: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoor.d: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amomin.d: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amominu.d: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amomax.d: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amomaxu.d: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) \ No newline at end of file From f400219e3698a280b0520f8051dc1062ee292de1 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Tue, 25 Jul 2023 21:17:50 +0500 Subject: [PATCH 013/101] Update cgf file Generate only signed values for `amominu` and `amomaxu` tests Signed-off-by: Abdul Wadood --- sample_cgfs/dataset.cgf | 7 ++++++- sample_cgfs/rv32ia.cgf | 26 +++++++++++++------------- sample_cgfs/rv64ia.cgf | 26 +++++++++++++------------- 3 files changed, 32 insertions(+), 27 deletions(-) diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index bf0f52e4..e73c6f46 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -224,7 +224,12 @@ datasets: 'rs2 == rd != rs1': 0 'rs1 == rs2 == rd': 0 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 - + + ramofmt_op_comb: &ramofmt_op_comb + 'rs1 == rd != rs2': 0 + 'rs2 == rd != rs1': 0 + 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 + r4fmt_op_comb: &r4fmt_op_comb 'rs1 == rs2 == rs3 == rd': 0 'rs1 == rs2 == rs3 != rd': 0 diff --git a/sample_cgfs/rv32ia.cgf b/sample_cgfs/rv32ia.cgf index 2ae2cd78..81d2e32c 100644 --- a/sample_cgfs/rv32ia.cgf +++ b/sample_cgfs/rv32ia.cgf @@ -10,7 +10,7 @@ amoadd.w: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -28,7 +28,7 @@ amoand.w: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -46,7 +46,7 @@ amoswap.w: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -64,7 +64,7 @@ amoxor.w: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -82,7 +82,7 @@ amoor.w: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -100,7 +100,7 @@ amomin.w: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -118,11 +118,11 @@ amominu.w: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: - <<: [*base_rs2val_sgn] + <<: [*base_rs2val_unsgn] abstract_comb: - <<: [*rs2val_walking] + <<: [*rs2val_walking_unsgn] amomax.w: config: @@ -136,7 +136,7 @@ amomax.w: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -154,8 +154,8 @@ amomaxu.w: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: - <<: [*base_rs2val_sgn] + <<: [*base_rs2val_unsgn] abstract_comb: - <<: [*rs2val_walking] \ No newline at end of file + <<: [*rs2val_walking_unsgn] \ No newline at end of file diff --git a/sample_cgfs/rv64ia.cgf b/sample_cgfs/rv64ia.cgf index 1277ffb7..974ddda5 100644 --- a/sample_cgfs/rv64ia.cgf +++ b/sample_cgfs/rv64ia.cgf @@ -10,7 +10,7 @@ amoadd.d: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -28,7 +28,7 @@ amoand.d: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -46,7 +46,7 @@ amoswap.d: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -64,7 +64,7 @@ amoxor.d: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -82,7 +82,7 @@ amoor.d: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -100,7 +100,7 @@ amomin.d: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -118,11 +118,11 @@ amominu.d: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: - <<: [*base_rs2val_sgn] + <<: [*base_rs2val_unsgn] abstract_comb: - <<: [*rs2val_walking] + <<: [*rs2val_walking_unsgn] amomax.d: config: @@ -136,7 +136,7 @@ amomax.d: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: <<: [*base_rs2val_sgn] abstract_comb: @@ -154,8 +154,8 @@ amomaxu.d: rd: <<: *all_regs op_comb: - <<: [*rfmt_op_comb] + <<: [*ramofmt_op_comb] val_comb: - <<: [*base_rs2val_sgn] + <<: [*base_rs2val_unsgn] abstract_comb: - <<: [*rs2val_walking] \ No newline at end of file + <<: [*rs2val_walking_unsgn] \ No newline at end of file From 9bf14f6a68a129d95b4a29609ffc6e4f471b262f Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Tue, 25 Jul 2023 21:50:30 +0500 Subject: [PATCH 014/101] Add test cases in RV64 Signed-off-by: Abdul Wadood --- sample_cgfs/rv64ia.cgf | 162 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 162 insertions(+) diff --git a/sample_cgfs/rv64ia.cgf b/sample_cgfs/rv64ia.cgf index 974ddda5..aa368acc 100644 --- a/sample_cgfs/rv64ia.cgf +++ b/sample_cgfs/rv64ia.cgf @@ -1,3 +1,165 @@ +amoadd.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoadd.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoand.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoand.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoswap.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoswap.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoxor.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoxor.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoor.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amoor.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomin.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amomin.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amominu.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amominu.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_unsgn] + abstract_comb: + <<: [*rs2val_walking_unsgn] + +amomax.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amomax.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomaxu.w: + config: + - check ISA:=regex(.*I.*A.*) + mnemonics: + amomaxu.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_unsgn] + abstract_comb: + <<: [*rs2val_walking_unsgn] + amoadd.d: config: - check ISA:=regex(.*I.*A.*) From 24c52e7fd82f5ecd237bfcac046e29a94d11ef6f Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Tue, 25 Jul 2023 21:50:57 +0500 Subject: [PATCH 015/101] Update test template Update stride to incorporate two signature per test instance Remove the register Signed-off-by: Abdul Wadood --- riscv_ctg/data/template.yaml | 90 ++++++++++++++++++------------------ 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 8ad7ee40..346aa23d 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10321,9 +10321,9 @@ czero.nez: amoadd.w: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' - xlen: [32] + xlen: [32,64] std_op: isa: - IA @@ -10337,13 +10337,13 @@ amoadd.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amoand.w: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' - xlen: [32] + xlen: [32,64] std_op: isa: - IA @@ -10357,13 +10357,13 @@ amoand.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amoswap.w: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' - xlen: [32] + xlen: [32,64] std_op: isa: - IA @@ -10377,13 +10377,13 @@ amoswap.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amoxor.w: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' - xlen: [32] + xlen: [32,64] std_op: isa: - IA @@ -10397,13 +10397,13 @@ amoxor.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amoor.w: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' - xlen: [32] + xlen: [32,64] std_op: isa: - IA @@ -10417,13 +10417,13 @@ amoor.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amomin.w: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' - xlen: [32] + xlen: [32,64] std_op: isa: - IA @@ -10437,13 +10437,13 @@ amomin.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amominu.w: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' - xlen: [32] + xlen: [32,64] std_op: isa: - IA @@ -10457,13 +10457,13 @@ amominu.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amomax.w: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' - xlen: [32] + xlen: [32,64] std_op: isa: - IA @@ -10477,13 +10477,13 @@ amomax.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amomaxu.w: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' - xlen: [32] + xlen: [32,64] std_op: isa: - IA @@ -10497,11 +10497,11 @@ amomaxu.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amoadd.d: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' xlen: [64] std_op: @@ -10517,11 +10517,11 @@ amoadd.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amoand.d: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' xlen: [64] std_op: @@ -10537,11 +10537,11 @@ amoand.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amoswap.d: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' xlen: [64] std_op: @@ -10557,11 +10557,11 @@ amoswap.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amoxor.d: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' xlen: [64] std_op: @@ -10577,11 +10577,11 @@ amoxor.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amoor.d: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' xlen: [64] std_op: @@ -10597,11 +10597,11 @@ amoor.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amomin.d: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' xlen: [64] std_op: @@ -10617,11 +10617,11 @@ amomin.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amominu.d: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' xlen: [64] std_op: @@ -10637,11 +10637,11 @@ amominu.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amomax.d: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' xlen: [64] std_op: @@ -10657,11 +10657,11 @@ amomax.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) amomaxu.d: sig: - stride: 1 + stride: 2 sz: 'XLEN/8' xlen: [64] std_op: @@ -10677,4 +10677,4 @@ amomaxu.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset, $testreg) \ No newline at end of file + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) From 77a4853877623892b317f31e643aedd38fc2b59b Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Thu, 3 Aug 2023 05:08:51 +0500 Subject: [PATCH 016/101] Update cgf files Signed-off-by: Abdul Wadood --- sample_cgfs/rv32ia.cgf | 8 ++++---- sample_cgfs/rv64ia.cgf | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/sample_cgfs/rv32ia.cgf b/sample_cgfs/rv32ia.cgf index 81d2e32c..e8f44425 100644 --- a/sample_cgfs/rv32ia.cgf +++ b/sample_cgfs/rv32ia.cgf @@ -120,9 +120,9 @@ amominu.w: op_comb: <<: [*ramofmt_op_comb] val_comb: - <<: [*base_rs2val_unsgn] + <<: [*base_rs2val_sgn] abstract_comb: - <<: [*rs2val_walking_unsgn] + <<: [*rs2val_walking] amomax.w: config: @@ -156,6 +156,6 @@ amomaxu.w: op_comb: <<: [*ramofmt_op_comb] val_comb: - <<: [*base_rs2val_unsgn] + <<: [*base_rs2val_sgn] abstract_comb: - <<: [*rs2val_walking_unsgn] \ No newline at end of file + <<: [*rs2val_walking] \ No newline at end of file diff --git a/sample_cgfs/rv64ia.cgf b/sample_cgfs/rv64ia.cgf index aa368acc..99dc8d03 100644 --- a/sample_cgfs/rv64ia.cgf +++ b/sample_cgfs/rv64ia.cgf @@ -120,9 +120,9 @@ amominu.w: op_comb: <<: [*ramofmt_op_comb] val_comb: - <<: [*base_rs2val_unsgn] + <<: [*base_rs2val_sgn] abstract_comb: - <<: [*rs2val_walking_unsgn] + <<: [*rs2val_walking] amomax.w: config: @@ -156,9 +156,9 @@ amomaxu.w: op_comb: <<: [*ramofmt_op_comb] val_comb: - <<: [*base_rs2val_unsgn] + <<: [*base_rs2val_sgn] abstract_comb: - <<: [*rs2val_walking_unsgn] + <<: [*rs2val_walking] amoadd.d: config: @@ -282,9 +282,9 @@ amominu.d: op_comb: <<: [*ramofmt_op_comb] val_comb: - <<: [*base_rs2val_unsgn] + <<: [*base_rs2val_sgn] abstract_comb: - <<: [*rs2val_walking_unsgn] + <<: [*rs2val_walking] amomax.d: config: @@ -318,6 +318,6 @@ amomaxu.d: op_comb: <<: [*ramofmt_op_comb] val_comb: - <<: [*base_rs2val_unsgn] + <<: [*base_rs2val_sgn] abstract_comb: - <<: [*rs2val_walking_unsgn] \ No newline at end of file + <<: [*rs2val_walking] \ No newline at end of file From 10f0cb9a759a5471e77251ce7fe0b2c31771efd2 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Sun, 20 Aug 2023 20:00:33 +0500 Subject: [PATCH 017/101] Update changelog entry Signed-off-by: Abdul Wadood --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index f540f0b2..1d032c1e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,7 @@ Only when a release to the main branch is done, the contents of the WIP-DEV are versioned header while the `WIP-DEV` is left empty ## [WIP-DEV] +- Added support of Standard Atomic (A) Extension (RV32 and RV64), excluding the LR/SC instruction. - Updating CONTRIBUTING.rst to capture the new git strategy adopted to follow a monthly release cadence. From 6c8154270f99cfe8b20b5eaeaffa608bc86857e8 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 19 Jun 2023 22:07:43 +0500 Subject: [PATCH 018/101] Added template and cgf for compressed load type instructions Signed-off-by: Abdul Wadood --- riscv_ctg/data/template.yaml | 59 +++++++++++++++++++++++++++++++++++- sample_cgfs/rv32i_zcb.cgf | 50 ++++++++++++++++++++++++++++++ sample_cgfs/rv64i_zcb.cgf | 50 ++++++++++++++++++++++++++++++ 3 files changed, 158 insertions(+), 1 deletion(-) create mode 100644 sample_cgfs/rv32i_zcb.cgf create mode 100644 sample_cgfs/rv64i_zcb.cgf diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 346aa23d..28e095c8 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10317,7 +10317,7 @@ czero.nez: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) amoadd.w: sig: @@ -10678,3 +10678,60 @@ amomaxu.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +c.lbu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'clformat' + rs1_val_data: '[0]' + imm_val_data: 'gen_usign_dataset(2)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) + +c.lhu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'clformat' + rs1_val_data: '[0]' + imm_val_data: 'gen_usign_dataset(2)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) + +c.lh: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'clformat' + rs1_val_data: '[0]' + imm_val_data: 'gen_usign_dataset(2)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) diff --git a/sample_cgfs/rv32i_zcb.cgf b/sample_cgfs/rv32i_zcb.cgf new file mode 100644 index 00000000..b47e66c2 --- /dev/null +++ b/sample_cgfs/rv32i_zcb.cgf @@ -0,0 +1,50 @@ + +clbu: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.lbu: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val == 1': 0 + 'imm_val == 2': 0 + 'imm_val == 3': 0 + +clhu: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.lhu: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val == 2': 0 + +clh: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.lh: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val == 2': 0 diff --git a/sample_cgfs/rv64i_zcb.cgf b/sample_cgfs/rv64i_zcb.cgf new file mode 100644 index 00000000..b47e66c2 --- /dev/null +++ b/sample_cgfs/rv64i_zcb.cgf @@ -0,0 +1,50 @@ + +clbu: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.lbu: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val == 1': 0 + 'imm_val == 2': 0 + 'imm_val == 3': 0 + +clhu: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.lhu: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val == 2': 0 + +clh: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.lh: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val == 2': 0 From 118969cdadee708e4694dfd28eaa7da1971b9326 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 19 Jun 2023 22:12:56 +0500 Subject: [PATCH 019/101] Added template and cgf for compressed store type instructions Signed-off-by: Abdul Wadood --- riscv_ctg/data/template.yaml | 40 ++++++++++++++++++++++++++++++++++++ sample_cgfs/rv32i_zcb.cgf | 32 +++++++++++++++++++++++++++++ sample_cgfs/rv64i_zcb.cgf | 32 +++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 28e095c8..0d77b063 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10735,3 +10735,43 @@ c.lh: // $comment // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) + +c.sb: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'csformat' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'gen_usign_dataset(2)' + template: |- + + // $comment + // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val + TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0) + +c.sh: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'csformat' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'gen_usign_dataset(2)' + template: |- + + // $comment + // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val + TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0) diff --git a/sample_cgfs/rv32i_zcb.cgf b/sample_cgfs/rv32i_zcb.cgf index b47e66c2..d7f43c8c 100644 --- a/sample_cgfs/rv32i_zcb.cgf +++ b/sample_cgfs/rv32i_zcb.cgf @@ -48,3 +48,35 @@ clh: val_comb: 'imm_val == 0': 0 'imm_val == 2': 0 + +csb: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.sb: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val == 1': 0 + 'imm_val == 2': 0 + 'imm_val == 3': 0 + +csh: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.sh: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val == 2': 0 \ No newline at end of file diff --git a/sample_cgfs/rv64i_zcb.cgf b/sample_cgfs/rv64i_zcb.cgf index b47e66c2..d7f43c8c 100644 --- a/sample_cgfs/rv64i_zcb.cgf +++ b/sample_cgfs/rv64i_zcb.cgf @@ -48,3 +48,35 @@ clh: val_comb: 'imm_val == 0': 0 'imm_val == 2': 0 + +csb: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.sb: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val == 1': 0 + 'imm_val == 2': 0 + 'imm_val == 3': 0 + +csh: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.sh: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val == 2': 0 \ No newline at end of file From 3923f65746dd837d8a4481613180a932bbcc8b2d Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 19 Jun 2023 22:16:03 +0500 Subject: [PATCH 020/101] Added template and cgf for compressed bitmanip instructions Signed-off-by: Abdul Wadood --- riscv_ctg/data/template.yaml | 85 ++++++++++++++++++++++++++++++++++++ sample_cgfs/rv32i_zcb.cgf | 61 +++++++++++++++++++++++++- sample_cgfs/rv64i_zcb.cgf | 76 +++++++++++++++++++++++++++++++- 3 files changed, 220 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 0d77b063..7cb14fd2 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10775,3 +10775,88 @@ c.sh: // $comment // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0) + +c.sext.b: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb_Zbb + formattype: 'ckformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.sext.h: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb_Zbb + formattype: 'ckformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[65408]' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.zext.b: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'ckformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_usign_dataset(xlen)+[128]' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.zext.h: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb_Zbb + formattype: 'ckformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.zext.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - I_Zca_Zcb_Zba + formattype: 'ckformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) \ No newline at end of file diff --git a/sample_cgfs/rv32i_zcb.cgf b/sample_cgfs/rv32i_zcb.cgf index d7f43c8c..53770611 100644 --- a/sample_cgfs/rv32i_zcb.cgf +++ b/sample_cgfs/rv32i_zcb.cgf @@ -79,4 +79,63 @@ csh: 'rs1 != rs2': 0 val_comb: 'imm_val == 0': 0 - 'imm_val == 2': 0 \ No newline at end of file + 'imm_val == 2': 0 + +csext.b: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*) + mnemonics: + c.sext.b: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0x8000': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 +csext.h: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*) + mnemonics: + c.sext.h: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x800': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + +czext.b: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.zext.b: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0x8000': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + +czext.h: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*) + mnemonics: + c.zext.h: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x800': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 diff --git a/sample_cgfs/rv64i_zcb.cgf b/sample_cgfs/rv64i_zcb.cgf index d7f43c8c..36282f01 100644 --- a/sample_cgfs/rv64i_zcb.cgf +++ b/sample_cgfs/rv64i_zcb.cgf @@ -79,4 +79,78 @@ csh: 'rs1 != rs2': 0 val_comb: 'imm_val == 0': 0 - 'imm_val == 2': 0 \ No newline at end of file + 'imm_val == 2': 0 + +csext.b: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*) + mnemonics: + c.sext.b: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0x8000': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 +csext.h: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*) + mnemonics: + c.sext.h: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x800': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + +czext.b: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.zext.b: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0x8000': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + +czext.h: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*) + mnemonics: + c.zext.h: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x800': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + +czext.w: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*.Zba.*) + mnemonics: + c.zext.w: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x800': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 \ No newline at end of file From 8e5be82dbda74885914229f4e9a03db5e87e500a Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 19 Jun 2023 22:36:23 +0500 Subject: [PATCH 021/101] Add new format for compressed bit manip instructions Signed-off-by: Abdul Wadood --- riscv_ctg/generator.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 035b97d5..742549d1 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -58,6 +58,7 @@ def get_rm(opcode): 'cbformat': ['rs1'], 'cjformat': [], 'kformat': ['rs1','rd'], + 'ckformat': ['rs1'], # 'frformat': ['rs1', 'rs2', 'rd'], 'fsrformat': ['rs1', 'rd'], # 'fr4format': ['rs1', 'rs2', 'rs3', 'rd'], @@ -103,6 +104,7 @@ def get_rm(opcode): 'cbformat': "['rs1_val', 'imm_val']", 'cjformat': "['imm_val']", 'kformat': "['rs1_val']", + 'ckformat': "['rs1_val']", # 'frformat': "['rs1_val', 'rs2_val', 'rm_val', 'fcsr']", 'fsrformat': "['rs1_val', 'fcsr'] + get_rm(opcode) + \ ([] if not is_nan_box else ['rs1_nan_prefix'])", From e5a4386c92c72ff1efc288d568107c31031e9db8 Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 19 Jun 2023 23:07:24 +0500 Subject: [PATCH 022/101] Added template and cgf for c.not and c.mul instructions Signed-off-by: Abdul Wadood --- riscv_ctg/data/template.yaml | 39 +++++++++++++++++++++++++++++++++++- sample_cgfs/rv32i_zcb.cgf | 33 ++++++++++++++++++++++++++++++ sample_cgfs/rv64i_zcb.cgf | 34 ++++++++++++++++++++++++++++++- 3 files changed, 104 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 7cb14fd2..e598adff 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10859,4 +10859,41 @@ c.zext.w: // $comment // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; - TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) \ No newline at end of file + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.not: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'kformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.mul: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IM_Zca_Zcb + formattype: 'crformat' + operation: 'hex((rs1_val * rs2_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) diff --git a/sample_cgfs/rv32i_zcb.cgf b/sample_cgfs/rv32i_zcb.cgf index 53770611..86ba722a 100644 --- a/sample_cgfs/rv32i_zcb.cgf +++ b/sample_cgfs/rv32i_zcb.cgf @@ -139,3 +139,36 @@ czext.h: abstract_comb: 'walking_ones("rs1_val", xlen, False)': 0 'walking_zeros("rs1_val", xlen, False)': 0 + +cnot: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.not: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x800': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + +cmul: + config: + - check ISA:=regex(.*I.*M.*Zca.*Zcb.*) + mnemonics: + c.mul: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + \ No newline at end of file diff --git a/sample_cgfs/rv64i_zcb.cgf b/sample_cgfs/rv64i_zcb.cgf index 36282f01..0b9a48f9 100644 --- a/sample_cgfs/rv64i_zcb.cgf +++ b/sample_cgfs/rv64i_zcb.cgf @@ -153,4 +153,36 @@ czext.w: 'rs1_val == 0xFF80': 0 abstract_comb: 'walking_ones("rs1_val", xlen, False)': 0 - 'walking_zeros("rs1_val", xlen, False)': 0 \ No newline at end of file + 'walking_zeros("rs1_val", xlen, False)': 0 + +cnot: + config: + - check ISA:=regex(.*I.*Zca.*Zcb.*) + mnemonics: + c.not: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x800': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + +cmul: + config: + - check ISA:=regex(.*I.*M.*Zca.*Zcb.*) + mnemonics: + c.mul: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] From fd740a1d9d1d7391549fe7fb263b8ccf3407d0ec Mon Sep 17 00:00:00 2001 From: Abdul Wadood Date: Mon, 21 Aug 2023 08:35:11 +0500 Subject: [PATCH 023/101] Update Chnagelog Signed-off-by: Abdul Wadood --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 1d032c1e..c947908a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,7 @@ Only when a release to the main branch is done, the contents of the WIP-DEV are versioned header while the `WIP-DEV` is left empty ## [WIP-DEV] +- Added support of Zcb from Code Size Reduction Extension. - Added support of Standard Atomic (A) Extension (RV32 and RV64), excluding the LR/SC instruction. - Updating CONTRIBUTING.rst to capture the new git strategy adopted to follow a monthly release cadence. From 5098df435b83a8197be8aed425365ddba188b8db Mon Sep 17 00:00:00 2001 From: EmanFatima-ef Date: Thu, 10 Aug 2023 15:20:50 +0500 Subject: [PATCH 024/101] Added zifenci and privilege tests ctg files for RV32E --- sample_cgfs/rv32e_fencei.cgf | 6 ++ sample_cgfs/rv32e_priv.cgf | 146 +++++++++++++++++++++++++++++++++++ 2 files changed, 152 insertions(+) create mode 100644 sample_cgfs/rv32e_fencei.cgf create mode 100644 sample_cgfs/rv32e_priv.cgf diff --git a/sample_cgfs/rv32e_fencei.cgf b/sample_cgfs/rv32e_fencei.cgf new file mode 100644 index 00000000..59086e9c --- /dev/null +++ b/sample_cgfs/rv32e_fencei.cgf @@ -0,0 +1,6 @@ +fencei: + config: + - check ISA:=regex(.*E.*Zifencei.*) ;def RVTEST_E = True + opcode: + fence.i: 0 + diff --git a/sample_cgfs/rv32e_priv.cgf b/sample_cgfs/rv32e_priv.cgf new file mode 100644 index 00000000..eb970b70 --- /dev/null +++ b/sample_cgfs/rv32e_priv.cgf @@ -0,0 +1,146 @@ +misalign-lh: + cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True + config: + - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True + opcode: + lh: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-lhu: + config: + - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True + opcode: + lhu: 0 + val_comb: + 'ea_align == 1': 0 + + +misalign-lw: + config: + - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True + opcode: + lw: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign-sh: + config: + - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True + opcode: + sh: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-sw: + config: + - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True + opcode: + sw: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign2-jalr: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True + opcode: + jalr: 0 + val_comb: + 'imm_val%2 == 1 and ea_align == 2': 0 + 'imm_val%2 == 0 and ea_align == 2': 0 + +misalign1-jalr: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + opcode: + jalr: 0 + val_comb: + 'imm_val%2 == 1 and ea_align == 1': 0 + 'imm_val%2 == 0 and ea_align == 1': 0 + +misalign-jal: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True + opcode: + jal: 0 + val_comb: + 'ea_align == 2': 0 + +misalign-bge: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True + opcode: + bge: 0 + val_comb: + ' rs1_val>rs2_val and ea_align == 2': 0 + +misalign-bgeu: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True + opcode: + bgeu: 0 + val_comb: + ' rs1_val>rs2_val and ea_align == 2': 0 + +misalign-blt: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True + opcode: + blt: 0 + val_comb: + ' rs1_val Date: Thu, 10 Aug 2023 15:26:07 +0500 Subject: [PATCH 025/101] Added Changelog Entry --- CHANGELOG.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index c947908a..ade372cc 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,8 @@ # CHANGELOG This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). +## [0.11.1] - 2023-8-10 +- Added Zifencei and Privilege tests ctg files for RV32E Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. Only when a release to the main branch is done, the contents of the WIP-DEV are put under a From c3edb51bd3696554c17aabf10b72dcc53e2006c6 Mon Sep 17 00:00:00 2001 From: EmanFatima-ef Date: Wed, 16 Aug 2023 15:38:13 +0500 Subject: [PATCH 026/101] Added Bit Manipulation tests for RV32E --- sample_cgfs/rv32e_b.cgf | 705 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 705 insertions(+) create mode 100644 sample_cgfs/rv32e_b.cgf diff --git a/sample_cgfs/rv32e_b.cgf b/sample_cgfs/rv32e_b.cgf new file mode 100644 index 00000000..ce8a0e64 --- /dev/null +++ b/sample_cgfs/rv32e_b.cgf @@ -0,0 +1,705 @@ +sh1add: + config: + - check ISA:=regex(.*E.*Zba.*) ;def RVTEST_E = True + mnemonics: + sh1add: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sh2add: + config: + - check ISA:=regex(.*E.*Zba.*) ;def RVTEST_E = True + mnemonics: + sh2add: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sh3add: + config: + - check ISA:=regex(.*E.*Zba.*) ;def RVTEST_E = True + mnemonics: + sh3add: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +xnor: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + xnor: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +zext.h_32: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + zext.h: 0 + base_op: pack + p_op_cond: rs2 == x0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 +andn: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + andn: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + 'bitmanip_dataset(xlen,["rs1_val","rs2_val"],False)': 0 + +clz: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + clz: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros("rs1_val", xlen, False)': 0 + 'leading_ones("rs1_val", xlen, False)': 0 + 'trailing_zeros("rs1_val", xlen, False)': 0 + 'trailing_ones("rs1_val", xlen, False)': 0 + +ctz: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + ctz: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros("rs1_val", xlen, False)': 0 + 'leading_ones("rs1_val", xlen, False)': 0 + 'trailing_zeros("rs1_val", xlen, False)': 0 + 'trailing_ones("rs1_val", xlen, False)': 0 + +cpop: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + cpop: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros("rs1_val", xlen, False)': 0 + 'leading_ones("rs1_val", xlen, False)': 0 + 'trailing_zeros("rs1_val", xlen, False)': 0 + 'trailing_ones("rs1_val", xlen, False)': 0 + +max: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + max: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +maxu: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + maxu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + +min: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + min: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +minu: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + minu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + +orcb_32: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + orc.b: 0 + base_op: gorci + p_op_cond: imm_val == 7 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0x1020408': 0 + 'rs1_val == 0x2040801': 0 + 'rs1_val == 0x4080102': 0 + 'rs1_val == 0x8010204': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn] + + +orn: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + orn: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +rev8_32: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + rev8: 0 + base_op: grevi + p_op_cond: imm_val == 24 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0x1020408': 0 + 'rs1_val == 0x2040801': 0 + 'rs1_val == 0x4080102': 0 + 'rs1_val == 0x8010204': 0 + abstract_comb: + 'leading_ones(32, ["rs1_val"], [32])': 0 + 'trailing_ones(32, ["rs1_val"], [32])': 0 + 'leading_zeros(32, ["rs1_val"], [32])': 0 + 'trailing_zeros(32, ["rs1_val"], [32])': 0 + 'bitmanip_dataset(xlen,["rs1_val"],signed=False)': 0 + +rol: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + rol: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +ror: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zks.*) ;def RVTEST_E = True + mnemonics: + ror: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +rori: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zks.*) ;def RVTEST_E = True + mnemonics: + rori: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","imm_val"],[32,5])': 0 + 'trailing_ones(32, ["rs1_val","imm_val"],[32,5])': 0 + 'leading_zeros(32, ["rs1_val","imm_val"],[32,5])': 0 + 'trailing_zeros(32, ["rs1_val","imm_val"],[32,5])': 0 + +sext.b: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + sext.b: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x8000': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +sext.h: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + sext.h: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0xff80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +clmul: + config: + - check ISA:=regex(.*E.*Zbc.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkc.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + mnemonics: + clmul: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +clmulh: + config: + - check ISA:=regex(.*E.*Zbc.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkc.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + clmulh: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + + +clmulr: + config: + - check ISA:=regex(.*E.*Zbc.*) ;def RVTEST_E = True + mnemonics: + clmulr: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +bclr: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bclr: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'xlenlim("rs1_val", xlen)': 0 + 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bclri: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bclri: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + + +bext: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bext: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'xlenlim("rs1_val", xlen)': 0 + 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bexti: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bexti: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + + +binv: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + binv: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'xlenlim("rs1_val", xlen)': 0 + 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +binvi: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + binvi: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + +bset: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bset: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'xlenlim("rs1_val", xlen)': 0 + 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bseti: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bseti: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 From 0a26f622330aec4f8435beae62c2efcd9f2cbd4a Mon Sep 17 00:00:00 2001 From: EmanFatima-ef Date: Wed, 16 Aug 2023 15:40:37 +0500 Subject: [PATCH 027/101] Modify Changelog --- CHANGELOG.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ade372cc..97a3ad1f 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,8 +1,8 @@ # CHANGELOG This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). -## [0.11.1] - 2023-8-10 -- Added Zifencei and Privilege tests ctg files for RV32E +## [0.11.1] - 2023-8-16 +- Added Zifencei, Bit Manipulation and Privilege tests ctg files for RV32E Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. Only when a release to the main branch is done, the contents of the WIP-DEV are put under a From 0225a2663ad6affad575afbb551da8e1deaf1b07 Mon Sep 17 00:00:00 2001 From: Eman Fatima <134972860+EmanFatima-ef@users.noreply.github.com> Date: Wed, 16 Aug 2023 18:36:16 +0500 Subject: [PATCH 028/101] Update CHANGELOG.md Signed-off-by: Eman Fatima <134972860+EmanFatima-ef@users.noreply.github.com> --- CHANGELOG.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 97a3ad1f..5ae03657 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,7 +1,7 @@ # CHANGELOG This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). -## [0.11.1] - 2023-8-16 +## [0.11.2] - 2023-8-16 - Added Zifencei, Bit Manipulation and Privilege tests ctg files for RV32E Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. From 061a6653f0172fe8c3007da80c0bda9dfee4a7b9 Mon Sep 17 00:00:00 2001 From: EmanFatima-ef Date: Mon, 21 Aug 2023 11:36:42 +0500 Subject: [PATCH 029/101] Update CHANGELOG.md --- CHANGELOG.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5ae03657..6b9d1fef 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,14 +1,13 @@ # CHANGELOG This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). -## [0.11.2] - 2023-8-16 -- Added Zifencei, Bit Manipulation and Privilege tests ctg files for RV32E Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. Only when a release to the main branch is done, the contents of the WIP-DEV are put under a versioned header while the `WIP-DEV` is left empty ## [WIP-DEV] +- Added Zifencei, Bit Manipulation and Privilege tests ctg files for RV32E - Added support of Zcb from Code Size Reduction Extension. - Added support of Standard Atomic (A) Extension (RV32 and RV64), excluding the LR/SC instruction. - Updating CONTRIBUTING.rst to capture the new git strategy adopted to follow a monthly release From 04ff804ea3f70bf117313132e1ec85feb03f48ce Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Sat, 9 Sep 2023 20:36:26 +0500 Subject: [PATCH 030/101] generator.py updated for the hardcoded register solution --- riscv_ctg/generator.py | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 035b97d5..53c7778d 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -12,6 +12,7 @@ import struct import sys import itertools +import re one_operand_finstructions = ["fsqrt.s","fmv.x.w","fcvt.wu.s","fcvt.w.s","fclass.s","fcvt.l.s","fcvt.lu.s","fcvt.s.l","fcvt.s.lu"] two_operand_finstructions = ["fadd.s","fsub.s","fmul.s","fdiv.s","fmax.s","fmin.s","feq.s","flt.s","fle.s","fsgnj.s","fsgnjn.s","fsgnjx.s"] @@ -271,10 +272,15 @@ def opcomb(self, cgf): to ensure that all those registers occur atleast once in the respective operand/destination location in the instruction. These contraints are then supplied to the solver for solutions - + If randomization is enabled we use the ``MinConflictsSolver`` solver to find solutions. + If harcoded registers are given in the cgf file, then for the conditions other + than the first one, there will be No Solution. To solve that problem, some code + is written which will find the required register in the condition and generate the + solution normally. + :param cgf: a covergroup in cgf format containing the set of coverpoints to be satisfied. :type cgf: dict @@ -324,6 +330,18 @@ def comb_constraint(*args): count = 0 solution = problem.getSolution() while (solution is None and count < 5): + pattern = r'(?:rs1|rs2|rd) == "(x\d+)"' + matches = re.findall(pattern, cond) + if not matches or any(int(match[1:]) > 31 for match in matches): + result = None + else: + result = matches + for match in result: + op_conds['rs1'].add(match) + op_conds['rs2'].add(match) + op_conds['rd'].add(match) + op_comb.add(cond) + break solution = problem.getSolution() count = count + 1 if solution is None: From 5807055a3366d12cba287965b8483906a4ad5ea5 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Fri, 22 Sep 2023 09:17:23 -0500 Subject: [PATCH 031/101] add template for Zimop extension instructions --- riscv_ctg/data/template.yaml | 803 +++++++++++++++++++++++++++++++++++ 1 file changed, 803 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index eb5a4218..66a98f74 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10318,3 +10318,806 @@ czero.nez: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.0: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +mop.rr.1: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +mop.rr.2: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.3: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.4: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.5: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.6: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.7: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.r.0: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.1: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.2: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.3: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.4: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.5: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.6: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.7: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.8: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.9: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.10: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.11: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.12: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.13: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.14: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.15: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.16: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.17: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.18: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.19: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.20: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.21: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.22: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.23: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.24: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.25: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.26: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.27: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.28: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.29: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.30: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.31: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + From 6cdc96807c993f32c01e8efe33c7d15c631b8e48 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Fri, 22 Sep 2023 09:17:45 -0500 Subject: [PATCH 032/101] add sample cgf for Zimop extension instructions --- sample_cgfs/zimop.cgf | 697 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 697 insertions(+) create mode 100644 sample_cgfs/zimop.cgf diff --git a/sample_cgfs/zimop.cgf b/sample_cgfs/zimop.cgf new file mode 100644 index 00000000..a47cbdb9 --- /dev/null +++ b/sample_cgfs/zimop.cgf @@ -0,0 +1,697 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +mop.rr.0: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.rr.0: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.1: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.rr.1: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.2: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.rr.2: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.3: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.rr.3: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.4: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.rr.4: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.5: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.rr.5: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.6: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.rr.6: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.7: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.rr.7: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.r.0: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.0: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.1: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.1: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.2: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.2: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.3: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.3: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.4: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.4: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.5: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.5: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.6: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.6: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.7: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.7: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.8: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.9: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.9: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.10: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.10: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.11: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.11: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.12: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.12: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.13: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.13: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.14: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.14: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.15: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.15: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.16: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.17: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.17: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.18: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.18: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.19: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.19: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.20: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.20: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.21: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.21: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.22: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.22: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.23: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.23: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.24: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.24: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.25: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.25: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.26: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.26: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.27: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.27: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.28: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.28: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.29: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.29: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.30: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.30: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.31: + config: + - check ISA:=regex(.*Zimop.*) + opcode: + mop.r.31: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] From f09302f2adc43c119bde51214570765bdcf68963 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Tue, 17 Oct 2023 10:58:35 -0500 Subject: [PATCH 033/101] add template for zcmop instructions --- riscv_ctg/data/template.yaml | 128 +++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 8498cc5a..cfba505e 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10986,3 +10986,131 @@ c.mul: // $comment // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +c.mop.1: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x1, $imm_val, $swreg, $testreg, $offset) + +c.mop.3: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x3, $imm_val, $swreg, $testreg, $offset) + +c.mop.5: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x5, $imm_val, $swreg, $testreg, $offset) + +c.mop.7: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x7, $imm_val, $swreg, $testreg, $offset) + +c.mop.9: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x9, $imm_val, $swreg, $testreg, $offset) + +c.mop.11: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x11, $imm_val, $swreg, $testreg, $offset) + +c.mop.13: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x13, $imm_val, $swreg, $testreg, $offset) + +c.mop.15: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x15, $imm_val, $swreg, $testreg, $offset) From e8683374732d496b76e65fa9630f1f62b0c372cd Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Tue, 17 Oct 2023 10:58:51 -0500 Subject: [PATCH 034/101] add sample cgf for zcmop instructions --- sample_cgfs/zcmop.cgf | 71 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 sample_cgfs/zcmop.cgf diff --git a/sample_cgfs/zcmop.cgf b/sample_cgfs/zcmop.cgf new file mode 100644 index 00000000..99329886 --- /dev/null +++ b/sample_cgfs/zcmop.cgf @@ -0,0 +1,71 @@ +c.mop.1: + config: + - check ISA:=regex(.*C.*Zcmop.*) + mnemonics: + c.mop.1: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.3: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.3: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.5: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.5: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.7: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.7: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.9: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.9: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.11: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.11: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.13: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.13: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.15: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.15: + val_comb: + abstract_comb: + <<: *cbimm_val_walking From e04590938d2ac928b7cf423781dffc799dd1d348 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 30 Oct 2023 17:06:41 -0500 Subject: [PATCH 035/101] add template for Zabha instructions --- riscv_ctg/data/template.yaml | 403 +++++++++++++++++++++++++++++++++++ 1 file changed, 403 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 8498cc5a..3aadfd33 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10986,3 +10986,406 @@ c.mul: // $comment // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoadd.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoand.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoswap.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoxor.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoor.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomin.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amominu.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomax.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomaxu.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amocas.b: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZacas + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + + template: |- + + // $comment + // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset + TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset); + +amoadd.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoand.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoswap.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoxor.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoor.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomin.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amominu.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomax.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomaxu.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amocas.h: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZacas + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + + template: |- + + // $comment + // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset + TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset); + From 6dda8445d84f485035674dd7807fd7dbf2ceea78 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 30 Oct 2023 17:10:19 -0500 Subject: [PATCH 036/101] add sample cgf for Zabha instructions --- sample_cgfs/rv32zabha.cgf | 362 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 362 insertions(+) create mode 100644 sample_cgfs/rv32zabha.cgf diff --git a/sample_cgfs/rv32zabha.cgf b/sample_cgfs/rv32zabha.cgf new file mode 100644 index 00000000..d58b1545 --- /dev/null +++ b/sample_cgfs/rv32zabha.cgf @@ -0,0 +1,362 @@ +amoadd.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoadd.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoand.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoand.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoswap.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoswap.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoxor.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoxor.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoor.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoor.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomin.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomin.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amominu.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amominu.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomax.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomax.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomaxu.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomaxu.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amocas.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*Zacas.*) + opcode: + amocas.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + + +amoadd.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoadd.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoand.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoand.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoswap.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoswap.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoxor.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoxor.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoor.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoor.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomin.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomin.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amominu.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amominu.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomax.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomax.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomaxu.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomaxu.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amocas.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*Zacas.*) + opcode: + amocas.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + + From a96793b651e0140faf4dab9ff8dd07efd1a714ec Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 27 Nov 2023 19:08:11 -0600 Subject: [PATCH 037/101] add template for Zicfilp tests --- riscv_ctg/data/template.yaml | 48 ++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 8498cc5a..45e6fc73 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10986,3 +10986,51 @@ c.mul: // $comment // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +lpad-m: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZicfilp + formattype: 'uformat' + imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)' + template: |- + + // $comment + // opcode: lpad ; dest:x0; immval:$imm_val + TEST_LPAD_MMODE($testreg, $swreg, $offset, $imm_val) + +lpad-s: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZicfilp + formattype: 'uformat' + imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)' + template: |- + + // $comment + // opcode: lpad ; dest:x0; immval:$imm_val + TEST_LPAD_SMODE($testreg, $swreg, $offset, $imm_val) + +lpad-u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZicfilp + formattype: 'uformat' + imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)' + template: |- + + // $comment + // opcode: lpad ; dest:x0; immval:$imm_val + TEST_LPAD_UMODE($testreg, $swreg, $offset, $imm_val) From 8181252d90863e58c55c68430f7bb3af424419cb Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 27 Nov 2023 19:08:31 -0600 Subject: [PATCH 038/101] add sample cgf for Zicfilp tests --- sample_cgfs/zicfilp.cgf | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 sample_cgfs/zicfilp.cgf diff --git a/sample_cgfs/zicfilp.cgf b/sample_cgfs/zicfilp.cgf new file mode 100644 index 00000000..61358bee --- /dev/null +++ b/sample_cgfs/zicfilp.cgf @@ -0,0 +1,44 @@ +lpad-m: + config: + - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + opcode: + lpad-m: 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 + +lpad-s: + config: + - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + opcode: + lpad-s: 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 + +lpad-u: + config: + - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + opcode: + lpad-u: 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 From c4e6e6a1674343e98fa90d0a90a9d71859b47641 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sun, 17 Dec 2023 09:08:57 -0600 Subject: [PATCH 039/101] add template for Zicfiss tests --- riscv_ctg/data/template.yaml | 193 +++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 8498cc5a..240a8f4c 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10986,3 +10986,196 @@ c.mul: // $comment // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sspushpopchk_u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32, 64] + std_op: + isa: + - I_Zicfiss_Zicsr + formattype: 'rformat' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + // $comment + TEST_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Umode) + +sspushpopchk_s: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32, 64] + std_op: + isa: + - I_Zicfiss_Zicsr + formattype: 'rformat' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + // $comment + TEST_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Smode) + +c.sspushpopchk_u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32, 64] + std_op: + isa: + - IC_Zicfiss_Zicsr + formattype: 'crformat' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + // $comment + TEST_C_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Umode) + +c.sspushpopchk_s: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32, 64] + std_op: + isa: + - IC_Zicfiss_Zicsr + formattype: 'crformat' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + // $comment + TEST_C_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Smode) + +ssamoswap.w_s: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA_Zicfiss_Zicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSAMOSWAP_OP(ssamoswap.w, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Smode) + +ssamoswap.d_s: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA_Zicfiss_Zicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSAMOSWAP_OP(ssamoswap.d, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Smode) + +ssamoswap.w_u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA_Zicfiss_Zicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSAMOSWAP_OP(ssamoswap.w, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Umode) + +ssamoswap.d_u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA_Zicfiss_Zicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSAMOSWAP_OP(ssamoswap.d, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Umode) + +ssrdp_s: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs_mx0 + xlen: [32,64] + std_op: + isa: + - I_Zicfiss_Zicsr + formattype: 'rformat' + template: |- + + // $comment + // opcode:ssrdp; dest: $rd; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSRDP_OP(ssrdp, $rd, $swreg, $testreg, Smode) + +ssrdp_u: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs_mx0 + xlen: [32,64] + std_op: + isa: + - I_Zicfiss_Zicsr + formattype: 'rformat' + template: |- + + // $comment + // opcode:ssrdp; dest: $rd; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSRDP_OP(ssrdp, $rd, $swreg, $testreg, Umode) + From 682f347cb61e0d0c2af05dfcb13ed9471ca65415 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sun, 17 Dec 2023 09:09:20 -0600 Subject: [PATCH 040/101] add sample cgf for Zicfiss tests --- sample_cgfs/zicfiss.cgf | 133 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 sample_cgfs/zicfiss.cgf diff --git a/sample_cgfs/zicfiss.cgf b/sample_cgfs/zicfiss.cgf new file mode 100644 index 00000000..39cbffa8 --- /dev/null +++ b/sample_cgfs/zicfiss.cgf @@ -0,0 +1,133 @@ +sspush_popchk_u: + config: + - check ISA:=regex(.*I.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + opcode: + sspushpopchk_u: 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +sspush_popchk_s: + config: + - check ISA:=regex(.*I.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + opcode: + sspushpopchk_s: 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +csspush_popchk_u: + config: + - check ISA:=regex(.*I.*C.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + opcode: + c.sspushpopchk_u: 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +csspush_popchk_s: + config: + - check ISA:=regex(.*I.*C.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + opcode: + c.sspushpopchk_s: 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +ssamoswap.w_s: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssamoswap.w_s: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +ssamoswap.d_s: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssamoswap.d_s: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + + +ssamoswap.w_u: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssamoswap.w_u: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +ssamoswap.d_u: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssamoswap.d_u: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +ssrdp_u: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssrdp_u: 0 + rd: + <<: *all_regs_mx0 + op_comb: + <<: *rfmt_op_comb + +ssrdp_s: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssrdp_s: 0 + rd: + <<: *all_regs_mx0 + op_comb: + <<: *rfmt_op_comb + From 812fa33981c73391be17028b3bfb9fa8cb786fe5 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Tue, 26 Dec 2023 21:03:26 +0530 Subject: [PATCH 041/101] fix template.yaml for compressed bitmanip instructions --- riscv_ctg/data/template.yaml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 8498cc5a..09d01163 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10842,7 +10842,7 @@ c.sb: template: |- // $comment - // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0) c.sh: @@ -10862,7 +10862,7 @@ c.sh: template: |- // $comment - // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0) c.sext.b: @@ -10877,7 +10877,7 @@ c.sext.b: rs1_op_data: *c_regs rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- - + // $comment // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -10894,7 +10894,7 @@ c.sext.h: rs1_op_data: *c_regs rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[65408]' template: |- - + // $comment // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -10911,7 +10911,7 @@ c.zext.b: rs1_op_data: *c_regs rs1_val_data: 'gen_usign_dataset(xlen)+[128]' template: |- - + // $comment // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -10928,7 +10928,7 @@ c.zext.h: rs1_op_data: *c_regs rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' template: |- - + // $comment // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -10945,7 +10945,7 @@ c.zext.w: rs1_op_data: *c_regs rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' template: |- - + // $comment // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) @@ -10962,7 +10962,7 @@ c.not: rs1_op_data: *c_regs rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' template: |- - + // $comment // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) From 22a65b8079030ada0a27ae5fa0bf2d8dff1710be Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Tue, 26 Dec 2023 21:04:40 +0530 Subject: [PATCH 042/101] Remove print statements from generator.py --- riscv_ctg/generator.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 2b95091c..ada44f00 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -1254,14 +1254,14 @@ def reformat_instr(self, instr_dict): if 'val' in field and field != 'correctval' and field != 'valaddr_reg' and \ field != 'val_section' and field != 'val_offset' and field != 'rm_val': value = (instr_dict[i][field]).strip() - print(value) + #print(value) if '0x' in value: value = '0x' + value[2:].zfill(int(self.xlen/4)) value = struct.unpack(size, bytes.fromhex(value[2:]))[0] else: value = int(value) # value = '0x' + struct.pack(size,value).hex() - print("test",hex(value)) + #print("test",hex(value)) instr_dict[i][field] = hex(value) return instr_dict From 4c69b0000afa43baee3ccb2fdc38c176dd2ba6ac Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 27 Dec 2023 10:35:39 +0530 Subject: [PATCH 043/101] Fix corner case for division --- riscv-isac | 1 + riscv_ctg/data/imc.yaml | 2 +- sample_cgfs/dataset.cgf | 4 +++- sample_cgfs/rv32im.cgf | 2 +- 4 files changed, 6 insertions(+), 3 deletions(-) create mode 160000 riscv-isac diff --git a/riscv-isac b/riscv-isac new file mode 160000 index 00000000..d5927473 --- /dev/null +++ b/riscv-isac @@ -0,0 +1 @@ +Subproject commit d59274739ebaaaeb65784d332b3824dcedd49665 diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index 571b6273..963f1eab 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1077,7 +1077,7 @@ div: - IM formattype: 'rformat' operation: 'hex(int(abs(rs1_val)//abs(rs2_val))) if (rs1_val * rs2_val > 0) else hex(-int(abs(rs1_val)//abs(rs2_val))) if rs2_val != 0 else "0x"+("F"*int(xlen/4))' - rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True) + 0x8000000000000000' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index a730178f..9211a639 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -291,9 +291,11 @@ datasets: 'rs1_val > 0 and rs2_val < 0': 0 'rs1_val < 0 and rs2_val < 0': 0 'rs1_val < 0 and rs2_val > 0': 0 - 'rs1_val == -0x8000000000000000 and rs2_val == -0x01': 0 'rs1_val == rs2_val': 0 'rs1_val != rs2_val': 0 + + div_corner_case: &div_corner_case + 'rs1_val == -0x8000000000000000 and rs2_val == -0x01': 0 rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn 'rs1_val > 0 and rs2_val > 0': 0 diff --git a/sample_cgfs/rv32im.cgf b/sample_cgfs/rv32im.cgf index 0af3d178..149f89d0 100644 --- a/sample_cgfs/rv32im.cgf +++ b/sample_cgfs/rv32im.cgf @@ -91,7 +91,7 @@ div: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] From f3d7ce90f65fb7d50c4887dc84bace735cceb1b5 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 27 Dec 2023 14:57:47 +0530 Subject: [PATCH 044/101] Remove corner case for division --- riscv_ctg/data/imc.yaml | 2 +- sample_cgfs/dataset.cgf | 3 --- sample_cgfs/rv32im.cgf | 2 +- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index 963f1eab..571b6273 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1077,7 +1077,7 @@ div: - IM formattype: 'rformat' operation: 'hex(int(abs(rs1_val)//abs(rs2_val))) if (rs1_val * rs2_val > 0) else hex(-int(abs(rs1_val)//abs(rs2_val))) if rs2_val != 0 else "0x"+("F"*int(xlen/4))' - rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True) + 0x8000000000000000' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index 9211a639..4e1b0b91 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -293,9 +293,6 @@ datasets: 'rs1_val < 0 and rs2_val > 0': 0 'rs1_val == rs2_val': 0 'rs1_val != rs2_val': 0 - - div_corner_case: &div_corner_case - 'rs1_val == -0x8000000000000000 and rs2_val == -0x01': 0 rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn 'rs1_val > 0 and rs2_val > 0': 0 diff --git a/sample_cgfs/rv32im.cgf b/sample_cgfs/rv32im.cgf index 149f89d0..0af3d178 100644 --- a/sample_cgfs/rv32im.cgf +++ b/sample_cgfs/rv32im.cgf @@ -91,7 +91,7 @@ div: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] From 2f7c48cba4f9bd55c3cde338aaf7c3127c354c94 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 27 Dec 2023 16:05:00 +0530 Subject: [PATCH 045/101] Add corner case for division operations --- riscv_ctg/data/imc.yaml | 4 ++-- sample_cgfs/dataset.cgf | 3 +++ sample_cgfs/rv32im.cgf | 4 ++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index 571b6273..684d7d3c 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1077,7 +1077,7 @@ div: - IM formattype: 'rformat' operation: 'hex(int(abs(rs1_val)//abs(rs2_val))) if (rs1_val * rs2_val > 0) else hex(-int(abs(rs1_val)//abs(rs2_val))) if rs2_val != 0 else "0x"+("F"*int(xlen/4))' - rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True) + [-(2**(xlen-1))]' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- @@ -1120,7 +1120,7 @@ rem: formattype: 'rformat' # operation: 'hex(rs1_val if rs2_val==0 or (rs1_val 0 else hex(-int(abs(rs1_val) % abs(rs2_val)))' - rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True) + [-(2**(xlen-1))]' rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index 4e1b0b91..724e0a5f 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -293,6 +293,9 @@ datasets: 'rs1_val < 0 and rs2_val > 0': 0 'rs1_val == rs2_val': 0 'rs1_val != rs2_val': 0 + + div_corner_case: &div_corner_case + 'rs1_val == -(2**(xlen-1)) and rs2_val == -0x01': 0 rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn 'rs1_val > 0 and rs2_val > 0': 0 diff --git a/sample_cgfs/rv32im.cgf b/sample_cgfs/rv32im.cgf index 0af3d178..f364cebd 100644 --- a/sample_cgfs/rv32im.cgf +++ b/sample_cgfs/rv32im.cgf @@ -91,7 +91,7 @@ div: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] @@ -129,7 +129,7 @@ rem: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] From bfa6e63894fb1a447fb837eb8905cc548274251b Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 27 Dec 2023 20:50:42 +0530 Subject: [PATCH 046/101] Fix OpComb for amocas.d_32 and amocas.q --- riscv_ctg/data/template.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 09d01163..e54621d6 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10713,8 +10713,8 @@ amocas.d_32: dcas_profile: 'pnp' formattype: 'dcasrformat' rs1_op_data: *all_regs_mx0 - rs2_op_data: *rv32rv64pair_regs - rd_op_data: *rv32rv64pair_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs rs1_val_data: 'gen_sign_dataset(64)' rs2_val_data: 'gen_sign_dataset(64)' @@ -10757,8 +10757,8 @@ amocas.q: dcas_profile: 'pnp' formattype: 'dcasrformat' rs1_op_data: *all_regs_mx0 - rs2_op_data: *rv32rv64pair_regs - rd_op_data: *rv32rv64pair_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs rs1_val_data: 'gen_sign_dataset(128)' rs2_val_data: 'gen_sign_dataset(128)' From 6695da62d5ed738b9ffc28e87341f22df1038e13 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 28 Dec 2023 18:00:51 +0530 Subject: [PATCH 047/101] Fix c.jr and c.jalr in rv32ic.cgf --- sample_cgfs/dataset.cgf | 10 ++++++++++ sample_cgfs/rv32ic.cgf | 14 ++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index 724e0a5f..1961b4fb 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -251,12 +251,22 @@ datasets: sfmt_op_comb: &sfmt_op_comb 'rs1 == rs2': 0 'rs1 != rs2': 0 + + r0fmt_op_comb: &r0fmt_op_comb + 'rs1 == 0': 0 + 'rs1 != 0': 0 base_rs1val_sgn: &base_rs1val_sgn 'rs1_val == (-2**(xlen-1))': 0 'rs1_val == 0': 0 'rs1_val == (2**(xlen-1)-1)': 0 'rs1_val == 1': 0 + + base_rs1val_sgn_rs2val_zero: &base_rs1val_sgn_rs2val_zero + 'rs1_val == (-2**(xlen-1)) and rs2_val == 0': 0 + 'rs1_val == 0 and rs2_val == 0': 0 + 'rs1_val == (2**(xlen-1)-1) and rs2_val == 0': 0 + 'rs1_val == 1 and rs2_val == 0': 0 base_rs2val_sgn: &base_rs2val_sgn 'rs2_val == (-2**(xlen-1))': 0 diff --git a/sample_cgfs/rv32ic.cgf b/sample_cgfs/rv32ic.cgf index a3991032..ff268449 100644 --- a/sample_cgfs/rv32ic.cgf +++ b/sample_cgfs/rv32ic.cgf @@ -401,6 +401,13 @@ cjr: c.jr: 0 rs1: <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking cmv: config: @@ -444,6 +451,13 @@ cjalr: c.jalr: 0 rs1: <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking cswsp: config: From a9a9c64ebda04a76754c86f38227bfb84a105d3b Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 28 Dec 2023 18:01:02 +0530 Subject: [PATCH 048/101] Fix imc.yaml for c.li, c.lwsp, c.jal, c.jr, c,jalr --- riscv_ctg/data/imc.yaml | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index 684d7d3c..1787ff66 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1595,6 +1595,7 @@ c.li: formattype: 'ciformat' operation : 'hex(sign_extend(imm_val,6))' imm_val_data: 'gen_sign_dataset(6)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- // $comment @@ -1709,6 +1710,7 @@ c.lwsp: - IC formattype: 'ciformat' imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- // $comment @@ -1830,6 +1832,7 @@ c.jal: - IC formattype: 'cbformat' imm_val_data: 'list(filter(lambda x: (x >=4 and x<2030) if x>0 else (x<=-4 and x> -2030 ),[x*2 for x in gen_sign_dataset(11)]))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- // $comment @@ -1846,11 +1849,13 @@ c.jr: isa: - IC formattype: 'crformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- // $comment - // opcode: c.jr; op1:$rs1 - TEST_CJR_OP($testreg, $rs1, $swreg, $offset) + // opcode: c.jr; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CJR_OP($testreg, $rs1, $rs2, $swreg, $offset) c.jalr: sig: @@ -1862,9 +1867,11 @@ c.jalr: isa: - IC formattype: 'crformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- // $comment - // opcode:c.jalr; op1:$rs1 - TEST_CJALR_OP($testreg, $rs1, $swreg, $offset) + // opcode: c.jr; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CJR_OP($testreg, $rs1, $rs2, $swreg, $offset) From 53394ea20f8d3f38623b0bce2a22408286419567 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 28 Dec 2023 18:01:41 +0530 Subject: [PATCH 049/101] Fix cnot in rv32i_zcb.cgf --- sample_cgfs/rv32i_zcb.cgf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sample_cgfs/rv32i_zcb.cgf b/sample_cgfs/rv32i_zcb.cgf index 86ba722a..2fc96375 100644 --- a/sample_cgfs/rv32i_zcb.cgf +++ b/sample_cgfs/rv32i_zcb.cgf @@ -147,6 +147,8 @@ cnot: c.not: 0 rs1: <<: *c_regs + op_comb: + <<: *r0fmt_op_comb val_comb: 'rs1_val == 0': 0 'rs1_val == 0x800': 0 From d65fbb512c75cfca621de1967290480ee2a76f1a Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Thu, 28 Dec 2023 16:12:52 -0600 Subject: [PATCH 050/101] add srmcfg CSR --- riscv_ctg/csr_comb.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv_ctg/csr_comb.py b/riscv_ctg/csr_comb.py index 2e83b3b6..4e73dde5 100644 --- a/riscv_ctg/csr_comb.py +++ b/riscv_ctg/csr_comb.py @@ -15,7 +15,7 @@ 'or' : -3, } -CSR_REGS = ['mvendorid', 'marchid', 'mimpid', 'mhartid', 'mstatus', 'misa', 'medeleg', 'mideleg', 'mie', 'mtvec', 'mcounteren', 'mscratch', 'mepc', 'mcause', 'mtval', 'mip', 'pmpcfg0', 'pmpcfg1', 'pmpcfg2', 'pmpcfg3', 'mcycle', 'minstret', 'mcycleh', 'minstreth', 'mcountinhibit', 'tselect', 'tdata1', 'tdata2', 'tdata3', 'dcsr', 'dpc', 'dscratch0', 'dscratch1', 'sstatus', 'sedeleg', 'sideleg', 'sie', 'stvec', 'scounteren', 'sscratch', 'sepc', 'scause', 'stval', 'sip', 'satp', 'vxsat', 'fflags', 'frm', 'fcsr'] +CSR_REGS = ['mvendorid', 'marchid', 'mimpid', 'mhartid', 'mstatus', 'misa', 'medeleg', 'mideleg', 'mie', 'mtvec', 'mcounteren', 'mscratch', 'mepc', 'mcause', 'mtval', 'mip', 'pmpcfg0', 'pmpcfg1', 'pmpcfg2', 'pmpcfg3', 'mcycle', 'minstret', 'mcycleh', 'minstreth', 'mcountinhibit', 'tselect', 'tdata1', 'tdata2', 'tdata3', 'dcsr', 'dpc', 'dscratch0', 'dscratch1', 'sstatus', 'sedeleg', 'sideleg', 'sie', 'stvec', 'scounteren', 'sscratch', 'sepc', 'scause', 'stval', 'sip', 'satp', 'vxsat', 'fflags', 'frm', 'fcsr', 'CSR_SRMCFG'] csr_regs_capture_group = f'({"|".join(CSR_REGS)})' csr_regs_with_modifiers_capture_group = r'(write|old) *\( *"' + csr_regs_capture_group + r'" *\)' From 7e46f40c2a6e5f40c8ebc99a428dc87effe190c1 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Thu, 28 Dec 2023 14:43:55 -0600 Subject: [PATCH 051/101] include Zicsr for CSR test ISA --- CHANGELOG.md | 2 ++ riscv_ctg/__init__.py | 2 +- riscv_ctg/csr_comb.py | 2 +- setup.cfg | 2 +- 4 files changed, 5 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 6b9d1fef..ee3299e5 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,6 +5,8 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.htm Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. Only when a release to the main branch is done, the contents of the WIP-DEV are put under a versioned header while the `WIP-DEV` is left empty +## [WIP-DEV] +- Add Zicsr to test ISA string for csr comb generated tests ## [WIP-DEV] - Added Zifencei, Bit Manipulation and Privilege tests ctg files for RV32E diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py index e0d030a3..cd7b2b43 100644 --- a/riscv_ctg/__init__.py +++ b/riscv_ctg/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'incorebot@gmail.com' -__version__ = '0.11.1' +__version__ = '0.11.2' diff --git a/riscv_ctg/csr_comb.py b/riscv_ctg/csr_comb.py index 2e83b3b6..b4cfecc7 100644 --- a/riscv_ctg/csr_comb.py +++ b/riscv_ctg/csr_comb.py @@ -260,7 +260,7 @@ class GeneratorCSRComb(): ''' def __init__(self, base_isa, xlen, randomize): - self.base_isa = base_isa + self.base_isa = base_isa + "_Zicsr" self.xlen = xlen self.randomize = randomize diff --git a/setup.cfg b/setup.cfg index a9364240..d4d3ae2c 100644 --- a/setup.cfg +++ b/setup.cfg @@ -1,5 +1,5 @@ [bumpversion] -current_version = 0.11.1 +current_version = 0.11.2 commit = True tag = True From 3a6cedf0b745000e79f6f38bef3c34104d6593a8 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Thu, 28 Dec 2023 15:54:56 -0600 Subject: [PATCH 052/101] offset must advance by xlen bits --- CHANGELOG.md | 2 -- riscv_ctg/__init__.py | 2 +- riscv_ctg/csr_comb.py | 2 +- setup.cfg | 2 +- 4 files changed, 3 insertions(+), 5 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ee3299e5..6b9d1fef 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,8 +5,6 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.htm Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. Only when a release to the main branch is done, the contents of the WIP-DEV are put under a versioned header while the `WIP-DEV` is left empty -## [WIP-DEV] -- Add Zicsr to test ISA string for csr comb generated tests ## [WIP-DEV] - Added Zifencei, Bit Manipulation and Privilege tests ctg files for RV32E diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py index cd7b2b43..e0d030a3 100644 --- a/riscv_ctg/__init__.py +++ b/riscv_ctg/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'incorebot@gmail.com' -__version__ = '0.11.2' +__version__ = '0.11.1' diff --git a/riscv_ctg/csr_comb.py b/riscv_ctg/csr_comb.py index b4cfecc7..e4c536e2 100644 --- a/riscv_ctg/csr_comb.py +++ b/riscv_ctg/csr_comb.py @@ -366,7 +366,7 @@ def csr_comb(self, cgf_node): instr_dict_csr_read_and_sig_upds.append({ 'csr_reg': csr_reg, 'dest_reg': dest_reg, 'offset': offset }) - offset += 4 + offset += (self.xlen >> 3) instr_dict.append((instr_dict_csr_writes, instr_dict_csr_read_and_sig_upds, instr_dict_csr_restores)) diff --git a/setup.cfg b/setup.cfg index d4d3ae2c..a9364240 100644 --- a/setup.cfg +++ b/setup.cfg @@ -1,5 +1,5 @@ [bumpversion] -current_version = 0.11.2 +current_version = 0.11.1 commit = True tag = True From 7b2237308a199488761ac23d8211af8264e474a2 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 10 Jan 2024 10:56:49 +0530 Subject: [PATCH 053/101] Fix c.jr and c.jalr in imc.yaml --- riscv_ctg/data/imc.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index 1787ff66..abd6617f 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1854,8 +1854,8 @@ c.jr: template: |- // $comment - // opcode: c.jr; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val - TEST_CJR_OP($testreg, $rs1, $rs2, $swreg, $offset) + // opcode: c.jr; op1:$rs1 + TEST_CJR_OP($testreg, $rs1, $swreg, $offset) c.jalr: sig: @@ -1872,6 +1872,6 @@ c.jalr: template: |- // $comment - // opcode: c.jr; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val - TEST_CJR_OP($testreg, $rs1, $rs2, $swreg, $offset) + // opcode: c.jalr; op1:$rs1 + TEST_CJALR_OP($testreg, $rs1, $swreg, $offset) From b39262899b802b6e91a42f9d6c28277410854bf5 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 10 Jan 2024 11:47:23 +0530 Subject: [PATCH 054/101] Fix c.jr and c.jalr in rv64ic.cgf --- sample_cgfs/rv64ic.cgf | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/sample_cgfs/rv64ic.cgf b/sample_cgfs/rv64ic.cgf index f6acf8f4..3aa8baec 100644 --- a/sample_cgfs/rv64ic.cgf +++ b/sample_cgfs/rv64ic.cgf @@ -493,6 +493,13 @@ cjr: c.jr: 0 rs1: <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking cmv: config: @@ -536,7 +543,14 @@ cjalr: c.jalr: 0 rs1: <<: *all_regs_mx0 - + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking + cswsp: config: - check ISA:=regex(.*I.*C.*) From 8511ca8c895814360c48bae51afe72ca2e03f658 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 10 Jan 2024 11:54:28 +0530 Subject: [PATCH 055/101] Fix cnot in rv64i_zcb.cgf --- sample_cgfs/rv64i_zcb.cgf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sample_cgfs/rv64i_zcb.cgf b/sample_cgfs/rv64i_zcb.cgf index 0b9a48f9..3bad58b7 100644 --- a/sample_cgfs/rv64i_zcb.cgf +++ b/sample_cgfs/rv64i_zcb.cgf @@ -162,6 +162,8 @@ cnot: c.not: 0 rs1: <<: *c_regs + op_comb: + <<: *r0fmt_op_comb val_comb: 'rs1_val == 0': 0 'rs1_val == 0x800': 0 From f0c47345b7dbc543824919955b53909572b9a8d7 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 10 Jan 2024 12:55:18 +0530 Subject: [PATCH 056/101] Fix rv32i_b.cgf and rv64i_b.cgf --- sample_cgfs/rv32i_b.cgf | 48 +++++++++++++-------------- sample_cgfs/rv64i_b.cgf | 72 ++++++++++++++++++++--------------------- 2 files changed, 60 insertions(+), 60 deletions(-) diff --git a/sample_cgfs/rv32i_b.cgf b/sample_cgfs/rv32i_b.cgf index 5893bc0e..7f2ef12b 100644 --- a/sample_cgfs/rv32i_b.cgf +++ b/sample_cgfs/rv32i_b.cgf @@ -138,10 +138,10 @@ clz: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 ctz: config: @@ -157,10 +157,10 @@ ctz: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 cpop: config: @@ -176,10 +176,10 @@ cpop: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 max: config: @@ -537,8 +537,8 @@ bclr: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -561,7 +561,7 @@ bclri: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 @@ -583,8 +583,8 @@ bext: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -607,7 +607,7 @@ bexti: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 @@ -629,8 +629,8 @@ binv: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -653,7 +653,7 @@ binvi: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 @@ -674,8 +674,8 @@ bset: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -698,7 +698,7 @@ bseti: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 diff --git a/sample_cgfs/rv64i_b.cgf b/sample_cgfs/rv64i_b.cgf index 7fc20838..7087ed6d 100644 --- a/sample_cgfs/rv64i_b.cgf +++ b/sample_cgfs/rv64i_b.cgf @@ -234,10 +234,10 @@ clz: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 clzw: @@ -254,10 +254,10 @@ clzw: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 ctz: config: @@ -273,10 +273,10 @@ ctz: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 ctzw: config: @@ -292,10 +292,10 @@ ctzw: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 cpop: @@ -312,10 +312,10 @@ cpop: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 cpopw: config: @@ -331,10 +331,10 @@ cpopw: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 max: config: @@ -764,8 +764,8 @@ bclr: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -788,7 +788,7 @@ bclri: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 @@ -810,8 +810,8 @@ bext: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -834,7 +834,7 @@ bexti: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 @@ -856,8 +856,8 @@ binv: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -880,7 +880,7 @@ binvi: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 @@ -901,8 +901,8 @@ bset: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -926,7 +926,7 @@ bseti: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 From 40497fbc357155334f4260b3a3088e57cf7ffafb Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 10 Jan 2024 12:57:45 +0530 Subject: [PATCH 057/101] Fix template.yaml for rolw, bclri, bexti, binvi, bseti --- riscv_ctg/data/template.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index e54621d6..94448f1a 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -2574,6 +2574,7 @@ bclri: rs1_op_data: *all_regs rd_op_data: *all_regs rs1_val_data: 'zerotoxlen(xlen)+[-1]' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' template: |- // $comment @@ -2682,6 +2683,7 @@ bexti: rs1_op_data: *all_regs rd_op_data: *all_regs rs1_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' template: |- // $comment @@ -2792,6 +2794,7 @@ binvi: rs1_op_data: *all_regs rd_op_data: *all_regs rs1_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' template: |- // $comment @@ -10131,6 +10134,7 @@ bseti: rs1_op_data: *all_regs rd_op_data: *all_regs rs1_val_data: 'zerotoxlen(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' template: |- // $comment From 1b3a0fac3964a96c508ebe31d9416e9282e7ac49 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 10 Jan 2024 13:17:46 +0530 Subject: [PATCH 058/101] Fix rv32e_b.cgf --- sample_cgfs/rv32e_b.cgf | 48 ++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/sample_cgfs/rv32e_b.cgf b/sample_cgfs/rv32e_b.cgf index ce8a0e64..6ab80eb1 100644 --- a/sample_cgfs/rv32e_b.cgf +++ b/sample_cgfs/rv32e_b.cgf @@ -138,10 +138,10 @@ clz: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 ctz: config: @@ -157,10 +157,10 @@ ctz: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 cpop: config: @@ -176,10 +176,10 @@ cpop: val_comb: abstract_comb: <<: [*rs1val_walking_unsgn] - 'leading_zeros("rs1_val", xlen, False)': 0 - 'leading_ones("rs1_val", xlen, False)': 0 - 'trailing_zeros("rs1_val", xlen, False)': 0 - 'trailing_ones("rs1_val", xlen, False)': 0 + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 max: config: @@ -537,8 +537,8 @@ bclr: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -561,7 +561,7 @@ bclri: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 @@ -583,8 +583,8 @@ bext: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -607,7 +607,7 @@ bexti: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 @@ -629,8 +629,8 @@ binv: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -653,7 +653,7 @@ binvi: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 @@ -674,8 +674,8 @@ bset: <<: *rfmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 - 'xlenlim("rs2_val", xlen )': 0 +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 @@ -698,7 +698,7 @@ bseti: <<: *ifmt_op_comb val_comb: abstract_comb: - 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs1_val", xlen)': 0 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 From 667e1598b6d6eb49ac059745b9ba124b151929a3 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 10 Jan 2024 13:58:54 +0530 Subject: [PATCH 059/101] Fix template.yaml for rolw --- riscv_ctg/data/template.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 94448f1a..423116ec 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -836,6 +836,8 @@ rolw: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- // $comment From 65f442143d69342011138933625f4f7e1504de2b Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 10 Jan 2024 15:23:47 +0530 Subject: [PATCH 060/101] Fix template.yaml for rolw --- riscv_ctg/data/template.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 423116ec..dfe4884c 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -836,8 +836,8 @@ rolw: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs - rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' - rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' template: |- // $comment From 3ffd4f1da1b92dc03fe6b12d51e737eb22562124 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 11 Jan 2024 10:24:33 +0530 Subject: [PATCH 061/101] Fix xperm8 in rv64i_k --- sample_cgfs/rv64i_k.cgf | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sample_cgfs/rv64i_k.cgf b/sample_cgfs/rv64i_k.cgf index a4310aea..87d34b96 100644 --- a/sample_cgfs/rv64i_k.cgf +++ b/sample_cgfs/rv64i_k.cgf @@ -140,8 +140,9 @@ xperm8: <<: *rfmt_op_comb val_comb: abstract_comb: - 'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64],False)': 0 - 'walikng_ones(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64])': 0 + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_ones("rs2_val", 64, False)': 0 'trailing_ones(64, ["rs1_val","rs2_val"], [64,64],False)': 0 'leading_zeros(64, ["rs1_val","rs2_val"], [64,64],False)': 0 'trailing_zeros(64, ["rs1_val","rs2_val"], [64,64],False)': 0 From 2a4f057af0528abe1b615654bfa0ee9c6dd694c5 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 11 Jan 2024 11:42:54 +0530 Subject: [PATCH 062/101] add rs1_val_data for sd, sw, sh, sb, ld, lwu, lw, lhu, lh, lbu, lb, jalr --- riscv_ctg/data/imc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index abd6617f..9e52b81d 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -744,6 +744,7 @@ sd: ea_align_data: '[0,1,2,3,4,5,6,7]' rs2_val_data: 'gen_sign_dataset(xlen)' imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' template: |- // $comment @@ -763,6 +764,7 @@ sw: formattype: 'sformat' ea_align_data: '[0,1,2,3]' rs2_val_data: 'gen_sign_dataset(xlen)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' imm_val_data: 'gen_sign_dataset(12)' template: |- @@ -783,6 +785,7 @@ sh: formattype: 'sformat' ea_align_data: '[0,1,2,3]' rs2_val_data: 'gen_sign_dataset(xlen)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' imm_val_data: 'gen_sign_dataset(12)' template: |- @@ -803,6 +806,7 @@ sb: formattype: 'sformat' ea_align_data: '[0,1,2,3]' rs2_val_data: 'gen_sign_dataset(xlen)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' imm_val_data: 'gen_sign_dataset(12)' template: |- @@ -823,6 +827,7 @@ ld: formattype: 'iformat' ea_align_data: '[0,1,2,3,4,5,6,7]' imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' template: |- // $comment @@ -842,6 +847,7 @@ lwu: formattype: 'iformat' ea_align_data: '[0,1,2,3]' imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,True)' template: |- // $comment @@ -860,6 +866,7 @@ lw: - I formattype: 'iformat' ea_align_data: '[0,1,2,3]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' imm_val_data: 'gen_sign_dataset(12)' template: |- @@ -879,6 +886,7 @@ lhu: - I formattype: 'iformat' ea_align_data: '[0,1,2,3]' + rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,True)' imm_val_data: 'gen_sign_dataset(12)' template: |- @@ -898,6 +906,7 @@ lh: - I formattype: 'iformat' ea_align_data: '[0,1,2,3]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' imm_val_data: 'gen_sign_dataset(12)' template: |- @@ -918,6 +927,7 @@ lbu: formattype: 'iformat' ea_align_data: '[0,1,2,3]' imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,True)' template: |- // $comment @@ -937,6 +947,7 @@ lb: formattype: 'iformat' ea_align_data: '[0,1,2,3]' imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' template: |- // $comment @@ -973,6 +984,7 @@ jalr: - I formattype: 'iformat' ea_align_data: '[0,1,2,3]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' imm_val_data: 'gen_sign_dataset(12)' template: |- From ae23d60a5e2870e0325ac589f545d4556be3ba74 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 11 Jan 2024 12:06:13 +0530 Subject: [PATCH 063/101] add rs1_val_data, rs2_val_data, imm_val_data for aes32dsi, aes32dsmi, aes32esi, aes32esmi, sm4ed, sm4ks --- riscv_ctg/data/template.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index dfe4884c..6fd0dbbf 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -15,6 +15,9 @@ aes32dsi: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' xlen: [32] std_op: isa: @@ -35,6 +38,9 @@ aes32dsmi: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' xlen: [32] std_op: isa: @@ -55,6 +61,9 @@ aes32esi: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' xlen: [32] std_op: isa: @@ -75,6 +84,9 @@ aes32esmi: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' xlen: [32] std_op: isa: @@ -95,6 +107,9 @@ sm4ed: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' xlen: [32,64] std_op: isa: @@ -114,6 +129,9 @@ sm4ks: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' xlen: [32,64] std_op: isa: From 704d795ecc15173891789490d98739bf94e95512 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 11 Jan 2024 12:10:57 +0530 Subject: [PATCH 064/101] add rs1_val_data for zip, unzip --- riscv_ctg/data/template.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 6fd0dbbf..fad5e14a 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -472,6 +472,7 @@ zip: formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- // $comment @@ -495,6 +496,7 @@ unzip: formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- // $comment From 3bcdf9132c9ecaf21e34636c21a86d92e5d168fa Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 11 Jan 2024 12:14:22 +0530 Subject: [PATCH 065/101] add rs1_val_data, rs2_val_data for pack, packh, aes64ds, aes64dsm, aes64es, aes64esm, packw --- riscv_ctg/data/template.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index fad5e14a..47942e8f 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -521,6 +521,8 @@ pack: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- // $comment @@ -560,6 +562,8 @@ packh: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- // $comment @@ -616,6 +620,8 @@ aes64ds: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- // $comment @@ -636,6 +642,8 @@ aes64dsm: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- // $comment @@ -656,6 +664,8 @@ aes64es: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- // $comment @@ -676,6 +686,8 @@ aes64esm: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- // $comment @@ -899,6 +911,8 @@ packw: rs1_op_data: *all_regs rs2_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- // $comment From de4aa9575e89ea0b47bbf35902bd8bcf1185b307 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 11 Jan 2024 12:15:28 +0530 Subject: [PATCH 066/101] add rs1_val_data and imm_val_data for aes64ks1i --- riscv_ctg/data/template.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 47942e8f..50a5c085 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -708,6 +708,8 @@ aes64ks1i: formattype: 'iformat' rs1_op_data: *all_regs rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' template: |- // $comment From ab58a0ba224d414a8f8221b80653b6060026a4ab Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 11 Jan 2024 14:59:21 +0530 Subject: [PATCH 067/101] Fix c.lui, c.jr, c.jalr in rv32ec.cgf --- sample_cgfs/rv32ec.cgf | 48 +++++++++++++----------------------------- 1 file changed, 15 insertions(+), 33 deletions(-) diff --git a/sample_cgfs/rv32ec.cgf b/sample_cgfs/rv32ec.cgf index cd8fb7c0..5a49383f 100644 --- a/sample_cgfs/rv32ec.cgf +++ b/sample_cgfs/rv32ec.cgf @@ -136,38 +136,7 @@ clui: opcode: c.lui: 0 rd: - x0: 0 - x1: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - x16: 0 - x17: 0 - x18: 0 - x19: 0 - x20: 0 - x21: 0 - x22: 0 - x23: 0 - x24: 0 - x25: 0 - x26: 0 - x27: 0 - x28: 0 - x29: 0 - x30: 0 - x31: 0 - + <<: *rv32e_regs_mx2 val_comb: 'rs1_val > 0 and imm_val > 32': 0 'rs1_val > 0 and imm_val < 32 and imm_val !=0 ': 0 @@ -401,6 +370,13 @@ cjr: c.jr: 0 rs1: <<: *rv32e_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking cmv: config: @@ -444,6 +420,13 @@ cjalr: c.jalr: 0 rs1: <<: *rv32e_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking cswsp: config: @@ -461,4 +444,3 @@ cswsp: 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 - From 939c17911951b40984687612e344ec681ef48522 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sun, 14 Jan 2024 13:35:42 -0600 Subject: [PATCH 068/101] Add B extension to template and CGF --- riscv_ctg/data/template.yaml | 39 +++++++++++++++++++++++++++++++++++ sample_cgfs/rv32i_b.cgf | 29 ++++++++++++++++++++++++++ sample_cgfs/rv64i_b.cgf | 40 ++++++++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 8498cc5a..bbe43414 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -407,6 +407,7 @@ rol: - IZk - IZkn - IZks + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -832,6 +833,7 @@ rolw: - IZk - IZkn - IZks + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -909,6 +911,7 @@ add.uw: std_op: isa: - IZba + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -929,6 +932,7 @@ sh1add: std_op: isa: - IZba + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -949,6 +953,7 @@ sh1add.uw: std_op: isa: - IZba + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -969,6 +974,7 @@ sh2add: std_op: isa: - IZba + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -989,6 +995,7 @@ sh2add.uw: std_op: isa: - IZba + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -1009,6 +1016,7 @@ sh3add: std_op: isa: - IZba + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -1029,6 +1037,7 @@ sh3add.uw: std_op: isa: - IZba + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -1049,6 +1058,7 @@ slli.uw: std_op: isa: - IZba + - IB formattype: 'iformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -1073,6 +1083,7 @@ andn: - IZk - IZkn - IZks + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -1476,6 +1487,7 @@ clz: std_op: isa: - IZbb + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -1493,6 +1505,7 @@ clzw: std_op: isa: - IZbb + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -1510,6 +1523,7 @@ cpop: std_op: isa: - IZbb + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -1527,6 +1541,7 @@ cpopw: std_op: isa: - IZbb + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -1544,6 +1559,7 @@ ctz: std_op: isa: - IZbb + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -1561,6 +1577,7 @@ ctzw: std_op: isa: - IZbb + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -1578,6 +1595,7 @@ max: std_op: isa: - IZbb + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -1623,6 +1641,7 @@ maxu: std_op: isa: - IZbb + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -1668,6 +1687,7 @@ min: std_op: isa: - IZbb + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -1713,6 +1733,7 @@ minu: std_op: isa: - IZbb + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -1784,6 +1805,7 @@ orc.b: std_op: orc.b isa: - IZbb + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -1805,6 +1827,7 @@ orn: - IZk - IZkn - IZks + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -1906,6 +1929,7 @@ rev8: - IZk - IZkn - IZks + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -1931,6 +1955,7 @@ ror: - IZk - IZkn - IZks + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -2032,6 +2057,7 @@ rori: - IZk - IZkn - IZks + - IB formattype: 'iformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -2055,6 +2081,7 @@ roriw: - IZk - IZkn - IZks + - IB formattype: 'iformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -2078,6 +2105,7 @@ rorw: - IZk - IZkn - IZks + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -2178,6 +2206,7 @@ sext.b: std_op: isa: - IZbb + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -2195,6 +2224,7 @@ sext.h: std_op: isa: - IZbb + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -2216,6 +2246,7 @@ xnor: - IZk - IZkn - IZks + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -2289,6 +2320,7 @@ zext.h: std_op: isa: - IZbb + - IB formattype: 'kformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -2480,6 +2512,7 @@ bclr: std_op: isa: - IZbs + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -2570,6 +2603,7 @@ bclri: std_op: isa: - IZbs + - IB formattype: 'iformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -2678,6 +2712,7 @@ bexti: std_op: isa: - IZbs + - IB formattype: 'iformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -2696,6 +2731,7 @@ binv: std_op: isa: - IZbs + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -2788,6 +2824,7 @@ binvi: std_op: isa: - IZbs + - IB formattype: 'iformat' rs1_op_data: *all_regs rd_op_data: *all_regs @@ -2806,6 +2843,7 @@ bset: std_op: isa: - IZbs + - IB formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10127,6 +10165,7 @@ bseti: std_op: isa: - IZbs + - IB formattype: 'iformat' rs1_op_data: *all_regs rd_op_data: *all_regs diff --git a/sample_cgfs/rv32i_b.cgf b/sample_cgfs/rv32i_b.cgf index 5893bc0e..919a9811 100644 --- a/sample_cgfs/rv32i_b.cgf +++ b/sample_cgfs/rv32i_b.cgf @@ -1,5 +1,6 @@ sh1add: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zba.*) mnemonics: sh1add: 0 @@ -19,6 +20,7 @@ sh1add: sh2add: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zba.*) mnemonics: sh2add: 0 @@ -38,6 +40,7 @@ sh2add: sh3add: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zba.*) mnemonics: sh3add: 0 @@ -57,6 +60,7 @@ sh3add: xnor: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -81,6 +85,7 @@ xnor: zext.h_32: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: zext.h: 0 @@ -102,6 +107,7 @@ zext.h_32: 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 andn: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -126,6 +132,7 @@ andn: clz: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: clz: 0 @@ -145,6 +152,7 @@ clz: ctz: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: ctz: 0 @@ -164,6 +172,7 @@ ctz: cpop: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: cpop: 0 @@ -183,6 +192,7 @@ cpop: max: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: max: 0 @@ -202,6 +212,7 @@ max: maxu: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: maxu: 0 @@ -221,6 +232,7 @@ maxu: min: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: min: 0 @@ -240,6 +252,7 @@ min: minu: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: minu: 0 @@ -259,6 +272,7 @@ minu: orcb_32: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: orc.b: 0 @@ -281,6 +295,7 @@ orcb_32: orn: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -305,6 +320,7 @@ orn: rev8_32: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -334,6 +350,7 @@ rev8_32: rol: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -358,6 +375,7 @@ rol: ror: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -382,6 +400,7 @@ ror: rori: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -404,6 +423,7 @@ rori: sext.b: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: sext.b: 0 @@ -423,6 +443,7 @@ sext.b: sext.h: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: sext.h: 0 @@ -524,6 +545,7 @@ clmulr: bclr: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bclr: 0 @@ -550,6 +572,7 @@ bclr: bclri: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bclri: 0 @@ -570,6 +593,7 @@ bclri: bext: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bext: 0 @@ -596,6 +620,7 @@ bext: bexti: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bexti: 0 @@ -616,6 +641,7 @@ bexti: binv: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: binv: 0 @@ -642,6 +668,7 @@ binv: binvi: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: binvi: 0 @@ -661,6 +688,7 @@ binvi: bset: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bset: 0 @@ -687,6 +715,7 @@ bset: bseti: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bseti: 0 diff --git a/sample_cgfs/rv64i_b.cgf b/sample_cgfs/rv64i_b.cgf index 7fc20838..26766635 100644 --- a/sample_cgfs/rv64i_b.cgf +++ b/sample_cgfs/rv64i_b.cgf @@ -1,5 +1,6 @@ add.uw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zba.*) mnemonics: add.uw: 0 @@ -19,6 +20,7 @@ add.uw: sh1add: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zba.*) mnemonics: sh1add: 0 @@ -39,6 +41,7 @@ sh1add: sh1add.uw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zba.*) mnemonics: sh1add.uw: 0 @@ -58,6 +61,7 @@ sh1add.uw: sh2add: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zba.*) mnemonics: sh2add: 0 @@ -77,6 +81,7 @@ sh2add: sh2add.uw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zba.*) mnemonics: sh2add.uw: 0 @@ -96,6 +101,7 @@ sh2add.uw: sh3add: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zba.*) mnemonics: sh3add: 0 @@ -115,6 +121,7 @@ sh3add: sh3add.uw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zba.*) mnemonics: sh3add.uw: 0 @@ -134,6 +141,7 @@ sh3add.uw: slli.uw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zba.*) mnemonics: slli.uw: 0 @@ -153,6 +161,7 @@ slli.uw: xnor: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -177,6 +186,7 @@ xnor: zext.h_64: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: zext.h: 0 @@ -198,6 +208,7 @@ zext.h_64: 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 andn: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -222,6 +233,7 @@ andn: clz: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: clz: 0 @@ -242,6 +254,7 @@ clz: clzw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zbb.*) mnemonics: clzw: 0 @@ -261,6 +274,7 @@ clzw: ctz: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: ctz: 0 @@ -280,6 +294,7 @@ ctz: ctzw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zbb.*) mnemonics: ctzw: 0 @@ -300,6 +315,7 @@ ctzw: cpop: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: cpop: 0 @@ -319,6 +335,7 @@ cpop: cpopw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zbb.*) mnemonics: cpopw: 0 @@ -338,6 +355,7 @@ cpopw: max: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: max: 0 @@ -357,6 +375,7 @@ max: maxu: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: maxu: 0 @@ -376,6 +395,7 @@ maxu: min: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: min: 0 @@ -395,6 +415,7 @@ min: minu: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: minu: 0 @@ -414,6 +435,7 @@ minu: orcb_64: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: orc.b: 0 @@ -436,6 +458,7 @@ orcb_64: orn: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -460,6 +483,7 @@ orn: rev8: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -489,6 +513,7 @@ rev8: rol: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -513,6 +538,7 @@ rol: rolw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zbb.*) - check ISA:=regex(.*RV64.*I.*Zbkb.*) - check ISA:=regex(.*RV64.*I.*Zk.*) @@ -537,6 +563,7 @@ rolw: ror: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -561,6 +588,7 @@ ror: rori: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) - check ISA:=regex(.*I.*Zbkb.*) - check ISA:=regex(.*I.*Zk.*) @@ -584,6 +612,7 @@ rori: roriw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zbb.*) - check ISA:=regex(.*RV64.*I.*Zbkb.*) - check ISA:=regex(.*RV64.*I.*Zk.*) @@ -606,6 +635,7 @@ roriw: rorw: config: + - check ISA:=regex(.*RV64.*I.*B.*) - check ISA:=regex(.*RV64.*I.*Zbb.*) - check ISA:=regex(.*RV64.*I.*Zbkb.*) - check ISA:=regex(.*RV64.*I.*Zk.*) @@ -631,6 +661,7 @@ rorw: sext.b: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: sext.b: 0 @@ -650,6 +681,7 @@ sext.b: sext.h: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbb.*) mnemonics: sext.h: 0 @@ -751,6 +783,7 @@ clmulr: bclr: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bclr: 0 @@ -777,6 +810,7 @@ bclr: bclri: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bclri: 0 @@ -797,6 +831,7 @@ bclri: bext: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bext: 0 @@ -823,6 +858,7 @@ bext: bexti: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bexti: 0 @@ -843,6 +879,7 @@ bexti: binv: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: binv: 0 @@ -869,6 +906,7 @@ binv: binvi: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: binvi: 0 @@ -888,6 +926,7 @@ binvi: bset: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bset: 0 @@ -915,6 +954,7 @@ bset: bseti: config: + - check ISA:=regex(.*I.*B.*) - check ISA:=regex(.*I.*Zbs.*) mnemonics: bseti: 0 From b3eb723801e667b4563c5e3fd4422c7e6d4c2f1f Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sun, 14 Jan 2024 13:41:26 -0600 Subject: [PATCH 069/101] Add CGF file --- sample_cgfs/srmcfg.cgf | 77 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 sample_cgfs/srmcfg.cgf diff --git a/sample_cgfs/srmcfg.cgf b/sample_cgfs/srmcfg.cgf new file mode 100644 index 00000000..411d0543 --- /dev/null +++ b/sample_cgfs/srmcfg.cgf @@ -0,0 +1,77 @@ +srmcfg: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssqosid.*); def rvtest_mtrap_routine=True + isa: + - I_Zicsr_Ssqosid + csr_comb: + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00000001': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00000003': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00000007': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0000000F': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0000001F': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0000003F': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0000007F': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x000000FF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x000001FF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x000003FF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x000007FF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00000FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00010FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00030FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00070FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x000F0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x001F0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x003F0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x007F0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00FF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x01FF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x03FF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFE': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFC': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FF8': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FF0': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FE0': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FC0': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0F80': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0F00': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0E00': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0C00': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0800': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFE0000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFC0000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FF80000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FF00000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FE00000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FC00000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0F800000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0F000000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0E000000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0C000000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x08000000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00000000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFD': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFB': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FF7': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FEF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FDF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FBF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0F7F': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0EFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0DFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0BFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF07FF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFE0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFD0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFB0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FF70FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FEF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FDF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FBF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0F7F0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0EFF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0DFF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0BFF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x07FF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFF': 0 + From 29d4ef20bc7adfeca3a2938f600d472946d0c477 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sun, 14 Jan 2024 13:47:14 -0600 Subject: [PATCH 070/101] update changelog --- CHANGELOG.md | 3 +++ riscv_ctg/__init__.py | 2 +- setup.cfg | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 6b9d1fef..8b75b68c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,9 @@ Please note the header `WIP-DEV` is to always remain indicating the changes done Only when a release to the main branch is done, the contents of the WIP-DEV are put under a versioned header while the `WIP-DEV` is left empty +## [WIP-DEV] +- Add B extension + ## [WIP-DEV] - Added Zifencei, Bit Manipulation and Privilege tests ctg files for RV32E - Added support of Zcb from Code Size Reduction Extension. diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py index e0d030a3..cd7b2b43 100644 --- a/riscv_ctg/__init__.py +++ b/riscv_ctg/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'incorebot@gmail.com' -__version__ = '0.11.1' +__version__ = '0.11.2' diff --git a/setup.cfg b/setup.cfg index a9364240..d4d3ae2c 100644 --- a/setup.cfg +++ b/setup.cfg @@ -1,5 +1,5 @@ [bumpversion] -current_version = 0.11.1 +current_version = 0.11.2 commit = True tag = True From 0b685eb552c0c0f641f90a07fecf480183ba7daa Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sun, 14 Jan 2024 14:39:37 -0600 Subject: [PATCH 071/101] Add Zaamo subcomponent of A --- riscv_ctg/data/template.yaml | 18 ++++++++++++ sample_cgfs/rv32ia.cgf | 29 ++++++++++++------- sample_cgfs/rv64ia.cgf | 56 ++++++++++++++++++++++++------------ 3 files changed, 74 insertions(+), 29 deletions(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 8498cc5a..f2474b7c 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10328,6 +10328,7 @@ amoadd.w: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10348,6 +10349,7 @@ amoand.w: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10368,6 +10370,7 @@ amoswap.w: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10388,6 +10391,7 @@ amoxor.w: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10408,6 +10412,7 @@ amoor.w: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10428,6 +10433,7 @@ amomin.w: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10448,6 +10454,7 @@ amominu.w: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10468,6 +10475,7 @@ amomax.w: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10488,6 +10496,7 @@ amomaxu.w: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10508,6 +10517,7 @@ amoadd.d: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10528,6 +10538,7 @@ amoand.d: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10548,6 +10559,7 @@ amoswap.d: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10568,6 +10580,7 @@ amoxor.d: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10588,6 +10601,7 @@ amoor.d: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10608,6 +10622,7 @@ amomin.d: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10628,6 +10643,7 @@ amominu.d: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10648,6 +10664,7 @@ amomax.d: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs @@ -10668,6 +10685,7 @@ amomaxu.d: std_op: isa: - IA + - IZaamo formattype: 'rformat' rs1_op_data: *all_regs rs2_op_data: *all_regs diff --git a/sample_cgfs/rv32ia.cgf b/sample_cgfs/rv32ia.cgf index e8f44425..cf5f345c 100644 --- a/sample_cgfs/rv32ia.cgf +++ b/sample_cgfs/rv32ia.cgf @@ -1,6 +1,7 @@ amoadd.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*32.*I.*A.*) + - check ISA:=regex(.*32.*I.*Zaamo.*) mnemonics: amoadd.w: 0 rs1: @@ -18,7 +19,8 @@ amoadd.w: amoand.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*32.*I.*A.*) + - check ISA:=regex(.*32.*I.*Zaamo.*) mnemonics: amoand.w: 0 rs1: @@ -36,7 +38,8 @@ amoand.w: amoswap.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*32.*I.*A.*) + - check ISA:=regex(.*32.*I.*Zaamo.*) mnemonics: amoswap.w: 0 rs1: @@ -54,7 +57,8 @@ amoswap.w: amoxor.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*32.*I.*A.*) + - check ISA:=regex(.*32.*I.*Zaamo.*) mnemonics: amoxor.w: 0 rs1: @@ -72,7 +76,8 @@ amoxor.w: amoor.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*32.*I.*A.*) + - check ISA:=regex(.*32.*I.*Zaamo.*) mnemonics: amoor.w: 0 rs1: @@ -90,7 +95,8 @@ amoor.w: amomin.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*32.*I.*A.*) + - check ISA:=regex(.*32.*I.*Zaamo.*) mnemonics: amomin.w: 0 rs1: @@ -108,7 +114,8 @@ amomin.w: amominu.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*32.*I.*A.*) + - check ISA:=regex(.*32.*I.*Zaamo.*) mnemonics: amominu.w: 0 rs1: @@ -126,7 +133,8 @@ amominu.w: amomax.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*32.*I.*A.*) + - check ISA:=regex(.*32.*I.*Zaamo.*) mnemonics: amomax.w: 0 rs1: @@ -144,7 +152,8 @@ amomax.w: amomaxu.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*32.*I.*A.*) + - check ISA:=regex(.*32.*I.*Zaamo.*) mnemonics: amomaxu.w: 0 rs1: @@ -158,4 +167,4 @@ amomaxu.w: val_comb: <<: [*base_rs2val_sgn] abstract_comb: - <<: [*rs2val_walking] \ No newline at end of file + <<: [*rs2val_walking] diff --git a/sample_cgfs/rv64ia.cgf b/sample_cgfs/rv64ia.cgf index 99dc8d03..2cd7895d 100644 --- a/sample_cgfs/rv64ia.cgf +++ b/sample_cgfs/rv64ia.cgf @@ -1,6 +1,7 @@ amoadd.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amoadd.w: 0 rs1: @@ -18,7 +19,8 @@ amoadd.w: amoand.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amoand.w: 0 rs1: @@ -36,7 +38,8 @@ amoand.w: amoswap.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amoswap.w: 0 rs1: @@ -54,7 +57,8 @@ amoswap.w: amoxor.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amoxor.w: 0 rs1: @@ -72,7 +76,8 @@ amoxor.w: amoor.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amoor.w: 0 rs1: @@ -90,7 +95,8 @@ amoor.w: amomin.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amomin.w: 0 rs1: @@ -108,7 +114,8 @@ amomin.w: amominu.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amominu.w: 0 rs1: @@ -126,7 +133,8 @@ amominu.w: amomax.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amomax.w: 0 rs1: @@ -144,7 +152,8 @@ amomax.w: amomaxu.w: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amomaxu.w: 0 rs1: @@ -162,7 +171,8 @@ amomaxu.w: amoadd.d: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amoadd.d: 0 rs1: @@ -180,7 +190,8 @@ amoadd.d: amoand.d: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amoand.d: 0 rs1: @@ -198,7 +209,8 @@ amoand.d: amoswap.d: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amoswap.d: 0 rs1: @@ -216,7 +228,8 @@ amoswap.d: amoxor.d: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amoxor.d: 0 rs1: @@ -234,7 +247,8 @@ amoxor.d: amoor.d: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amoor.d: 0 rs1: @@ -252,7 +266,8 @@ amoor.d: amomin.d: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amomin.d: 0 rs1: @@ -270,7 +285,8 @@ amomin.d: amominu.d: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amominu.d: 0 rs1: @@ -288,7 +304,8 @@ amominu.d: amomax.d: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amomax.d: 0 rs1: @@ -306,7 +323,8 @@ amomax.d: amomaxu.d: config: - - check ISA:=regex(.*I.*A.*) + - check ISA:=regex(.*64.*I.*A.*) + - check ISA:=regex(.*64.*I.*Zaamo.*) mnemonics: amomaxu.d: 0 rs1: @@ -320,4 +338,4 @@ amomaxu.d: val_comb: <<: [*base_rs2val_sgn] abstract_comb: - <<: [*rs2val_walking] \ No newline at end of file + <<: [*rs2val_walking] From 03b5eb2549ca84db656e2d785eec2aaeb25f7902 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sun, 14 Jan 2024 14:39:50 -0600 Subject: [PATCH 072/101] update changelog --- CHANGELOG.md | 3 +++ riscv_ctg/__init__.py | 2 +- setup.cfg | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 6b9d1fef..b158e6bd 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,9 @@ Please note the header `WIP-DEV` is to always remain indicating the changes done Only when a release to the main branch is done, the contents of the WIP-DEV are put under a versioned header while the `WIP-DEV` is left empty +## [WIP-DEV] +- Add Zaamo subcomponent of A + ## [WIP-DEV] - Added Zifencei, Bit Manipulation and Privilege tests ctg files for RV32E - Added support of Zcb from Code Size Reduction Extension. diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py index e0d030a3..cd7b2b43 100644 --- a/riscv_ctg/__init__.py +++ b/riscv_ctg/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'incorebot@gmail.com' -__version__ = '0.11.1' +__version__ = '0.11.2' diff --git a/setup.cfg b/setup.cfg index a9364240..d4d3ae2c 100644 --- a/setup.cfg +++ b/setup.cfg @@ -1,5 +1,5 @@ [bumpversion] -current_version = 0.11.1 +current_version = 0.11.2 commit = True tag = True From 986a3fb7ba0b9edcd61136f9f6686ab8a218b16c Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Mon, 15 Jan 2024 16:46:17 +0530 Subject: [PATCH 073/101] Replaced all_regs with pair_regs in amocas.w, amocas.d_32 and amocas.d_64 for rs2_op_data and rd_op_data in template.yaml --- riscv_ctg/data/template.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 50a5c085..8b7367e1 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10732,8 +10732,8 @@ amocas.w: - IZacas formattype: 'rformat' rs1_op_data: *all_regs_mx0 - rs2_op_data: *all_regs - rd_op_data: *all_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs rs1_val_data: 'gen_sign_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)' @@ -10755,8 +10755,8 @@ amocas.d_32: dcas_profile: 'pnp' formattype: 'dcasrformat' rs1_op_data: *all_regs_mx0 - rs2_op_data: *all_regs - rd_op_data: *all_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs rs1_val_data: 'gen_sign_dataset(64)' rs2_val_data: 'gen_sign_dataset(64)' @@ -10776,8 +10776,8 @@ amocas.d_64: - IZacas formattype: 'rformat' rs1_op_data: *all_regs_mx0 - rs2_op_data: *all_regs - rd_op_data: *all_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs rs1_val_data: 'gen_sign_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)' From d198a5331143a745712013229a2c50e9e43988c5 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Mon, 15 Jan 2024 16:47:12 +0530 Subject: [PATCH 074/101] Replaced all_regs with pair_regs in amocas.w for rs2 and rd in rv32zacas.cgf --- sample_cgfs/rv32zacas.cgf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sample_cgfs/rv32zacas.cgf b/sample_cgfs/rv32zacas.cgf index 6569f3ba..4ded5bed 100644 --- a/sample_cgfs/rv32zacas.cgf +++ b/sample_cgfs/rv32zacas.cgf @@ -7,9 +7,9 @@ amocas.w: rs1: <<: *all_regs_mx0 rs2: - <<: *all_regs + <<: *pair_regs rd: - <<: *all_regs + <<: *pair_regs op_comb: <<: *zacas_op_comb val_comb: From be88b6edab1028e4d3ca7acb76bc8aff286a907d Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Mon, 15 Jan 2024 16:47:48 +0530 Subject: [PATCH 075/101] Replaced all_regs with pair_regs in amocas.w, amocas.d_64 for rs2 and rd in rv64zacas.cgf --- sample_cgfs/rv64zacas.cgf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sample_cgfs/rv64zacas.cgf b/sample_cgfs/rv64zacas.cgf index 4acc4a1e..f0f4a781 100644 --- a/sample_cgfs/rv64zacas.cgf +++ b/sample_cgfs/rv64zacas.cgf @@ -7,9 +7,9 @@ amocas.w: rs1: <<: *all_regs_mx0 rs2: - <<: *all_regs + <<: *pair_regs rd: - <<: *all_regs + <<: *pair_regs op_comb: <<: *zacas_op_comb val_comb: @@ -25,9 +25,9 @@ amocas.d_64: rs1: <<: *all_regs_mx0 rs2: - <<: *all_regs + <<: *pair_regs rd: - <<: *all_regs + <<: *pair_regs op_comb: <<: *zacas_op_comb val_comb: From d6f0ecec7121ace5872a8bf1fd422f01fa734e20 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Tue, 16 Jan 2024 16:20:05 +0530 Subject: [PATCH 076/101] add sig and sz for kadd64, ukadd64, ksub64, uksub64, kmar64, kmsr64, ukmar64, ukmsr64 in template.yaml --- riscv_ctg/data/template.yaml | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 8b7367e1..efd7412a 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -6668,7 +6668,9 @@ uradd64: TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg) kadd64: - stride: 3 + sig: + stride: 3 + sz: 'XLEN/8' xlen: [32,64] std_op: isa: @@ -6689,7 +6691,9 @@ kadd64: TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg) ukadd64: - stride: 3 + sig: + stride: 3 + sz: 'XLEN/8' xlen: [32,64] std_op: isa: @@ -6779,7 +6783,9 @@ ursub64: TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg) ksub64: - stride: 3 + sig: + stride: 3 + sz: 'XLEN/8' xlen: [32,64] std_op: isa: @@ -6800,7 +6806,9 @@ ksub64: TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg) uksub64: - stride: 3 + sig: + stride: 3 + sz: 'XLEN/8' xlen: [32,64] std_op: isa: @@ -6923,7 +6931,9 @@ umsr64: TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) kmar64: - stride: 3 + sig: + stride: 3 + sz: 'XLEN/8' xlen: [32,64] std_op: isa: @@ -6946,7 +6956,9 @@ kmar64: TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) kmsr64: - stride: 3 + sig: + stride: 3 + sz: 'XLEN/8' xlen: [32,64] std_op: isa: @@ -6969,7 +6981,9 @@ kmsr64: TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) ukmar64: - stride: 3 + sig: + stride: 3 + sz: 'XLEN/8' xlen: [32,64] std_op: isa: @@ -6992,7 +7006,9 @@ ukmar64: TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) ukmsr64: - stride: 3 + sig: + stride: 3 + sz: 'XLEN/8' xlen: [32,64] std_op: isa: From 499d61e628fcd5303532503766f7894ff3cf4dc6 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Tue, 16 Jan 2024 16:23:09 +0530 Subject: [PATCH 077/101] Fix incorrect 'sig:' entry in aes32dsi --- riscv_ctg/data/template.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index efd7412a..7d235975 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -9,7 +9,6 @@ metadata: aes32dsi: sig: - sig: stride: 1 sz: 'XLEN/8' rs1_op_data: *all_regs From ca6c0f6684a668dedcf9652baba1e3093aa3136a Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Tue, 16 Jan 2024 16:24:15 +0530 Subject: [PATCH 078/101] Fix kslraw.u in rv32ip.cgf --- sample_cgfs/rv32ip.cgf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sample_cgfs/rv32ip.cgf b/sample_cgfs/rv32ip.cgf index 1f95d79c..5260c5de 100644 --- a/sample_cgfs/rv32ip.cgf +++ b/sample_cgfs/rv32ip.cgf @@ -4004,11 +4004,11 @@ kslraw.u: op_comb: <<: *rfmt_op_comb val_comb: + 'rs1_w0_val == rs2_w0_val': 0 + 'rs1_w0_val != rs2_w0_val': 0 abstract_comb: 'simd_base_val("rs1", xlen, 32, signed=False)': 0 'simd_base_val("rs2", xlen, 32, signed=True)': 0 - 'rs1_val == rs2_val': 0 - 'rs1_val != rs2_val': 0 ksllw: config: From 21cf4451da2ecf5b0a8903d8647e83cb89e04c5e Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 17 Jan 2024 10:22:55 +0530 Subject: [PATCH 079/101] Delete riscv-isac in riscv-ctg --- riscv-isac | 1 - 1 file changed, 1 deletion(-) delete mode 160000 riscv-isac diff --git a/riscv-isac b/riscv-isac deleted file mode 160000 index d5927473..00000000 --- a/riscv-isac +++ /dev/null @@ -1 +0,0 @@ -Subproject commit d59274739ebaaaeb65784d332b3824dcedd49665 From 6152d77f70d9a0ef2086158a3498c059dad0b7bf Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Tue, 23 Jan 2024 08:49:39 -0600 Subject: [PATCH 080/101] merge with dev --- riscv_ctg/data/template.yaml | 68 ++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index a39217e6..cfa909d5 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -10422,7 +10422,7 @@ amoadd.w: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10442,7 +10442,7 @@ amoand.w: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10462,7 +10462,7 @@ amoswap.w: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10482,7 +10482,7 @@ amoxor.w: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10502,7 +10502,7 @@ amoor.w: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10522,7 +10522,7 @@ amomin.w: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10542,7 +10542,7 @@ amominu.w: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10562,7 +10562,7 @@ amomax.w: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10575,14 +10575,14 @@ amomax.w: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) - + amomaxu.w: sig: stride: 2 sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10602,7 +10602,7 @@ amoadd.d: sz: 'XLEN/8' xlen: [64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10622,7 +10622,7 @@ amoand.d: sz: 'XLEN/8' xlen: [64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10642,7 +10642,7 @@ amoswap.d: sz: 'XLEN/8' xlen: [64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10662,7 +10662,7 @@ amoxor.d: sz: 'XLEN/8' xlen: [64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10682,7 +10682,7 @@ amoor.d: sz: 'XLEN/8' xlen: [64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10702,7 +10702,7 @@ amomin.d: sz: 'XLEN/8' xlen: [64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10722,7 +10722,7 @@ amominu.d: sz: 'XLEN/8' xlen: [64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10742,7 +10742,7 @@ amomax.d: sz: 'XLEN/8' xlen: [64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10755,14 +10755,14 @@ amomax.d: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) - + amomaxu.d: sig: stride: 2 sz: 'XLEN/8' xlen: [64] std_op: - isa: + isa: - IA formattype: 'rformat' rs1_op_data: *all_regs @@ -10872,7 +10872,7 @@ c.lbu: rd_op_data: *c_regs xlen: [32,64] std_op: - isa: + isa: - I_Zca_Zcb formattype: 'clformat' rs1_val_data: '[0]' @@ -10882,7 +10882,7 @@ c.lbu: // $comment // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) - + c.lhu: sig: stride: 1 @@ -10891,7 +10891,7 @@ c.lhu: rd_op_data: *c_regs xlen: [32,64] std_op: - isa: + isa: - I_Zca_Zcb formattype: 'clformat' rs1_val_data: '[0]' @@ -10901,7 +10901,7 @@ c.lhu: // $comment // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) - + c.lh: sig: stride: 1 @@ -10910,7 +10910,7 @@ c.lh: rd_op_data: *c_regs xlen: [32,64] std_op: - isa: + isa: - I_Zca_Zcb formattype: 'clformat' rs1_val_data: '[0]' @@ -10929,7 +10929,7 @@ c.sb: rs2_op_data: *c_regs xlen: [32,64] std_op: - isa: + isa: - I_Zca_Zcb formattype: 'csformat' rs1_val_data: '[0]' @@ -10949,7 +10949,7 @@ c.sh: rs2_op_data: *c_regs xlen: [32,64] std_op: - isa: + isa: - I_Zca_Zcb formattype: 'csformat' rs1_val_data: '[0]' @@ -10967,7 +10967,7 @@ c.sext.b: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - I_Zca_Zcb_Zbb formattype: 'ckformat' rs1_op_data: *c_regs @@ -10984,7 +10984,7 @@ c.sext.h: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - I_Zca_Zcb_Zbb formattype: 'ckformat' rs1_op_data: *c_regs @@ -11001,7 +11001,7 @@ c.zext.b: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - I_Zca_Zcb formattype: 'ckformat' rs1_op_data: *c_regs @@ -11018,7 +11018,7 @@ c.zext.h: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - I_Zca_Zcb_Zbb formattype: 'ckformat' rs1_op_data: *c_regs @@ -11035,7 +11035,7 @@ c.zext.w: sz: 'XLEN/8' xlen: [64] std_op: - isa: + isa: - I_Zca_Zcb_Zba formattype: 'ckformat' rs1_op_data: *c_regs @@ -11052,7 +11052,7 @@ c.not: sz: 'XLEN/8' xlen: [32,64] std_op: - isa: + isa: - I_Zca_Zcb formattype: 'kformat' rs1_op_data: *c_regs @@ -11071,7 +11071,7 @@ c.mul: rs2_op_data: *c_regs xlen: [32,64] std_op: - isa: + isa: - IM_Zca_Zcb formattype: 'crformat' operation: 'hex((rs1_val * rs2_val) & (2**(xlen)-1))' From 8e025855e5f3d24af7c6e3b4a49d480056e085f8 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Tue, 23 Jan 2024 12:59:53 -0600 Subject: [PATCH 081/101] merge with dev --- riscv_ctg/data/template.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index b7a67260..e642bff9 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -11320,6 +11320,7 @@ amoand.h: rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' template: |- + // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) From 11180e7ba8336825b1db6f34a898ef5ed38f6783 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Mon, 29 Jan 2024 13:48:41 +0530 Subject: [PATCH 082/101] add corner case of division to rv64im.cgf --- sample_cgfs/rv64im.cgf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sample_cgfs/rv64im.cgf b/sample_cgfs/rv64im.cgf index 87129aaf..a960b9bd 100644 --- a/sample_cgfs/rv64im.cgf +++ b/sample_cgfs/rv64im.cgf @@ -91,7 +91,7 @@ div: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] @@ -129,7 +129,7 @@ rem: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] @@ -186,7 +186,7 @@ divw: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] @@ -224,7 +224,7 @@ remw: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] From c4a44d0d29a436b9da27064ddac713e3971b6ca1 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Mon, 29 Jan 2024 13:49:50 +0530 Subject: [PATCH 083/101] add logger.debug to csr_comb.py --- riscv_ctg/csr_comb.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/csr_comb.py b/riscv_ctg/csr_comb.py index 435c30e6..ef75d388 100644 --- a/riscv_ctg/csr_comb.py +++ b/riscv_ctg/csr_comb.py @@ -413,8 +413,9 @@ def write_test(self, fprefix, cgf_node, usage_str, cov_label, instr_dict): case_str = ''.join([case_template.safe_substitute(xlen = self.xlen, num = i, cov_label = cov_label) for i, cond in enumerate(cgf_node.get('config', []))]) test_str = part_template.safe_substitute(case_str = case_str, code = '\n'.join(code)) - - with open(fprefix + '_csr-comb.S', 'w') as fp: + fname = fprefix + '_csr-comb.S' + logger.debug("Writing Test to %s", str(fname)) + with open(fname, 'w') as fp: fp.write(usage_str + csr_comb_test_template.safe_substitute( isa = self.base_isa.upper(), # how to get the extensions? test = test_str, From c26eefc9af9a9080cc68428cf2bd62174f31b096 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Mon, 29 Jan 2024 14:26:28 +0530 Subject: [PATCH 084/101] undo changes --- riscv_ctg/csr_comb.py | 5 ++--- sample_cgfs/rv64im.cgf | 8 ++++---- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/riscv_ctg/csr_comb.py b/riscv_ctg/csr_comb.py index ef75d388..55300d67 100644 --- a/riscv_ctg/csr_comb.py +++ b/riscv_ctg/csr_comb.py @@ -413,9 +413,8 @@ def write_test(self, fprefix, cgf_node, usage_str, cov_label, instr_dict): case_str = ''.join([case_template.safe_substitute(xlen = self.xlen, num = i, cov_label = cov_label) for i, cond in enumerate(cgf_node.get('config', []))]) test_str = part_template.safe_substitute(case_str = case_str, code = '\n'.join(code)) - fname = fprefix + '_csr-comb.S' - logger.debug("Writing Test to %s", str(fname)) - with open(fname, 'w') as fp: + + with open(fprefix + '_csr-comb.S', 'w') as fp: fp.write(usage_str + csr_comb_test_template.safe_substitute( isa = self.base_isa.upper(), # how to get the extensions? test = test_str, diff --git a/sample_cgfs/rv64im.cgf b/sample_cgfs/rv64im.cgf index a960b9bd..87129aaf 100644 --- a/sample_cgfs/rv64im.cgf +++ b/sample_cgfs/rv64im.cgf @@ -91,7 +91,7 @@ div: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] @@ -129,7 +129,7 @@ rem: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] @@ -186,7 +186,7 @@ divw: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] @@ -224,7 +224,7 @@ remw: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] From 22e004960da61feab83845b2ed0f372ca05c8567 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Mon, 29 Jan 2024 14:29:21 +0530 Subject: [PATCH 085/101] add corner case of division to rv64im.cgf --- sample_cgfs/rv64im.cgf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sample_cgfs/rv64im.cgf b/sample_cgfs/rv64im.cgf index 87129aaf..a960b9bd 100644 --- a/sample_cgfs/rv64im.cgf +++ b/sample_cgfs/rv64im.cgf @@ -91,7 +91,7 @@ div: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] @@ -129,7 +129,7 @@ rem: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] @@ -186,7 +186,7 @@ divw: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] @@ -224,7 +224,7 @@ remw: op_comb: <<: *rfmt_op_comb val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: 'sp_dataset(xlen)': 0 <<: [*rs1val_walking, *rs2val_walking] From 4ec38dfaf94ce7839d3e5d820f8fcf246415097f Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Mon, 29 Jan 2024 14:29:34 +0530 Subject: [PATCH 086/101] add logger.debug to csr_comb.py --- riscv_ctg/csr_comb.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/csr_comb.py b/riscv_ctg/csr_comb.py index 55300d67..ef75d388 100644 --- a/riscv_ctg/csr_comb.py +++ b/riscv_ctg/csr_comb.py @@ -413,8 +413,9 @@ def write_test(self, fprefix, cgf_node, usage_str, cov_label, instr_dict): case_str = ''.join([case_template.safe_substitute(xlen = self.xlen, num = i, cov_label = cov_label) for i, cond in enumerate(cgf_node.get('config', []))]) test_str = part_template.safe_substitute(case_str = case_str, code = '\n'.join(code)) - - with open(fprefix + '_csr-comb.S', 'w') as fp: + fname = fprefix + '_csr-comb.S' + logger.debug("Writing Test to %s", str(fname)) + with open(fname, 'w') as fp: fp.write(usage_str + csr_comb_test_template.safe_substitute( isa = self.base_isa.upper(), # how to get the extensions? test = test_str, From 6c47f98490d5fcc5780f42b151081b25a9497492 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 7 Feb 2024 17:47:51 +0530 Subject: [PATCH 087/101] Add rs1_val_data for c.ldsp in imc.yaml --- riscv_ctg/data/imc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index 9e52b81d..be5b1995 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1740,6 +1740,7 @@ c.ldsp: - IC formattype: 'ciformat' imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- // $comment From 24596a7377e35aa735f633ee637ccb4de2ccbfad Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 7 Feb 2024 17:49:24 +0530 Subject: [PATCH 088/101] comment coverage code for hard coded register testcases --- riscv_ctg/generator.py | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index ada44f00..6446b936 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -334,18 +334,18 @@ def comb_constraint(*args): count = 0 solution = problem.getSolution() while (solution is None and count < 5): - pattern = r'(?:rs1|rs2|rd) == "(x\d+)"' - matches = re.findall(pattern, cond) - if not matches or any(int(match[1:]) > 31 for match in matches): - result = None - else: - result = matches - for match in result: - op_conds['rs1'].add(match) - op_conds['rs2'].add(match) - op_conds['rd'].add(match) - op_comb.add(cond) - break +# pattern = r'(?:rs1|rs2|rd) == "(x\d+)"' +# matches = re.findall(pattern, cond) +# if not matches or any(int(match[1:]) > 31 for match in matches): +# result = None +# else: +# result = matches +# for match in result: +# op_conds['rs1'].add(match) +# op_conds['rs2'].add(match) +# op_conds['rd'].add(match) +# op_comb.add(cond) +# break solution = problem.getSolution() count = count + 1 if solution is None: @@ -358,7 +358,6 @@ def comb_constraint(*args): else: individual = True continue - op_tuple = [] for key in self.op_vars: op_tuple.append(solution[key]) @@ -1386,4 +1385,4 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str): sign.append("#ifdef rvtest_gpr_save\n"+signode_template.substitute( {'n':32,'label':"gpr_save",'sz':'XLEN/32'})+"\n#endif\n") with open(file_name,"w") as fd: - fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label)) + fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label)) \ No newline at end of file From 00462b844e8e300d8df21a5212ae1fac700e82fa Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 7 Feb 2024 17:49:44 +0530 Subject: [PATCH 089/101] Add 'warning' as a verbose level --- riscv_ctg/main.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv_ctg/main.py b/riscv_ctg/main.py index b127689b..0e0bc30d 100644 --- a/riscv_ctg/main.py +++ b/riscv_ctg/main.py @@ -10,7 +10,7 @@ from riscv_isac.cgf_normalize import expand_cgf @click.command() @click.version_option(prog_name="RISC-V Compliance Test Generator",version=__version__) -@click.option('--verbose', '-v', default='error', help='Set verbose level', type=click.Choice(['info','error','debug'],case_sensitive=False)) +@click.option('--verbose', '-v', default='error', help='Set verbose level', type=click.Choice(['info','error','debug','warning'],case_sensitive=False)) @click.option('--out-dir', '-d', default='./', type=click.Path(resolve_path=True,writable=True), help='Output directory path') @click.option('--randomize','-r', default=False , is_flag='True', help='Randomize Outputs.') @click.option('--cgf','-cf',multiple=True,type=click.Path(exists=True,resolve_path=True,readable=True),help="Path to the cgf file(s). Multiple allowed.") From 891b414a8a2bafdca5d1b6b88f6240bd061cd6e6 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 7 Feb 2024 17:50:06 +0530 Subject: [PATCH 090/101] Add test-1.yml for CI --- .github/workflows/test-1.yml | 80 ++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 .github/workflows/test-1.yml diff --git a/.github/workflows/test-1.yml b/.github/workflows/test-1.yml new file mode 100644 index 00000000..fb6e858c --- /dev/null +++ b/.github/workflows/test-1.yml @@ -0,0 +1,80 @@ +name: test-1 +on: + pull_request: + branches: + -master + -dev + workflow_dispatch: + +jobs: + build: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - name: Set up Python + uses: actions/setup-python@v2 + with: + python-version: '3.7' + + - name: Install dependencies + run: | + python -m pip install --upgrade pip + pip install -r riscv_ctg/requirements.txt + pip install --editable . + + + - name: Run RISC-V CTG for all CGF files except FP + run: | + set -e + for cgf_file in ./sample_cgfs/*.cgf; do + if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then + if [[ "$cgf_file" == *rv32e* ]]; then + cmd="riscv_ctg -r -d ./tests -bi rv32e -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" + echo $cmd + eval $cmd || { echo "Error executing command: $cmd"; exit 1; } + elif [[ "$cgf_file" == *rv32* && "$cgf_file" != *rv32e* ]]; then + cmd="riscv_ctg -r -d ./tests -bi rv32i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" + echo $cmd + eval $cmd || { echo "Error executing command: $cmd"; exit 1; } + elif [[ "$cgf_file" == *rv64* ]]; then + cmd="riscv_ctg -r -d ./tests -bi rv64i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" + echo $cmd + eval $cmd || { echo "Error executing command: $cmd"; exit 1; } + else + for arch in rv32i rv64i; do + cmd="riscv_ctg -r -d ./tests -bi $arch -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" + echo $cmd + eval $cmd || { echo "Error executing command: $cmd"; exit 1; } + done + fi + fi + done + + check-version: + if: github.ref == 'refs/heads/master' + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + + - name: version check + run: | + export CHNGVER=$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md); + echo "CHANGELOG VERSION: $CHNGVER" + export INITVER=$(grep -P "__version__ = '.*?'" riscv_ctg/__init__.py | awk '{print $3}'|sed "s/'//g"); + echo "INIT VERSION: $INITVER" + if [ "$CHNGVER" = "$INITVER" ]; then + echo "Versions are equal in Changelog and init.py." + else + echo "Versions are not equal in Changelog and init.py." + exit 1 + fi + export TAGVER=${{ steps.get-latest-tag.outputs.tag }}; + echo "TAG VERSION: $TAGVER" + if [ "$CHNGVER" = "$TAGVER" ]; then + echo "No changelog update." + exit 1 + else + echo "Changelog updated." + fi + + \ No newline at end of file From 2e9dd17034c0fb28f7ce9bf790a18a84ab626c08 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Wed, 7 Feb 2024 17:56:37 +0530 Subject: [PATCH 091/101] Update 'opcode' to 'mnemonics' in the cgf files --- sample_cgfs/rv32e.cgf | 76 +++--- sample_cgfs/rv32e_fencei.cgf | 2 +- sample_cgfs/rv32e_priv.cgf | 28 +- sample_cgfs/rv32ec.cgf | 54 ++-- sample_cgfs/rv32em.cgf | 16 +- sample_cgfs/rv32i.cgf | 76 +++--- sample_cgfs/rv32i_fencei.cgf | 2 +- sample_cgfs/rv32i_priv.cgf | 32 +-- sample_cgfs/rv32ic.cgf | 54 ++-- sample_cgfs/rv32im.cgf | 16 +- sample_cgfs/rv32ip.cgf | 488 +++++++++++++++++------------------ sample_cgfs/rv32zabha.cgf | 4 +- sample_cgfs/rv32zacas.cgf | 4 +- sample_cgfs/rv64i.cgf | 100 +++---- sample_cgfs/rv64i_fencei.cgf | 2 +- sample_cgfs/rv64i_priv.cgf | 38 +-- sample_cgfs/rv64ic.cgf | 66 ++--- sample_cgfs/rv64im.cgf | 26 +- sample_cgfs/rv64ip.cgf | 168 ++++++------ sample_cgfs/rv64zacas.cgf | 6 +- sample_cgfs/zcmop.cgf | 14 +- sample_cgfs/zicfilp.cgf | 6 +- sample_cgfs/zicfiss.cgf | 8 +- sample_cgfs/zicond.cgf | 4 +- sample_cgfs/zimop.cgf | 80 +++--- 25 files changed, 685 insertions(+), 685 deletions(-) diff --git a/sample_cgfs/rv32e.cgf b/sample_cgfs/rv32e.cgf index 033d4b3b..31b4c8af 100644 --- a/sample_cgfs/rv32e.cgf +++ b/sample_cgfs/rv32e.cgf @@ -3,13 +3,13 @@ fence: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: fence: 0 addi: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: addi: 0 rs1: <<: *rv32e_regs @@ -26,7 +26,7 @@ addi: slti: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: slti: 0 rs1: <<: *rv32e_regs @@ -43,7 +43,7 @@ slti: sltiu: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: sltiu: 0 rs1: <<: *rv32e_regs @@ -60,7 +60,7 @@ sltiu: andi: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: andi: 0 rs1: <<: *rv32e_regs @@ -77,7 +77,7 @@ andi: ori: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: ori: 0 rs1: <<: *rv32e_regs @@ -94,7 +94,7 @@ ori: xori: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: xori: 0 rs1: <<: *rv32e_regs @@ -111,7 +111,7 @@ xori: slli: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: slli: 0 rs1: <<: *rv32e_regs @@ -131,7 +131,7 @@ slli: srai: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: srai: 0 rs1: <<: *rv32e_regs @@ -151,7 +151,7 @@ srai: srli: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: srli: 0 rs1: <<: *rv32e_regs @@ -171,7 +171,7 @@ srli: add: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: add: 0 rs1: <<: *rv32e_regs @@ -190,7 +190,7 @@ add: sub: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: sub: 0 rs1: <<: *rv32e_regs @@ -209,7 +209,7 @@ sub: slt: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: slt: 0 rs1: <<: *rv32e_regs @@ -228,7 +228,7 @@ slt: sltu: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: sltu: 0 rs1: <<: *rv32e_regs @@ -247,7 +247,7 @@ sltu: and: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: and: 0 rs1: <<: *rv32e_regs @@ -266,7 +266,7 @@ and: or: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: or: 0 rs1: <<: *rv32e_regs @@ -285,7 +285,7 @@ or: xor: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: xor: 0 rs1: <<: *rv32e_regs @@ -304,7 +304,7 @@ xor: sll: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: sll: 0 rs1: <<: *rv32e_regs @@ -326,7 +326,7 @@ sll: srl: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: srl: 0 rs1: <<: *rv32e_regs @@ -348,7 +348,7 @@ srl: sra: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: sra: 0 rs1: <<: *rv32e_regs @@ -370,7 +370,7 @@ sra: beq: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: beq: 0 rs1: <<: *rv32e_regs @@ -387,7 +387,7 @@ beq: bge: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: bge: 0 rs1: <<: *rv32e_regs @@ -404,7 +404,7 @@ bge: bgeu: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: bgeu: 0 rs1: <<: *rv32e_regs @@ -421,7 +421,7 @@ bgeu: blt: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: blt: 0 rs1: <<: *rv32e_regs @@ -438,7 +438,7 @@ blt: bltu: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: bltu: 0 rs1: <<: *rv32e_regs @@ -455,7 +455,7 @@ bltu: bne: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: bne: 0 rs1: <<: *rv32e_regs @@ -472,7 +472,7 @@ bne: lhu-align: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: lhu: 0 rs1: <<: *rv32e_regs_mx0 @@ -496,7 +496,7 @@ lhu-align: lh-align: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: lh: 0 rs1: <<: *rv32e_regs_mx0 @@ -520,7 +520,7 @@ lh-align: lbu-align: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: lbu: 0 rs1: <<: *rv32e_regs_mx0 @@ -552,7 +552,7 @@ lbu-align: lb-align: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: lb: 0 rs1: <<: *rv32e_regs_mx0 @@ -584,7 +584,7 @@ lb-align: lw-align: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: lw: 0 rs1: <<: *rv32e_regs_mx0 @@ -605,7 +605,7 @@ lw-align: sh-align: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: sh: 0 rs1: <<: *rv32e_regs_mx0 @@ -632,7 +632,7 @@ sh-align: sb-align: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: sb: 0 rs1: <<: *rv32e_regs_mx0 @@ -667,7 +667,7 @@ sb-align: sw-align: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: sw: 0 rs1: <<: *rv32e_regs_mx0 @@ -690,7 +690,7 @@ sw-align: auipc: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: auipc: 0 rd: <<: *rv32e_regs @@ -707,7 +707,7 @@ auipc: lui: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: lui: 0 rd: <<: *rv32e_regs @@ -724,7 +724,7 @@ lui: jal: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: jal: 0 rd: <<: *rv32e_regs @@ -737,7 +737,7 @@ jal: jalr: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: jalr: 0 rs1: <<: *rv32e_regs_mx0 diff --git a/sample_cgfs/rv32e_fencei.cgf b/sample_cgfs/rv32e_fencei.cgf index 59086e9c..0339821e 100644 --- a/sample_cgfs/rv32e_fencei.cgf +++ b/sample_cgfs/rv32e_fencei.cgf @@ -1,6 +1,6 @@ fencei: config: - check ISA:=regex(.*E.*Zifencei.*) ;def RVTEST_E = True - opcode: + mnemonics: fence.i: 0 diff --git a/sample_cgfs/rv32e_priv.cgf b/sample_cgfs/rv32e_priv.cgf index eb970b70..129677f1 100644 --- a/sample_cgfs/rv32e_priv.cgf +++ b/sample_cgfs/rv32e_priv.cgf @@ -3,7 +3,7 @@ misalign-lh: config: - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True - opcode: + mnemonics: lh: 0 val_comb: 'ea_align == 1': 0 @@ -13,7 +13,7 @@ misalign-lhu: - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True - opcode: + mnemonics: lhu: 0 val_comb: 'ea_align == 1': 0 @@ -24,7 +24,7 @@ misalign-lw: - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True - opcode: + mnemonics: lw: 0 val_comb: 'ea_align == 1': 0 @@ -36,7 +36,7 @@ misalign-sh: - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True - opcode: + mnemonics: sh: 0 val_comb: 'ea_align == 1': 0 @@ -46,7 +46,7 @@ misalign-sw: - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True - opcode: + mnemonics: sw: 0 val_comb: 'ea_align == 1': 0 @@ -58,7 +58,7 @@ misalign2-jalr: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: jalr: 0 val_comb: 'imm_val%2 == 1 and ea_align == 2': 0 @@ -67,7 +67,7 @@ misalign2-jalr: misalign1-jalr: config: - check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: jalr: 0 val_comb: 'imm_val%2 == 1 and ea_align == 1': 0 @@ -78,7 +78,7 @@ misalign-jal: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: jal: 0 val_comb: 'ea_align == 2': 0 @@ -88,7 +88,7 @@ misalign-bge: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: bge: 0 val_comb: ' rs1_val>rs2_val and ea_align == 2': 0 @@ -98,7 +98,7 @@ misalign-bgeu: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: bgeu: 0 val_comb: ' rs1_val>rs2_val and ea_align == 2': 0 @@ -108,7 +108,7 @@ misalign-blt: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True - opcode: + mnemonics: blt: 0 val_comb: ' rs1_val 0': 0 @@ -102,7 +102,7 @@ cjal: cli: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.li: 0 rd: <<: *rv32e_regs @@ -116,7 +116,7 @@ cli: caddi16sp: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.addi16sp: 0 rd: x2: 0 @@ -133,7 +133,7 @@ caddi16sp: clui: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.lui: 0 rd: <<: *rv32e_regs_mx2 @@ -150,7 +150,7 @@ clui: csrli: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.srli: 0 rs1: <<: *c_regs @@ -172,7 +172,7 @@ csrli: csrai: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.srai: 0 rs1: <<: *c_regs @@ -194,7 +194,7 @@ csrai: candi: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.andi: 0 rs1: <<: *c_regs @@ -207,7 +207,7 @@ candi: csub: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.sub: 0 rs1: <<: *c_regs @@ -224,7 +224,7 @@ csub: cxor: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.xor: 0 rs1: <<: *c_regs @@ -241,7 +241,7 @@ cxor: cor: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.or: 0 rs1: <<: *c_regs @@ -258,7 +258,7 @@ cor: cand: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.and: 0 rs1: <<: *c_regs @@ -277,7 +277,7 @@ cand: cj: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.j: 0 val_comb: 'imm_val > 0': 0 @@ -290,7 +290,7 @@ cj: cbeqz: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.beqz: 0 rs1: <<: *c_regs @@ -309,7 +309,7 @@ cbeqz: cbnez: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.bnez: 0 rs1: <<: *c_regs @@ -328,7 +328,7 @@ cbnez: cslli: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.slli: 0 rd: <<: *c_regs @@ -350,7 +350,7 @@ cslli: clwsp: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.lwsp: 0 rd: <<: *rv32e_regs_mx0 @@ -366,7 +366,7 @@ clwsp: cjr: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.jr: 0 rs1: <<: *rv32e_regs_mx0 @@ -381,7 +381,7 @@ cjr: cmv: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.mv: 0 rs2: <<: *rv32e_regs_mx0 @@ -399,7 +399,7 @@ cmv: cadd: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.add: 0 rs1: <<: *rv32e_regs @@ -416,7 +416,7 @@ cadd: cjalr: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.jalr: 0 rs1: <<: *rv32e_regs_mx0 @@ -431,7 +431,7 @@ cjalr: cswsp: config: - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True - opcode: + mnemonics: c.swsp: 0 rs2: <<: *rv32e_regs_mx2 diff --git a/sample_cgfs/rv32em.cgf b/sample_cgfs/rv32em.cgf index ca7cc093..0bee9655 100644 --- a/sample_cgfs/rv32em.cgf +++ b/sample_cgfs/rv32em.cgf @@ -3,7 +3,7 @@ mul: config: - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True - opcode: + mnemonics: mul: 0 rs1: <<: *rv32e_regs @@ -22,7 +22,7 @@ mul: mulh: config: - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True - opcode: + mnemonics: mulh: 0 rs1: <<: *rv32e_regs @@ -41,7 +41,7 @@ mulh: mulhu: config: - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True - opcode: + mnemonics: mulhu: 0 rs1: <<: *rv32e_regs @@ -60,7 +60,7 @@ mulhu: mulhsu: config: - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True - opcode: + mnemonics: mulhsu: 0 rs1: <<: *rv32e_regs @@ -80,7 +80,7 @@ mulhsu: div: config: - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True - opcode: + mnemonics: div: 0 rs1: <<: *rv32e_regs @@ -99,7 +99,7 @@ div: divu: config: - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True - opcode: + mnemonics: divu: 0 rs1: <<: *rv32e_regs @@ -118,7 +118,7 @@ divu: rem: config: - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True - opcode: + mnemonics: rem: 0 rs1: <<: *rv32e_regs @@ -137,7 +137,7 @@ rem: remu: config: - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True - opcode: + mnemonics: remu: 0 rs1: <<: *rv32e_regs diff --git a/sample_cgfs/rv32i.cgf b/sample_cgfs/rv32i.cgf index c548d63f..54ce07fb 100644 --- a/sample_cgfs/rv32i.cgf +++ b/sample_cgfs/rv32i.cgf @@ -3,13 +3,13 @@ fence: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: fence: 0 addi: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: addi: 0 rs1: <<: *all_regs @@ -26,7 +26,7 @@ addi: slti: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: slti: 0 rs1: <<: *all_regs @@ -43,7 +43,7 @@ slti: sltiu: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sltiu: 0 rs1: <<: *all_regs @@ -60,7 +60,7 @@ sltiu: andi: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: andi: 0 rs1: <<: *all_regs @@ -77,7 +77,7 @@ andi: ori: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: ori: 0 rs1: <<: *all_regs @@ -94,7 +94,7 @@ ori: xori: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: xori: 0 rs1: <<: *all_regs @@ -111,7 +111,7 @@ xori: slli: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: slli: 0 rs1: <<: *all_regs @@ -131,7 +131,7 @@ slli: srai: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: srai: 0 rs1: <<: *all_regs @@ -151,7 +151,7 @@ srai: srli: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: srli: 0 rs1: <<: *all_regs @@ -171,7 +171,7 @@ srli: add: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: add: 0 rs1: <<: *all_regs @@ -190,7 +190,7 @@ add: sub: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sub: 0 rs1: <<: *all_regs @@ -209,7 +209,7 @@ sub: slt: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: slt: 0 rs1: <<: *all_regs @@ -228,7 +228,7 @@ slt: sltu: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sltu: 0 rs1: <<: *all_regs @@ -247,7 +247,7 @@ sltu: and: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: and: 0 rs1: <<: *all_regs @@ -266,7 +266,7 @@ and: or: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: or: 0 rs1: <<: *all_regs @@ -285,7 +285,7 @@ or: xor: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: xor: 0 rs1: <<: *all_regs @@ -304,7 +304,7 @@ xor: sll: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sll: 0 rs1: <<: *all_regs @@ -326,7 +326,7 @@ sll: srl: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: srl: 0 rs1: <<: *all_regs @@ -348,7 +348,7 @@ srl: sra: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sra: 0 rs1: <<: *all_regs @@ -370,7 +370,7 @@ sra: beq: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: beq: 0 rs1: <<: *all_regs @@ -387,7 +387,7 @@ beq: bge: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: bge: 0 rs1: <<: *all_regs @@ -404,7 +404,7 @@ bge: bgeu: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: bgeu: 0 rs1: <<: *all_regs @@ -421,7 +421,7 @@ bgeu: blt: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: blt: 0 rs1: <<: *all_regs @@ -438,7 +438,7 @@ blt: bltu: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: bltu: 0 rs1: <<: *all_regs @@ -455,7 +455,7 @@ bltu: bne: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: bne: 0 rs1: <<: *all_regs @@ -472,7 +472,7 @@ bne: lhu-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lhu: 0 rs1: <<: *all_regs_mx0 @@ -496,7 +496,7 @@ lhu-align: lh-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lh: 0 rs1: <<: *all_regs_mx0 @@ -520,7 +520,7 @@ lh-align: lbu-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lbu: 0 rs1: <<: *all_regs_mx0 @@ -552,7 +552,7 @@ lbu-align: lb-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lb: 0 rs1: <<: *all_regs_mx0 @@ -584,7 +584,7 @@ lb-align: lw-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lw: 0 rs1: <<: *all_regs_mx0 @@ -605,7 +605,7 @@ lw-align: sh-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sh: 0 rs1: <<: *all_regs_mx0 @@ -632,7 +632,7 @@ sh-align: sb-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sb: 0 rs1: <<: *all_regs_mx0 @@ -667,7 +667,7 @@ sb-align: sw-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sw: 0 rs1: <<: *all_regs_mx0 @@ -690,7 +690,7 @@ sw-align: auipc: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: auipc: 0 rd: <<: *all_regs @@ -707,7 +707,7 @@ auipc: lui: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lui: 0 rd: <<: *all_regs @@ -724,7 +724,7 @@ lui: jal: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: jal: 0 rd: <<: *all_regs @@ -737,7 +737,7 @@ jal: jalr: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: jalr: 0 rs1: <<: *all_regs_mx0 diff --git a/sample_cgfs/rv32i_fencei.cgf b/sample_cgfs/rv32i_fencei.cgf index 6f1a71bc..7699d7c4 100644 --- a/sample_cgfs/rv32i_fencei.cgf +++ b/sample_cgfs/rv32i_fencei.cgf @@ -1,6 +1,6 @@ fencei: config: - check ISA:=regex(.*I.*Zifencei.*) - opcode: + mnemonics: fence.i: 0 diff --git a/sample_cgfs/rv32i_priv.cgf b/sample_cgfs/rv32i_priv.cgf index 320dbda2..94131f0a 100644 --- a/sample_cgfs/rv32i_priv.cgf +++ b/sample_cgfs/rv32i_priv.cgf @@ -1,13 +1,13 @@ ecall: config: - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: + mnemonics: ecall: 0 ebreak: config: - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: + mnemonics: ebreak: 0 misalign-lh: @@ -15,7 +15,7 @@ misalign-lh: config: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - opcode: + mnemonics: lh: 0 val_comb: 'ea_align == 1': 0 @@ -25,7 +25,7 @@ misalign-lhu: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: + mnemonics: lhu: 0 val_comb: 'ea_align == 1': 0 @@ -36,7 +36,7 @@ misalign-lw: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: + mnemonics: lw: 0 val_comb: 'ea_align == 1': 0 @@ -48,7 +48,7 @@ misalign-sh: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: + mnemonics: sh: 0 val_comb: 'ea_align == 1': 0 @@ -58,7 +58,7 @@ misalign-sw: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: + mnemonics: sw: 0 val_comb: 'ea_align == 1': 0 @@ -70,7 +70,7 @@ misalign2-jalr: - check ISA:=regex(.*I.*C.*) - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*) - opcode: + mnemonics: jalr: 0 val_comb: 'imm_val%2 == 1 and ea_align == 2': 0 @@ -79,7 +79,7 @@ misalign2-jalr: misalign1-jalr: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: jalr: 0 val_comb: 'imm_val%2 == 1 and ea_align == 1': 0 @@ -90,7 +90,7 @@ misalign-jal: - check ISA:=regex(.*I.*C.*) - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*) - opcode: + mnemonics: jal: 0 val_comb: 'ea_align == 2': 0 @@ -100,7 +100,7 @@ misalign-bge: - check ISA:=regex(.*I.*C.*) - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*) - opcode: + mnemonics: bge: 0 val_comb: ' rs1_val>rs2_val and ea_align == 2': 0 @@ -110,7 +110,7 @@ misalign-bgeu: - check ISA:=regex(.*I.*C.*) - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*) - opcode: + mnemonics: bgeu: 0 val_comb: ' rs1_val>rs2_val and ea_align == 2': 0 @@ -120,7 +120,7 @@ misalign-blt: - check ISA:=regex(.*I.*C.*) - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*) - opcode: + mnemonics: blt: 0 val_comb: ' rs1_val 0': 0 @@ -102,7 +102,7 @@ cjal: cli: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.li: 0 rd: <<: *all_regs @@ -116,7 +116,7 @@ cli: caddi16sp: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.addi16sp: 0 rd: x2: 0 @@ -133,7 +133,7 @@ caddi16sp: clui: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.lui: 0 rd: x0: 0 @@ -181,7 +181,7 @@ clui: csrli: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.srli: 0 rs1: <<: *c_regs @@ -203,7 +203,7 @@ csrli: csrai: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.srai: 0 rs1: <<: *c_regs @@ -225,7 +225,7 @@ csrai: candi: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.andi: 0 rs1: <<: *c_regs @@ -238,7 +238,7 @@ candi: csub: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.sub: 0 rs1: <<: *c_regs @@ -255,7 +255,7 @@ csub: cxor: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.xor: 0 rs1: <<: *c_regs @@ -272,7 +272,7 @@ cxor: cor: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.or: 0 rs1: <<: *c_regs @@ -289,7 +289,7 @@ cor: cand: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.and: 0 rs1: <<: *c_regs @@ -308,7 +308,7 @@ cand: cj: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.j: 0 val_comb: 'imm_val > 0': 0 @@ -321,7 +321,7 @@ cj: cbeqz: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.beqz: 0 rs1: <<: *c_regs @@ -340,7 +340,7 @@ cbeqz: cbnez: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.bnez: 0 rs1: <<: *c_regs @@ -359,7 +359,7 @@ cbnez: cslli: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.slli: 0 rd: <<: *c_regs @@ -381,7 +381,7 @@ cslli: clwsp: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.lwsp: 0 rd: <<: *all_regs_mx0 @@ -397,7 +397,7 @@ clwsp: cjr: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.jr: 0 rs1: <<: *all_regs_mx0 @@ -412,7 +412,7 @@ cjr: cmv: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.mv: 0 rs2: <<: *all_regs_mx0 @@ -430,7 +430,7 @@ cmv: cadd: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.add: 0 rs1: <<: *all_regs @@ -447,7 +447,7 @@ cadd: cjalr: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.jalr: 0 rs1: <<: *all_regs_mx0 @@ -462,7 +462,7 @@ cjalr: cswsp: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.swsp: 0 rs2: <<: *all_regs_mx2 diff --git a/sample_cgfs/rv32im.cgf b/sample_cgfs/rv32im.cgf index f364cebd..5c5d7b8d 100644 --- a/sample_cgfs/rv32im.cgf +++ b/sample_cgfs/rv32im.cgf @@ -3,7 +3,7 @@ mul: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: mul: 0 rs1: <<: *all_regs @@ -22,7 +22,7 @@ mul: mulh: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: mulh: 0 rs1: <<: *all_regs @@ -41,7 +41,7 @@ mulh: mulhu: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: mulhu: 0 rs1: <<: *all_regs @@ -60,7 +60,7 @@ mulhu: mulhsu: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: mulhsu: 0 rs1: <<: *all_regs @@ -80,7 +80,7 @@ mulhsu: div: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: div: 0 rs1: <<: *all_regs @@ -99,7 +99,7 @@ div: divu: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: divu: 0 rs1: <<: *all_regs @@ -118,7 +118,7 @@ divu: rem: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: rem: 0 rs1: <<: *all_regs @@ -137,7 +137,7 @@ rem: remu: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: remu: 0 rs1: <<: *all_regs diff --git a/sample_cgfs/rv32ip.cgf b/sample_cgfs/rv32ip.cgf index 5260c5de..3fa586ed 100644 --- a/sample_cgfs/rv32ip.cgf +++ b/sample_cgfs/rv32ip.cgf @@ -3,7 +3,7 @@ add16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: add16: 0 rs1: <<: *all_regs @@ -22,7 +22,7 @@ add16: radd16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: radd16: 0 rs1: <<: *all_regs @@ -41,7 +41,7 @@ radd16: uradd16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uradd16: 0 rs1: <<: *all_regs @@ -60,7 +60,7 @@ uradd16: kadd16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kadd16: 0 rs1: <<: *all_regs @@ -79,7 +79,7 @@ kadd16: ukadd16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukadd16: 0 rs1: <<: *all_regs @@ -98,7 +98,7 @@ ukadd16: sub16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sub16: 0 rs1: <<: *all_regs @@ -117,7 +117,7 @@ sub16: rsub16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rsub16: 0 rs1: <<: *all_regs @@ -137,7 +137,7 @@ rsub16: ursub16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ursub16: 0 rs1: <<: *all_regs @@ -156,7 +156,7 @@ ursub16: ksub16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ksub16: 0 rs1: <<: *all_regs @@ -175,7 +175,7 @@ ksub16: uksub16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uksub16: 0 rs1: <<: *all_regs @@ -194,7 +194,7 @@ uksub16: cras16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: cras16: 0 rs1: <<: *all_regs @@ -213,7 +213,7 @@ cras16: rcras16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rcras16: 0 rs1: <<: *all_regs @@ -232,7 +232,7 @@ rcras16: urcras16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: urcras16: 0 rs1: <<: *all_regs @@ -251,7 +251,7 @@ urcras16: kcras16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kcras16: 0 rs1: <<: *all_regs @@ -270,7 +270,7 @@ kcras16: ukcras16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukcras16: 0 rs1: <<: *all_regs @@ -289,7 +289,7 @@ ukcras16: crsa16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: crsa16: 0 rs1: <<: *all_regs @@ -308,7 +308,7 @@ crsa16: rcrsa16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rcrsa16: 0 rs1: <<: *all_regs @@ -327,7 +327,7 @@ rcrsa16: urcrsa16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: urcrsa16: 0 rs1: <<: *all_regs @@ -346,7 +346,7 @@ urcrsa16: kcrsa16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kcrsa16: 0 rs1: <<: *all_regs @@ -365,7 +365,7 @@ kcrsa16: ukcrsa16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukcrsa16: 0 rs1: <<: *all_regs @@ -384,7 +384,7 @@ ukcrsa16: stas16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: stas16: 0 rs1: <<: *all_regs @@ -403,7 +403,7 @@ stas16: rstas16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rstas16: 0 rs1: <<: *all_regs @@ -422,7 +422,7 @@ rstas16: urstas16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: urstas16: 0 rs1: <<: *all_regs @@ -441,7 +441,7 @@ urstas16: kstas16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kstas16: 0 rs1: <<: *all_regs @@ -460,7 +460,7 @@ kstas16: ukstas16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukstas16: 0 rs1: <<: *all_regs @@ -479,7 +479,7 @@ ukstas16: stsa16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: stsa16: 0 rs1: <<: *all_regs @@ -498,7 +498,7 @@ stsa16: rstsa16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rstsa16: 0 rs1: <<: *all_regs @@ -517,7 +517,7 @@ rstsa16: urstsa16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: urstsa16: 0 rs1: <<: *all_regs @@ -536,7 +536,7 @@ urstsa16: kstsa16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kstsa16: 0 rs1: <<: *all_regs @@ -555,7 +555,7 @@ kstsa16: ukstsa16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukstsa16: 0 rs1: <<: *all_regs @@ -574,7 +574,7 @@ ukstsa16: add8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: add8: 0 rs1: <<: *all_regs @@ -593,7 +593,7 @@ add8: radd8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: radd8: 0 rs1: <<: *all_regs @@ -612,7 +612,7 @@ radd8: uradd8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uradd8: 0 rs1: <<: *all_regs @@ -631,7 +631,7 @@ uradd8: kadd8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kadd8: 0 rs1: <<: *all_regs @@ -650,7 +650,7 @@ kadd8: ukadd8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukadd8: 0 rs1: <<: *all_regs @@ -669,7 +669,7 @@ ukadd8: sub8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sub8: 0 rs1: <<: *all_regs @@ -688,7 +688,7 @@ sub8: rsub8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rsub8: 0 rs1: <<: *all_regs @@ -707,7 +707,7 @@ rsub8: ursub8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ursub8: 0 rs1: <<: *all_regs @@ -726,7 +726,7 @@ ursub8: ksub8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ksub8: 0 rs1: <<: *all_regs @@ -745,7 +745,7 @@ ksub8: uksub8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uksub8: 0 rs1: <<: *all_regs @@ -764,7 +764,7 @@ uksub8: sra16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sra16: 0 rs1: <<: *all_regs @@ -784,7 +784,7 @@ sra16: srai16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srai16: 0 rs1: <<: *all_regs @@ -800,7 +800,7 @@ srai16: sra16.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sra16.u: 0 rs1: <<: *all_regs @@ -820,7 +820,7 @@ sra16.u: srai16.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srai16.u: 0 rs1: <<: *all_regs @@ -836,7 +836,7 @@ srai16.u: srl16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srl16: 0 rs1: <<: *all_regs @@ -856,7 +856,7 @@ srl16: srli16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srli16: 0 rs1: <<: *all_regs @@ -872,7 +872,7 @@ srli16: srl16.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srl16.u: 0 rs1: <<: *all_regs @@ -892,7 +892,7 @@ srl16.u: srli16.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srli16.u: 0 rs1: <<: *all_regs @@ -908,7 +908,7 @@ srli16.u: sll16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sll16: 0 rs1: <<: *all_regs @@ -928,7 +928,7 @@ sll16: slli16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: slli16: 0 rs1: <<: *all_regs @@ -944,7 +944,7 @@ slli16: ksll16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ksll16: 0 rs1: <<: *all_regs @@ -964,7 +964,7 @@ ksll16: kslli16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslli16: 0 rs1: <<: *all_regs @@ -980,7 +980,7 @@ kslli16: kslra16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslra16: 0 rs1: <<: *all_regs @@ -1000,7 +1000,7 @@ kslra16: kslra16.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslra16.u: 0 rs1: <<: *all_regs @@ -1020,7 +1020,7 @@ kslra16.u: sra8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sra8: 0 rs1: <<: *all_regs @@ -1040,7 +1040,7 @@ sra8: srai8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srai8: 0 rs1: <<: *all_regs @@ -1056,7 +1056,7 @@ srai8: sra8.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sra8.u: 0 rs1: <<: *all_regs @@ -1076,7 +1076,7 @@ sra8.u: srai8.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srai8.u: 0 rs1: <<: *all_regs @@ -1092,7 +1092,7 @@ srai8.u: srl8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srl8: 0 rs1: <<: *all_regs @@ -1112,7 +1112,7 @@ srl8: srli8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srli8: 0 rs1: <<: *all_regs @@ -1128,7 +1128,7 @@ srli8: srl8.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srl8.u: 0 rs1: <<: *all_regs @@ -1148,7 +1148,7 @@ srl8.u: srli8.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srli8.u: 0 rs1: <<: *all_regs @@ -1164,7 +1164,7 @@ srli8.u: sll8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sll8: 0 rs1: <<: *all_regs @@ -1184,7 +1184,7 @@ sll8: slli8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: slli8: 0 rs1: <<: *all_regs @@ -1200,7 +1200,7 @@ slli8: ksll8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ksll8: 0 rs1: <<: *all_regs @@ -1220,7 +1220,7 @@ ksll8: kslli8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslli8: 0 rs1: <<: *all_regs @@ -1236,7 +1236,7 @@ kslli8: kslra8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslra8: 0 rs1: <<: *all_regs @@ -1256,7 +1256,7 @@ kslra8: kslra8.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslra8.u: 0 rs1: <<: *all_regs @@ -1276,7 +1276,7 @@ kslra8.u: cmpeq16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: cmpeq16: 0 rs1: <<: *all_regs @@ -1295,7 +1295,7 @@ cmpeq16: scmplt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: scmplt16: 0 rs1: <<: *all_regs @@ -1314,7 +1314,7 @@ scmplt16: scmple16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: scmple16: 0 rs1: <<: *all_regs @@ -1333,7 +1333,7 @@ scmple16: ucmplt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ucmplt16: 0 rs1: <<: *all_regs @@ -1352,7 +1352,7 @@ ucmplt16: ucmple16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ucmple16: 0 rs1: <<: *all_regs @@ -1371,7 +1371,7 @@ ucmple16: cmpeq8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: cmpeq8: 0 rs1: <<: *all_regs @@ -1390,7 +1390,7 @@ cmpeq8: scmplt8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: scmplt8: 0 rs1: <<: *all_regs @@ -1409,7 +1409,7 @@ scmplt8: scmple8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: scmple8: 0 rs1: <<: *all_regs @@ -1428,7 +1428,7 @@ scmple8: ucmplt8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ucmplt8: 0 rs1: <<: *all_regs @@ -1447,7 +1447,7 @@ ucmplt8: ucmple8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ucmple8: 0 rs1: <<: *all_regs @@ -1466,7 +1466,7 @@ ucmple8: smul16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smul16: 0 rs1: <<: *all_regs @@ -1485,7 +1485,7 @@ smul16: smulx16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smulx16: 0 rs1: <<: *all_regs @@ -1504,7 +1504,7 @@ smulx16: umul16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umul16: 0 rs1: <<: *all_regs @@ -1523,7 +1523,7 @@ umul16: umulx16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umulx16: 0 rs1: <<: *all_regs @@ -1542,7 +1542,7 @@ umulx16: khm16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: khm16: 0 rs1: <<: *all_regs @@ -1561,7 +1561,7 @@ khm16: khmx16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: khmx16: 0 rs1: <<: *all_regs @@ -1580,7 +1580,7 @@ khmx16: smul8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smul8: 0 rs1: <<: *all_regs @@ -1599,7 +1599,7 @@ smul8: smulx8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smulx8: 0 rs1: <<: *all_regs @@ -1618,7 +1618,7 @@ smulx8: umul8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umul8: 0 rs1: <<: *all_regs @@ -1637,7 +1637,7 @@ umul8: umulx8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umulx8: 0 rs1: <<: *all_regs @@ -1656,7 +1656,7 @@ umulx8: khm8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: khm8: 0 rs1: <<: *all_regs @@ -1675,7 +1675,7 @@ khm8: khmx8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: khmx8: 0 rs1: <<: *all_regs @@ -1694,7 +1694,7 @@ khmx8: smin16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smin16: 0 rs1: <<: *all_regs @@ -1713,7 +1713,7 @@ smin16: umin16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umin16: 0 rs1: <<: *all_regs @@ -1732,7 +1732,7 @@ umin16: smax16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smax16: 0 rs1: <<: *all_regs @@ -1751,7 +1751,7 @@ smax16: umax16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umax16: 0 rs1: <<: *all_regs @@ -1770,7 +1770,7 @@ umax16: sclip16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sclip16: 0 rs1: <<: *all_regs @@ -1786,7 +1786,7 @@ sclip16: uclip16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uclip16: 0 rs1: <<: *all_regs @@ -1802,7 +1802,7 @@ uclip16: kabs16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kabs16: 0 rs1: <<: *all_regs @@ -1815,7 +1815,7 @@ kabs16: clrs16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: clrs16: 0 rs1: <<: *all_regs @@ -1828,7 +1828,7 @@ clrs16: clz16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: clz16: 0 rs1: <<: *all_regs @@ -1842,7 +1842,7 @@ clz16: # swap16: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # swap16: 0 # rs1: # <<: *all_regs @@ -1855,7 +1855,7 @@ clz16: smin8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smin8: 0 rs1: <<: *all_regs @@ -1874,7 +1874,7 @@ smin8: umin8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umin8: 0 rs1: <<: *all_regs @@ -1893,7 +1893,7 @@ umin8: smax8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smax8: 0 rs1: <<: *all_regs @@ -1912,7 +1912,7 @@ smax8: umax8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umax8: 0 rs1: <<: *all_regs @@ -1931,7 +1931,7 @@ umax8: kabs8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kabs8: 0 rs1: <<: *all_regs @@ -1944,7 +1944,7 @@ kabs8: sclip8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sclip8: 0 rs1: <<: *all_regs @@ -1960,7 +1960,7 @@ sclip8: uclip8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uclip8: 0 rs1: <<: *all_regs @@ -1976,7 +1976,7 @@ uclip8: clrs8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: clrs8: 0 rs1: <<: *all_regs @@ -1989,7 +1989,7 @@ clrs8: clz8: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: clz8: 0 rs1: <<: *all_regs @@ -2003,7 +2003,7 @@ clz8: # swap8: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # swap8: 0 # rs1: # <<: *all_regs @@ -2016,7 +2016,7 @@ clz8: sunpkd810: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sunpkd810: 0 rs1: <<: *all_regs @@ -2029,7 +2029,7 @@ sunpkd810: sunpkd820: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sunpkd820: 0 rs1: <<: *all_regs @@ -2042,7 +2042,7 @@ sunpkd820: sunpkd830: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sunpkd830: 0 rs1: <<: *all_regs @@ -2055,7 +2055,7 @@ sunpkd830: sunpkd831: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sunpkd831: 0 rs1: <<: *all_regs @@ -2068,7 +2068,7 @@ sunpkd831: sunpkd832: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sunpkd832: 0 rs1: <<: *all_regs @@ -2081,7 +2081,7 @@ sunpkd832: zunpkd810: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: zunpkd810: 0 rs1: <<: *all_regs @@ -2094,7 +2094,7 @@ zunpkd810: zunpkd820: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: zunpkd820: 0 rs1: <<: *all_regs @@ -2107,7 +2107,7 @@ zunpkd820: zunpkd830: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: zunpkd830: 0 rs1: <<: *all_regs @@ -2120,7 +2120,7 @@ zunpkd830: zunpkd831: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: zunpkd831: 0 rs1: <<: *all_regs @@ -2133,7 +2133,7 @@ zunpkd831: zunpkd832: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: zunpkd832: 0 rs1: <<: *all_regs @@ -2147,7 +2147,7 @@ zunpkd832: # pkbb16: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # pkbb16: 0 # rs1: # <<: *all_regs @@ -2166,7 +2166,7 @@ zunpkd832: pkbt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: pkbt16: 0 rs1: <<: *all_regs @@ -2185,7 +2185,7 @@ pkbt16: pktb16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: pktb16: 0 rs1: <<: *all_regs @@ -2205,7 +2205,7 @@ pktb16: # pktt16: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # pktt16: 0 # rs1: # <<: *all_regs @@ -2225,7 +2225,7 @@ pktb16: smmul: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smmul: 0 rs1: <<: *all_regs @@ -2243,7 +2243,7 @@ smmul: smmul.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smmul.u: 0 rs1: <<: *all_regs @@ -2261,7 +2261,7 @@ smmul.u: kmmac: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmac: 0 rs1: <<: *all_regs @@ -2279,7 +2279,7 @@ kmmac: kmmac.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmac.u: 0 rs1: <<: *all_regs @@ -2297,7 +2297,7 @@ kmmac.u: kmmsb: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmsb: 0 rs1: <<: *all_regs @@ -2315,7 +2315,7 @@ kmmsb: kmmsb.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmsb.u: 0 rs1: <<: *all_regs @@ -2333,7 +2333,7 @@ kmmsb.u: kwmmul: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kwmmul: 0 rs1: <<: *all_regs @@ -2351,7 +2351,7 @@ kwmmul: kwmmul.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kwmmul.u: 0 rs1: <<: *all_regs @@ -2372,7 +2372,7 @@ kwmmul.u: smmwb: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smmwb: 0 rs1: <<: *all_regs @@ -2390,7 +2390,7 @@ smmwb: smmwb.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smmwb.u: 0 rs1: <<: *all_regs @@ -2408,7 +2408,7 @@ smmwb.u: smmwt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smmwt: 0 rs1: <<: *all_regs @@ -2426,7 +2426,7 @@ smmwt: smmwt.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smmwt.u: 0 rs1: <<: *all_regs @@ -2445,7 +2445,7 @@ smmwt.u: kmmawb: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmawb: 0 rs1: <<: *all_regs @@ -2463,7 +2463,7 @@ kmmawb: kmmawb.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmawb.u: 0 rs1: <<: *all_regs @@ -2481,7 +2481,7 @@ kmmawb.u: kmmawt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmawt: 0 rs1: <<: *all_regs @@ -2499,7 +2499,7 @@ kmmawt: kmmawt.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmawt.u: 0 rs1: <<: *all_regs @@ -2518,7 +2518,7 @@ kmmawt.u: kmmwb2: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmwb2: 0 rs1: <<: *all_regs @@ -2536,7 +2536,7 @@ kmmwb2: kmmwb2.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmwb2.u: 0 rs1: <<: *all_regs @@ -2554,7 +2554,7 @@ kmmwb2.u: kmmwt2: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmwt2: 0 rs1: <<: *all_regs @@ -2572,7 +2572,7 @@ kmmwt2: kmmwt2.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmwt2.u: 0 rs1: <<: *all_regs @@ -2591,7 +2591,7 @@ kmmwt2.u: kmmawb2: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmawb2: 0 rs1: <<: *all_regs @@ -2609,7 +2609,7 @@ kmmawb2: kmmawb2.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmawb2.u: 0 rs1: <<: *all_regs @@ -2627,7 +2627,7 @@ kmmawb2.u: kmmawt2: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmawt2: 0 rs1: <<: *all_regs @@ -2645,7 +2645,7 @@ kmmawt2: kmmawt2.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmmawt2.u: 0 rs1: <<: *all_regs @@ -2665,7 +2665,7 @@ kmmawt2.u: smbb16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smbb16: 0 rs1: <<: *all_regs @@ -2684,7 +2684,7 @@ smbb16: smbt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smbt16: 0 rs1: <<: *all_regs @@ -2703,7 +2703,7 @@ smbt16: smtt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smtt16: 0 rs1: <<: *all_regs @@ -2722,7 +2722,7 @@ smtt16: kmda: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmda: 0 rs1: <<: *all_regs @@ -2741,7 +2741,7 @@ kmda: kmxda: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmxda: 0 rs1: <<: *all_regs @@ -2759,7 +2759,7 @@ kmxda: smds: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smds: 0 rs1: <<: *all_regs @@ -2778,7 +2778,7 @@ smds: smdrs: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smdrs: 0 rs1: <<: *all_regs @@ -2797,7 +2797,7 @@ smdrs: smxds: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smxds: 0 rs1: <<: *all_regs @@ -2816,7 +2816,7 @@ smxds: kmabb: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmabb: 0 rs1: <<: *all_regs @@ -2835,7 +2835,7 @@ kmabb: kmabt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmabt: 0 rs1: <<: *all_regs @@ -2854,7 +2854,7 @@ kmabt: kmatt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmatt: 0 rs1: <<: *all_regs @@ -2873,7 +2873,7 @@ kmatt: kmada: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmada: 0 rs1: <<: *all_regs @@ -2892,7 +2892,7 @@ kmada: kmaxda: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmaxda: 0 rs1: <<: *all_regs @@ -2911,7 +2911,7 @@ kmaxda: kmads: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmads: 0 rs1: <<: *all_regs @@ -2930,7 +2930,7 @@ kmads: kmadrs: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmadrs: 0 rs1: <<: *all_regs @@ -2949,7 +2949,7 @@ kmadrs: kmaxds: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmaxds: 0 rs1: <<: *all_regs @@ -2968,7 +2968,7 @@ kmaxds: kmsda: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmsda: 0 rs1: <<: *all_regs @@ -2987,7 +2987,7 @@ kmsda: kmsxda: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmsxda: 0 rs1: <<: *all_regs @@ -3007,7 +3007,7 @@ kmsxda: smal: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smal: 0 rs1: <<: *pair_regs @@ -3027,7 +3027,7 @@ smal: sclip32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sclip32: 0 rs1: <<: *all_regs @@ -3043,7 +3043,7 @@ sclip32: uclip32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uclip32: 0 rs1: <<: *all_regs @@ -3059,7 +3059,7 @@ uclip32: clrs32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: clrs32: 0 rs1: <<: *all_regs @@ -3073,7 +3073,7 @@ clrs32: # clz32: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # clz32: 0 # rs1: # <<: *all_regs @@ -3086,7 +3086,7 @@ clrs32: pbsad: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: pbsad: 0 rs1: <<: *all_regs @@ -3105,7 +3105,7 @@ pbsad: pbsada: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: pbsada: 0 rs1: <<: *all_regs @@ -3124,7 +3124,7 @@ pbsada: smaqa: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smaqa: 0 rs1: <<: *all_regs @@ -3143,7 +3143,7 @@ smaqa: umaqa: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umaqa: 0 rs1: <<: *all_regs @@ -3162,7 +3162,7 @@ umaqa: smaqa.su: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smaqa.su: 0 rs1: <<: *all_regs @@ -3182,7 +3182,7 @@ smaqa.su: add64: config: - check ISA:=regex(.*32.*I.*P.*Zicsr.*) - opcode: + mnemonics: add64: 0 rs1: <<: *pair_regs @@ -3200,7 +3200,7 @@ add64: radd64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: radd64: 0 rs1: <<: *pair_regs @@ -3218,7 +3218,7 @@ radd64: uradd64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uradd64: 0 rs1: <<: *pair_regs @@ -3236,7 +3236,7 @@ uradd64: kadd64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kadd64: 0 rs1: <<: *pair_regs @@ -3254,7 +3254,7 @@ kadd64: ukadd64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukadd64: 0 rs1: <<: *pair_regs @@ -3272,7 +3272,7 @@ ukadd64: sub64: config: - check ISA:=regex(.*32.*I.*P.*Zicsr.*) - opcode: + mnemonics: sub64: 0 rs1: <<: *pair_regs @@ -3290,7 +3290,7 @@ sub64: rsub64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rsub64: 0 rs1: <<: *pair_regs @@ -3308,7 +3308,7 @@ rsub64: ursub64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ursub64: 0 rs1: <<: *pair_regs @@ -3326,7 +3326,7 @@ ursub64: ksub64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ksub64: 0 rs1: <<: *pair_regs @@ -3344,7 +3344,7 @@ ksub64: uksub64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uksub64: 0 rs1: <<: *pair_regs @@ -3363,7 +3363,7 @@ uksub64: smar64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smar64: 0 rs1: <<: *all_regs @@ -3382,7 +3382,7 @@ smar64: smsr64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smsr64: 0 rs1: <<: *all_regs @@ -3401,7 +3401,7 @@ smsr64: umar64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umar64: 0 rs1: <<: *all_regs @@ -3420,7 +3420,7 @@ umar64: umsr64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umsr64: 0 rs1: <<: *all_regs @@ -3439,7 +3439,7 @@ umsr64: kmar64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmar64: 0 rs1: <<: *all_regs @@ -3458,7 +3458,7 @@ kmar64: kmsr64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmsr64: 0 rs1: <<: *all_regs @@ -3477,7 +3477,7 @@ kmsr64: ukmar64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukmar64: 0 rs1: <<: *all_regs @@ -3496,7 +3496,7 @@ ukmar64: ukmsr64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukmsr64: 0 rs1: <<: *all_regs @@ -3516,7 +3516,7 @@ ukmsr64: smalbb: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smalbb: 0 rs1: <<: *all_regs @@ -3535,7 +3535,7 @@ smalbb: smalbt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smalbt: 0 rs1: <<: *all_regs @@ -3554,7 +3554,7 @@ smalbt: smaltt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smaltt: 0 rs1: <<: *all_regs @@ -3573,7 +3573,7 @@ smaltt: smalda: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smalda: 0 rs1: <<: *all_regs @@ -3592,7 +3592,7 @@ smalda: smalxda: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smalxda: 0 rs1: <<: *all_regs @@ -3611,7 +3611,7 @@ smalxda: smalds: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smalds: 0 rs1: <<: *all_regs @@ -3630,7 +3630,7 @@ smalds: smaldrs: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smaldrs: 0 rs1: <<: *all_regs @@ -3649,7 +3649,7 @@ smaldrs: smalxds: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smalxds: 0 rs1: <<: *all_regs @@ -3668,7 +3668,7 @@ smalxds: smslda: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smslda: 0 rs1: <<: *all_regs @@ -3687,7 +3687,7 @@ smslda: smslxda: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smslxda: 0 rs1: <<: *all_regs @@ -3708,7 +3708,7 @@ smslxda: kaddh: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kaddh: 0 rs1: <<: *all_regs @@ -3727,7 +3727,7 @@ kaddh: ksubh: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ksubh: 0 rs1: <<: *all_regs @@ -3746,7 +3746,7 @@ ksubh: khmbb: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: khmbb: 0 rs1: <<: *all_regs @@ -3765,7 +3765,7 @@ khmbb: khmbt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: khmbt: 0 rs1: <<: *all_regs @@ -3784,7 +3784,7 @@ khmbt: khmtt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: khmtt: 0 rs1: <<: *all_regs @@ -3803,7 +3803,7 @@ khmtt: ukaddh: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukaddh: 0 rs1: <<: *all_regs @@ -3822,7 +3822,7 @@ ukaddh: uksubh: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uksubh: 0 rs1: <<: *all_regs @@ -3841,7 +3841,7 @@ uksubh: kaddw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kaddw: 0 rs1: <<: *all_regs @@ -3860,7 +3860,7 @@ kaddw: ukaddw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukaddw: 0 rs1: <<: *all_regs @@ -3879,7 +3879,7 @@ ukaddw: ksubw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ksubw: 0 rs1: <<: *all_regs @@ -3898,7 +3898,7 @@ ksubw: uksubw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uksubw: 0 rs1: <<: *all_regs @@ -3917,7 +3917,7 @@ uksubw: kdmbb: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmbb: 0 rs1: <<: *all_regs @@ -3936,7 +3936,7 @@ kdmbb: kdmbt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmbt: 0 rs1: <<: *all_regs @@ -3955,7 +3955,7 @@ kdmbt: kdmtt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmtt: 0 rs1: <<: *all_regs @@ -3974,7 +3974,7 @@ kdmtt: kslraw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslraw: 0 rs1: <<: *all_regs @@ -3993,7 +3993,7 @@ kslraw: kslraw.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslraw.u: 0 rs1: <<: *all_regs @@ -4013,7 +4013,7 @@ kslraw.u: ksllw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ksllw: 0 rs1: <<: *all_regs @@ -4033,7 +4033,7 @@ ksllw: kslliw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslliw: 0 rs1: <<: *all_regs @@ -4049,7 +4049,7 @@ kslliw: kdmabb: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmabb: 0 rs1: <<: *all_regs @@ -4068,7 +4068,7 @@ kdmabb: kdmabt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmabt: 0 rs1: <<: *all_regs @@ -4087,7 +4087,7 @@ kdmabt: kdmatt: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmatt: 0 rs1: <<: *all_regs @@ -4106,7 +4106,7 @@ kdmatt: kabsw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kabsw: 0 rs1: <<: *all_regs @@ -4120,7 +4120,7 @@ kabsw: raddw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: raddw: 0 rs1: <<: *all_regs @@ -4138,7 +4138,7 @@ raddw: uraddw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uraddw: 0 rs1: <<: *all_regs @@ -4156,7 +4156,7 @@ uraddw: rsubw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rsubw: 0 rs1: <<: *all_regs @@ -4174,7 +4174,7 @@ rsubw: ursubw: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ursubw: 0 rs1: <<: *all_regs @@ -4192,7 +4192,7 @@ ursubw: mulr64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: mulr64: 0 rs1: <<: *all_regs @@ -4209,7 +4209,7 @@ mulr64: mulsr64: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: mulsr64: 0 rs1: <<: *all_regs @@ -4227,7 +4227,7 @@ mulsr64: maddr32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: maddr32: 0 rs1: <<: *all_regs @@ -4245,7 +4245,7 @@ maddr32: msubr32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: msubr32: 0 rs1: <<: *all_regs @@ -4265,7 +4265,7 @@ msubr32: # rdov: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # rdov: 0 # rd: # <<: *all_regs @@ -4274,7 +4274,7 @@ msubr32: # clrov: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # clrov: 0 # rd: # <<: *all_regs @@ -4283,7 +4283,7 @@ msubr32: ave: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ave: 0 rs1: <<: *all_regs @@ -4301,7 +4301,7 @@ ave: sra.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sra.u: 0 rs1: <<: *all_regs @@ -4319,7 +4319,7 @@ sra.u: srai.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srai.u: 0 rs1: <<: *all_regs @@ -4336,7 +4336,7 @@ srai.u: # bitrev: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # bitrev: 0 # rs1: # <<: *all_regs @@ -4355,7 +4355,7 @@ srai.u: # bitrevi: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # bitrevi: 0 # rs1: # <<: *all_regs @@ -4371,7 +4371,7 @@ srai.u: # wext: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # wext: 0 # rs1: # <<: *pair_regs @@ -4389,7 +4389,7 @@ srai.u: # wexti: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # wexti: 0 # rs1: # <<: *pair_regs @@ -4405,7 +4405,7 @@ srai.u: insb: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: insb: 0 rs1: <<: *all_regs diff --git a/sample_cgfs/rv32zabha.cgf b/sample_cgfs/rv32zabha.cgf index d58b1545..754130df 100644 --- a/sample_cgfs/rv32zabha.cgf +++ b/sample_cgfs/rv32zabha.cgf @@ -163,7 +163,7 @@ amomaxu.b: amocas.b: config: - check ISA:=regex(.*I.*A.*Zabha.*Zacas.*) - opcode: + mnemonics: amocas.b: 0 rs1: <<: *all_regs_mx0 @@ -344,7 +344,7 @@ amomaxu.h: amocas.h: config: - check ISA:=regex(.*I.*A.*Zabha.*Zacas.*) - opcode: + mnemonics: amocas.h: 0 rs1: <<: *all_regs_mx0 diff --git a/sample_cgfs/rv32zacas.cgf b/sample_cgfs/rv32zacas.cgf index 4ded5bed..70935c46 100644 --- a/sample_cgfs/rv32zacas.cgf +++ b/sample_cgfs/rv32zacas.cgf @@ -2,7 +2,7 @@ amocas.w: config: - check ISA:=regex(.*Zacas.*) - opcode: + mnemonics: amocas.w: 0 rs1: <<: *all_regs_mx0 @@ -20,7 +20,7 @@ amocas.w: amocas.d_32: config: - check ISA:=regex(.*Zacas.*) - opcode: + mnemonics: amocas.d_32: 0 rs1: <<: *all_regs_mx0 diff --git a/sample_cgfs/rv64i.cgf b/sample_cgfs/rv64i.cgf index c499bb47..0a4a816d 100644 --- a/sample_cgfs/rv64i.cgf +++ b/sample_cgfs/rv64i.cgf @@ -3,13 +3,13 @@ fence: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: fence: 0 addi: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: addi: 0 rs1: <<: *all_regs @@ -26,7 +26,7 @@ addi: slti: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: slti: 0 rs1: <<: *all_regs @@ -43,7 +43,7 @@ slti: sltiu: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sltiu: 0 rs1: <<: *all_regs @@ -60,7 +60,7 @@ sltiu: andi: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: andi: 0 rs1: <<: *all_regs @@ -77,7 +77,7 @@ andi: ori: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: ori: 0 rs1: <<: *all_regs @@ -94,7 +94,7 @@ ori: xori: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: xori: 0 rs1: <<: *all_regs @@ -111,7 +111,7 @@ xori: slli: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: slli: 0 rs1: <<: *all_regs @@ -131,7 +131,7 @@ slli: srai: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: srai: 0 rs1: <<: *all_regs @@ -151,7 +151,7 @@ srai: srli: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: srli: 0 rs1: <<: *all_regs @@ -171,7 +171,7 @@ srli: add: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: add: 0 rs1: <<: *all_regs @@ -190,7 +190,7 @@ add: sub: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sub: 0 rs1: <<: *all_regs @@ -209,7 +209,7 @@ sub: slt: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: slt: 0 rs1: <<: *all_regs @@ -228,7 +228,7 @@ slt: sltu: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sltu: 0 rs1: <<: *all_regs @@ -247,7 +247,7 @@ sltu: and: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: and: 0 rs1: <<: *all_regs @@ -266,7 +266,7 @@ and: or: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: or: 0 rs1: <<: *all_regs @@ -285,7 +285,7 @@ or: xor: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: xor: 0 rs1: <<: *all_regs @@ -304,7 +304,7 @@ xor: sll: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sll: 0 rs1: <<: *all_regs @@ -326,7 +326,7 @@ sll: srl: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: srl: 0 rs1: <<: *all_regs @@ -348,7 +348,7 @@ srl: sra: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sra: 0 rs1: <<: *all_regs @@ -370,7 +370,7 @@ sra: beq: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: beq: 0 rs1: <<: *all_regs @@ -387,7 +387,7 @@ beq: bge: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: bge: 0 rs1: <<: *all_regs @@ -404,7 +404,7 @@ bge: bgeu: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: bgeu: 0 rs1: <<: *all_regs @@ -421,7 +421,7 @@ bgeu: blt: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: blt: 0 rs1: <<: *all_regs @@ -438,7 +438,7 @@ blt: bltu: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: bltu: 0 rs1: <<: *all_regs @@ -455,7 +455,7 @@ bltu: bne: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: bne: 0 rs1: <<: *all_regs @@ -472,7 +472,7 @@ bne: lhu-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lhu: 0 rs1: <<: *all_regs_mx0 @@ -496,7 +496,7 @@ lhu-align: lh-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lh: 0 rs1: <<: *all_regs_mx0 @@ -520,7 +520,7 @@ lh-align: lbu-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lbu: 0 rs1: <<: *all_regs_mx0 @@ -552,7 +552,7 @@ lbu-align: lb-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lb: 0 rs1: <<: *all_regs_mx0 @@ -584,7 +584,7 @@ lb-align: lw-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lw: 0 rs1: <<: *all_regs_mx0 @@ -605,7 +605,7 @@ lw-align: sh-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sh: 0 rs1: <<: *all_regs_mx0 @@ -632,7 +632,7 @@ sh-align: sb-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sb: 0 rs1: <<: *all_regs_mx0 @@ -667,7 +667,7 @@ sb-align: sw-align: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: sw: 0 rs1: <<: *all_regs_mx0 @@ -690,7 +690,7 @@ sw-align: auipc: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: auipc: 0 rd: <<: *all_regs @@ -707,7 +707,7 @@ auipc: lui: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: lui: 0 rd: <<: *all_regs @@ -724,7 +724,7 @@ lui: jal: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: jal: 0 rd: <<: *all_regs @@ -737,7 +737,7 @@ jal: jalr: config: - check ISA:=regex(.*I.*) - opcode: + mnemonics: jalr: 0 rs1: <<: *all_regs_mx0 @@ -754,7 +754,7 @@ jalr: lwu-align: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: lwu: 0 rs1: <<: *all_regs_mx0 @@ -774,7 +774,7 @@ lwu-align: ld-align: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: ld: 0 rs1: <<: *all_regs_mx0 @@ -798,7 +798,7 @@ ld-align: sd-align: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: sd: 0 rs1: <<: *all_regs_mx0 @@ -825,7 +825,7 @@ sd-align: addiw: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: addiw: 0 rs1: <<: *all_regs @@ -842,7 +842,7 @@ addiw: slliw: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: slliw: 0 rs1: <<: *all_regs @@ -862,7 +862,7 @@ slliw: srliw: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: srliw: 0 rs1: <<: *all_regs @@ -882,7 +882,7 @@ srliw: sraiw: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: sraiw: 0 rs1: <<: *all_regs @@ -902,7 +902,7 @@ sraiw: addw: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: addw: 0 rs1: <<: *all_regs @@ -921,7 +921,7 @@ addw: subw: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: subw: 0 rs1: <<: *all_regs @@ -940,7 +940,7 @@ subw: sllw: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: sllw: 0 rs1: <<: *all_regs @@ -962,7 +962,7 @@ sllw: srlw: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: srlw: 0 rs1: <<: *all_regs @@ -983,7 +983,7 @@ srlw: sraw: config: - check ISA:=regex(.*RV64.*I.*) - opcode: + mnemonics: sraw: 0 rs1: <<: *all_regs diff --git a/sample_cgfs/rv64i_fencei.cgf b/sample_cgfs/rv64i_fencei.cgf index 9a32e494..3397e5a0 100644 --- a/sample_cgfs/rv64i_fencei.cgf +++ b/sample_cgfs/rv64i_fencei.cgf @@ -2,7 +2,7 @@ fencei: config: - check ISA:=regex(.*I.*Zifencei.*) - opcode: + mnemonics: fence.i: 0 diff --git a/sample_cgfs/rv64i_priv.cgf b/sample_cgfs/rv64i_priv.cgf index 184d45e0..8babd644 100644 --- a/sample_cgfs/rv64i_priv.cgf +++ b/sample_cgfs/rv64i_priv.cgf @@ -1,13 +1,13 @@ ecall: config: - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: + mnemonics: ecall: 0 ebreak: config: - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: + mnemonics: ebreak: 0 misalign-lh: @@ -15,7 +15,7 @@ misalign-lh: config: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - opcode: + mnemonics: lh: 0 val_comb: 'ea_align == 1': 0 @@ -25,7 +25,7 @@ misalign-lhu: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: + mnemonics: lhu: 0 val_comb: 'ea_align == 1': 0 @@ -35,7 +35,7 @@ misalign-lwu: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*64.*I.*Zicsr.*) - opcode: + mnemonics: lwu: 0 val_comb: 'ea_align == 1': 0 @@ -47,7 +47,7 @@ misalign-sd: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*64.*I.*Zicsr.*) - opcode: + mnemonics: sd: 0 val_comb: 'ea_align == 1': 0 @@ -63,7 +63,7 @@ misalign-ld: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*64.*I.*) - opcode: + mnemonics: ld: 0 val_comb: 'ea_align == 1': 0 @@ -79,7 +79,7 @@ misalign-lw: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: + mnemonics: lw: 0 val_comb: 'ea_align == 1': 0 @@ -91,7 +91,7 @@ misalign-sh: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: + mnemonics: sh: 0 val_comb: 'ea_align == 1': 0 @@ -101,7 +101,7 @@ misalign-sw: - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: + mnemonics: sw: 0 val_comb: 'ea_align == 1': 0 @@ -113,7 +113,7 @@ misalign2-jalr: - check ISA:=regex(.*I.*C.*) - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*) - opcode: + mnemonics: jalr: 0 val_comb: 'ea_align == 2': 0 @@ -121,7 +121,7 @@ misalign2-jalr: misalign1-jalr: config: - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: + mnemonics: jalr: 0 val_comb: 'ea_align == 1': 0 @@ -131,7 +131,7 @@ misalign-jal: - check ISA:=regex(.*I.*C.*) - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*) - opcode: + mnemonics: jal: 0 val_comb: 'ea_align == 2': 0 @@ -141,7 +141,7 @@ misalign-bge: - check ISA:=regex(.*I.*C.*) - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*) - opcode: + mnemonics: bge: 0 val_comb: ' rs1_val>rs2_val and ea_align == 2': 0 @@ -151,7 +151,7 @@ misalign-bgeu: - check ISA:=regex(.*I.*C.*) - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*) - opcode: + mnemonics: bgeu: 0 val_comb: ' rs1_val>rs2_val and ea_align == 2': 0 @@ -161,7 +161,7 @@ misalign-blt: - check ISA:=regex(.*I.*C.*) - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True cond: check ISA:=regex(.*I.*) - opcode: + mnemonics: blt: 0 val_comb: ' rs1_val 0': 0 @@ -399,7 +399,7 @@ cj: cbeqz: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.beqz: 0 rs1: <<: *c_regs @@ -418,7 +418,7 @@ cbeqz: cbnez: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.bnez: 0 rs1: <<: *c_regs @@ -437,7 +437,7 @@ cbnez: cslli: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.slli: 0 rd: <<: *c_regs @@ -459,7 +459,7 @@ cslli: clwsp: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.lwsp: 0 rd: <<: *all_regs_mx0 @@ -474,7 +474,7 @@ clwsp: cldsp: config: - check ISA:=regex(.*RV64.*I.*C.*) - opcode: + mnemonics: c.ldsp: 0 rd: <<: *all_regs_mx0 @@ -489,7 +489,7 @@ cldsp: cjr: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.jr: 0 rs1: <<: *all_regs_mx0 @@ -504,7 +504,7 @@ cjr: cmv: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.mv: 0 rs2: <<: *all_regs_mx0 @@ -522,7 +522,7 @@ cmv: cadd: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.add: 0 rs1: <<: *all_regs @@ -539,7 +539,7 @@ cadd: cjalr: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.jalr: 0 rs1: <<: *all_regs_mx0 @@ -554,7 +554,7 @@ cjalr: cswsp: config: - check ISA:=regex(.*I.*C.*) - opcode: + mnemonics: c.swsp: 0 rs2: <<: *all_regs_mx2 @@ -571,7 +571,7 @@ cswsp: csdsp: config: - check ISA:=regex(.*RV64.*I.*C.*) - opcode: + mnemonics: c.sdsp: 0 rs2: <<: *all_regs_mx2 diff --git a/sample_cgfs/rv64im.cgf b/sample_cgfs/rv64im.cgf index a960b9bd..92ac8c09 100644 --- a/sample_cgfs/rv64im.cgf +++ b/sample_cgfs/rv64im.cgf @@ -3,7 +3,7 @@ mul: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: mul: 0 rs1: <<: *all_regs @@ -22,7 +22,7 @@ mul: mulh: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: mulh: 0 rs1: <<: *all_regs @@ -41,7 +41,7 @@ mulh: mulhu: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: mulhu: 0 rs1: <<: *all_regs @@ -60,7 +60,7 @@ mulhu: mulhsu: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: mulhsu: 0 rs1: <<: *all_regs @@ -80,7 +80,7 @@ mulhsu: div: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: div: 0 rs1: <<: *all_regs @@ -99,7 +99,7 @@ div: divu: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: divu: 0 rs1: <<: *all_regs @@ -118,7 +118,7 @@ divu: rem: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: rem: 0 rs1: <<: *all_regs @@ -137,7 +137,7 @@ rem: remu: config: - check ISA:=regex(.*I.*M.*) - opcode: + mnemonics: remu: 0 rs1: <<: *all_regs @@ -156,7 +156,7 @@ remu: mulw: config: - check ISA:=regex(.*RV64.*I.*M.*) - opcode: + mnemonics: mulw: 0 rs1: <<: *all_regs @@ -175,7 +175,7 @@ mulw: divw: config: - check ISA:=regex(.*RV64.*I.*M.*) - opcode: + mnemonics: divw: 0 rs1: <<: *all_regs @@ -194,7 +194,7 @@ divw: divuw: config: - check ISA:=regex(.*RV64.*I.*M.*) - opcode: + mnemonics: divuw: 0 rs1: <<: *all_regs @@ -213,7 +213,7 @@ divuw: remw: config: - check ISA:=regex(.*RV64.*I.*M.*) - opcode: + mnemonics: remw: 0 rs1: <<: *all_regs @@ -232,7 +232,7 @@ remw: remuw: config: - check ISA:=regex(.*RV64.*I.*M.*) - opcode: + mnemonics: remuw: 0 rs1: <<: *all_regs diff --git a/sample_cgfs/rv64ip.cgf b/sample_cgfs/rv64ip.cgf index 6b2ed4ac..cf0ca4ba 100644 --- a/sample_cgfs/rv64ip.cgf +++ b/sample_cgfs/rv64ip.cgf @@ -3,7 +3,7 @@ add32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: add32: 0 rs1: <<: *all_regs @@ -22,7 +22,7 @@ add32: radd32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: radd32: 0 rs1: <<: *all_regs @@ -41,7 +41,7 @@ radd32: uradd32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uradd32: 0 rs1: <<: *all_regs @@ -60,7 +60,7 @@ uradd32: kadd32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kadd32: 0 rs1: <<: *all_regs @@ -79,7 +79,7 @@ kadd32: ukadd32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukadd32: 0 rs1: <<: *all_regs @@ -98,7 +98,7 @@ ukadd32: sub32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sub32: 0 rs1: <<: *all_regs @@ -117,7 +117,7 @@ sub32: rsub32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rsub32: 0 rs1: <<: *all_regs @@ -137,7 +137,7 @@ rsub32: ursub32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ursub32: 0 rs1: <<: *all_regs @@ -156,7 +156,7 @@ ursub32: ksub32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ksub32: 0 rs1: <<: *all_regs @@ -175,7 +175,7 @@ ksub32: uksub32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: uksub32: 0 rs1: <<: *all_regs @@ -194,7 +194,7 @@ uksub32: cras32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: cras32: 0 rs1: <<: *all_regs @@ -213,7 +213,7 @@ cras32: rcras32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rcras32: 0 rs1: <<: *all_regs @@ -232,7 +232,7 @@ rcras32: urcras32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: urcras32: 0 rs1: <<: *all_regs @@ -251,7 +251,7 @@ urcras32: kcras32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kcras32: 0 rs1: <<: *all_regs @@ -270,7 +270,7 @@ kcras32: ukcras32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukcras32: 0 rs1: <<: *all_regs @@ -289,7 +289,7 @@ ukcras32: crsa32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: crsa32: 0 rs1: <<: *all_regs @@ -308,7 +308,7 @@ crsa32: rcrsa32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rcrsa32: 0 rs1: <<: *all_regs @@ -327,7 +327,7 @@ rcrsa32: urcrsa32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: urcrsa32: 0 rs1: <<: *all_regs @@ -346,7 +346,7 @@ urcrsa32: kcrsa32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kcrsa32: 0 rs1: <<: *all_regs @@ -365,7 +365,7 @@ kcrsa32: ukcrsa32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukcrsa32: 0 rs1: <<: *all_regs @@ -384,7 +384,7 @@ ukcrsa32: stas32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: stas32: 0 rs1: <<: *all_regs @@ -403,7 +403,7 @@ stas32: rstas32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rstas32: 0 rs1: <<: *all_regs @@ -422,7 +422,7 @@ rstas32: urstas32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: urstas32: 0 rs1: <<: *all_regs @@ -441,7 +441,7 @@ urstas32: kstas32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kstas32: 0 rs1: <<: *all_regs @@ -460,7 +460,7 @@ kstas32: ukstas32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukstas32: 0 rs1: <<: *all_regs @@ -479,7 +479,7 @@ ukstas32: stsa32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: stsa32: 0 rs1: <<: *all_regs @@ -498,7 +498,7 @@ stsa32: rstsa32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: rstsa32: 0 rs1: <<: *all_regs @@ -517,7 +517,7 @@ rstsa32: urstsa32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: urstsa32: 0 rs1: <<: *all_regs @@ -536,7 +536,7 @@ urstsa32: kstsa32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kstsa32: 0 rs1: <<: *all_regs @@ -555,7 +555,7 @@ kstsa32: ukstsa32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ukstsa32: 0 rs1: <<: *all_regs @@ -574,7 +574,7 @@ ukstsa32: sra32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sra32: 0 rs1: <<: *all_regs @@ -594,7 +594,7 @@ sra32: srai32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srai32: 0 rs1: <<: *all_regs @@ -610,7 +610,7 @@ srai32: sra32.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sra32.u: 0 rs1: <<: *all_regs @@ -630,7 +630,7 @@ sra32.u: srai32.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srai32.u: 0 rs1: <<: *all_regs @@ -646,7 +646,7 @@ srai32.u: srl32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srl32: 0 rs1: <<: *all_regs @@ -666,7 +666,7 @@ srl32: srli32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srli32: 0 rs1: <<: *all_regs @@ -682,7 +682,7 @@ srli32: srl32.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srl32.u: 0 rs1: <<: *all_regs @@ -702,7 +702,7 @@ srl32.u: srli32.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: srli32.u: 0 rs1: <<: *all_regs @@ -718,7 +718,7 @@ srli32.u: sll32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sll32: 0 rs1: <<: *all_regs @@ -738,7 +738,7 @@ sll32: slli32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: slli32: 0 rs1: <<: *all_regs @@ -754,7 +754,7 @@ slli32: ksll32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: ksll32: 0 rs1: <<: *all_regs @@ -774,7 +774,7 @@ ksll32: kslli32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslli32: 0 rs1: <<: *all_regs @@ -790,7 +790,7 @@ kslli32: kslra32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslra32: 0 rs1: <<: *all_regs @@ -810,7 +810,7 @@ kslra32: kslra32.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kslra32.u: 0 rs1: <<: *all_regs @@ -830,7 +830,7 @@ kslra32.u: smin32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smin32: 0 rs1: <<: *all_regs @@ -849,7 +849,7 @@ smin32: umin32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umin32: 0 rs1: <<: *all_regs @@ -868,7 +868,7 @@ umin32: smax32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smax32: 0 rs1: <<: *all_regs @@ -887,7 +887,7 @@ smax32: umax32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: umax32: 0 rs1: <<: *all_regs @@ -906,7 +906,7 @@ umax32: kabs32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kabs32: 0 rs1: <<: *all_regs @@ -919,7 +919,7 @@ kabs32: khmbb16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: khmbb16: 0 rs1: <<: *all_regs @@ -938,7 +938,7 @@ khmbb16: khmbt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: khmbt16: 0 rs1: <<: *all_regs @@ -957,7 +957,7 @@ khmbt16: khmtt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: khmtt16: 0 rs1: <<: *all_regs @@ -976,7 +976,7 @@ khmtt16: kdmbb16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmbb16: 0 rs1: <<: *all_regs @@ -995,7 +995,7 @@ kdmbb16: kdmbt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmbt16: 0 rs1: <<: *all_regs @@ -1014,7 +1014,7 @@ kdmbt16: kdmtt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmtt16: 0 rs1: <<: *all_regs @@ -1033,7 +1033,7 @@ kdmtt16: kdmabb16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmabb16: 0 rs1: <<: *all_regs @@ -1052,7 +1052,7 @@ kdmabb16: kdmabt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmabt16: 0 rs1: <<: *all_regs @@ -1071,7 +1071,7 @@ kdmabt16: kdmatt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kdmatt16: 0 rs1: <<: *all_regs @@ -1091,7 +1091,7 @@ kdmatt16: # smbb32: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # smbb32: 0 # rs1: # <<: *all_regs @@ -1110,7 +1110,7 @@ kdmatt16: smbt32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smbt32: 0 rs1: <<: *all_regs @@ -1129,7 +1129,7 @@ smbt32: smtt32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smtt32: 0 rs1: <<: *all_regs @@ -1148,7 +1148,7 @@ smtt32: kmabb32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmabb32: 0 rs1: <<: *all_regs @@ -1167,7 +1167,7 @@ kmabb32: kmabt32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmabt32: 0 rs1: <<: *all_regs @@ -1186,7 +1186,7 @@ kmabt32: kmatt32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmatt32: 0 rs1: <<: *all_regs @@ -1205,7 +1205,7 @@ kmatt32: kmda32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmda32: 0 rs1: <<: *all_regs @@ -1224,7 +1224,7 @@ kmda32: kmxda32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmxda32: 0 rs1: <<: *all_regs @@ -1244,7 +1244,7 @@ kmxda32: # kmada32: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # kmada32: 0 # rs1: # <<: *all_regs @@ -1263,7 +1263,7 @@ kmxda32: kmaxda32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmaxda32: 0 rs1: <<: *all_regs @@ -1282,7 +1282,7 @@ kmaxda32: kmads32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmads32: 0 rs1: <<: *all_regs @@ -1301,7 +1301,7 @@ kmads32: kmadrs32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmadrs32: 0 rs1: <<: *all_regs @@ -1320,7 +1320,7 @@ kmadrs32: kmaxds32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmaxds32: 0 rs1: <<: *all_regs @@ -1339,7 +1339,7 @@ kmaxds32: kmsda32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmsda32: 0 rs1: <<: *all_regs @@ -1358,7 +1358,7 @@ kmsda32: kmsxda32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: kmsxda32: 0 rs1: <<: *all_regs @@ -1377,7 +1377,7 @@ kmsxda32: smds32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smds32: 0 rs1: <<: *all_regs @@ -1396,7 +1396,7 @@ smds32: smdrs32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smdrs32: 0 rs1: <<: *all_regs @@ -1415,7 +1415,7 @@ smdrs32: smxds32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: smxds32: 0 rs1: <<: *all_regs @@ -1434,7 +1434,7 @@ smxds32: sraiw.u: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: sraiw.u: 0 rs1: <<: *all_regs @@ -1451,7 +1451,7 @@ sraiw.u: # pkbb32: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # pkbb32: 0 # rs1: # <<: *all_regs @@ -1470,7 +1470,7 @@ sraiw.u: pkbt32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: pkbt32: 0 rs1: <<: *all_regs @@ -1489,7 +1489,7 @@ pkbt32: pktb32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: pktb32: 0 rs1: <<: *all_regs @@ -1509,7 +1509,7 @@ pktb32: # pktt32: # config: # - check ISA:=regex(.*I.*P.*Zicsr.*) -# opcode: +# mnemonics: # pktt32: 0 # rs1: # <<: *all_regs @@ -1529,7 +1529,7 @@ pktb32: clz32: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: clz32: 0 rs1: <<: *all_regs @@ -1542,7 +1542,7 @@ clz32: pkbb16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: pkbb16: 0 rs1: <<: *all_regs @@ -1561,7 +1561,7 @@ pkbb16: pktt16: config: - check ISA:=regex(.*I.*P.*Zicsr.*) - opcode: + mnemonics: pktt16: 0 rs1: <<: *all_regs diff --git a/sample_cgfs/rv64zacas.cgf b/sample_cgfs/rv64zacas.cgf index f0f4a781..6d4db482 100644 --- a/sample_cgfs/rv64zacas.cgf +++ b/sample_cgfs/rv64zacas.cgf @@ -2,7 +2,7 @@ amocas.w: config: - check ISA:=regex(.*Zacas.*) - opcode: + mnemonics: amocas.w: 0 rs1: <<: *all_regs_mx0 @@ -20,7 +20,7 @@ amocas.w: amocas.d_64: config: - check ISA:=regex(.*Zacas.*) - opcode: + mnemonics: amocas.d_64: 0 rs1: <<: *all_regs_mx0 @@ -38,7 +38,7 @@ amocas.d_64: amocas.q: config: - check ISA:=regex(.*Zacas.*) - opcode: + mnemonics: amocas.q: 0 rs1: <<: *all_regs_mx0 diff --git a/sample_cgfs/zcmop.cgf b/sample_cgfs/zcmop.cgf index 99329886..8af2caa0 100644 --- a/sample_cgfs/zcmop.cgf +++ b/sample_cgfs/zcmop.cgf @@ -10,7 +10,7 @@ c.mop.1: c.mop.3: config: - check ISA:=regex(.*C.*Zcmop.*) - opcode: + mnemonics: c.mop.3: val_comb: abstract_comb: @@ -19,7 +19,7 @@ c.mop.3: c.mop.5: config: - check ISA:=regex(.*C.*Zcmop.*) - opcode: + mnemonics: c.mop.5: val_comb: abstract_comb: @@ -28,7 +28,7 @@ c.mop.5: c.mop.7: config: - check ISA:=regex(.*C.*Zcmop.*) - opcode: + mnemonics: c.mop.7: val_comb: abstract_comb: @@ -37,7 +37,7 @@ c.mop.7: c.mop.9: config: - check ISA:=regex(.*C.*Zcmop.*) - opcode: + mnemonics: c.mop.9: val_comb: abstract_comb: @@ -46,7 +46,7 @@ c.mop.9: c.mop.11: config: - check ISA:=regex(.*C.*Zcmop.*) - opcode: + mnemonics: c.mop.11: val_comb: abstract_comb: @@ -55,7 +55,7 @@ c.mop.11: c.mop.13: config: - check ISA:=regex(.*C.*Zcmop.*) - opcode: + mnemonics: c.mop.13: val_comb: abstract_comb: @@ -64,7 +64,7 @@ c.mop.13: c.mop.15: config: - check ISA:=regex(.*C.*Zcmop.*) - opcode: + mnemonics: c.mop.15: val_comb: abstract_comb: diff --git a/sample_cgfs/zicfilp.cgf b/sample_cgfs/zicfilp.cgf index 61358bee..6ead1de8 100644 --- a/sample_cgfs/zicfilp.cgf +++ b/sample_cgfs/zicfilp.cgf @@ -1,7 +1,7 @@ lpad-m: config: - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True - opcode: + mnemonics: lpad-m: 0 val_comb: 'imm_val == 0': 0 @@ -16,7 +16,7 @@ lpad-m: lpad-s: config: - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True - opcode: + mnemonics: lpad-s: 0 val_comb: 'imm_val == 0': 0 @@ -31,7 +31,7 @@ lpad-s: lpad-u: config: - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True - opcode: + mnemonics: lpad-u: 0 val_comb: 'imm_val == 0': 0 diff --git a/sample_cgfs/zicfiss.cgf b/sample_cgfs/zicfiss.cgf index 39cbffa8..b1c1140c 100644 --- a/sample_cgfs/zicfiss.cgf +++ b/sample_cgfs/zicfiss.cgf @@ -1,7 +1,7 @@ sspush_popchk_u: config: - check ISA:=regex(.*I.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True - opcode: + mnemonics: sspushpopchk_u: 0 val_comb: <<: [*base_rs2val_sgn] @@ -11,7 +11,7 @@ sspush_popchk_u: sspush_popchk_s: config: - check ISA:=regex(.*I.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True - opcode: + mnemonics: sspushpopchk_s: 0 val_comb: <<: [*base_rs2val_sgn] @@ -21,7 +21,7 @@ sspush_popchk_s: csspush_popchk_u: config: - check ISA:=regex(.*I.*C.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True - opcode: + mnemonics: c.sspushpopchk_u: 0 val_comb: <<: [*base_rs2val_sgn] @@ -31,7 +31,7 @@ csspush_popchk_u: csspush_popchk_s: config: - check ISA:=regex(.*I.*C.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True - opcode: + mnemonics: c.sspushpopchk_s: 0 val_comb: <<: [*base_rs2val_sgn] diff --git a/sample_cgfs/zicond.cgf b/sample_cgfs/zicond.cgf index f7f2a499..af6c1b82 100644 --- a/sample_cgfs/zicond.cgf +++ b/sample_cgfs/zicond.cgf @@ -1,7 +1,7 @@ czero.eqz: config: - check ISA:=regex(.*Zicond.*) - opcode: + mnemonics: czero.eqz: 0 rs1: <<: *all_regs @@ -20,7 +20,7 @@ czero.eqz: czero.nez: config: - check ISA:=regex(.*Zicond.*) - opcode: + mnemonics: czero.nez: 0 rs1: <<: *all_regs diff --git a/sample_cgfs/zimop.cgf b/sample_cgfs/zimop.cgf index a47cbdb9..25fb014c 100644 --- a/sample_cgfs/zimop.cgf +++ b/sample_cgfs/zimop.cgf @@ -3,7 +3,7 @@ mop.rr.0: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.rr.0: 0 rs1: <<: *all_regs @@ -22,7 +22,7 @@ mop.rr.0: mop.rr.1: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.rr.1: 0 rs1: <<: *all_regs @@ -41,7 +41,7 @@ mop.rr.1: mop.rr.2: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.rr.2: 0 rs1: <<: *all_regs @@ -60,7 +60,7 @@ mop.rr.2: mop.rr.3: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.rr.3: 0 rs1: <<: *all_regs @@ -79,7 +79,7 @@ mop.rr.3: mop.rr.4: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.rr.4: 0 rs1: <<: *all_regs @@ -98,7 +98,7 @@ mop.rr.4: mop.rr.5: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.rr.5: 0 rs1: <<: *all_regs @@ -117,7 +117,7 @@ mop.rr.5: mop.rr.6: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.rr.6: 0 rs1: <<: *all_regs @@ -136,7 +136,7 @@ mop.rr.6: mop.rr.7: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.rr.7: 0 rs1: <<: *all_regs @@ -155,7 +155,7 @@ mop.rr.7: mop.r.0: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.0: 0 rs1: <<: *all_regs @@ -172,7 +172,7 @@ mop.r.0: mop.r.1: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.1: 0 rs1: <<: *all_regs @@ -189,7 +189,7 @@ mop.r.1: mop.r.2: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.2: 0 rs1: <<: *all_regs @@ -206,7 +206,7 @@ mop.r.2: mop.r.3: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.3: 0 rs1: <<: *all_regs @@ -223,7 +223,7 @@ mop.r.3: mop.r.4: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.4: 0 rs1: <<: *all_regs @@ -240,7 +240,7 @@ mop.r.4: mop.r.5: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.5: 0 rs1: <<: *all_regs @@ -257,7 +257,7 @@ mop.r.5: mop.r.6: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.6: 0 rs1: <<: *all_regs @@ -274,7 +274,7 @@ mop.r.6: mop.r.7: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.7: 0 rs1: <<: *all_regs @@ -291,7 +291,7 @@ mop.r.7: mop.r.8: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.8: 0 rs1: <<: *all_regs @@ -308,7 +308,7 @@ mop.r.8: mop.r.9: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.9: 0 rs1: <<: *all_regs @@ -325,7 +325,7 @@ mop.r.9: mop.r.10: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.10: 0 rs1: <<: *all_regs @@ -342,7 +342,7 @@ mop.r.10: mop.r.11: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.11: 0 rs1: <<: *all_regs @@ -359,7 +359,7 @@ mop.r.11: mop.r.12: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.12: 0 rs1: <<: *all_regs @@ -376,7 +376,7 @@ mop.r.12: mop.r.13: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.13: 0 rs1: <<: *all_regs @@ -393,7 +393,7 @@ mop.r.13: mop.r.14: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.14: 0 rs1: <<: *all_regs @@ -410,7 +410,7 @@ mop.r.14: mop.r.15: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.15: 0 rs1: <<: *all_regs @@ -427,7 +427,7 @@ mop.r.15: mop.r.16: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.16: 0 rs1: <<: *all_regs @@ -444,7 +444,7 @@ mop.r.16: mop.r.17: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.17: 0 rs1: <<: *all_regs @@ -461,7 +461,7 @@ mop.r.17: mop.r.18: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.18: 0 rs1: <<: *all_regs @@ -478,7 +478,7 @@ mop.r.18: mop.r.19: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.19: 0 rs1: <<: *all_regs @@ -495,7 +495,7 @@ mop.r.19: mop.r.20: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.20: 0 rs1: <<: *all_regs @@ -512,7 +512,7 @@ mop.r.20: mop.r.21: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.21: 0 rs1: <<: *all_regs @@ -529,7 +529,7 @@ mop.r.21: mop.r.22: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.22: 0 rs1: <<: *all_regs @@ -546,7 +546,7 @@ mop.r.22: mop.r.23: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.23: 0 rs1: <<: *all_regs @@ -563,7 +563,7 @@ mop.r.23: mop.r.24: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.24: 0 rs1: <<: *all_regs @@ -580,7 +580,7 @@ mop.r.24: mop.r.25: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.25: 0 rs1: <<: *all_regs @@ -597,7 +597,7 @@ mop.r.25: mop.r.26: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.26: 0 rs1: <<: *all_regs @@ -614,7 +614,7 @@ mop.r.26: mop.r.27: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.27: 0 rs1: <<: *all_regs @@ -631,7 +631,7 @@ mop.r.27: mop.r.28: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.28: 0 rs1: <<: *all_regs @@ -648,7 +648,7 @@ mop.r.28: mop.r.29: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.29: 0 rs1: <<: *all_regs @@ -665,7 +665,7 @@ mop.r.29: mop.r.30: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.30: 0 rs1: <<: *all_regs @@ -682,7 +682,7 @@ mop.r.30: mop.r.31: config: - check ISA:=regex(.*Zimop.*) - opcode: + mnemonics: mop.r.31: 0 rs1: <<: *all_regs From 70efe8c84d1ac7cc7768b5717de86f77471228cd Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Tue, 20 Feb 2024 12:45:18 +0530 Subject: [PATCH 092/101] Update test-1.yml for CI --- .github/workflows/test-1.yml | 43 +++++++++++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/.github/workflows/test-1.yml b/.github/workflows/test-1.yml index fb6e858c..4399b394 100644 --- a/.github/workflows/test-1.yml +++ b/.github/workflows/test-1.yml @@ -1,4 +1,4 @@ -name: test-1 +name: test-2 on: pull_request: branches: @@ -9,6 +9,10 @@ on: jobs: build: runs-on: ubuntu-latest + strategy: + matrix: + cgf_files: ["./sample_cgfs/*.cgf"] + architecture: ["rv32e", "rv32i", "rv64i", "rv32i_64i"] steps: - uses: actions/checkout@v2 - name: Set up Python @@ -23,24 +27,51 @@ jobs: pip install --editable . - - name: Run RISC-V CTG for all CGF files except FP + - name: Run RISC-V CTG for RV32E run: | set -e for cgf_file in ./sample_cgfs/*.cgf; do if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then - if [[ "$cgf_file" == *rv32e* ]]; then + if [[ "$cgf_file" == *rv32e* ]] && [ "${{matrix.architecture}}" == "rv32e" ] ; then cmd="riscv_ctg -r -d ./tests -bi rv32e -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" echo $cmd eval $cmd || { echo "Error executing command: $cmd"; exit 1; } - elif [[ "$cgf_file" == *rv32* && "$cgf_file" != *rv32e* ]]; then + fi + fi + done + + - name: Run RISC-V CTG for RV32I + run: | + set -e + for cgf_file in ./sample_cgfs/*.cgf; do + if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then + if [[ "$cgf_file" != *rv32e* ]] && [[ "cgf_file" == *rv32* ]] && [ "${{matrix.architecture}}" == "rv32i" ] ; then cmd="riscv_ctg -r -d ./tests -bi rv32i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" echo $cmd eval $cmd || { echo "Error executing command: $cmd"; exit 1; } - elif [[ "$cgf_file" == *rv64* ]]; then + fi + fi + done + + - name: Run RISC-V CTG for RV64I + run: | + set -e + for cgf_file in ./sample_cgfs/*.cgf; do + if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then + if [[ "$cgf_file" == *rv64* ]] && [ "${{matrix.architecture}}" == "rv64i" ] ; then cmd="riscv_ctg -r -d ./tests -bi rv64i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" echo $cmd eval $cmd || { echo "Error executing command: $cmd"; exit 1; } - else + fi + fi + done + + - name: Run RISC-V CTG for RV64I and RV32I + run: | + set -e + for cgf_file in ./sample_cgfs/*.cgf; do + if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then + if [[ "$cgf_file" != *rv32e* ]] && [[ "$cgf_file" != *rv32* ]] && [[ "$cgf_file" != *rv64* ]] && [ "${{matrix.architecture}}" == "rv32i_64i" ] ; then for arch in rv32i rv64i; do cmd="riscv_ctg -r -d ./tests -bi $arch -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" echo $cmd From 05381047090bfedf73b5b3118385a8c9596f35f4 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Tue, 20 Feb 2024 12:45:49 +0530 Subject: [PATCH 093/101] Update test-1.yml for CI --- .github/workflows/test-1.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-1.yml b/.github/workflows/test-1.yml index 4399b394..f1fe2553 100644 --- a/.github/workflows/test-1.yml +++ b/.github/workflows/test-1.yml @@ -1,4 +1,4 @@ -name: test-2 +name: test-1 on: pull_request: branches: From f53f17f80557bf7ecd48155d84d650c9eed9b0d1 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Tue, 20 Feb 2024 12:46:31 +0530 Subject: [PATCH 094/101] Update generator.py for hardcoded register testcases --- riscv_ctg/generator.py | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 6446b936..d666b408 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -294,6 +294,7 @@ def opcomb(self, cgf): logger.debug(self.opcode + ' : Generating OpComb') solutions = [] op_conds = {} + opcomb_value = cgf.get("op_comb") if "op_comb" in cgf: op_comb = set(cgf["op_comb"]) else: @@ -333,21 +334,26 @@ def comb_constraint(*args): problem.addConstraint(AllDifferentConstraint()) count = 0 solution = problem.getSolution() - while (solution is None and count < 5): -# pattern = r'(?:rs1|rs2|rd) == "(x\d+)"' -# matches = re.findall(pattern, cond) -# if not matches or any(int(match[1:]) > 31 for match in matches): -# result = None -# else: -# result = matches -# for match in result: -# op_conds['rs1'].add(match) -# op_conds['rs2'].add(match) -# op_conds['rd'].add(match) -# op_comb.add(cond) -# break + while solution is None and count < 5: + if opcomb_value: + for i in opcomb_value: + opcomb_match = re.search(r'x\d{1,2}', i) + if opcomb_match is not None: + pattern = r'(?:rs1|rs2|rd) == "(x\d+)"' + matches = re.findall(pattern, cond) + if not matches or any(int(match[1:]) > 31 for match in matches): + result = None + else: + result = matches + for match in result: + op_conds['rs1'].add(match) + op_conds['rs2'].add(match) + op_conds['rd'].add(match) + op_comb.add(cond) + break solution = problem.getSolution() count = count + 1 + if solution is None: if individual: if nodiff: From 3f27b30927e5069ce35174526b0ac295c4540c59 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Tue, 20 Feb 2024 12:47:08 +0530 Subject: [PATCH 095/101] Add hardcoded register testcases to dataset.cgf and rv32im.cgf --- sample_cgfs/dataset.cgf | 6 ++++++ sample_cgfs/rv32im.cgf | 8 ++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index 1961b4fb..2d3565ea 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -225,6 +225,12 @@ datasets: 'rs1 == rs2 == rd': 0 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 + div_hardcoded_opcomb: &div_hardcoded_opcomb + 'rs1 == rd != rs2 and rd != "x0"': 0 + 'rs1 == rd != rs2 and rd == "x0"': 0 + 'rs1 == "x0" != rd': 0 + 'rd == "x0" != rs1': 0 + ramofmt_op_comb: &ramofmt_op_comb 'rs1 == rd != rs2': 0 'rs2 == rd != rs1': 0 diff --git a/sample_cgfs/rv32im.cgf b/sample_cgfs/rv32im.cgf index 5c5d7b8d..d69131e4 100644 --- a/sample_cgfs/rv32im.cgf +++ b/sample_cgfs/rv32im.cgf @@ -89,7 +89,7 @@ div: rd: <<: *all_regs op_comb: - <<: *rfmt_op_comb + <<: [*rfmt_op_comb , *div_hardcoded_opcomb] val_comb: <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: @@ -108,7 +108,7 @@ divu: rd: <<: *all_regs op_comb: - <<: *rfmt_op_comb + <<: [*rfmt_op_comb , *div_hardcoded_opcomb] val_comb: <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] abstract_comb: @@ -127,7 +127,7 @@ rem: rd: <<: *all_regs op_comb: - <<: *rfmt_op_comb + <<: [*rfmt_op_comb , *div_hardcoded_opcomb] val_comb: <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] abstract_comb: @@ -146,7 +146,7 @@ remu: rd: <<: *all_regs op_comb: - <<: *rfmt_op_comb + <<: [*rfmt_op_comb , *div_hardcoded_opcomb] val_comb: <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] abstract_comb: From 2bcd66e06a48e39651534cd4603fac2813b9f059 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 22 Feb 2024 11:43:59 +0530 Subject: [PATCH 096/101] define rs1_val_data for instructions from zicfiss.cgf in template.yaml --- riscv_ctg/data/template.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index 788299b6..d1f87c8d 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -12477,6 +12477,7 @@ sspushpopchk_u: isa: - I_Zicfiss_Zicsr formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)' template: |- // $comment @@ -12491,6 +12492,7 @@ sspushpopchk_s: isa: - I_Zicfiss_Zicsr formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)' template: |- // $comment @@ -12505,6 +12507,7 @@ c.sspushpopchk_u: isa: - IC_Zicfiss_Zicsr formattype: 'crformat' + rs1_val_data: 'gen_sign_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)' template: |- // $comment @@ -12519,6 +12522,7 @@ c.sspushpopchk_s: isa: - IC_Zicfiss_Zicsr formattype: 'crformat' + rs1_val_data: 'gen_sign_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)' template: |- // $comment @@ -12625,6 +12629,8 @@ ssrdp_s: std_op: isa: - I_Zicfiss_Zicsr + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' formattype: 'rformat' template: |- // $comment @@ -12644,6 +12650,8 @@ ssrdp_u: std_op: isa: - I_Zicfiss_Zicsr + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' formattype: 'rformat' template: |- // $comment From da934a94ee7dab7b03588752af4c539c9e57c288 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 22 Feb 2024 17:18:23 +0530 Subject: [PATCH 097/101] Update test.yml --- .github/workflows/test.yml | 95 ++++++++++++++++++++++++++------------ 1 file changed, 65 insertions(+), 30 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 174651c2..f77b8a39 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -1,26 +1,19 @@ -# This is a basic workflow to help you get started with Actions - name: test - -# Controls when the action will run. on: - # Triggers the workflow on push or pull request events but only for the master branch pull_request: - branches: [ master ] - - # Allows you to run this workflow manually from the Actions tab + branches: + -master + -dev workflow_dispatch: -# A workflow run is made up of one or more jobs that can run sequentially or in parallel jobs: - # This workflow contains a single job called "build" build: - # The type of runner that the job will run on runs-on: ubuntu-latest - - # Steps represent a sequence of tasks that will be executed as part of the job + strategy: + matrix: + cgf_files: ["./sample_cgfs/*.cgf"] + architecture: ["rv32e", "rv32i", "rv64i", "rv32i_64i"] steps: - # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it - uses: actions/checkout@v2 - name: Set up Python uses: actions/setup-python@v2 @@ -33,10 +26,63 @@ jobs: pip install -r riscv_ctg/requirements.txt pip install --editable . - - name: Run rv32i - run: riscv_ctg -r -d rv32i -bi rv32i -cf sample_cgfs/dataset.cgf -cf sample_cgfs/rv32i.cgf -v debug -p $(nproc) + + - name: Run RISC-V CTG for RV32E + run: | + set -e + for cgf_file in ./sample_cgfs/*.cgf; do + if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then + if [[ "$cgf_file" == *rv32e* ]] && [ "${{matrix.architecture}}" == "rv32e" ] ; then + cmd="riscv_ctg -r -d ./tests -bi rv32e -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" + echo $cmd + eval $cmd || { echo "Error executing command: $cmd"; exit 1; } + fi + fi + done + + - name: Run RISC-V CTG for RV32I + run: | + set -e + for cgf_file in ./sample_cgfs/*.cgf; do + if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then + if [[ "$cgf_file" != *rv32e* ]] && [[ "cgf_file" == *rv32* ]] && [ "${{matrix.architecture}}" == "rv32i" ] ; then + cmd="riscv_ctg -r -d ./tests -bi rv32i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" + echo $cmd + eval $cmd || { echo "Error executing command: $cmd"; exit 1; } + fi + fi + done + + - name: Run RISC-V CTG for RV64I + run: | + set -e + for cgf_file in ./sample_cgfs/*.cgf; do + if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then + if [[ "$cgf_file" == *rv64* ]] && [ "${{matrix.architecture}}" == "rv64i" ] ; then + cmd="riscv_ctg -r -d ./tests -bi rv64i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" + echo $cmd + eval $cmd || { echo "Error executing command: $cmd"; exit 1; } + fi + fi + done + + - name: Run RISC-V CTG for RV64I and RV32I + run: | + set -e + for cgf_file in ./sample_cgfs/*.cgf; do + if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then + if [[ "$cgf_file" != *rv32e* ]] && [[ "$cgf_file" != *rv32* ]] && [[ "$cgf_file" != *rv64* ]] && [ "${{matrix.architecture}}" == "rv32i_64i" ] ; then + for arch in rv32i rv64i; do + cmd="riscv_ctg -r -d ./tests -bi $arch -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" + echo $cmd + eval $cmd || { echo "Error executing command: $cmd"; exit 1; } + done + fi + fi + done check-version: + if: github.ref == 'refs/heads/master' runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 @@ -51,21 +97,8 @@ jobs: echo "Versions are equal in Changelog and init.py." else echo "Versions are not equal in Changelog and init.py." - exit 1 + exit 1 fi - - check-version-changelog: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v2 - - - uses: actions-ecosystem/action-get-latest-tag@v1 - id: get-latest-tag - - - name: version check - run: | - export CHNGVER=$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md); - echo "CHANGELOG VERSION: $CHNGVER" export TAGVER=${{ steps.get-latest-tag.outputs.tag }}; echo "TAG VERSION: $TAGVER" if [ "$CHNGVER" = "$TAGVER" ]; then @@ -74,3 +107,5 @@ jobs: else echo "Changelog updated." fi + + \ No newline at end of file From 82080942fb83f94f2dcf9ab3aad0c03fe365b50d Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 22 Feb 2024 17:18:43 +0530 Subject: [PATCH 098/101] Update changelog --- CHANGELOG.md | 47 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index b158e6bd..7e13d0f7 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,15 +6,44 @@ Please note the header `WIP-DEV` is to always remain indicating the changes done Only when a release to the main branch is done, the contents of the WIP-DEV are put under a versioned header while the `WIP-DEV` is left empty -## [WIP-DEV] -- Add Zaamo subcomponent of A - -## [WIP-DEV] -- Added Zifencei, Bit Manipulation and Privilege tests ctg files for RV32E -- Added support of Zcb from Code Size Reduction Extension. -- Added support of Standard Atomic (A) Extension (RV32 and RV64), excluding the LR/SC instruction. -- Updating CONTRIBUTING.rst to capture the new git strategy adopted to follow a monthly release - cadence. +## [0.12.0] - 2024-02-22 +- Update generator.py to take care of hard coded register testcases only if a hard coded register is assigned in the op_comb node of a coverpoint of an instruction. +- Add hardcoded register testcases to dataset.cgf and rv32im.cgf +- Define rs1_val_data for c.ldsp in imc.yaml +- Update "opcode" to "mnemonics" in the cgf files +- Delete main.yml +- Update test.yml for CI +- Define rs1_val_data for instructions from zicfiss.cgf in template.yaml +- Add "warning" in the verbose definition +- Add unratified Zicfiss extension +- Add unratified Zicfilp extension +- Add corner case of division for division operations for RV64 +- Fix csr_comb to write test information +- Add unratified Zaamo subcomponent of A extension +- Add unratified B extension +- Fix issues with csr_comb +- Minor fix in kslraw.u in rv32ip +- Fix incorrect 'sig:' entry in aes32dsi in template.yaml +- Add sig and sz for instructions in template.yaml +- Minor change of rd definition in c.lui in rv32ec +- Minor fix in rv32i_k +- Add rs1_val_data, rs2_val_data, imm_val_data for instructions in template.yaml +- Comment xlenlim out of val_comb in rv32i_b, rv64i_b +- Fix the formats of leading_ones, leading_zeros, trailing_ones, trailing_zeros for instructions in rv32i_b, rv32e_b +- Add op_comb for instructions in rv32i_zcb +- Add rs1_val_data for instructions in imc.yaml +- Add op_comb and val_comb for instructions in rv32ic, rv64ic, rv32ec +- Add corner case of division for division operations for RV32 +- Comment print statements out from generator.py +- Fix whitespaces on empty lines in yaml template files. +- Add unratified Zabha extension +- Add support for unratified Zcmop extension +- Add support for unratified Zimop extension +- Add missing coverage for hard coded register testcases +- Updated CONTRIBUTING.rst to capture the new git strategy adopted to follow a monthly release cadence. +- Add Zifencei, Bit Manipulation and Privilege tests cgf files for RV32E +- Add unratified Zacas extension +- Add support for standard Atomic(A) extension ## [0.11.1] - 2023-08-15 - Fixed hex values handling for K extensions From 60781d9ed8f747fc7280bc68220dba4019404091 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 22 Feb 2024 17:19:01 +0530 Subject: [PATCH 099/101] =?UTF-8?q?Bump=20version:=200.11.1=20=E2=86=92=20?= =?UTF-8?q?0.12.0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- riscv_ctg/__init__.py | 2 +- setup.cfg | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py index cd7b2b43..1d96eb63 100644 --- a/riscv_ctg/__init__.py +++ b/riscv_ctg/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'incorebot@gmail.com' -__version__ = '0.11.2' +__version__ = '0.12.0' diff --git a/setup.cfg b/setup.cfg index d4d3ae2c..0c3d811e 100644 --- a/setup.cfg +++ b/setup.cfg @@ -1,5 +1,5 @@ [bumpversion] -current_version = 0.11.2 +current_version = 0.12.0 commit = True tag = True From 3de51842ff49ea48335ee8c5713c733c94e4f942 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 22 Feb 2024 17:19:27 +0530 Subject: [PATCH 100/101] delete main.yml and test-1.yml --- .github/workflows/main.yml | 98 ------------------------------- .github/workflows/test-1.yml | 111 ----------------------------------- 2 files changed, 209 deletions(-) delete mode 100644 .github/workflows/main.yml delete mode 100644 .github/workflows/test-1.yml diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml deleted file mode 100644 index 28b8f6f7..00000000 --- a/.github/workflows/main.yml +++ /dev/null @@ -1,98 +0,0 @@ -# This is a basic workflow to help you get started with Actions - -name: CI - -# Controls when the action will run. -on: - # Triggers the workflow on push or pull request events but only for the master branch - push: - branches: [ master ] - - # Allows you to run this workflow manually from the Actions tab - workflow_dispatch: - -# A workflow run is made up of one or more jobs that can run sequentially or in parallel -jobs: - # This workflow contains a single job called "build" - build: - # The type of runner that the job will run on - runs-on: ubuntu-latest - - # Steps represent a sequence of tasks that will be executed as part of the job - steps: - # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 - - - name: Get version - id: get_version - run: | - echo "::set-output name=version::$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md)" - - - name: Set up Python - uses: actions/setup-python@v2 - with: - python-version: '3.7' - - - name: Install dependencies - run: | - pip install -r riscv_ctg/requirements.txt - python -m pip install --upgrade pip - pip install setuptools wheel twine - - - name: Publish package - if: github.ref == 'refs/heads/master' - env: - TWINE_USERNAME: ${{ secrets.PYPIUSERNAME }} - TWINE_PASSWORD: ${{ secrets.PYPIPASSWORD }} - run: | - python setup.py sdist bdist_wheel - twine upload dist/* - - - - name: Extract release notes - id: extract-release-notes - if: github.ref == 'refs/heads/master' - uses: ffurrer2/extract-release-notes@v1 - - - name: Tag - if: github.ref == 'refs/heads/master' - run: | - git tag ${{ steps.get_version.outputs.version }} - git push origin ${{ steps.get_version.outputs.version }} - - - name: Create Release - id: create_release - if: github.ref == 'refs/heads/master' - uses: actions/create-release@v1 - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # This token is provided by Actions, you do not need to create your own token - with: - release_branch: refs/heads/master - release_name: ${{ steps.get_version.outputs.version }} - tag_name: ${{ steps.get_version.outputs.version }} - body: ${{ steps.extract-release-notes.outputs.release_notes }} - draft: false - prerelease: false - - # - name: Script - # uses: ammaraskar/sphinx-action@master - # with: - # docs-folder: "docs/" - # pre-build-command: " apt-get update -y && apt-get install -y latexmk texlive-latex-recommended texlive-latex-extra texlive-fonts-recommended" - # build-command: " make latexpdf " - - - # - name: Upload Release Asset - # id: upload-release-asset - # if: github.ref == 'refs/heads/master' - # uses: actions/upload-release-asset@v1 - # env: - # GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - # with: - # upload_url: ${{ steps.create_release.outputs.upload_url }} # This pulls from the CREATE RELEASE step above, referencing it's ID to get its outputs object, which include a `upload_url`. See this blog post for more info: https://jasonet.co/posts/new-features-of-github-actions/#passing-data-to-future-steps - # asset_path: ./docs/build/latex/riscv_config.pdf - # asset_name: riscv_config.pdf - # asset_content_type: application/pdf - - - diff --git a/.github/workflows/test-1.yml b/.github/workflows/test-1.yml deleted file mode 100644 index f1fe2553..00000000 --- a/.github/workflows/test-1.yml +++ /dev/null @@ -1,111 +0,0 @@ -name: test-1 -on: - pull_request: - branches: - -master - -dev - workflow_dispatch: - -jobs: - build: - runs-on: ubuntu-latest - strategy: - matrix: - cgf_files: ["./sample_cgfs/*.cgf"] - architecture: ["rv32e", "rv32i", "rv64i", "rv32i_64i"] - steps: - - uses: actions/checkout@v2 - - name: Set up Python - uses: actions/setup-python@v2 - with: - python-version: '3.7' - - - name: Install dependencies - run: | - python -m pip install --upgrade pip - pip install -r riscv_ctg/requirements.txt - pip install --editable . - - - - name: Run RISC-V CTG for RV32E - run: | - set -e - for cgf_file in ./sample_cgfs/*.cgf; do - if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then - if [[ "$cgf_file" == *rv32e* ]] && [ "${{matrix.architecture}}" == "rv32e" ] ; then - cmd="riscv_ctg -r -d ./tests -bi rv32e -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" - echo $cmd - eval $cmd || { echo "Error executing command: $cmd"; exit 1; } - fi - fi - done - - - name: Run RISC-V CTG for RV32I - run: | - set -e - for cgf_file in ./sample_cgfs/*.cgf; do - if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then - if [[ "$cgf_file" != *rv32e* ]] && [[ "cgf_file" == *rv32* ]] && [ "${{matrix.architecture}}" == "rv32i" ] ; then - cmd="riscv_ctg -r -d ./tests -bi rv32i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" - echo $cmd - eval $cmd || { echo "Error executing command: $cmd"; exit 1; } - fi - fi - done - - - name: Run RISC-V CTG for RV64I - run: | - set -e - for cgf_file in ./sample_cgfs/*.cgf; do - if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then - if [[ "$cgf_file" == *rv64* ]] && [ "${{matrix.architecture}}" == "rv64i" ] ; then - cmd="riscv_ctg -r -d ./tests -bi rv64i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" - echo $cmd - eval $cmd || { echo "Error executing command: $cmd"; exit 1; } - fi - fi - done - - - name: Run RISC-V CTG for RV64I and RV32I - run: | - set -e - for cgf_file in ./sample_cgfs/*.cgf; do - if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then - if [[ "$cgf_file" != *rv32e* ]] && [[ "$cgf_file" != *rv32* ]] && [[ "$cgf_file" != *rv64* ]] && [ "${{matrix.architecture}}" == "rv32i_64i" ] ; then - for arch in rv32i rv64i; do - cmd="riscv_ctg -r -d ./tests -bi $arch -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)" - echo $cmd - eval $cmd || { echo "Error executing command: $cmd"; exit 1; } - done - fi - fi - done - - check-version: - if: github.ref == 'refs/heads/master' - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v2 - - - name: version check - run: | - export CHNGVER=$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md); - echo "CHANGELOG VERSION: $CHNGVER" - export INITVER=$(grep -P "__version__ = '.*?'" riscv_ctg/__init__.py | awk '{print $3}'|sed "s/'//g"); - echo "INIT VERSION: $INITVER" - if [ "$CHNGVER" = "$INITVER" ]; then - echo "Versions are equal in Changelog and init.py." - else - echo "Versions are not equal in Changelog and init.py." - exit 1 - fi - export TAGVER=${{ steps.get-latest-tag.outputs.tag }}; - echo "TAG VERSION: $TAGVER" - if [ "$CHNGVER" = "$TAGVER" ]; then - echo "No changelog update." - exit 1 - else - echo "Changelog updated." - fi - - \ No newline at end of file From e24cb24b057a8aaf9610b1b5a7c4c46b98b5f664 Mon Sep 17 00:00:00 2001 From: Sowmya3062 Date: Thu, 22 Feb 2024 18:21:28 +0530 Subject: [PATCH 101/101] add main.yml --- .github/workflows/main.yml | 97 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 .github/workflows/main.yml diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml new file mode 100644 index 00000000..b8308b32 --- /dev/null +++ b/.github/workflows/main.yml @@ -0,0 +1,97 @@ +# This is a basic workflow to help you get started with Actions + +name: CI + +# Controls when the action will run. +on: + # Triggers the workflow on push or pull request events but only for the master branch + push: + branches: [ master ] + + # Allows you to run this workflow manually from the Actions tab + workflow_dispatch: + +# A workflow run is made up of one or more jobs that can run sequentially or in parallel +jobs: + # This workflow contains a single job called "build" + build: + # The type of runner that the job will run on + runs-on: ubuntu-latest + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v2 + + - name: Get version + id: get_version + run: | + echo "::set-output name=version::$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md)" + + - name: Set up Python + uses: actions/setup-python@v2 + with: + python-version: '3.7' + + - name: Install dependencies + run: | + pip install -r riscv_ctg/requirements.txt + python -m pip install --upgrade pip + pip install setuptools wheel twine + + - name: Publish package + if: github.ref == 'refs/heads/master' + env: + TWINE_USERNAME: ${{ secrets.PYPIUSERNAME }} + TWINE_PASSWORD: ${{ secrets.PYPIPASSWORD }} + run: | + python setup.py sdist bdist_wheel + twine upload dist/* + + + - name: Extract release notes + id: extract-release-notes + if: github.ref == 'refs/heads/master' + uses: ffurrer2/extract-release-notes@v1 + + - name: Tag + if: github.ref == 'refs/heads/master' + run: | + git tag ${{ steps.get_version.outputs.version }} + git push origin ${{ steps.get_version.outputs.version }} + + - name: Create Release + id: create_release + if: github.ref == 'refs/heads/master' + uses: actions/create-release@v1 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # This token is provided by Actions, you do not need to create your own token + with: + release_branch: refs/heads/master + release_name: ${{ steps.get_version.outputs.version }} + tag_name: ${{ steps.get_version.outputs.version }} + body: ${{ steps.extract-release-notes.outputs.release_notes }} + draft: false + prerelease: false + + # - name: Script + # uses: ammaraskar/sphinx-action@master + # with: + # docs-folder: "docs/" + # pre-build-command: " apt-get update -y && apt-get install -y latexmk texlive-latex-recommended texlive-latex-extra texlive-fonts-recommended" + # build-command: " make latexpdf " + + + # - name: Upload Release Asset + # id: upload-release-asset + # if: github.ref == 'refs/heads/master' + # uses: actions/upload-release-asset@v1 + # env: + # GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + # with: + # upload_url: ${{ steps.create_release.outputs.upload_url }} # This pulls from the CREATE RELEASE step above, referencing it's ID to get its outputs object, which include a `upload_url`. See this blog post for more info: https://jasonet.co/posts/new-features-of-github-actions/#passing-data-to-future-steps + # asset_path: ./docs/build/latex/riscv_config.pdf + # asset_name: riscv_config.pdf + # asset_content_type: application/pdf + +