From cf29462e467f70964bfae11320df0f3160759b93 Mon Sep 17 00:00:00 2001
From: Nelson Chu <nelson@rivosinc.com>
Date: Fri, 21 Jul 2023 08:24:32 +0800
Subject: [PATCH] Refer mapping symbol into R_RISCV_RELAX for rvc/norvc
 relaxations.

---
 riscv-elf.adoc | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/riscv-elf.adoc b/riscv-elf.adoc
index 9e341acb..6ab2eaa8 100644
--- a/riscv-elf.adoc
+++ b/riscv-elf.adoc
@@ -201,6 +201,7 @@ below.
 
 +
 --
+[[EF_RISCV_RVC]]
   EF_RISCV_RVC (0x0001)::: This bit is set when the binary targets the C ABI,
   which allows instructions to be aligned to 16-bit boundaries (the base RV32
   and RV64 ISAs only allow 32-bit instruction alignment).  When linking
@@ -1622,6 +1623,37 @@ instructions. It is recommended to initialize `jvt` CSR immediately after
     csrw  jvt, a0
 ----
 
+=== Compressed and Non-compressed Relaxations in the Same Object
+
+Linker used to enables and disables the compressed relaxations by checking the
+[[EF_RISCV_RVC]] of each intput object. Since [[EF_RISCV_RVC]] is an
+object-level tag, it cannot handle the case that if `.option arch, +c` and
+`.option arch, -c` are in the same object. Therefore, encode the mapping symbols
+into each R_RISCV_RELAX can resolve the problem.
+
+  Example::
++
+--
+Relaxation candidate:
+[,asm]
+----
+    .option arch, rv32i
+    auipc ra, 0          # R_RISCV_CALL_PLT (symbol), R_RISCV_RELAX ($xrv32i)
+    jalr  ra, ra, 0
+
+    .option arch, +c
+    auipc ra, 0          # R_RISCV_CALL_PLT (symbol), R_RISCV_RELAX ($xrv32ic)
+    jalr  ra, ra, 0
+----
+Relaxation result:
+[,asm]
+----
+    jal    ra, 0         # R_RISCV_JAL (symbol)
+
+    c.jal  ra, <offset-between-pc-and-symbol>
+----
+--
+
 [bibliography]
 == References