From a9b8c6ccceac5778ba8751643a2db5f94156cb9c Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Tue, 17 Sep 2024 18:53:39 +0500 Subject: [PATCH] Added Covergroups and updated tests --- coverage/pmm.cgf | 640 ++++++++++++++++++ .../pmm_atomics/PMM_atomic_01_S_sv48_tag00.S | 2 +- .../pmm_atomics/PMM_atomic_01_S_sv48_tag01.S | 2 +- .../pmm_atomics/PMM_atomic_01_S_sv48_tag10.S | 2 +- .../pmm_atomics/PMM_atomic_01_S_sv48_tag11.S | 2 +- .../pmm_atomics/PMM_atomic_01_U_sv48_tag00.S | 2 +- .../pmm_atomics/PMM_atomic_01_U_sv48_tag01.S | 4 +- .../pmm_atomics/PMM_atomic_01_U_sv48_tag10.S | 2 +- .../pmm_atomics/PMM_atomic_01_U_sv48_tag11.S | 2 +- .../pmm/pmm_basic/PMM_basic_01_S_sv48_tag00.S | 52 +- .../pmm/pmm_basic/PMM_basic_01_S_sv48_tag01.S | 49 +- .../pmm/pmm_basic/PMM_basic_01_S_sv48_tag10.S | 50 +- .../pmm/pmm_basic/PMM_basic_01_S_sv48_tag11.S | 50 +- .../pmm/pmm_basic/PMM_basic_01_U_sv48_tag00.S | 50 +- .../pmm/pmm_basic/PMM_basic_01_U_sv48_tag01.S | 52 +- .../pmm/pmm_basic/PMM_basic_01_U_sv48_tag10.S | 50 +- .../pmm/pmm_basic/PMM_basic_01_U_sv48_tag11.S | 50 +- .../PMM_compressed_01_S_sv48_tag00.S | 44 +- .../PMM_compressed_01_S_sv48_tag01.S | 44 +- .../PMM_compressed_01_S_sv48_tag10.S | 44 +- .../PMM_compressed_01_S_sv48_tag11.S | 44 +- .../PMM_compressed_01_U_sv48_tag00.S | 44 +- .../PMM_compressed_01_U_sv48_tag01.S | 46 +- .../PMM_compressed_01_U_sv48_tag10.S | 44 +- .../PMM_compressed_01_U_sv48_tag11.S | 44 +- .../pmm/pmm_float/PMM_float_01_S_sv48_tag00.S | 13 +- .../pmm/pmm_float/PMM_float_01_S_sv48_tag01.S | 13 +- .../pmm/pmm_float/PMM_float_01_S_sv48_tag10.S | 12 +- .../pmm/pmm_float/PMM_float_01_S_sv48_tag11.S | 12 +- .../pmm/pmm_float/PMM_float_01_U_sv48_tag00.S | 13 +- .../pmm/pmm_float/PMM_float_01_U_sv48_tag01.S | 14 +- .../pmm/pmm_float/PMM_float_01_U_sv48_tag10.S | 12 +- .../pmm/pmm_float/PMM_float_01_U_sv48_tag11.S | 12 +- 33 files changed, 1230 insertions(+), 286 deletions(-) create mode 100644 coverage/pmm.cgf diff --git a/coverage/pmm.cgf b/coverage/pmm.cgf new file mode 100644 index 000000000..0e7d9bc9f --- /dev/null +++ b/coverage/pmm.cgf @@ -0,0 +1,640 @@ +#Test Case 1 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_atomic_S_mode_SV48_tag00: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lr.w, sc.w, lr.d, sc.d}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + +#Test Case 2 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_atomic_S_mode_SV48_tag01: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lr.w, sc.w, lr.d, sc.d}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lr.w', 'lr.d', 'sc.w', 'sc.d'} and mcause == {0xd, 0xf}{[$1/2]}": 0 + +#Test Case 3 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_atomic_S_mode_SV48_tag02: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lr.w, sc.w, lr.d, sc.d}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lr.w', 'lr.d', 'sc.w', 'sc.d'} and mcause == {0xd, 0xf}{[$1/2]}": 0 + +#Test Case 4 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_atomic_S_mode_SV48_tag03: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lr.w, sc.w, lr.d, sc.d}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + +#Test Case 1 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_atomic_U_mode_SV48_tag00: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lr.w, sc.w, lr.d, sc.d}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + +#Test Case 2 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_atomic_U_mode_SV48_tag01: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lr.w, sc.w, lr.d, sc.d}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lr.w', 'lr.d', 'sc.w', 'sc.d'} and mcause == {0xd, 0xf}{[$1/2]}": 0 + +#Test Case 3 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_atomic_U_mode_SV48_tag02: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lr.w, sc.w, lr.d, sc.d}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lr.w', 'lr.d', 'sc.w', 'sc.d'} and mcause == {0xd, 0xf}{[$1/2]}": 0 + +#Test Case 4 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_atomic_U_mode_SV48_tag03: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lr.w, sc.w, lr.d, sc.d}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lr.w', 'sc.w', 'lr.d', 'sc.d'} and (len_dptw == 1)": 0 + +#Test Case 1 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_basic_S_mode_SV48_tag00: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lb, lh, lw, sb, sh, sw}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + +#Test Case 2 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_basic_S_mode_SV48_tag01: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lb, lh, lw, sb, sh, sw}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and mcause == {0xd, 0xf}{[$1/3]}": 0 + +#Test Case 3 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_basic_S_mode_SV48_tag02: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lb, lh, lw, sb, sh, sw}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and mcause == {0xd, 0xf}{[$1/3]}": 0 + +#Test Case 4 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_basic_S_mode_SV48_tag03: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lb, lh, lw, sb, sh, sw}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + +#Test Case 1 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_basic_U_mode_SV48_tag00: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lb, lh, lw, sb, sh, sw}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + +#Test Case 2 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_basic_U_mode_SV48_tag01: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lb, lh, lw, sb, sh, sw}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and mcause == {0xd, 0xf}{[$1/3]}": 0 + +#Test Case 3 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_basic_U_mode_SV48_tag02: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lb, lh, lw, sb, sh, sw}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and mcause == {0xd, 0xf}{[$1/3]}": 0 + +#Test Case 4 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_basic_U_mode_SV48_tag03: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, lb, lh, lw, sb, sh, sw}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'lb', 'lh', 'lw', 'sb', 'sh', 'sw'} and (len_dptw == 1)": 0 + +#Test Case 1 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_compressed_S_mode_SV48_tag00: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, c.lw, c.sw, c.ld, c.sd, c.lwsp, c.swsp, c.ldsp, c.sdsp}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + +#Test Case 2 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_compressed_S_mode_SV48_tag01: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, c.lw, c.sw, c.ld, c.sd, c.lwsp, c.swsp, c.ldsp, c.sdsp}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and mcause == {0xd, 0xf}{[$1/4]}": 0 + +#Test Case 3 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_compressed_S_mode_SV48_tag02: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, c.lw, c.sw, c.ld, c.sd, c.lwsp, c.swsp, c.ldsp, c.sdsp}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and mcause == {0xd, 0xf}{[$1/4]}": 0 + +#Test Case 4 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_compressed_S_mode_SV48_tag03: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, c.lw, c.sw, c.ld, c.sd, c.lwsp, c.swsp, c.ldsp, c.sdsp}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + +#Test Case 1 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_compressed_U_mode_SV48_tag00: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, c.lw, c.sw, c.ld, c.sd, c.lwsp, c.swsp, c.ldsp, c.sdsp}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + +#Test Case 2 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_compressed_U_mode_SV48_tag01: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, c.lw, c.sw, c.ld, c.sd, c.lwsp, c.swsp, c.ldsp, c.sdsp}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and mcause == {0xd, 0xf}{[$1/4]}": 0 + +#Test Case 3 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_compressed_U_mode_SV48_tag02: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, c.lw, c.sw, c.ld, c.sd, c.lwsp, c.swsp, c.ldsp, c.sdsp}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and mcause == {0xd, 0xf}{[$1/4]}": 0 + +#Test Case 4 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_compressed_U_mode_SV48_tag03: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, c.lw, c.sw, c.ld, c.sd, c.lwsp, c.swsp, c.ldsp, c.sdsp}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'c.lw', 'c.ld', 'c.lwsp', 'c.ldsp', 'c.sw', 'c.sd', 'c.swsp', 'c.sdsp'} and (len_dptw == 1)": 0 + +#Test Case 1 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_float_S_mode_SV48_tag00: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, flw, fsw, fld, fsd}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + +#Test Case 2 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_float_S_mode_SV48_tag01: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, flw, fsw, fld, fsd}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and mcause == {0xd, 0xf}{[$1/2]}": 0 + +#Test Case 3 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_float_S_mode_SV48_tag02: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, flw, fsw, fld, fsd}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and mcause == {0xd, 0xf}{[$1/2]}": 0 + +#Test Case 4 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_float_S_mode_SV48_tag03: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, flw, fsw, fld, fsd}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'S' and ((menvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + +#Test Case 1 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_float_U_mode_SV48_tag00: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, flw, fsw, fld, fsd}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + +#Test Case 2 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_float_U_mode_SV48_tag01: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, flw, fsw, fld, fsd}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and mcause == {0xd, 0xf}{[$1/2]}": 0 + +#Test Case 3 +#Pointer Masking Disabled -> Page faults +#Pointer Masking Enabled -> No fault +pm_float_U_mode_SV48_tag02: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, flw, fsw, fld, fsd}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was expected page faults + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and mcause == {0xd, 0xf}{[$1/2]}": 0 + +#Test Case 4 +#Pointer Masking Disabled -> No fault +#Pointer Masking Enabled -> No fault +pm_float_U_mode_SV48_tag03: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + #LR/SC instructions for atomic + "{csrrw, flw, fsw, fld, fsd}": 0 + csr_comb: + #check whether the Pointer Masking is enabled for SV-48 + "((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48})": 0 + val_comb: + #Enabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_SV48}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + #Disabled Pointer Masking + #Verify that there was no fault by confirming there is atleast a page table walk of length 1 + "mode == 'U' and ((senvcfg & ${PMM_MASK}) == ${PMM_MASK_DISABLED}) and mnemonic == {'flw', 'fld', 'fsw', 'fsd'} and (len_dptw == 1)": 0 + diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag00.S b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag00.S index 722574111..009e577a5 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag00.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag00.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV48_tag00) RVTEST_SIGBASE( x13,signature_x13_1) diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag01.S b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag01.S index 6785578e2..380d444b5 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag01.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag01.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV48_tag01) RVTEST_SIGBASE( x13,signature_x13_1) diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag10.S b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag10.S index f64963385..09d7aa2e3 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag10.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag10.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV48_tag02) RVTEST_SIGBASE( x13,signature_x13_1) diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag11.S b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag11.S index b960d34e2..4d28e5d74 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag11.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag11.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV48_tag03) RVTEST_SIGBASE( x13,signature_x13_1) diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag00.S b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag00.S index 819ea19b8..03b3888db 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag00.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag00.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_U_mode_SV48_tag00) RVTEST_SIGBASE( x13,signature_x13_1) diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag01.S b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag01.S index a5f2feada..e8141a6d0 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag01.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag01.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_U_mode_SV48_tag01) RVTEST_SIGBASE( x13,signature_x13_1) @@ -117,7 +117,7 @@ satp_setup: # -------------------- Enter and Exit M Mode ---------------------------------- - RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode + RVTEST_GOTO_LOWER_MODE Umode // Go back to Supervisor mode # -------------------- Test PMM (Pointer Masking) without Masking -------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag10.S b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag10.S index 3d271bdff..b59d5b5ab 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag10.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag10.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_U_mode_SV48_tag02) RVTEST_SIGBASE( x13,signature_x13_1) diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag11.S b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag11.S index 9bb4a2ed2..49ddc882f 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag11.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag11.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_U_mode_SV48_tag03) RVTEST_SIGBASE( x13,signature_x13_1) diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag00.S b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag00.S index 67108e98b..7da57850d 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag00.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag00.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_S_mode_SV48_tag00) RVTEST_SIGBASE( x13,signature_x13_1) @@ -36,7 +36,7 @@ main: # --------------------------- Define Addresses ------------------------------- .set pa_rvtest_code_begin, 0x8000000000039c // 56-bit physical address of the code section .set pa_rvtest_data_begin, 0x80000000003530 // 56-bit physical address of the data section - .set pa_rvtest_sig_begin, 0x80000000006218 // 56-bit physical address of the signature section + .set pa_rvtest_sig_begin, 0x80000000006218 // 56-bit physical address of the signature section .set va_rvtest_code_begin, 0xFFFF80000000039c // 48-bit virtual address of the code section .set va_rvtest_data_begin, 0x0000500000000000 // 48-bit virtual address of the data section .set va_rvtest_sig_begin, 0x0000500000006218 // 48-bit virtual address of the signature section @@ -124,30 +124,28 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode @@ -167,30 +165,28 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag01.S b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag01.S index 216ea9747..919c6074b 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag01.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag01.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_S_mode_SV48_tag01) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,29 +124,28 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access + nop + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) nop - # -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode @@ -167,30 +166,28 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag10.S b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag10.S index 43d597be0..3558545b4 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag10.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag10.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_S_mode_SV48_tag02) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,30 +124,28 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode @@ -167,30 +165,28 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag11.S b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag11.S index 036f0504c..e7eb7b3bc 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag11.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag11.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_S_mode_SV48_tag03) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,30 +124,28 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode @@ -167,30 +165,28 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag00.S b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag00.S index 45e90efea..8691b4ee5 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag00.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag00.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_U_mode_SV48_tag00) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,30 +124,28 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode @@ -168,30 +166,28 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag01.S b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag01.S index 741b6d6c0..2d7d37387 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag01.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag01.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_U_mode_SV48_tag01) RVTEST_SIGBASE( x13,signature_x13_1) @@ -117,37 +117,35 @@ satp_setup: # -------------------- Enter and Exit M Mode ---------------------------------- - RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode + RVTEST_GOTO_LOWER_MODE Umode // Go back to Supervisor mode # -------------------- Test PMM (Pointer Masking) without Masking -------------- vm_en: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode @@ -167,30 +165,28 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag10.S b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag10.S index 4e30e6843..e38d66978 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag10.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag10.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_U_mode_SV48_tag02) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,30 +124,28 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode @@ -167,30 +165,28 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag11.S b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag11.S index e486d9e9c..87fc2d090 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag11.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_U_sv48_tag11.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_U_mode_SV48_tag03) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,30 +124,28 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode @@ -167,30 +165,28 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - LREG x9, 0(x8) // test the load access - nop - SREG x9, 0(x8) // test the store access - nop lb x9, 0(x8) // test the load access nop - sb x9, 0(x8) // test the store access - nop lh x9, 0(x8) // test the load access nop - sh x9, 0(x8) // test the store access + lw x9, 0(x8) // test the load access nop ld x9, 0(x8) // test the load access nop - sd x9, 0(x8) // test the store access + sb x9, 0(x8) // test the store access nop - lbu x9, 0(x8) // test the load access + sh x9, 0(x8) // test the store access nop - lhu x9, 0(x8) // test the load access + sw x9, 0(x8) // test the store access nop - lwu x9, 0(x8) + sd x9, 0(x8) // test the store access nop - -# -------------------- Disable Virtualization --------------------------------- + # lbu x9, 0(x8) // test the load access + # nop + # lhu x9, 0(x8) // test the load access + # nop + # lwu x9, 0(x8) + nop# -------------------- Disable Virtualization --------------------------------- RVTEST_GOTO_MMODE // Switch back to Machine mode diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag00.S b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag00.S index daa3433b0..9c4aef8fd 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag00.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag00.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_compressed_S_mode_SV48_tag00) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,22 +124,39 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- @@ -161,22 +178,39 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag01.S b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag01.S index 845b2af2e..d4cd97a38 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag01.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag01.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_compressed_S_mode_SV48_tag01) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,22 +124,39 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- @@ -161,22 +178,39 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag10.S b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag10.S index 93f050053..0723f28a8 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag10.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag10.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_compressed_S_mode_SV48_tag02) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,22 +124,39 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- @@ -161,22 +178,39 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag11.S b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag11.S index b8f7d10ac..8c3769160 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag11.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_S_sv48_tag11.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_compressed_S_mode_SV48_tag03) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,22 +124,39 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- @@ -161,22 +178,39 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag00.S b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag00.S index 518b7ce64..3b33ba11a 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag00.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag00.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_compressed_U_mode_SV48_tag00) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,22 +124,39 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- @@ -162,22 +179,39 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag01.S b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag01.S index 9e5249b3a..b664308bd 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag01.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag01.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_compressed_U_mode_SV48_tag01) RVTEST_SIGBASE( x13,signature_x13_1) @@ -117,29 +117,46 @@ satp_setup: # -------------------- Enter and Exit M Mode ---------------------------------- - RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode + RVTEST_GOTO_LOWER_MODE Umode // Go back to Supervisor mode # -------------------- Test PMM (Pointer Masking) without Masking -------------- vm_en: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- @@ -161,22 +178,39 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag10.S b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag10.S index a7f2ee023..e7651d926 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag10.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag10.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_compressed_U_mode_SV48_tag02) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,22 +124,39 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- @@ -161,22 +178,39 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag11.S b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag11.S index c9c507a01..b0820cd15 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag11.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_compressed/PMM_compressed_01_U_sv48_tag11.S @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*C.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_compressed_U_mode_SV48_tag03) RVTEST_SIGBASE( x13,signature_x13_1) @@ -124,22 +124,39 @@ satp_setup: vm_en: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- @@ -161,22 +178,39 @@ vm_en: vm_en_with_pointer_masking: LI (x8, va_rvtest_data_begin) nop - c.lw x9, 0(x8) // test the load access + c.lw x9, 0(x8) // test the load access + nop nop c.sw x9, 0(x8) // test the store access nop + nop + nop c.ld x9, 0(x8) // test the load access + nop + nop nop c.sd x9, 0(x8) // test the store access nop + nop + nop + LI (x2, va_rvtest_data_begin) + nop c.lwsp x9, 0(x2) // test the load access + nop + nop nop c.swsp x9, 0(x2) // test the store access nop + nop + nop c.ldsp x9, 0(x2) // test the load access + nop + nop nop c.sdsp x9, 0(x2) // test the store access - nop + nop + nop + nop # -------------------- Disable Virtualization --------------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag00.S b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag00.S index fa9e76681..ee0dedf24 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag00.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag00.S @@ -11,7 +11,7 @@ due to the invalid Virtual Address, #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IF_Zicsr") +RVTEST_ISA("RV64IFD_Zicsr") # Test code region .section .text.init @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_float_S_mode_SV48_tag00) RVTEST_SIGBASE( x13,signature_x13_1) @@ -116,7 +116,10 @@ satp_setup: SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode # -------------------- Enter and Exit M Mode ---------------------------------- - + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode # -------------------- Test PMM (Pointer Masking) without Masking -------------- @@ -146,6 +149,10 @@ vm_en: sfence.vma // Flush the TLB SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode # -------------------- Test PMM with Masking Enabled -------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag01.S b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag01.S index 74c5b91b0..c1c722ded 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag01.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag01.S @@ -11,7 +11,7 @@ due to the invalid Virtual Address, #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IF_Zicsr") +RVTEST_ISA("RV64IFD_Zicsr") # Test code region .section .text.init @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_float_S_mode_SV48_tag01) RVTEST_SIGBASE( x13,signature_x13_1) @@ -117,6 +117,11 @@ satp_setup: # -------------------- Enter and Exit M Mode ---------------------------------- + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register + RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode # -------------------- Test PMM (Pointer Masking) without Masking -------------- @@ -146,6 +151,10 @@ vm_en: sfence.vma // Flush the TLB SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode # -------------------- Test PMM with Masking Enabled -------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag10.S b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag10.S index bc03f829d..6f34ac1da 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag10.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag10.S @@ -11,7 +11,7 @@ due to the invalid Virtual Address, #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IF_Zicsr") +RVTEST_ISA("RV64IFD_Zicsr") # Test code region .section .text.init @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_float_S_mode_SV48_tag02) RVTEST_SIGBASE( x13,signature_x13_1) @@ -116,6 +116,10 @@ satp_setup: SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode # -------------------- Enter and Exit M Mode ---------------------------------- + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode @@ -146,6 +150,10 @@ vm_en: sfence.vma // Flush the TLB SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode # -------------------- Test PMM with Masking Enabled -------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag11.S b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag11.S index 4682815ae..b47f97e72 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag11.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_S_sv48_tag11.S @@ -11,7 +11,7 @@ due to the invalid Virtual Address, #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IF_Zicsr") +RVTEST_ISA("RV64IFD_Zicsr") # Test code region .section .text.init @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_float_S_mode_SV48_tag03) RVTEST_SIGBASE( x13,signature_x13_1) @@ -116,6 +116,10 @@ satp_setup: SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode # -------------------- Enter and Exit M Mode ---------------------------------- + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode @@ -146,6 +150,10 @@ vm_en: sfence.vma // Flush the TLB SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode # -------------------- Test PMM with Masking Enabled -------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag00.S b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag00.S index 3cac7bc1c..ad784cd38 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag00.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag00.S @@ -11,7 +11,7 @@ due to the invalid Virtual Address, #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IF_Zicsr") +RVTEST_ISA("RV64IFD_Zicsr") # Test code region .section .text.init @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_float_U_mode_SV48_tag00) RVTEST_SIGBASE( x13,signature_x13_1) @@ -116,6 +116,10 @@ satp_setup: SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode # -------------------- Enter and Exit M Mode ---------------------------------- + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Umode // Go back to User mode @@ -146,7 +150,10 @@ vm_en: sfence.vma // Flush the TLB SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode - + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Umode // Go back to User mode # -------------------- Test PMM with Masking Enabled -------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag01.S b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag01.S index ee101188a..cdf1c059a 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag01.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag01.S @@ -11,7 +11,7 @@ due to the invalid Virtual Address, #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IF_Zicsr") +RVTEST_ISA("RV64IFD_Zicsr") # Test code region .section .text.init @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_float_U_mode_SV48_tag01) RVTEST_SIGBASE( x13,signature_x13_1) @@ -116,8 +116,12 @@ satp_setup: SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode # -------------------- Enter and Exit M Mode ---------------------------------- + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register - RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode + RVTEST_GOTO_LOWER_MODE Umode // Go back to Supervisor mode # -------------------- Test PMM (Pointer Masking) without Masking -------------- @@ -146,6 +150,10 @@ vm_en: sfence.vma // Flush the TLB SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Umode // Go back to User mode # -------------------- Test PMM with Masking Enabled -------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag10.S b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag10.S index f50433b01..7e94d4203 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag10.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag10.S @@ -11,7 +11,7 @@ due to the invalid Virtual Address, #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IF_Zicsr") +RVTEST_ISA("RV64IFD_Zicsr") # Test code region .section .text.init @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_float_U_mode_SV48_tag02) RVTEST_SIGBASE( x13,signature_x13_1) @@ -116,6 +116,10 @@ satp_setup: SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode # -------------------- Enter and Exit M Mode ---------------------------------- + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Umode // Go back to User mode @@ -146,6 +150,10 @@ vm_en: sfence.vma // Flush the TLB SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Umode // Go back to User mode # -------------------- Test PMM with Masking Enabled -------------------------- diff --git a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag11.S b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag11.S index f613af4cb..994c5e55d 100644 --- a/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag11.S +++ b/riscv-test-suite/rv64i_m/pmm/pmm_float/PMM_float_01_U_sv48_tag11.S @@ -11,7 +11,7 @@ due to the invalid Virtual Address, #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IF_Zicsr") +RVTEST_ISA("RV64IFD_Zicsr") # Test code region .section .text.init @@ -21,7 +21,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*F.*D.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_float_U_mode_SV48_tag03) RVTEST_SIGBASE( x13,signature_x13_1) @@ -116,6 +116,10 @@ satp_setup: SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode # -------------------- Enter and Exit M Mode ---------------------------------- + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Umode // Go back to User mode @@ -146,6 +150,10 @@ vm_en: sfence.vma // Flush the TLB SATP_SETUP_RV64(sv48) // Set SATP for SV48 mode + csrr t0, mstatus # Read the mstatus register into temporary register t0 + li t1, 0x00006000 # Load the FS field value to enable the FPU (set FS = 11) + or t0, t0, t1 # Set the FS field in mstatus + csrw mstatus, t0 # Write the modified value back to the mstatus register RVTEST_GOTO_LOWER_MODE Umode // Go back to User mode # -------------------- Test PMM with Masking Enabled --------------------------