From 62aea4662fc98a6c91fb7c2847159142a1561412 Mon Sep 17 00:00:00 2001
From: MingZhu Yan <yanmingzhu@iscas.ac.cn>
Date: Thu, 24 Oct 2024 10:02:48 +0800
Subject: [PATCH] Keep using some `import *` and variables in ctg and isca to
 support `eval()` working correctly

Signed-off-by: MingZhu Yan <yanmingzhu@iscas.ac.cn>
---
 riscv-ctg/riscv_ctg/constants.py       | 1 +
 riscv-ctg/riscv_ctg/generator.py       | 6 ++++--
 riscv-isac/riscv_isac/cgf_normalize.py | 2 ++
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/riscv-ctg/riscv_ctg/constants.py b/riscv-ctg/riscv_ctg/constants.py
index 72eb07255..bb8e3a996 100644
--- a/riscv-ctg/riscv_ctg/constants.py
+++ b/riscv-ctg/riscv_ctg/constants.py
@@ -2,6 +2,7 @@
 
 import os
 from math import sqrt
+from math import *  # noqa: F403
 from string import Template
 
 root = os.path.abspath(os.path.dirname(__file__))
diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py
index e813fc586..95c5eed0e 100644
--- a/riscv-ctg/riscv_ctg/generator.py
+++ b/riscv-ctg/riscv_ctg/generator.py
@@ -4,9 +4,11 @@
 from constraint import Problem, MinConflictsSolver, AllDifferentConstraint
 import re
 from riscv_ctg.constants import twos, e_regset, signode_template, case_template, part_template, test_template, default_regset
+from riscv_ctg.constants import *  # noqa: F403
 from riscv_ctg.log import logger
 from riscv_ctg.helpers import nan_box, sgn_extd, merge_fields_f, ExtractException
 from riscv_ctg.dsp_function import gen_pair_reg_data, concat_simd_data
+from riscv_ctg.dsp_function import *  # noqa: F403
 from riscv_isac.InstructionObject import instructionObject
 import struct
 import sys
@@ -1010,7 +1012,7 @@ def valreg(self,instr_dict):
             else:
                 FLEN = 0
             XLEN = max(self.opnode['xlen'])
-            _SIGALIGN = max(XLEN,FLEN)/8
+            SIGALIGN = max(XLEN,FLEN)/8  # noqa: F841
             stride_sz = eval(suffix)
             template = Template(eval(self.opnode['val']['val_template']))
             width = self.iflen if self.is_fext else self.flen
@@ -1135,7 +1137,7 @@ def swreg(self, instr_dict):
         else:
             FLEN = 0
         XLEN = max(self.opnode['xlen'])
-        _SIGALIGN = max(XLEN,FLEN)/8
+        SIGALIGN = max(XLEN,FLEN)/8  # noqa: F841
         stride_sz = eval(suffix)
         for instr in instr_dict:
             if 'rs1' in instr and instr['rs1'] in available_reg:
diff --git a/riscv-isac/riscv_isac/cgf_normalize.py b/riscv-isac/riscv_isac/cgf_normalize.py
index 16f9a0428..11ac08941 100644
--- a/riscv-isac/riscv_isac/cgf_normalize.py
+++ b/riscv-isac/riscv_isac/cgf_normalize.py
@@ -1,9 +1,11 @@
 # See LICENSE.incore for details
 from math import ceil, sqrt
+from math import *  # noqa: F403
 import riscv_isac.utils as utils
 import itertools
 import random
 from riscv_isac.fp_dataset import logger
+from riscv_isac.fp_dataset import *  # noqa: F403
 
 
 def twos(val,bits):