From 5e8a42c5b7ab49531bb949c04af95ae4febd820d Mon Sep 17 00:00:00 2001 From: umershahidengr Date: Fri, 27 Oct 2023 17:00:34 +0500 Subject: [PATCH] Updated PMP Tests --- .../rv32i_m/privilege/pmp32/PMP-CFG-reg.S | 25 +- .../rv32i_m/privilege/pmp32/PMP-CSR-access.S | 11 +- .../rv32i_m/privilege/pmp32/PMP-NAPOT-RX.S | 2 +- .../rv32i_m/privilege/pmp32/PMP-granularity.S | 25 +- .../rv32i_m/privilege/pmp32/pmp-NA4-R.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-NA4-RW.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-NA4-RWX.S | 38 ++- .../rv32i_m/privilege/pmp32/pmp-NA4-RX.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-NA4-X.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-NAPOT-R.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-NAPOT-RW.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-NAPOT-RWX.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-NAPOT-RX.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-NAPOT-X.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-na4-RWX.S | 259 ------------------ .../rv32i_m/privilege/pmp32/pmp-na4-RX.S | 259 ------------------ .../rv32i_m/privilege/pmp32/pmp-tor-R.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-tor-RW.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-tor-RWX.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-tor-RX.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-tor-X.S | 2 +- .../rv32i_m/privilege/pmp32/pmp-tor-overlap.S | 2 +- 22 files changed, 57 insertions(+), 592 deletions(-) delete mode 100644 riscv-test-suite/rv32i_m/privilege/pmp32/pmp-na4-RWX.S delete mode 100644 riscv-test-suite/rv32i_m/privilege/pmp32/pmp-na4-RX.S diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-CFG-reg.S b/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-CFG-reg.S index 2cbd4a3c8..e13fa9e1b 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-CFG-reg.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-CFG-reg.S @@ -27,7 +27,7 @@ */ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point @@ -43,7 +43,6 @@ RVTEST_SIGBASE( x3,signature_x3_1) .attribute stack_align, 16 .align 2 .option norvc -//#define OFFSET 4 // In case of RV32 #define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) #define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) main: @@ -54,19 +53,18 @@ main: // Loop to SET ALL pmpcfg REGs to zero .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value) .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg .endr // END OF LOOP BODY // Loop to SET ALL pmpaddr REGs to zero .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value) .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg .endr // END OF LOOP BODY //////////////////// Locked bit TEST 1 ///////////////////////////////////////////// .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .set OFFSET, 0 .rept 4 // START OF LOOP csrw pmpcfgi, a5 // WRITE pmpcfgi with ALL 1s, Locked the lock-bit [7,15,23,31] nop // Added nop in case of trap @@ -74,18 +72,15 @@ main: // THIS READ WILL ALSO CONFIRM THE ZERO BITs OF PMPCFGi REG. // BIT 5-6, BIT 13-14, BIT 21-22, BIT 29-30 must be hardwired to zero // Verify that LOCKED bits are HIGH, and ZERO bits are zero - RVTEST_SIGUPD(x3,a4, OFFSET) - .set OFFSET, OFFSET+REGWIDTH // Added offset in x9 + RVTEST_SIGUPD(x3,a4) // TRY TO WRITE CFG REGISTER AGAIN (TRAP in case of LOCKED bit is HIGH) csrw pmpcfgi, x5 // WRITE pmpcfgi with some other values nop // Added nop in case of trap csrr a4, pmpcfgi // READ pmpcfgi // Since Locked bit is high, so this should return the old value!!! - RVTEST_SIGUPD(x3,a4,OFFSET) - .set OFFSET, OFFSET+REGWIDTH // Added offset in x9 + RVTEST_SIGUPD(x3,a4) - - .set pmpaddri, pmpcfgi+(PMPADDR0-PMPCFG0)+(pmpcfgi-PMPCFG0) + .set pmpaddri, PMPADDR0+4*(pmpcfgi-PMPCFG0) // Initialize an iterating variable with the address of pmpaddr0 in 1st iteration (when pmpcfgi=pmpcfg0) // Initialize an iterating variable with the address of pmpaddr4 in 2nd iteration (when pmpcfgi=pmpcfg1) // Initialize an iterating variable with the address of pmpaddr8 in 3rd iteration (when pmpcfgi=pmpcfg2) @@ -97,19 +92,15 @@ main: nop // Added nop in case of trap csrr a4, pmpaddri // READ pmpaddr0, value should not have been changed nop // Added nop in case of trap - RVTEST_SIGUPD(x3,a4, OFFSET) - .set OFFSET, OFFSET+REGWIDTH // Added offset in x9 + RVTEST_SIGUPD(x3,a4) .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg .endr // END OF INNER LOOP BODY .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg .endr // END OF OUTER LOOP BODY - #endif - # --------------------------------------------------------------------------------------------- # HALT - RVTEST_CODE_END RVMODEL_HALT @@ -152,4 +143,4 @@ gpr_save: sig_end_canary: CANARY; rvtest_sig_end: -RVMODEL_DATA_END \ No newline at end of file +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-CSR-access.S b/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-CSR-access.S index 441a158b4..883ebdfde 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-CSR-access.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-CSR-access.S @@ -17,7 +17,7 @@ #define rvtest_strap_routine #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point @@ -41,13 +41,13 @@ main: // Loop to SET ALL pmpcfg REGs to zero .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value) .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg .endr // END OF LOOP BODY // Loop to SET ALL pmpaddr REGs to zero .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value) .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg .endr // END OF LOOP BODY //////////////// VERIFICATION ///////////////////////////////////////// @@ -104,7 +104,6 @@ main: nop // Added nop in case of trap /////////////////// Switch back to M-mode //////////////////////////////////////////// RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode nop // Added nop in case of trap RVTEST_SIGUPD(x13,a4) @@ -127,11 +126,11 @@ main: /////////////////// TEST 01 //////////////////////////////////////////// // WRITING pmpaddr registers ////////////////////////////////////////// // Write in M-mode will be valid, Write in other modes will cause trap - csrw pmpaddr8, x2 // Write pmpaddr8 in u mode (TRAP) + csrw pmpaddr0, x2 // Write pmpaddr0 in u mode (TRAP) nop // Added nop in case of trap //////////////// VERIFICATION ///////////////////////////////////////// // READING pmpaddr in S-mode ///////////////////////////////////////// - csrr a4, pmpaddr12 // Reading pmpaddr12 in U mode (TRAP) + csrr a4, pmpaddr0 // Reading pmpaddr0 in U mode (TRAP) nop // Added nop in case of trap #endif diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-NAPOT-RX.S b/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-NAPOT-RX.S index 76c91d286..b705fcdec 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-NAPOT-RX.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-NAPOT-RX.S @@ -13,7 +13,7 @@ #define rvtest_strap_routine #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-granularity.S b/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-granularity.S index 4b5e2f1fc..ec9740c67 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-granularity.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/PMP-granularity.S @@ -13,7 +13,7 @@ #define rvtest_strap_routine #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init @@ -29,27 +29,6 @@ RVTEST_SIGBASE( x3,signature_x3_1) .attribute stack_align, 16 .align 2 main: -////////////// SETTING DEFAULTS TO ZERO /////////////////////////////////////// - csrw pmpcfg0, x0 - csrw pmpcfg1, x0 - csrw pmpcfg2, x0 - csrw pmpcfg3, x0 - csrw pmpaddr0, x0 - csrw pmpaddr1, x0 - csrw pmpaddr2, x0 - csrw pmpaddr3, x0 - csrw pmpaddr4, x0 - csrw pmpaddr5, x0 - csrw pmpaddr6, x0 - csrw pmpaddr7, x0 - csrw pmpaddr8, x0 - csrw pmpaddr9, x0 - csrw pmpaddr10, x0 - csrw pmpaddr11, x0 - csrw pmpaddr12, x0 - csrw pmpaddr13, x0 - csrw pmpaddr14, x0 - csrw pmpaddr15, x0 //////////////////// Granularity TEST 1 ///////////////////////////////////////////// detect_granule: // AS INSTRUCTED IN RISC-V Privileged Architectures V1.12-draft // RISC-V Priv Architecture Manual (Article 3.7.1) @@ -89,12 +68,10 @@ calculations: RVTEST_SIGUPD(x3,x7) //////////////////////// DETECT pmpaddri[G-1:0] bits must be read zero in case of pmpcfgi.A[1]==0 //////////////////////// uneffecting the underlaying actual value for G>=1 - csrw pmpcfg0, 0 // WRITE 0 to pmpcfg0 nop // Added nop in case of trap csrw pmpaddr0, a4 // WRITE ALL 1s in pmpaddr0 csrr a5, pmpaddr0 // READ the address - // DISPLAY pmpaddr0 RVTEST_SIGUPD(x3,a5) #endif diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-R.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-R.S index 9cb1956a0..16d578a59 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-R.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-R.S @@ -23,7 +23,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RW.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RW.S index 3131c2641..80d786fdf 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RW.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RW.S @@ -24,7 +24,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RWX.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RWX.S index 96dee4748..d7e75cf4b 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RWX.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RWX.S @@ -22,7 +22,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point @@ -64,13 +64,13 @@ main: // Loop to SET ALL pmpcfg REGs to zero .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value) .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg .endr // END OF LOOP BODY // Loop to SET ALL pmpaddr REGs to zero .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value) .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg .endr // END OF LOOP BODY @@ -106,13 +106,27 @@ main: csrw satp, x0 // Disable Address Translation // PMP Configuration /* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. +1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. +This region is the part of the code memory containing our code and the region between code_end to data_begin. +For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to +declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. + +2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail.) +This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. +Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 + +3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. +This region has been declared by entering rvtest_code_end into pmpaddr3 and +RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) +to pmpaddr3(rvtest_code_end) into TOR mode +by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) + +4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. +This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. +For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) +into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). +This PMP Region is mandatory to access signature area in S,U mode */ -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ /* Assigning addresses to PMP address registers */ LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 srl x4, x4, PMP_SHIFT // Shift right by 2 times @@ -157,8 +171,8 @@ main: // VERIFICATION IN U-Mode RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode VERIFICATION_RWX TEST_FOR_EXECUTION + nop j exit - RAM_LOCATION_FOR_TEST: .fill 3*(XLEN/32),4,0x12345678 TEST_FOR_EXECUTION: @@ -176,6 +190,8 @@ RVMODEL_HALT RVTEST_DATA_BEGIN .align 4 + + rvtest_data: .word 0xbabecafe .word 0xbabecafe @@ -213,4 +229,4 @@ sig_end_canary: CANARY; rvtest_sig_end: PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RX.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RX.S index 061568bce..b3d44ffde 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RX.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RX.S @@ -22,7 +22,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-X.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-X.S index f216b24f5..3faa56295 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-X.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-X.S @@ -22,7 +22,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-R.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-R.S index 8f41058ae..8568ef316 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-R.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-R.S @@ -24,7 +24,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RW.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RW.S index c864ec747..0f344b579 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RW.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RW.S @@ -24,7 +24,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RWX.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RWX.S index b800645eb..613e36b2d 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RWX.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RWX.S @@ -24,7 +24,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RX.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RX.S index 8cb00d907..c6b81d87b 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RX.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RX.S @@ -24,7 +24,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-X.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-X.S index fffbe5395..02ddaee46 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-X.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-X.S @@ -24,7 +24,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-na4-RWX.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-na4-RWX.S deleted file mode 100644 index 80acc6e29..000000000 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-na4-RWX.S +++ /dev/null @@ -1,259 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to PMP Test plan developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1TwiNvnGmAvSCAXhnsTnn6E295kD4p97CLVjh49zRVF8/edit?usp=sharing -/* - PMP Test for RWX of memory region in NA4 address matching mode - PMP memory region is defined @pmpaddr1, - pmpcfg0 is used with the corresponding address registers - */ -#define rvtest_strap_routine -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I") - -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",pmp-tor) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 3 -main: -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -/* SETTING DEFAULTS TO ZERO */ - csrw pmpcfg0, x0 - csrw pmpcfg1, x0 - csrw pmpcfg2, x0 - csrw pmpcfg3, x0 - csrw pmpaddr0, x0 - csrw pmpaddr1, x0 - csrw pmpaddr2, x0 - csrw pmpaddr3, x0 - csrw pmpaddr4, x0 - csrw pmpaddr5, x0 - csrw pmpaddr6, x0 - csrw pmpaddr7, x0 - csrw pmpaddr8, x0 - csrw pmpaddr9, x0 - csrw pmpaddr10, x0 - csrw pmpaddr11, x0 - csrw pmpaddr12, x0 - csrw pmpaddr13, x0 - csrw pmpaddr14, x0 - csrw pmpaddr15, x0 - -// pmpcfg0 value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPCONFIG0 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// pmpcfg0pmpcfg0[15:8] value to configure address (RAM_LOCATION_FOR_TEST)->(RAM_LOCATION_FOR_TEST+3*(XLEN/32)) -// in TOR Mode with RWX enabled =========> THIS IS OUR REGION UNDER OBSERVATION -#define PMPCONFIG1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// pmpcfg0[31:24] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPCONFIG3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -/* Setup some data for testing */ -#define DATA_VALUE_FOR_READ1 0xAAAAAAAA -#define DATA_VALUE_FOR_READ2 0xBBBBBBBB -#define DATA_VALUE_FOR_WRITE1 0x11111111 -#define DATA_VALUE_FOR_WRITE2 0x22222222 - - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation - LA(a5, RAM_LOCATION_FOR_TEST) // Get the address to RAM_LOCATION_FOR_TEST - LI(a4, DATA_VALUE_FOR_READ1) // Load the value to initialize memory region - sw a4,0(a5) // Store the value @ RAM_LOCATION_FOR_TEST - lw a4,0(a5) // Reload it to verify -// VERIFICATION - RVTEST_SIGUPD(x13,a4) // Store into the signature - - LI(a4, DATA_VALUE_FOR_READ2) // Load the 2nd value - sw a4, 4(a5) // Update it @ RAM_LOCATION_FOR_TEST+4 address - lw a4, 4(a5) // Reload it to verify -// VERIFICATION - RVTEST_SIGUPD(x13,a4) -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address RAM_LOCATION_FOR_TEST to Address RAM_LOCATION_FOR_TEST+12*(XLEN/32) => PMP region under test. This region has been declared by entering RAM_LOCATION_FOR_TEST+3*(XLEN/32) into pmpaddr1, and configure pmpaddr0(RAM_LOCATION_FOR_TEST) to pmpaddr1(RAM_LOCATION_FOR_TEST+3*(XLEN/32)) into TOR mode by setting pmpcfg0[15:8]=0x8F - -3. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr2(rvtest_code_end) to pmpaddr3(PMP_region_High) into TOR mode by setting pmpcfg0[31:24]=0x8F. This PMP Region is mandatory to access signature area in S,U mode */ - - /* Assigning addresses to PMP address registers */ - LA(a5, RAM_LOCATION_FOR_TEST) // Value to be stored in pmpaddr0 - srl a5, a5, PMP_SHIFT // Shift Right by PMP_SHIFT times - csrw pmpaddr0, a5 // Updated pmpaddr0 - nop // Added nop in case of trap - - LA(a5, RAM_LOCATION_FOR_TEST+4*(XLEN/32)) // Value to be stored in pmpaddr1 - srl a5, a5, PMP_SHIFT // Shift Right by PMP_SHIFT times - csrw pmpaddr1, a5 // Updated pmpaddr1 - nop // Added nop in case of trap - -////////////////// DECLARE SIGNATURE AREA & TRAP HANDLER INTO A PMP REGION ///////////////// -// It has been done to avoid getting store/amo access faults in S or U mode -// when RVTEST_SIGUPD will be used to update signatures in S-mode or U-mode -// In order to declare PMP region consisting on whole data region, -// RVMODEL_DATA_BEGIN & RVMODEL_DATA_END have been used as ranges in TOR mode. -/////////////////////////////////////////////////////////////////////////////// - LA(x4, rvtest_code_end) // Loaded the upper address of PMP region - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMP_region_High) // Loaded the upper address of PMP region - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPCONFIG0 | PMPCONFIG1 | PMPCONFIG3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg - nop // Added nop in case of trap -//////////// PMP Region for Signature Area defined, it was mandatory to access signature area in S,U mode - -// PMP Region configured - /* VERIFICATION in M-mode */ - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address which is inside pmp region - lw a4,0(a5) // Load data from it - RVTEST_SIGUPD(x13,a4) - - lw a4,4(a5) // Load data of next location - RVTEST_SIGUPD(x13,a4) - - /* WRITING new value to memory region - Throws exception if the WRITability is blocked */ - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address - LI(a4, DATA_VALUE_FOR_WRITE1) // Load the new value - sw a4,0(a5) // Store the new value (WILL NOT TRAP - W enabled) - lw a4,0(a5) // Reload for verification - RVTEST_SIGUPD(x13,a4) - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address - LI(a4, DATA_VALUE_FOR_WRITE1) // Load the new value - sw a4,4(a5) // Store the new value at address outside PMP region - // (WILL NOT TRAP - W enabled) - lw a4,4(a5) // Reload for verification - RVTEST_SIGUPD(x13,a4) - -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode -// READING data from the memory region -// Throws exception if READability is blocked */ - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address which is inside pmp region - lw a4,0(a5) // Load data from it - RVTEST_SIGUPD(x13,a4) - - lw a4,4(a5) // Load data of next location (TRAP -> its outside PMP region) - RVTEST_SIGUPD(x13,a4) - - /* WRITING new value to memory region - Throws exception if the WRITability is blocked */ - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address - LI(a4, DATA_VALUE_FOR_WRITE1) // Load the new value - sw a4,0(a5) // Store the new value (WILL NOT TRAP - W enabled) - lw a4,0(a5) // Reload for verification (Will not TRAP) - RVTEST_SIGUPD(x13,a4) - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop - RVTEST_SIGUPD(x13,a4) -// VERIFICATION IN U-Mode - csrw satp, x0 // Disable Address Translation - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode -// READING data from the memory region -// Throws exception if READability is blocked */ - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address which is inside pmp region - lw a4,0(a5) // Load data from it - RVTEST_SIGUPD(x13,a4) - - lw a4,4(a5) // Load data of next location (TRAP -> its outside PMP region) - RVTEST_SIGUPD(x13,a4) - - /* WRITING new value to memory region - Throws exception if the WRITability is blocked */ - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address - LI(a4, DATA_VALUE_FOR_WRITE1) // Load the new value - sw a4,0(a5) // Store the new value (WILL NOT TRAP - W enabled) - lw a4,0(a5) // Reload for verification - RVTEST_SIGUPD(x13,a4) - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address - LI(a4, DATA_VALUE_FOR_WRITE1) // Load the new value - sw a4,4(a5) // Store the new value at address outside PMP region - // (TRAP - outside PMP region, no access in U-mode) - lw a4,4(a5) // Reload for verification - RVTEST_SIGUPD(x13,a4) - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -exit: - -#endif - - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-na4-RX.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-na4-RX.S deleted file mode 100644 index 2deaff5af..000000000 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-na4-RX.S +++ /dev/null @@ -1,259 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to PMP Test plan developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1TwiNvnGmAvSCAXhnsTnn6E295kD4p97CLVjh49zRVF8/edit?usp=sharing -/* - PMP Test for RX of memory region in NA4 address matching mode - PMP memory region is defined @pmpaddr1, - pmpcfg0 is used with the corresponding address registers - */ -#define rvtest_strap_routine -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I") - -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",pmp-tor) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 3 -main: -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -/* SETTING DEFAULTS TO ZERO */ - csrw pmpcfg0, x0 - csrw pmpcfg1, x0 - csrw pmpcfg2, x0 - csrw pmpcfg3, x0 - csrw pmpaddr0, x0 - csrw pmpaddr1, x0 - csrw pmpaddr2, x0 - csrw pmpaddr3, x0 - csrw pmpaddr4, x0 - csrw pmpaddr5, x0 - csrw pmpaddr6, x0 - csrw pmpaddr7, x0 - csrw pmpaddr8, x0 - csrw pmpaddr9, x0 - csrw pmpaddr10, x0 - csrw pmpaddr11, x0 - csrw pmpaddr12, x0 - csrw pmpaddr13, x0 - csrw pmpaddr14, x0 - csrw pmpaddr15, x0 - -// pmpcfg0 value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPCONFIG0 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// pmpcfg0pmpcfg0[15:8] value to configure address (RAM_LOCATION_FOR_TEST)->(RAM_LOCATION_FOR_TEST+3*(XLEN/32)) -// in TOR Mode with RWX enabled =========> THIS IS OUR REGION UNDER OBSERVATION -#define PMPCONFIG1 ((((PMP_R|PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// pmpcfg0[31:24] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPCONFIG3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -/* Setup some data for testing */ -#define DATA_VALUE_FOR_READ1 0xAAAAAAAA -#define DATA_VALUE_FOR_READ2 0xBBBBBBBB -#define DATA_VALUE_FOR_WRITE1 0x11111111 -#define DATA_VALUE_FOR_WRITE2 0x22222222 - - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation - LA(a5, RAM_LOCATION_FOR_TEST) // Get the address to RAM_LOCATION_FOR_TEST - LI(a4, DATA_VALUE_FOR_READ1) // Load the value to initialize memory region - sw a4,0(a5) // Store the value @ RAM_LOCATION_FOR_TEST - lw a4,0(a5) // Reload it to verify -// VERIFICATION - RVTEST_SIGUPD(x13,a4) // Store into the signature - - LI(a4, DATA_VALUE_FOR_READ2) // Load the 2nd value - sw a4, 4(a5) // Update it @ RAM_LOCATION_FOR_TEST+4 address - lw a4, 4(a5) // Reload it to verify -// VERIFICATION - RVTEST_SIGUPD(x13,a4) -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address RAM_LOCATION_FOR_TEST to Address RAM_LOCATION_FOR_TEST+12*(XLEN/32) => PMP region under test. This region has been declared by entering RAM_LOCATION_FOR_TEST+3*(XLEN/32) into pmpaddr1, and configure pmpaddr0(RAM_LOCATION_FOR_TEST) to pmpaddr1(RAM_LOCATION_FOR_TEST+3*(XLEN/32)) into TOR mode by setting pmpcfg0[15:8]=0x8F - -3. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr2(rvtest_code_end) to pmpaddr3(PMP_region_High) into TOR mode by setting pmpcfg0[31:24]=0x8F. This PMP Region is mandatory to access signature area in S,U mode */ - - /* Assigning addresses to PMP address registers */ - LA(a5, RAM_LOCATION_FOR_TEST) // Value to be stored in pmpaddr0 - srl a5, a5, PMP_SHIFT // Shift Right by PMP_SHIFT times - csrw pmpaddr0, a5 // Updated pmpaddr0 - nop // Added nop in case of trap - - LA(a5, RAM_LOCATION_FOR_TEST+4*(XLEN/32)) // Value to be stored in pmpaddr1 - srl a5, a5, PMP_SHIFT // Shift Right by PMP_SHIFT times - csrw pmpaddr1, a5 // Updated pmpaddr1 - nop // Added nop in case of trap - -////////////////// DECLARE SIGNATURE AREA & TRAP HANDLER INTO A PMP REGION ///////////////// -// It has been done to avoid getting store/amo access faults in S or U mode -// when RVTEST_SIGUPD will be used to update signatures in S-mode or U-mode -// In order to declare PMP region consisting on whole data region, -// RVMODEL_DATA_BEGIN & RVMODEL_DATA_END have been used as ranges in TOR mode. -/////////////////////////////////////////////////////////////////////////////// - LA(x4, rvtest_code_end) // Loaded the upper address of PMP region - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMP_region_High) // Loaded the upper address of PMP region - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPCONFIG0 | PMPCONFIG1 | PMPCONFIG3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg - nop // Added nop in case of trap -//////////// PMP Region for Signature Area defined, it was mandatory to access signature area in S,U mode - -// PMP Region configured - /* VERIFICATION in M-mode */ - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address which is inside pmp region - lw a4,0(a5) // Load data from it - RVTEST_SIGUPD(x13,a4) - - lw a4,4(a5) // Load data of next location - RVTEST_SIGUPD(x13,a4) - - /* WRITING new value to memory region - Throws exception if the WRITability is blocked */ - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address - LI(a4, DATA_VALUE_FOR_WRITE1) // Load the new value - sw a4,0(a5) // Store the new value (WILL NOT TRAP - W enabled) - lw a4,0(a5) // Reload for verification - RVTEST_SIGUPD(x13,a4) - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address - LI(a4, DATA_VALUE_FOR_WRITE1) // Load the new value - sw a4,4(a5) // Store the new value at address outside PMP region - // (WILL NOT TRAP - W enabled) - lw a4,4(a5) // Reload for verification - RVTEST_SIGUPD(x13,a4) - -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode -// READING data from the memory region -// Throws exception if READability is blocked */ - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address which is inside pmp region - lw a4,0(a5) // Load data from it - RVTEST_SIGUPD(x13,a4) - - lw a4,4(a5) // Load data of next location (TRAP -> its outside PMP region) - RVTEST_SIGUPD(x13,a4) - - /* WRITING new value to memory region - Throws exception if the WRITability is blocked */ - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address - LI(a4, DATA_VALUE_FOR_WRITE1) // Load the new value - sw a4,0(a5) // Store the new value (WILL NOT TRAP - W enabled) - lw a4,0(a5) // Reload for verification (Will not TRAP) - RVTEST_SIGUPD(x13,a4) - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop - RVTEST_SIGUPD(x13,a4) -// VERIFICATION IN U-Mode - csrw satp, x0 // Disable Address Translation - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode -// READING data from the memory region -// Throws exception if READability is blocked */ - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address which is inside pmp region - lw a4,0(a5) // Load data from it - RVTEST_SIGUPD(x13,a4) - - lw a4,4(a5) // Load data of next location (TRAP -> its outside PMP region) - RVTEST_SIGUPD(x13,a4) - - /* WRITING new value to memory region - Throws exception if the WRITability is blocked */ - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address - LI(a4, DATA_VALUE_FOR_WRITE1) // Load the new value - sw a4,0(a5) // Store the new value (WILL NOT TRAP - W enabled) - lw a4,0(a5) // Reload for verification - RVTEST_SIGUPD(x13,a4) - - LA(a5, RAM_LOCATION_FOR_TEST) // Fetch the address - LI(a4, DATA_VALUE_FOR_WRITE1) // Load the new value - sw a4,4(a5) // Store the new value at address outside PMP region - // (TRAP - outside PMP region, no access in U-mode) - lw a4,4(a5) // Reload for verification - RVTEST_SIGUPD(x13,a4) - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -exit: - -#endif - - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-R.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-R.S index e11f50626..2469d9b28 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-R.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-R.S @@ -23,7 +23,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RW.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RW.S index 64bcc34c1..8ab96df22 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RW.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RW.S @@ -23,7 +23,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RWX.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RWX.S index ea404d671..f5e5a8cd5 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RWX.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RWX.S @@ -23,7 +23,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RX.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RX.S index ab1cbcaa9..f6b457bee 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RX.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-RX.S @@ -23,7 +23,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-X.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-X.S index 4cc4f4670..915c2e9b1 100644 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-X.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-X.S @@ -23,7 +23,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-overlap.S b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-overlap.S index cce195f0c..b6676707b 100755 --- a/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-overlap.S +++ b/riscv-test-suite/rv32i_m/privilege/pmp32/pmp-tor-overlap.S @@ -20,7 +20,7 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32I") +RVTEST_ISA("RV32I_Zicsr") # Test code region .section .text.init .globl rvtest_entry_point