diff --git a/CHANGELOG.md b/CHANGELOG.md
index 8742fc7a1..c6f043dea 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,4 +1,8 @@
 # CHANGELOG
+
+## [3.7.5] - 2023-10-11
+Add missing check ISA fields in recently modified div and amo tests
+
 ## [3.7.4] - 2023-10-04
 - Fix typos in CONTRIBUTION.md
 
diff --git a/riscv-test-suite/rv32i_m/A/src/amoadd.w-01.S b/riscv-test-suite/rv32i_m/A/src/amoadd.w-01.S
index feb72d84f..b230b3cfc 100644
--- a/riscv-test-suite/rv32i_m/A/src/amoadd.w-01.S
+++ b/riscv-test-suite/rv32i_m/A/src/amoadd.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv32i_m/A/src/amoand.w-01.S b/riscv-test-suite/rv32i_m/A/src/amoand.w-01.S
index d48be3713..22b57ee00 100644
--- a/riscv-test-suite/rv32i_m/A/src/amoand.w-01.S
+++ b/riscv-test-suite/rv32i_m/A/src/amoand.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv32i_m/A/src/amomax.w-01.S b/riscv-test-suite/rv32i_m/A/src/amomax.w-01.S
index 3c8342544..a2f272d8d 100644
--- a/riscv-test-suite/rv32i_m/A/src/amomax.w-01.S
+++ b/riscv-test-suite/rv32i_m/A/src/amomax.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv32i_m/A/src/amomaxu.w-01.S b/riscv-test-suite/rv32i_m/A/src/amomaxu.w-01.S
index 35514140e..4e46c501b 100644
--- a/riscv-test-suite/rv32i_m/A/src/amomaxu.w-01.S
+++ b/riscv-test-suite/rv32i_m/A/src/amomaxu.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv32i_m/A/src/amomin.w-01.S b/riscv-test-suite/rv32i_m/A/src/amomin.w-01.S
index 29127630b..e36518142 100644
--- a/riscv-test-suite/rv32i_m/A/src/amomin.w-01.S
+++ b/riscv-test-suite/rv32i_m/A/src/amomin.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv32i_m/A/src/amominu.w-01.S b/riscv-test-suite/rv32i_m/A/src/amominu.w-01.S
index 5bd7dcf3b..2db3b0a6d 100644
--- a/riscv-test-suite/rv32i_m/A/src/amominu.w-01.S
+++ b/riscv-test-suite/rv32i_m/A/src/amominu.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv32i_m/A/src/amoor.w-01.S b/riscv-test-suite/rv32i_m/A/src/amoor.w-01.S
index 1faeebfc3..eab932c2e 100644
--- a/riscv-test-suite/rv32i_m/A/src/amoor.w-01.S
+++ b/riscv-test-suite/rv32i_m/A/src/amoor.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv32i_m/A/src/amoswap.w-01.S b/riscv-test-suite/rv32i_m/A/src/amoswap.w-01.S
index 91f789f93..7e1ec82a4 100644
--- a/riscv-test-suite/rv32i_m/A/src/amoswap.w-01.S
+++ b/riscv-test-suite/rv32i_m/A/src/amoswap.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S b/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S
index e06d94ce2..33d0a5155 100644
--- a/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S
+++ b/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv32i_m/M/src/div-01.S b/riscv-test-suite/rv32i_m/M/src/div-01.S
index e50295203..08908e514 100644
--- a/riscv-test-suite/rv32i_m/M/src/div-01.S
+++ b/riscv-test-suite/rv32i_m/M/src/div-01.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",div)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",div)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amoadd.d-01.S b/riscv-test-suite/rv64i_m/A/src/amoadd.d-01.S
index 6a38bccda..754b07724 100644
--- a/riscv-test-suite/rv64i_m/A/src/amoadd.d-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amoadd.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amoadd.w-01.S b/riscv-test-suite/rv64i_m/A/src/amoadd.w-01.S
index 733ba5a13..529956c4a 100644
--- a/riscv-test-suite/rv64i_m/A/src/amoadd.w-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amoadd.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amoand.d-01.S b/riscv-test-suite/rv64i_m/A/src/amoand.d-01.S
index c8259f834..478dd839f 100644
--- a/riscv-test-suite/rv64i_m/A/src/amoand.d-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amoand.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amoand.w-01.S b/riscv-test-suite/rv64i_m/A/src/amoand.w-01.S
index 1e7e269ef..7aa1aa5fb 100644
--- a/riscv-test-suite/rv64i_m/A/src/amoand.w-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amoand.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amomax.d-01.S b/riscv-test-suite/rv64i_m/A/src/amomax.d-01.S
index 993b0a619..de7e8714e 100644
--- a/riscv-test-suite/rv64i_m/A/src/amomax.d-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amomax.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amomax.w-01.S b/riscv-test-suite/rv64i_m/A/src/amomax.w-01.S
index 505e3e95e..79ae5e4b6 100644
--- a/riscv-test-suite/rv64i_m/A/src/amomax.w-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amomax.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amomaxu.d-01.S b/riscv-test-suite/rv64i_m/A/src/amomaxu.d-01.S
index 25c7f629e..fbbbb11e3 100644
--- a/riscv-test-suite/rv64i_m/A/src/amomaxu.d-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amomaxu.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amomaxu.w-01.S b/riscv-test-suite/rv64i_m/A/src/amomaxu.w-01.S
index 0e0eb5da0..422417778 100644
--- a/riscv-test-suite/rv64i_m/A/src/amomaxu.w-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amomaxu.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amomin.d-01.S b/riscv-test-suite/rv64i_m/A/src/amomin.d-01.S
index ab21d38b1..caec9e892 100644
--- a/riscv-test-suite/rv64i_m/A/src/amomin.d-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amomin.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amomin.w-01.S b/riscv-test-suite/rv64i_m/A/src/amomin.w-01.S
index 109098baa..1a4bbb058 100644
--- a/riscv-test-suite/rv64i_m/A/src/amomin.w-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amomin.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amominu.d-01.S b/riscv-test-suite/rv64i_m/A/src/amominu.d-01.S
index 37ff51b3f..adc2088a7 100644
--- a/riscv-test-suite/rv64i_m/A/src/amominu.d-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amominu.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amominu.w-01.S b/riscv-test-suite/rv64i_m/A/src/amominu.w-01.S
index 589693479..033f0cd11 100644
--- a/riscv-test-suite/rv64i_m/A/src/amominu.w-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amominu.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amoor.d-01.S b/riscv-test-suite/rv64i_m/A/src/amoor.d-01.S
index 832a1e368..1c0a326ce 100644
--- a/riscv-test-suite/rv64i_m/A/src/amoor.d-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amoor.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amoor.w-01.S b/riscv-test-suite/rv64i_m/A/src/amoor.w-01.S
index a915c98df..a7eff3d68 100644
--- a/riscv-test-suite/rv64i_m/A/src/amoor.w-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amoor.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amoswap.d-01.S b/riscv-test-suite/rv64i_m/A/src/amoswap.d-01.S
index 1828ecbef..e9d2653b9 100644
--- a/riscv-test-suite/rv64i_m/A/src/amoswap.d-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amoswap.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amoswap.w-01.S b/riscv-test-suite/rv64i_m/A/src/amoswap.w-01.S
index 3ff72d03d..f588a7393 100644
--- a/riscv-test-suite/rv64i_m/A/src/amoswap.w-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amoswap.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amoxor.d-01.S b/riscv-test-suite/rv64i_m/A/src/amoxor.d-01.S
index ac794d853..a7d4138da 100644
--- a/riscv-test-suite/rv64i_m/A/src/amoxor.d-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amoxor.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S b/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S
index be9cb60d7..31a96a895 100644
--- a/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S
+++ b/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/M/src/div-01.S b/riscv-test-suite/rv64i_m/M/src/div-01.S
index 1bd6b8abc..c6666ab6f 100644
--- a/riscv-test-suite/rv64i_m/M/src/div-01.S
+++ b/riscv-test-suite/rv64i_m/M/src/div-01.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",div)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",div)
 
 RVTEST_SIGBASE(x1,signature_x1_1)