diff --git a/doc/openocd.texi b/doc/openocd.texi
index b2236dd32..73e2e7f60 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11631,6 +11631,12 @@ riscv exec_progbuf 0x0330000f 0x0000100f
 riscv exec_progbuf 0x94a20405
 @end example
 
+@deffn {Command} {riscv autofence} [on|off]
+When on (default), some situations, such as stepi, will automatically execute fence.
+When off, user needs to take care of the cache themselves, for example, using the
+riscv exec_progbuf to execute fence or cmo command.
+@end deffn
+
 @section ARC Architecture
 @cindex ARC
 
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 6003064e4..d0b751a66 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -2918,6 +2918,10 @@ static int execute_fence(struct target *target)
 	if (dm013_select_target(target) != ERROR_OK)
 		return ERROR_FAIL;
 
+	RISCV_INFO(r);
+	if (!r->auto_fence)
+		return ERROR_OK;
+
 	/* FIXME: For non-coherent systems we need to flush the caches right
 	 * here, but there's no ISA-defined way of doing that. */
 	struct riscv_program program;
@@ -2941,6 +2945,7 @@ static int execute_fence(struct target *target)
 			}
 			LOG_TARGET_DEBUG(target, "Unable to execute fence");
 		}
+		LOG_TARGET_DEBUG(target, "Successfully executed fence");
 		return ERROR_OK;
 	}
 
@@ -2954,6 +2959,7 @@ static int execute_fence(struct target *target)
 			}
 			LOG_TARGET_DEBUG(target, "Unable to execute fence.i");
 		}
+		LOG_TARGET_DEBUG(target, "Successfully executed fence.i");
 
 		riscv_program_init(&program, target);
 		riscv_program_fence_rw_rw(&program);
@@ -2964,6 +2970,7 @@ static int execute_fence(struct target *target)
 			}
 			LOG_TARGET_DEBUG(target, "Unable to execute fence rw, rw");
 		}
+		LOG_TARGET_DEBUG(target, "Successfully executed fence rw, rw");
 		return ERROR_OK;
 	}
 
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index aa4bc6757..4023e0440 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -4521,6 +4521,23 @@ COMMAND_HANDLER(riscv_set_maskisr)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(riscv_set_autofence)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	RISCV_INFO(r);
+
+	if (CMD_ARGC != 1) {
+		command_print(CMD, "autofence enabled: %s", r->autofence ? "on" : "off");
+		return ERROR_OK;
+	} else if (CMD_ARGC == 1) {
+		COMMAND_PARSE_ON_OFF(CMD_ARGV[0], r->autofence);
+		return ERROR_OK;
+	}
+
+	LOG_ERROR("Command takes 0 or 1 parameters");
+	return ERROR_COMMAND_SYNTAX_ERROR;
+}
+
 COMMAND_HANDLER(riscv_set_ebreakm)
 {
 	struct target *target = get_current_target(CMD_CTX);
@@ -5428,6 +5445,16 @@ static const struct command_registration riscv_exec_command_handlers[] = {
 				"hw - translate vaddr to paddr by hardware, "
 				"off - no address translation."
 	},
+	{
+		.name = "autofence",
+		.handler = riscv_set_autofence,
+		.mode = COMMAND_ANY,
+		.usage = "[on|off]",
+		.help = "When on (default), some situations, such as stepi, will automatically execute fence. "
+			"When off, user needs to take care of the cache themselves, for example, using the "
+			"riscv exec_progbuf to execute fence or cmo command."
+
+	},
 	COMMAND_REGISTRATION_DONE
 };
 
@@ -5569,6 +5596,8 @@ static void riscv_info_init(struct target *target, struct riscv_info *r)
 	r->wp_allow_equality_match_trigger = true;
 	r->wp_allow_ge_lt_trigger = true;
 	r->wp_allow_napot_trigger = true;
+
+	r->autofence = true;
 }
 
 static int riscv_resume_go_all_harts(struct target *target)
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
index 0b65f5f95..79d6ba847 100644
--- a/src/target/riscv/riscv.h
+++ b/src/target/riscv/riscv.h
@@ -321,6 +321,8 @@ struct riscv_info {
 	bool wp_allow_equality_match_trigger;
 	bool wp_allow_napot_trigger;
 	bool wp_allow_ge_lt_trigger;
+
+	bool autofence;
 };
 
 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,