From c52ffb99755aab0db4a1eab3d3e05600e50e0939 Mon Sep 17 00:00:00 2001 From: Marek Vrbka Date: Mon, 21 Aug 2023 13:49:43 +0200 Subject: [PATCH] target/riscv: Don't write to zero. During a previous patch, the ignoring of writes to register zero was deleted. This patch restores it to the original. Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c Signed-off-by: Marek Vrbka --- src/target/riscv/riscv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index c404b14bde..99aa0d409f 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -4718,6 +4718,10 @@ unsigned int riscv_count_harts(struct target *target) */ static bool gdb_regno_cacheable(enum gdb_regno regno, bool is_write) { + /* Writes to register zero are rare and should always result in 0 */ + if (regno == GDB_REGNO_ZERO) + return false; + /* GPRs, FPRs, vector registers are just normal data stores. */ if (regno <= GDB_REGNO_XPR31 || (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||