diff --git a/src/target/riscv/Makefile.am b/src/target/riscv/Makefile.am
index 4b6a74f0b8..1a814d2075 100644
--- a/src/target/riscv/Makefile.am
+++ b/src/target/riscv/Makefile.am
@@ -5,6 +5,7 @@ noinst_LTLIBRARIES += %D%/libriscv.la
        %D%/asm.h \
        %D%/batch.h \
        %D%/debug_defines.h \
+       %D%/debug_register_printers.h \
        %D%/encoding.h \
        %D%/gdb_regs.h \
        %D%/opcodes.h \
@@ -15,4 +16,6 @@ noinst_LTLIBRARIES += %D%/libriscv.la
        %D%/riscv-011.c \
        %D%/riscv-013.c \
        %D%/riscv.c \
-       %D%/riscv_semihosting.c
+       %D%/riscv_semihosting.c \
+       %D%/debug_defines.c \
+       %D%/debug_register_printers.c
diff --git a/src/target/riscv/debug_defines.c b/src/target/riscv/debug_defines.c
new file mode 100644
index 0000000000..e3ad6c80dc
--- /dev/null
+++ b/src/target/riscv/debug_defines.c
@@ -0,0 +1,5308 @@
+#include "debug_defines.h"
+#include <stddef.h>
+#include <assert.h>
+static inline unsigned int DTM_IDCODE_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DTM_IDCODE_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DTM_IDCODE_VERSION_OFFSET:
+	case DTM_IDCODE_PARTNUMBER_OFFSET:
+	case DTM_IDCODE_MANUFID_OFFSET:
+	case DTM_IDCODE_1_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DTM_IDCODE_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DTM_IDCODE_VERSION_OFFSET:
+		return "Version";
+	case DTM_IDCODE_PARTNUMBER_OFFSET:
+		return "PartNumber";
+	case DTM_IDCODE_MANUFID_OFFSET:
+		return "ManufId";
+	case DTM_IDCODE_1_OFFSET:
+		return "1";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DTM_IDCODE_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DTM_IDCODE_width(context));
+	switch (offset) {
+	case DTM_IDCODE_VERSION_OFFSET:
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	case DTM_IDCODE_PARTNUMBER_OFFSET:
+		return (value & ((unsigned long long)0xffff << offset)) >> offset;
+	case DTM_IDCODE_MANUFID_OFFSET:
+		return (value & ((unsigned long long)0x7ff << offset)) >> offset;
+	case DTM_IDCODE_1_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DTM_IDCODE_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DTM_DTMCS_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DTM_DTMCS_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DTM_DTMCS_DMIHARDRESET_OFFSET:
+	case DTM_DTMCS_DMIRESET_OFFSET:
+	case DTM_DTMCS_IDLE_OFFSET:
+	case DTM_DTMCS_DMISTAT_OFFSET:
+	case DTM_DTMCS_ABITS_OFFSET:
+	case DTM_DTMCS_VERSION_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DTM_DTMCS_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DTM_DTMCS_DMIHARDRESET_OFFSET:
+		return "dmihardreset";
+	case DTM_DTMCS_DMIRESET_OFFSET:
+		return "dmireset";
+	case DTM_DTMCS_IDLE_OFFSET:
+		return "idle";
+	case DTM_DTMCS_DMISTAT_OFFSET:
+		return "dmistat";
+	case DTM_DTMCS_ABITS_OFFSET:
+		return "abits";
+	case DTM_DTMCS_VERSION_OFFSET:
+		return "version";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DTM_DTMCS_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DTM_DTMCS_width(context));
+	switch (offset) {
+	case DTM_DTMCS_DMIHARDRESET_OFFSET:
+	case DTM_DTMCS_DMIRESET_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case DTM_DTMCS_IDLE_OFFSET:
+		return (value & ((unsigned long long)7 << offset)) >> offset;
+	case DTM_DTMCS_DMISTAT_OFFSET:
+		return (value & ((unsigned long long)3 << offset)) >> offset;
+	case DTM_DTMCS_ABITS_OFFSET:
+		return (value & ((unsigned long long)0x3f << offset)) >> offset;
+	case DTM_DTMCS_VERSION_OFFSET:
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DTM_DTMCS_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case DTM_DTMCS_VERSION_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "0.11";
+		case 1:
+			return "1.0";
+		case 15:
+			return "custom";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int DTM_DMI_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.abits.is_set))
+		return 0;
+	return (0x21 > (context.abits.value + 0x21) ? 0x21 : (context.abits.value + 0x21) + 1);
+}
+
+static unsigned int DTM_DMI_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DTM_DMI_DATA_OFFSET:
+	case DTM_DMI_OP_OFFSET:
+		return 1;
+	default:
+		if (!(context.abits.is_set))
+			return 0;
+		if (offset == 0x22)
+			return 1;
+		return 0;
+	}
+}
+
+static const char *DTM_DMI_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DTM_DMI_DATA_OFFSET:
+		return "data";
+	case DTM_DMI_OP_OFFSET:
+		return "op";
+	default:
+		if (!(context.abits.is_set))
+			return NULL;
+		if (offset == 0x22)
+			return "address";
+		return NULL;
+	}
+}
+
+static unsigned long long DTM_DMI_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DTM_DMI_width(context));
+	switch (offset) {
+	case DTM_DMI_DATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	case DTM_DMI_OP_OFFSET:
+		return (value & ((unsigned long long)3 << offset)) >> offset;
+	default:
+		if (!(context.abits.is_set))
+			return 0;
+		if (offset == 0x22)
+			return (value & ((unsigned long long)((1ULL << context.abits.value) + -1) << offset)) >> offset;
+		return 0;
+	}
+}
+
+static const char *DTM_DMI_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DTM_BYPASS_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 1;
+}
+
+static unsigned int DTM_BYPASS_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	return 0;
+}
+
+static const char *DTM_BYPASS_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	return NULL;
+}
+
+static unsigned long long DTM_BYPASS_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DTM_BYPASS_width(context));
+	return 0;
+}
+
+static const char *DTM_BYPASS_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int CSR_DCSR_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int CSR_DCSR_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_DCSR_DEBUGVER_OFFSET:
+	case CSR_DCSR_EBREAKVS_OFFSET:
+	case CSR_DCSR_EBREAKVU_OFFSET:
+	case CSR_DCSR_EBREAKM_OFFSET:
+	case CSR_DCSR_EBREAKS_OFFSET:
+	case CSR_DCSR_EBREAKU_OFFSET:
+	case CSR_DCSR_STEPIE_OFFSET:
+	case CSR_DCSR_STOPCOUNT_OFFSET:
+	case CSR_DCSR_STOPTIME_OFFSET:
+	case CSR_DCSR_CAUSE_OFFSET:
+	case CSR_DCSR_V_OFFSET:
+	case CSR_DCSR_MPRVEN_OFFSET:
+	case CSR_DCSR_NMIP_OFFSET:
+	case CSR_DCSR_STEP_OFFSET:
+	case CSR_DCSR_PRV_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *CSR_DCSR_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_DCSR_DEBUGVER_OFFSET:
+		return "debugver";
+	case CSR_DCSR_EBREAKVS_OFFSET:
+		return "ebreakvs";
+	case CSR_DCSR_EBREAKVU_OFFSET:
+		return "ebreakvu";
+	case CSR_DCSR_EBREAKM_OFFSET:
+		return "ebreakm";
+	case CSR_DCSR_EBREAKS_OFFSET:
+		return "ebreaks";
+	case CSR_DCSR_EBREAKU_OFFSET:
+		return "ebreaku";
+	case CSR_DCSR_STEPIE_OFFSET:
+		return "stepie";
+	case CSR_DCSR_STOPCOUNT_OFFSET:
+		return "stopcount";
+	case CSR_DCSR_STOPTIME_OFFSET:
+		return "stoptime";
+	case CSR_DCSR_CAUSE_OFFSET:
+		return "cause";
+	case CSR_DCSR_V_OFFSET:
+		return "v";
+	case CSR_DCSR_MPRVEN_OFFSET:
+		return "mprven";
+	case CSR_DCSR_NMIP_OFFSET:
+		return "nmip";
+	case CSR_DCSR_STEP_OFFSET:
+		return "step";
+	case CSR_DCSR_PRV_OFFSET:
+		return "prv";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_DCSR_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_DCSR_width(context));
+	switch (offset) {
+	case CSR_DCSR_DEBUGVER_OFFSET:
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	case CSR_DCSR_EBREAKVS_OFFSET:
+	case CSR_DCSR_EBREAKVU_OFFSET:
+	case CSR_DCSR_EBREAKM_OFFSET:
+	case CSR_DCSR_EBREAKS_OFFSET:
+	case CSR_DCSR_EBREAKU_OFFSET:
+	case CSR_DCSR_STEPIE_OFFSET:
+	case CSR_DCSR_STOPCOUNT_OFFSET:
+	case CSR_DCSR_STOPTIME_OFFSET:
+	case CSR_DCSR_V_OFFSET:
+	case CSR_DCSR_MPRVEN_OFFSET:
+	case CSR_DCSR_NMIP_OFFSET:
+	case CSR_DCSR_STEP_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case CSR_DCSR_CAUSE_OFFSET:
+		return (value & ((unsigned long long)7 << offset)) >> offset;
+	case CSR_DCSR_PRV_OFFSET:
+		return (value & ((unsigned long long)3 << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *CSR_DCSR_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_DCSR_DEBUGVER_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "none";
+		case 4:
+			return "1.0";
+		case 15:
+			return "custom";
+		default:
+			return NULL;
+		}
+	case CSR_DCSR_EBREAKVS_OFFSET:
+	case CSR_DCSR_EBREAKVU_OFFSET:
+	case CSR_DCSR_EBREAKM_OFFSET:
+	case CSR_DCSR_EBREAKS_OFFSET:
+	case CSR_DCSR_EBREAKU_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "exception";
+		case 1:
+			return "debug mode";
+		default:
+			return NULL;
+		}
+	case CSR_DCSR_STEPIE_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "interrupts disabled";
+		case 1:
+			return "interrupts enabled";
+		default:
+			return NULL;
+		}
+	case CSR_DCSR_STOPCOUNT_OFFSET:
+	case CSR_DCSR_STOPTIME_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "normal";
+		case 1:
+			return "freeze";
+		default:
+			return NULL;
+		}
+	case CSR_DCSR_CAUSE_OFFSET:
+		switch (field_value) {
+		case 1:
+			return "ebreak";
+		case 2:
+			return "trigger";
+		case 3:
+			return "haltreq";
+		case 4:
+			return "step";
+		case 5:
+			return "resethaltreq";
+		case 6:
+			return "group";
+		default:
+			return NULL;
+		}
+	case CSR_DCSR_MPRVEN_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "disabled";
+		case 1:
+			return "enabled";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int CSR_DPC_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.DXLEN.is_set))
+		return 0;
+	return context.DXLEN.value;
+}
+
+static unsigned int CSR_DPC_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	if (!(context.DXLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return 1;
+	return 0;
+}
+
+static const char *CSR_DPC_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	if (!(context.DXLEN.is_set))
+		return NULL;
+	if (offset == 0)
+		return "dpc";
+	return NULL;
+}
+
+static unsigned long long CSR_DPC_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_DPC_width(context));
+	if (!(context.DXLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return (value & ((unsigned long long)((1ULL << context.DXLEN.value) + -1) << offset)) >> offset;
+	return 0;
+}
+
+static const char *CSR_DPC_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int CSR_TSELECT_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return context.XLEN.value;
+}
+
+static unsigned int CSR_TSELECT_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return 1;
+	return 0;
+}
+
+static const char *CSR_TSELECT_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return NULL;
+	if (offset == 0)
+		return "index";
+	return NULL;
+}
+
+static unsigned long long CSR_TSELECT_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_TSELECT_width(context));
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return (value & ((unsigned long long)((1ULL << context.XLEN.value) + -1) << offset)) >> offset;
+	return 0;
+}
+
+static const char *CSR_TSELECT_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int CSR_TDATA1_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return context.XLEN.value;
+}
+
+static unsigned int CSR_TDATA1_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == (context.XLEN.value + -4))
+		return 1;
+	if (offset == (context.XLEN.value + -5))
+		return 1;
+	if (offset == 0)
+		return 1;
+	return 0;
+}
+
+static const char *CSR_TDATA1_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return NULL;
+	if (offset == (context.XLEN.value + -4))
+		return "type";
+	if (offset == (context.XLEN.value + -5))
+		return "dmode";
+	if (offset == 0)
+		return "data";
+	return NULL;
+}
+
+static unsigned long long CSR_TDATA1_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_TDATA1_width(context));
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == (context.XLEN.value + -4))
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	if (offset == (context.XLEN.value + -5))
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	if (offset == 0)
+		return (value & ((unsigned long long)((1ULL << (context.XLEN.value + -5)) + -1) << offset)) >> offset;
+	return 0;
+}
+
+static const char *CSR_TDATA1_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return NULL;
+	if (offset == (context.XLEN.value + -4))
+		switch (field_value) {
+		case 0:
+			return "none";
+		case 1:
+			return "legacy";
+		case 2:
+			return "mcontrol";
+		case 3:
+			return "icount";
+		case 4:
+			return "itrigger";
+		case 5:
+			return "etrigger";
+		case 6:
+			return "mcontrol6";
+		case 7:
+			return "tmexttrigger";
+		case 15:
+			return "disabled";
+		default:
+			return NULL;
+		}
+	if (offset == (context.XLEN.value + -5))
+		switch (field_value) {
+		case 0:
+			return "both";
+		case 1:
+			return "dmode";
+		default:
+			return NULL;
+		}
+	if (offset == 0)
+		return NULL;
+	return NULL;
+}
+static inline unsigned int CSR_TDATA2_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return context.XLEN.value;
+}
+
+static unsigned int CSR_TDATA2_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return 1;
+	return 0;
+}
+
+static const char *CSR_TDATA2_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return NULL;
+	if (offset == 0)
+		return "data";
+	return NULL;
+}
+
+static unsigned long long CSR_TDATA2_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_TDATA2_width(context));
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return (value & ((unsigned long long)((1ULL << context.XLEN.value) + -1) << offset)) >> offset;
+	return 0;
+}
+
+static const char *CSR_TDATA2_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int CSR_TDATA3_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return context.XLEN.value;
+}
+
+static unsigned int CSR_TDATA3_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return 1;
+	return 0;
+}
+
+static const char *CSR_TDATA3_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return NULL;
+	if (offset == 0)
+		return "data";
+	return NULL;
+}
+
+static unsigned long long CSR_TDATA3_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_TDATA3_width(context));
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return (value & ((unsigned long long)((1ULL << context.XLEN.value) + -1) << offset)) >> offset;
+	return 0;
+}
+
+static const char *CSR_TDATA3_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int CSR_TINFO_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return (0xf > (context.XLEN.value + -1) ? 0xf : (context.XLEN.value + -1) + 1);
+}
+
+static unsigned int CSR_TINFO_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TINFO_INFO_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *CSR_TINFO_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TINFO_INFO_OFFSET:
+		return "info";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_TINFO_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_TINFO_width(context));
+	switch (offset) {
+	case CSR_TINFO_INFO_OFFSET:
+		return (value & ((unsigned long long)0xffff << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *CSR_TINFO_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int CSR_TCONTROL_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return (7 > (context.XLEN.value + -1) ? 7 : (context.XLEN.value + -1) + 1);
+}
+
+static unsigned int CSR_TCONTROL_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TCONTROL_MPTE_OFFSET:
+	case CSR_TCONTROL_MTE_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *CSR_TCONTROL_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TCONTROL_MPTE_OFFSET:
+		return "mpte";
+	case CSR_TCONTROL_MTE_OFFSET:
+		return "mte";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_TCONTROL_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_TCONTROL_width(context));
+	switch (offset) {
+	case CSR_TCONTROL_MPTE_OFFSET:
+	case CSR_TCONTROL_MTE_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *CSR_TCONTROL_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TCONTROL_MTE_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "disabled";
+		case 1:
+			return "enabled";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int CSR_HCONTEXT_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return context.XLEN.value;
+}
+
+static unsigned int CSR_HCONTEXT_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return 1;
+	return 0;
+}
+
+static const char *CSR_HCONTEXT_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return NULL;
+	if (offset == 0)
+		return "hcontext";
+	return NULL;
+}
+
+static unsigned long long CSR_HCONTEXT_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_HCONTEXT_width(context));
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return (value & ((unsigned long long)((1ULL << context.XLEN.value) + -1) << offset)) >> offset;
+	return 0;
+}
+
+static const char *CSR_HCONTEXT_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int CSR_SCONTEXT_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return context.XLEN.value;
+}
+
+static unsigned int CSR_SCONTEXT_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return 1;
+	return 0;
+}
+
+static const char *CSR_SCONTEXT_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return NULL;
+	if (offset == 0)
+		return "data";
+	return NULL;
+}
+
+static unsigned long long CSR_SCONTEXT_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_SCONTEXT_width(context));
+	if (!(context.XLEN.is_set))
+		return 0;
+	if (offset == 0)
+		return (value & ((unsigned long long)((1ULL << context.XLEN.value) + -1) << offset)) >> offset;
+	return 0;
+}
+
+static const char *CSR_SCONTEXT_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int CSR_MCONTROL_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return (0x16 > (context.XLEN.value + -1) ? 0x16 : (context.XLEN.value + -1) + 1);
+}
+
+static unsigned int CSR_MCONTROL_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_MCONTROL_SIZEHI_OFFSET:
+	case CSR_MCONTROL_HIT_OFFSET:
+	case CSR_MCONTROL_SELECT_OFFSET:
+	case CSR_MCONTROL_TIMING_OFFSET:
+	case CSR_MCONTROL_SIZELO_OFFSET:
+	case CSR_MCONTROL_ACTION_OFFSET:
+	case CSR_MCONTROL_CHAIN_OFFSET:
+	case CSR_MCONTROL_MATCH_OFFSET:
+	case CSR_MCONTROL_M_OFFSET:
+	case CSR_MCONTROL_S_OFFSET:
+	case CSR_MCONTROL_U_OFFSET:
+	case CSR_MCONTROL_EXECUTE_OFFSET:
+	case CSR_MCONTROL_STORE_OFFSET:
+	case CSR_MCONTROL_LOAD_OFFSET:
+		return 1;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return 1;
+		if (offset == (context.XLEN.value + -5))
+			return 1;
+		if (offset == (context.XLEN.value + -0xb))
+			return 1;
+		return 0;
+	}
+}
+
+static const char *CSR_MCONTROL_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_MCONTROL_SIZEHI_OFFSET:
+		return "sizehi";
+	case CSR_MCONTROL_HIT_OFFSET:
+		return "hit";
+	case CSR_MCONTROL_SELECT_OFFSET:
+		return "select";
+	case CSR_MCONTROL_TIMING_OFFSET:
+		return "timing";
+	case CSR_MCONTROL_SIZELO_OFFSET:
+		return "sizelo";
+	case CSR_MCONTROL_ACTION_OFFSET:
+		return "action";
+	case CSR_MCONTROL_CHAIN_OFFSET:
+		return "chain";
+	case CSR_MCONTROL_MATCH_OFFSET:
+		return "match";
+	case CSR_MCONTROL_M_OFFSET:
+		return "m";
+	case CSR_MCONTROL_S_OFFSET:
+		return "s";
+	case CSR_MCONTROL_U_OFFSET:
+		return "u";
+	case CSR_MCONTROL_EXECUTE_OFFSET:
+		return "execute";
+	case CSR_MCONTROL_STORE_OFFSET:
+		return "store";
+	case CSR_MCONTROL_LOAD_OFFSET:
+		return "load";
+	default:
+		if (!(context.XLEN.is_set))
+			return NULL;
+		if (offset == (context.XLEN.value + -4))
+			return "type";
+		if (offset == (context.XLEN.value + -5))
+			return "dmode";
+		if (offset == (context.XLEN.value + -0xb))
+			return "maskmax";
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_MCONTROL_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_MCONTROL_width(context));
+	switch (offset) {
+	case CSR_MCONTROL_SIZEHI_OFFSET:
+	case CSR_MCONTROL_SIZELO_OFFSET:
+		return (value & ((unsigned long long)3 << offset)) >> offset;
+	case CSR_MCONTROL_HIT_OFFSET:
+	case CSR_MCONTROL_SELECT_OFFSET:
+	case CSR_MCONTROL_TIMING_OFFSET:
+	case CSR_MCONTROL_CHAIN_OFFSET:
+	case CSR_MCONTROL_M_OFFSET:
+	case CSR_MCONTROL_S_OFFSET:
+	case CSR_MCONTROL_U_OFFSET:
+	case CSR_MCONTROL_EXECUTE_OFFSET:
+	case CSR_MCONTROL_STORE_OFFSET:
+	case CSR_MCONTROL_LOAD_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case CSR_MCONTROL_ACTION_OFFSET:
+	case CSR_MCONTROL_MATCH_OFFSET:
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return (value & ((unsigned long long)0xf << offset)) >> offset;
+		if (offset == (context.XLEN.value + -5))
+			return (value & ((unsigned long long)1 << offset)) >> offset;
+		if (offset == (context.XLEN.value + -0xb))
+			return (value & ((unsigned long long)0x3f << offset)) >> offset;
+		return 0;
+	}
+}
+
+static const char *CSR_MCONTROL_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_MCONTROL_SELECT_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "address";
+		case 1:
+			return "data";
+		default:
+			return NULL;
+		}
+	case CSR_MCONTROL_TIMING_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "before";
+		case 1:
+			return "after";
+		default:
+			return NULL;
+		}
+	case CSR_MCONTROL_SIZELO_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "any";
+		case 1:
+			return "8bit";
+		case 2:
+			return "16bit";
+		case 3:
+			return "32bit";
+		case 4:
+			return "48bit";
+		case 5:
+			return "64bit";
+		case 6:
+			return "80bit";
+		case 7:
+			return "96bit";
+		case 8:
+			return "112bit";
+		case 9:
+			return "128bit";
+		default:
+			return NULL;
+		}
+	case CSR_MCONTROL_ACTION_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "breakpoint";
+		case 1:
+			return "debug mode";
+		case 2:
+			return "trace on";
+		case 3:
+			return "trace off";
+		case 4:
+			return "trace notify";
+		case 8:
+			return "external0";
+		case 9:
+			return "external1";
+		default:
+			return NULL;
+		}
+	case CSR_MCONTROL_CHAIN_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "disabled";
+		case 1:
+			return "enabled";
+		default:
+			return NULL;
+		}
+	case CSR_MCONTROL_MATCH_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "equal";
+		case 1:
+			return "napot";
+		case 2:
+			return "ge";
+		case 3:
+			return "lt";
+		case 4:
+			return "mask low";
+		case 5:
+			return "mask high";
+		case 8:
+			return "not equal";
+		case 9:
+			return "not napot";
+		case 12:
+			return "not mask low";
+		case 13:
+			return "not mask high";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int CSR_MCONTROL6_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return (0x18 > (context.XLEN.value + -1) ? 0x18 : (context.XLEN.value + -1) + 1);
+}
+
+static unsigned int CSR_MCONTROL6_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_MCONTROL6_VS_OFFSET:
+	case CSR_MCONTROL6_VU_OFFSET:
+	case CSR_MCONTROL6_HIT_OFFSET:
+	case CSR_MCONTROL6_SELECT_OFFSET:
+	case CSR_MCONTROL6_TIMING_OFFSET:
+	case CSR_MCONTROL6_SIZE_OFFSET:
+	case CSR_MCONTROL6_ACTION_OFFSET:
+	case CSR_MCONTROL6_CHAIN_OFFSET:
+	case CSR_MCONTROL6_MATCH_OFFSET:
+	case CSR_MCONTROL6_M_OFFSET:
+	case CSR_MCONTROL6_S_OFFSET:
+	case CSR_MCONTROL6_U_OFFSET:
+	case CSR_MCONTROL6_EXECUTE_OFFSET:
+	case CSR_MCONTROL6_STORE_OFFSET:
+	case CSR_MCONTROL6_LOAD_OFFSET:
+		return 1;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return 1;
+		if (offset == (context.XLEN.value + -5))
+			return 1;
+		return 0;
+	}
+}
+
+static const char *CSR_MCONTROL6_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_MCONTROL6_VS_OFFSET:
+		return "vs";
+	case CSR_MCONTROL6_VU_OFFSET:
+		return "vu";
+	case CSR_MCONTROL6_HIT_OFFSET:
+		return "hit";
+	case CSR_MCONTROL6_SELECT_OFFSET:
+		return "select";
+	case CSR_MCONTROL6_TIMING_OFFSET:
+		return "timing";
+	case CSR_MCONTROL6_SIZE_OFFSET:
+		return "size";
+	case CSR_MCONTROL6_ACTION_OFFSET:
+		return "action";
+	case CSR_MCONTROL6_CHAIN_OFFSET:
+		return "chain";
+	case CSR_MCONTROL6_MATCH_OFFSET:
+		return "match";
+	case CSR_MCONTROL6_M_OFFSET:
+		return "m";
+	case CSR_MCONTROL6_S_OFFSET:
+		return "s";
+	case CSR_MCONTROL6_U_OFFSET:
+		return "u";
+	case CSR_MCONTROL6_EXECUTE_OFFSET:
+		return "execute";
+	case CSR_MCONTROL6_STORE_OFFSET:
+		return "store";
+	case CSR_MCONTROL6_LOAD_OFFSET:
+		return "load";
+	default:
+		if (!(context.XLEN.is_set))
+			return NULL;
+		if (offset == (context.XLEN.value + -4))
+			return "type";
+		if (offset == (context.XLEN.value + -5))
+			return "dmode";
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_MCONTROL6_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_MCONTROL6_width(context));
+	switch (offset) {
+	case CSR_MCONTROL6_VS_OFFSET:
+	case CSR_MCONTROL6_VU_OFFSET:
+	case CSR_MCONTROL6_HIT_OFFSET:
+	case CSR_MCONTROL6_SELECT_OFFSET:
+	case CSR_MCONTROL6_TIMING_OFFSET:
+	case CSR_MCONTROL6_CHAIN_OFFSET:
+	case CSR_MCONTROL6_M_OFFSET:
+	case CSR_MCONTROL6_S_OFFSET:
+	case CSR_MCONTROL6_U_OFFSET:
+	case CSR_MCONTROL6_EXECUTE_OFFSET:
+	case CSR_MCONTROL6_STORE_OFFSET:
+	case CSR_MCONTROL6_LOAD_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case CSR_MCONTROL6_SIZE_OFFSET:
+	case CSR_MCONTROL6_ACTION_OFFSET:
+	case CSR_MCONTROL6_MATCH_OFFSET:
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return (value & ((unsigned long long)0xf << offset)) >> offset;
+		if (offset == (context.XLEN.value + -5))
+			return (value & ((unsigned long long)1 << offset)) >> offset;
+		return 0;
+	}
+}
+
+static const char *CSR_MCONTROL6_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_MCONTROL6_SELECT_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "address";
+		case 1:
+			return "data";
+		default:
+			return NULL;
+		}
+	case CSR_MCONTROL6_TIMING_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "before";
+		case 1:
+			return "after";
+		default:
+			return NULL;
+		}
+	case CSR_MCONTROL6_SIZE_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "any";
+		case 1:
+			return "8bit";
+		case 2:
+			return "16bit";
+		case 3:
+			return "32bit";
+		case 4:
+			return "48bit";
+		case 5:
+			return "64bit";
+		case 6:
+			return "80bit";
+		case 7:
+			return "96bit";
+		case 8:
+			return "112bit";
+		case 9:
+			return "128bit";
+		default:
+			return NULL;
+		}
+	case CSR_MCONTROL6_ACTION_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "breakpoint";
+		case 1:
+			return "debug mode";
+		case 2:
+			return "trace on";
+		case 3:
+			return "trace off";
+		case 4:
+			return "trace notify";
+		case 8:
+			return "external0";
+		case 9:
+			return "external1";
+		default:
+			return NULL;
+		}
+	case CSR_MCONTROL6_CHAIN_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "disabled";
+		case 1:
+			return "enabled";
+		default:
+			return NULL;
+		}
+	case CSR_MCONTROL6_MATCH_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "equal";
+		case 1:
+			return "napot";
+		case 2:
+			return "ge";
+		case 3:
+			return "lt";
+		case 4:
+			return "mask low";
+		case 5:
+			return "mask high";
+		case 8:
+			return "not equal";
+		case 9:
+			return "not napot";
+		case 12:
+			return "not mask low";
+		case 13:
+			return "not mask high";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int CSR_ICOUNT_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return (0x1a > (context.XLEN.value + -1) ? 0x1a : (context.XLEN.value + -1) + 1);
+}
+
+static unsigned int CSR_ICOUNT_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_ICOUNT_VS_OFFSET:
+	case CSR_ICOUNT_VU_OFFSET:
+	case CSR_ICOUNT_HIT_OFFSET:
+	case CSR_ICOUNT_COUNT_OFFSET:
+	case CSR_ICOUNT_M_OFFSET:
+	case CSR_ICOUNT_PENDING_OFFSET:
+	case CSR_ICOUNT_S_OFFSET:
+	case CSR_ICOUNT_U_OFFSET:
+	case CSR_ICOUNT_ACTION_OFFSET:
+		return 1;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return 1;
+		if (offset == (context.XLEN.value + -5))
+			return 1;
+		return 0;
+	}
+}
+
+static const char *CSR_ICOUNT_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_ICOUNT_VS_OFFSET:
+		return "vs";
+	case CSR_ICOUNT_VU_OFFSET:
+		return "vu";
+	case CSR_ICOUNT_HIT_OFFSET:
+		return "hit";
+	case CSR_ICOUNT_COUNT_OFFSET:
+		return "count";
+	case CSR_ICOUNT_M_OFFSET:
+		return "m";
+	case CSR_ICOUNT_PENDING_OFFSET:
+		return "pending";
+	case CSR_ICOUNT_S_OFFSET:
+		return "s";
+	case CSR_ICOUNT_U_OFFSET:
+		return "u";
+	case CSR_ICOUNT_ACTION_OFFSET:
+		return "action";
+	default:
+		if (!(context.XLEN.is_set))
+			return NULL;
+		if (offset == (context.XLEN.value + -4))
+			return "type";
+		if (offset == (context.XLEN.value + -5))
+			return "dmode";
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_ICOUNT_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_ICOUNT_width(context));
+	switch (offset) {
+	case CSR_ICOUNT_VS_OFFSET:
+	case CSR_ICOUNT_VU_OFFSET:
+	case CSR_ICOUNT_HIT_OFFSET:
+	case CSR_ICOUNT_M_OFFSET:
+	case CSR_ICOUNT_PENDING_OFFSET:
+	case CSR_ICOUNT_S_OFFSET:
+	case CSR_ICOUNT_U_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case CSR_ICOUNT_COUNT_OFFSET:
+		return (value & ((unsigned long long)0x3fff << offset)) >> offset;
+	case CSR_ICOUNT_ACTION_OFFSET:
+		return (value & ((unsigned long long)0x3f << offset)) >> offset;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return (value & ((unsigned long long)0xf << offset)) >> offset;
+		if (offset == (context.XLEN.value + -5))
+			return (value & ((unsigned long long)1 << offset)) >> offset;
+		return 0;
+	}
+}
+
+static const char *CSR_ICOUNT_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_ICOUNT_ACTION_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "breakpoint";
+		case 1:
+			return "debug mode";
+		case 2:
+			return "trace on";
+		case 3:
+			return "trace off";
+		case 4:
+			return "trace notify";
+		case 8:
+			return "external0";
+		case 9:
+			return "external1";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int CSR_ITRIGGER_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return (0xc > (context.XLEN.value + -1) ? 0xc : (context.XLEN.value + -1) + 1);
+}
+
+static unsigned int CSR_ITRIGGER_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_ITRIGGER_VS_OFFSET:
+	case CSR_ITRIGGER_VU_OFFSET:
+	case CSR_ITRIGGER_NMI_OFFSET:
+	case CSR_ITRIGGER_M_OFFSET:
+	case CSR_ITRIGGER_S_OFFSET:
+	case CSR_ITRIGGER_U_OFFSET:
+	case CSR_ITRIGGER_ACTION_OFFSET:
+		return 1;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return 1;
+		if (offset == (context.XLEN.value + -5))
+			return 1;
+		if (offset == (context.XLEN.value + -6))
+			return 1;
+		return 0;
+	}
+}
+
+static const char *CSR_ITRIGGER_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_ITRIGGER_VS_OFFSET:
+		return "vs";
+	case CSR_ITRIGGER_VU_OFFSET:
+		return "vu";
+	case CSR_ITRIGGER_NMI_OFFSET:
+		return "nmi";
+	case CSR_ITRIGGER_M_OFFSET:
+		return "m";
+	case CSR_ITRIGGER_S_OFFSET:
+		return "s";
+	case CSR_ITRIGGER_U_OFFSET:
+		return "u";
+	case CSR_ITRIGGER_ACTION_OFFSET:
+		return "action";
+	default:
+		if (!(context.XLEN.is_set))
+			return NULL;
+		if (offset == (context.XLEN.value + -4))
+			return "type";
+		if (offset == (context.XLEN.value + -5))
+			return "dmode";
+		if (offset == (context.XLEN.value + -6))
+			return "hit";
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_ITRIGGER_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_ITRIGGER_width(context));
+	switch (offset) {
+	case CSR_ITRIGGER_VS_OFFSET:
+	case CSR_ITRIGGER_VU_OFFSET:
+	case CSR_ITRIGGER_NMI_OFFSET:
+	case CSR_ITRIGGER_M_OFFSET:
+	case CSR_ITRIGGER_S_OFFSET:
+	case CSR_ITRIGGER_U_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case CSR_ITRIGGER_ACTION_OFFSET:
+		return (value & ((unsigned long long)0x3f << offset)) >> offset;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return (value & ((unsigned long long)0xf << offset)) >> offset;
+		if (offset == (context.XLEN.value + -5))
+			return (value & ((unsigned long long)1 << offset)) >> offset;
+		if (offset == (context.XLEN.value + -6))
+			return (value & ((unsigned long long)1 << offset)) >> offset;
+		return 0;
+	}
+}
+
+static const char *CSR_ITRIGGER_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_ITRIGGER_ACTION_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "breakpoint";
+		case 1:
+			return "debug mode";
+		case 2:
+			return "trace on";
+		case 3:
+			return "trace off";
+		case 4:
+			return "trace notify";
+		case 8:
+			return "external0";
+		case 9:
+			return "external1";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int CSR_ETRIGGER_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return (0xc > (context.XLEN.value + -1) ? 0xc : (context.XLEN.value + -1) + 1);
+}
+
+static unsigned int CSR_ETRIGGER_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_ETRIGGER_VS_OFFSET:
+	case CSR_ETRIGGER_VU_OFFSET:
+	case CSR_ETRIGGER_M_OFFSET:
+	case CSR_ETRIGGER_S_OFFSET:
+	case CSR_ETRIGGER_U_OFFSET:
+	case CSR_ETRIGGER_ACTION_OFFSET:
+		return 1;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return 1;
+		if (offset == (context.XLEN.value + -5))
+			return 1;
+		if (offset == (context.XLEN.value + -6))
+			return 1;
+		return 0;
+	}
+}
+
+static const char *CSR_ETRIGGER_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_ETRIGGER_VS_OFFSET:
+		return "vs";
+	case CSR_ETRIGGER_VU_OFFSET:
+		return "vu";
+	case CSR_ETRIGGER_M_OFFSET:
+		return "m";
+	case CSR_ETRIGGER_S_OFFSET:
+		return "s";
+	case CSR_ETRIGGER_U_OFFSET:
+		return "u";
+	case CSR_ETRIGGER_ACTION_OFFSET:
+		return "action";
+	default:
+		if (!(context.XLEN.is_set))
+			return NULL;
+		if (offset == (context.XLEN.value + -4))
+			return "type";
+		if (offset == (context.XLEN.value + -5))
+			return "dmode";
+		if (offset == (context.XLEN.value + -6))
+			return "hit";
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_ETRIGGER_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_ETRIGGER_width(context));
+	switch (offset) {
+	case CSR_ETRIGGER_VS_OFFSET:
+	case CSR_ETRIGGER_VU_OFFSET:
+	case CSR_ETRIGGER_M_OFFSET:
+	case CSR_ETRIGGER_S_OFFSET:
+	case CSR_ETRIGGER_U_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case CSR_ETRIGGER_ACTION_OFFSET:
+		return (value & ((unsigned long long)0x3f << offset)) >> offset;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return (value & ((unsigned long long)0xf << offset)) >> offset;
+		if (offset == (context.XLEN.value + -5))
+			return (value & ((unsigned long long)1 << offset)) >> offset;
+		if (offset == (context.XLEN.value + -6))
+			return (value & ((unsigned long long)1 << offset)) >> offset;
+		return 0;
+	}
+}
+
+static const char *CSR_ETRIGGER_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_ETRIGGER_ACTION_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "breakpoint";
+		case 1:
+			return "debug mode";
+		case 2:
+			return "trace on";
+		case 3:
+			return "trace off";
+		case 4:
+			return "trace notify";
+		case 8:
+			return "external0";
+		case 9:
+			return "external1";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int CSR_TMEXTTRIGGER_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	if (!(context.XLEN.is_set))
+		return 0;
+	return (0x16 > (context.XLEN.value + -1) ? 0x16 : (context.XLEN.value + -1) + 1);
+}
+
+static unsigned int CSR_TMEXTTRIGGER_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TMEXTTRIGGER_INTCTL_OFFSET:
+	case CSR_TMEXTTRIGGER_SELECT_OFFSET:
+	case CSR_TMEXTTRIGGER_ACTION_OFFSET:
+		return 1;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return 1;
+		if (offset == (context.XLEN.value + -5))
+			return 1;
+		if (offset == (context.XLEN.value + -6))
+			return 1;
+		return 0;
+	}
+}
+
+static const char *CSR_TMEXTTRIGGER_field_name(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TMEXTTRIGGER_INTCTL_OFFSET:
+		return "intctl";
+	case CSR_TMEXTTRIGGER_SELECT_OFFSET:
+		return "select";
+	case CSR_TMEXTTRIGGER_ACTION_OFFSET:
+		return "action";
+	default:
+		if (!(context.XLEN.is_set))
+			return NULL;
+		if (offset == (context.XLEN.value + -4))
+			return "type";
+		if (offset == (context.XLEN.value + -5))
+			return "dmode";
+		if (offset == (context.XLEN.value + -6))
+			return "hit";
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_TMEXTTRIGGER_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_TMEXTTRIGGER_width(context));
+	switch (offset) {
+	case CSR_TMEXTTRIGGER_INTCTL_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case CSR_TMEXTTRIGGER_SELECT_OFFSET:
+		return (value & ((unsigned long long)0xffff << offset)) >> offset;
+	case CSR_TMEXTTRIGGER_ACTION_OFFSET:
+		return (value & ((unsigned long long)0x3f << offset)) >> offset;
+	default:
+		if (!(context.XLEN.is_set))
+			return 0;
+		if (offset == (context.XLEN.value + -4))
+			return (value & ((unsigned long long)0xf << offset)) >> offset;
+		if (offset == (context.XLEN.value + -5))
+			return (value & ((unsigned long long)1 << offset)) >> offset;
+		if (offset == (context.XLEN.value + -6))
+			return (value & ((unsigned long long)1 << offset)) >> offset;
+		return 0;
+	}
+}
+
+static const char *CSR_TMEXTTRIGGER_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TMEXTTRIGGER_ACTION_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "breakpoint";
+		case 1:
+			return "debug mode";
+		case 2:
+			return "trace on";
+		case 3:
+			return "trace off";
+		case 4:
+			return "trace notify";
+		case 8:
+			return "external0";
+		case 9:
+			return "external1";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int CSR_TEXTRA32_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int CSR_TEXTRA32_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TEXTRA32_MHVALUE_OFFSET:
+	case CSR_TEXTRA32_MHSELECT_OFFSET:
+	case CSR_TEXTRA32_SBYTEMASK_OFFSET:
+	case CSR_TEXTRA32_SVALUE_OFFSET:
+	case CSR_TEXTRA32_SSELECT_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *CSR_TEXTRA32_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TEXTRA32_MHVALUE_OFFSET:
+		return "mhvalue";
+	case CSR_TEXTRA32_MHSELECT_OFFSET:
+		return "mhselect";
+	case CSR_TEXTRA32_SBYTEMASK_OFFSET:
+		return "sbytemask";
+	case CSR_TEXTRA32_SVALUE_OFFSET:
+		return "svalue";
+	case CSR_TEXTRA32_SSELECT_OFFSET:
+		return "sselect";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_TEXTRA32_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_TEXTRA32_width(context));
+	switch (offset) {
+	case CSR_TEXTRA32_MHVALUE_OFFSET:
+		return (value & ((unsigned long long)0x3f << offset)) >> offset;
+	case CSR_TEXTRA32_MHSELECT_OFFSET:
+		return (value & ((unsigned long long)7 << offset)) >> offset;
+	case CSR_TEXTRA32_SBYTEMASK_OFFSET:
+	case CSR_TEXTRA32_SSELECT_OFFSET:
+		return (value & ((unsigned long long)3 << offset)) >> offset;
+	case CSR_TEXTRA32_SVALUE_OFFSET:
+		return (value & ((unsigned long long)0xffff << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *CSR_TEXTRA32_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TEXTRA32_MHSELECT_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "ignore";
+		case 4:
+			return "mcontext";
+		default:
+			return NULL;
+		}
+	case CSR_TEXTRA32_SSELECT_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "ignore";
+		case 1:
+			return "scontext";
+		case 2:
+			return "asid";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int CSR_TEXTRA64_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x40;
+}
+
+static unsigned int CSR_TEXTRA64_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TEXTRA64_MHVALUE_OFFSET:
+	case CSR_TEXTRA64_MHSELECT_OFFSET:
+	case CSR_TEXTRA64_SBYTEMASK_OFFSET:
+	case CSR_TEXTRA64_SVALUE_OFFSET:
+	case CSR_TEXTRA64_SSELECT_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *CSR_TEXTRA64_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case CSR_TEXTRA64_MHVALUE_OFFSET:
+		return "mhvalue";
+	case CSR_TEXTRA64_MHSELECT_OFFSET:
+		return "mhselect";
+	case CSR_TEXTRA64_SBYTEMASK_OFFSET:
+		return "sbytemask";
+	case CSR_TEXTRA64_SVALUE_OFFSET:
+		return "svalue";
+	case CSR_TEXTRA64_SSELECT_OFFSET:
+		return "sselect";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long CSR_TEXTRA64_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < CSR_TEXTRA64_width(context));
+	switch (offset) {
+	case CSR_TEXTRA64_MHVALUE_OFFSET:
+		return (value & ((unsigned long long)0x1fff << offset)) >> offset;
+	case CSR_TEXTRA64_MHSELECT_OFFSET:
+		return (value & ((unsigned long long)7 << offset)) >> offset;
+	case CSR_TEXTRA64_SBYTEMASK_OFFSET:
+		return (value & ((unsigned long long)0x1f << offset)) >> offset;
+	case CSR_TEXTRA64_SVALUE_OFFSET:
+		return (value & ((unsigned long long)0x3ffffffffULL << offset)) >> offset;
+	case CSR_TEXTRA64_SSELECT_OFFSET:
+		return (value & ((unsigned long long)3 << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *CSR_TEXTRA64_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_DMSTATUS_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_DMSTATUS_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DMSTATUS_NDMRESETPENDING_OFFSET:
+	case DM_DMSTATUS_STICKYUNAVAIL_OFFSET:
+	case DM_DMSTATUS_IMPEBREAK_OFFSET:
+	case DM_DMSTATUS_ALLHAVERESET_OFFSET:
+	case DM_DMSTATUS_ANYHAVERESET_OFFSET:
+	case DM_DMSTATUS_ALLRESUMEACK_OFFSET:
+	case DM_DMSTATUS_ANYRESUMEACK_OFFSET:
+	case DM_DMSTATUS_ALLNONEXISTENT_OFFSET:
+	case DM_DMSTATUS_ANYNONEXISTENT_OFFSET:
+	case DM_DMSTATUS_ALLUNAVAIL_OFFSET:
+	case DM_DMSTATUS_ANYUNAVAIL_OFFSET:
+	case DM_DMSTATUS_ALLRUNNING_OFFSET:
+	case DM_DMSTATUS_ANYRUNNING_OFFSET:
+	case DM_DMSTATUS_ALLHALTED_OFFSET:
+	case DM_DMSTATUS_ANYHALTED_OFFSET:
+	case DM_DMSTATUS_AUTHENTICATED_OFFSET:
+	case DM_DMSTATUS_AUTHBUSY_OFFSET:
+	case DM_DMSTATUS_HASRESETHALTREQ_OFFSET:
+	case DM_DMSTATUS_CONFSTRPTRVALID_OFFSET:
+	case DM_DMSTATUS_VERSION_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_DMSTATUS_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DMSTATUS_NDMRESETPENDING_OFFSET:
+		return "ndmresetpending";
+	case DM_DMSTATUS_STICKYUNAVAIL_OFFSET:
+		return "stickyunavail";
+	case DM_DMSTATUS_IMPEBREAK_OFFSET:
+		return "impebreak";
+	case DM_DMSTATUS_ALLHAVERESET_OFFSET:
+		return "allhavereset";
+	case DM_DMSTATUS_ANYHAVERESET_OFFSET:
+		return "anyhavereset";
+	case DM_DMSTATUS_ALLRESUMEACK_OFFSET:
+		return "allresumeack";
+	case DM_DMSTATUS_ANYRESUMEACK_OFFSET:
+		return "anyresumeack";
+	case DM_DMSTATUS_ALLNONEXISTENT_OFFSET:
+		return "allnonexistent";
+	case DM_DMSTATUS_ANYNONEXISTENT_OFFSET:
+		return "anynonexistent";
+	case DM_DMSTATUS_ALLUNAVAIL_OFFSET:
+		return "allunavail";
+	case DM_DMSTATUS_ANYUNAVAIL_OFFSET:
+		return "anyunavail";
+	case DM_DMSTATUS_ALLRUNNING_OFFSET:
+		return "allrunning";
+	case DM_DMSTATUS_ANYRUNNING_OFFSET:
+		return "anyrunning";
+	case DM_DMSTATUS_ALLHALTED_OFFSET:
+		return "allhalted";
+	case DM_DMSTATUS_ANYHALTED_OFFSET:
+		return "anyhalted";
+	case DM_DMSTATUS_AUTHENTICATED_OFFSET:
+		return "authenticated";
+	case DM_DMSTATUS_AUTHBUSY_OFFSET:
+		return "authbusy";
+	case DM_DMSTATUS_HASRESETHALTREQ_OFFSET:
+		return "hasresethaltreq";
+	case DM_DMSTATUS_CONFSTRPTRVALID_OFFSET:
+		return "confstrptrvalid";
+	case DM_DMSTATUS_VERSION_OFFSET:
+		return "version";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_DMSTATUS_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_DMSTATUS_width(context));
+	switch (offset) {
+	case DM_DMSTATUS_NDMRESETPENDING_OFFSET:
+	case DM_DMSTATUS_STICKYUNAVAIL_OFFSET:
+	case DM_DMSTATUS_IMPEBREAK_OFFSET:
+	case DM_DMSTATUS_ALLHAVERESET_OFFSET:
+	case DM_DMSTATUS_ANYHAVERESET_OFFSET:
+	case DM_DMSTATUS_ALLRESUMEACK_OFFSET:
+	case DM_DMSTATUS_ANYRESUMEACK_OFFSET:
+	case DM_DMSTATUS_ALLNONEXISTENT_OFFSET:
+	case DM_DMSTATUS_ANYNONEXISTENT_OFFSET:
+	case DM_DMSTATUS_ALLUNAVAIL_OFFSET:
+	case DM_DMSTATUS_ANYUNAVAIL_OFFSET:
+	case DM_DMSTATUS_ALLRUNNING_OFFSET:
+	case DM_DMSTATUS_ANYRUNNING_OFFSET:
+	case DM_DMSTATUS_ALLHALTED_OFFSET:
+	case DM_DMSTATUS_ANYHALTED_OFFSET:
+	case DM_DMSTATUS_AUTHENTICATED_OFFSET:
+	case DM_DMSTATUS_AUTHBUSY_OFFSET:
+	case DM_DMSTATUS_HASRESETHALTREQ_OFFSET:
+	case DM_DMSTATUS_CONFSTRPTRVALID_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case DM_DMSTATUS_VERSION_OFFSET:
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_DMSTATUS_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DMSTATUS_NDMRESETPENDING_OFFSET:
+	case DM_DMSTATUS_AUTHENTICATED_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "false";
+		case 1:
+			return "true";
+		default:
+			return NULL;
+		}
+	case DM_DMSTATUS_STICKYUNAVAIL_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "current";
+		case 1:
+			return "sticky";
+		default:
+			return NULL;
+		}
+	case DM_DMSTATUS_AUTHBUSY_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "ready";
+		case 1:
+			return "busy";
+		default:
+			return NULL;
+		}
+	case DM_DMSTATUS_CONFSTRPTRVALID_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "invalid";
+		case 1:
+			return "valid";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int DM_DMCONTROL_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_DMCONTROL_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DMCONTROL_HALTREQ_OFFSET:
+	case DM_DMCONTROL_RESUMEREQ_OFFSET:
+	case DM_DMCONTROL_HARTRESET_OFFSET:
+	case DM_DMCONTROL_ACKHAVERESET_OFFSET:
+	case DM_DMCONTROL_ACKUNAVAIL_OFFSET:
+	case DM_DMCONTROL_HASEL_OFFSET:
+	case DM_DMCONTROL_HARTSELLO_OFFSET:
+	case DM_DMCONTROL_HARTSELHI_OFFSET:
+	case DM_DMCONTROL_SETKEEPALIVE_OFFSET:
+	case DM_DMCONTROL_CLRKEEPALIVE_OFFSET:
+	case DM_DMCONTROL_SETRESETHALTREQ_OFFSET:
+	case DM_DMCONTROL_CLRRESETHALTREQ_OFFSET:
+	case DM_DMCONTROL_NDMRESET_OFFSET:
+	case DM_DMCONTROL_DMACTIVE_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_DMCONTROL_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DMCONTROL_HALTREQ_OFFSET:
+		return "haltreq";
+	case DM_DMCONTROL_RESUMEREQ_OFFSET:
+		return "resumereq";
+	case DM_DMCONTROL_HARTRESET_OFFSET:
+		return "hartreset";
+	case DM_DMCONTROL_ACKHAVERESET_OFFSET:
+		return "ackhavereset";
+	case DM_DMCONTROL_ACKUNAVAIL_OFFSET:
+		return "ackunavail";
+	case DM_DMCONTROL_HASEL_OFFSET:
+		return "hasel";
+	case DM_DMCONTROL_HARTSELLO_OFFSET:
+		return "hartsello";
+	case DM_DMCONTROL_HARTSELHI_OFFSET:
+		return "hartselhi";
+	case DM_DMCONTROL_SETKEEPALIVE_OFFSET:
+		return "setkeepalive";
+	case DM_DMCONTROL_CLRKEEPALIVE_OFFSET:
+		return "clrkeepalive";
+	case DM_DMCONTROL_SETRESETHALTREQ_OFFSET:
+		return "setresethaltreq";
+	case DM_DMCONTROL_CLRRESETHALTREQ_OFFSET:
+		return "clrresethaltreq";
+	case DM_DMCONTROL_NDMRESET_OFFSET:
+		return "ndmreset";
+	case DM_DMCONTROL_DMACTIVE_OFFSET:
+		return "dmactive";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_DMCONTROL_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_DMCONTROL_width(context));
+	switch (offset) {
+	case DM_DMCONTROL_HALTREQ_OFFSET:
+	case DM_DMCONTROL_RESUMEREQ_OFFSET:
+	case DM_DMCONTROL_HARTRESET_OFFSET:
+	case DM_DMCONTROL_ACKHAVERESET_OFFSET:
+	case DM_DMCONTROL_ACKUNAVAIL_OFFSET:
+	case DM_DMCONTROL_HASEL_OFFSET:
+	case DM_DMCONTROL_SETKEEPALIVE_OFFSET:
+	case DM_DMCONTROL_CLRKEEPALIVE_OFFSET:
+	case DM_DMCONTROL_SETRESETHALTREQ_OFFSET:
+	case DM_DMCONTROL_CLRRESETHALTREQ_OFFSET:
+	case DM_DMCONTROL_NDMRESET_OFFSET:
+	case DM_DMCONTROL_DMACTIVE_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case DM_DMCONTROL_HARTSELLO_OFFSET:
+	case DM_DMCONTROL_HARTSELHI_OFFSET:
+		return (value & ((unsigned long long)0x3ff << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_DMCONTROL_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DMCONTROL_ACKHAVERESET_OFFSET:
+	case DM_DMCONTROL_ACKUNAVAIL_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "nop";
+		case 1:
+			return "ack";
+		default:
+			return NULL;
+		}
+	case DM_DMCONTROL_HASEL_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "single";
+		case 1:
+			return "multiple";
+		default:
+			return NULL;
+		}
+	case DM_DMCONTROL_DMACTIVE_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "inactive";
+		case 1:
+			return "active";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int DM_HARTINFO_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_HARTINFO_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HARTINFO_NSCRATCH_OFFSET:
+	case DM_HARTINFO_DATAACCESS_OFFSET:
+	case DM_HARTINFO_DATASIZE_OFFSET:
+	case DM_HARTINFO_DATAADDR_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HARTINFO_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HARTINFO_NSCRATCH_OFFSET:
+		return "nscratch";
+	case DM_HARTINFO_DATAACCESS_OFFSET:
+		return "dataaccess";
+	case DM_HARTINFO_DATASIZE_OFFSET:
+		return "datasize";
+	case DM_HARTINFO_DATAADDR_OFFSET:
+		return "dataaddr";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_HARTINFO_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_HARTINFO_width(context));
+	switch (offset) {
+	case DM_HARTINFO_NSCRATCH_OFFSET:
+	case DM_HARTINFO_DATASIZE_OFFSET:
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	case DM_HARTINFO_DATAACCESS_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case DM_HARTINFO_DATAADDR_OFFSET:
+		return (value & ((unsigned long long)0xfff << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HARTINFO_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HARTINFO_DATAACCESS_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "csr";
+		case 1:
+			return "memory";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int DM_HAWINDOWSEL_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_HAWINDOWSEL_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HAWINDOWSEL_field_name(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET:
+		return "hawindowsel";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_HAWINDOWSEL_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_HAWINDOWSEL_width(context));
+	switch (offset) {
+	case DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET:
+		return (value & ((unsigned long long)0x7fff << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HAWINDOWSEL_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_HAWINDOW_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_HAWINDOW_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HAWINDOW_MASKDATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HAWINDOW_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HAWINDOW_MASKDATA_OFFSET:
+		return "maskdata";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_HAWINDOW_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_HAWINDOW_width(context));
+	switch (offset) {
+	case DM_HAWINDOW_MASKDATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HAWINDOW_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_ABSTRACTCS_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_ABSTRACTCS_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_ABSTRACTCS_PROGBUFSIZE_OFFSET:
+	case DM_ABSTRACTCS_BUSY_OFFSET:
+	case DM_ABSTRACTCS_RELAXEDPRIV_OFFSET:
+	case DM_ABSTRACTCS_CMDERR_OFFSET:
+	case DM_ABSTRACTCS_DATACOUNT_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_ABSTRACTCS_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_ABSTRACTCS_PROGBUFSIZE_OFFSET:
+		return "progbufsize";
+	case DM_ABSTRACTCS_BUSY_OFFSET:
+		return "busy";
+	case DM_ABSTRACTCS_RELAXEDPRIV_OFFSET:
+		return "relaxedpriv";
+	case DM_ABSTRACTCS_CMDERR_OFFSET:
+		return "cmderr";
+	case DM_ABSTRACTCS_DATACOUNT_OFFSET:
+		return "datacount";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_ABSTRACTCS_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_ABSTRACTCS_width(context));
+	switch (offset) {
+	case DM_ABSTRACTCS_PROGBUFSIZE_OFFSET:
+		return (value & ((unsigned long long)0x1f << offset)) >> offset;
+	case DM_ABSTRACTCS_BUSY_OFFSET:
+	case DM_ABSTRACTCS_RELAXEDPRIV_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case DM_ABSTRACTCS_CMDERR_OFFSET:
+		return (value & ((unsigned long long)7 << offset)) >> offset;
+	case DM_ABSTRACTCS_DATACOUNT_OFFSET:
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_ABSTRACTCS_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case DM_ABSTRACTCS_BUSY_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "ready";
+		case 1:
+			return "busy";
+		default:
+			return NULL;
+		}
+	case DM_ABSTRACTCS_CMDERR_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "none";
+		case 1:
+			return "busy";
+		case 2:
+			return "not supported";
+		case 3:
+			return "exception";
+		case 4:
+			return "halt/resume";
+		case 5:
+			return "bus";
+		case 6:
+			return "reserved";
+		case 7:
+			return "other";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int DM_COMMAND_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_COMMAND_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_COMMAND_CMDTYPE_OFFSET:
+	case DM_COMMAND_CONTROL_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_COMMAND_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_COMMAND_CMDTYPE_OFFSET:
+		return "cmdtype";
+	case DM_COMMAND_CONTROL_OFFSET:
+		return "control";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_COMMAND_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_COMMAND_width(context));
+	switch (offset) {
+	case DM_COMMAND_CMDTYPE_OFFSET:
+		return (value & ((unsigned long long)0xff << offset)) >> offset;
+	case DM_COMMAND_CONTROL_OFFSET:
+		return (value & ((unsigned long long)0xffffff << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_COMMAND_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_ABSTRACTAUTO_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_ABSTRACTAUTO_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET:
+	case DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_ABSTRACTAUTO_field_name(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET:
+		return "autoexecprogbuf";
+	case DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET:
+		return "autoexecdata";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_ABSTRACTAUTO_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_ABSTRACTAUTO_width(context));
+	switch (offset) {
+	case DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET:
+		return (value & ((unsigned long long)0xffff << offset)) >> offset;
+	case DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET:
+		return (value & ((unsigned long long)0xfff << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_ABSTRACTAUTO_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_CONFSTRPTR0_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_CONFSTRPTR0_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_CONFSTRPTR0_ADDR_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_CONFSTRPTR0_field_name(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_CONFSTRPTR0_ADDR_OFFSET:
+		return "addr";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_CONFSTRPTR0_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_CONFSTRPTR0_width(context));
+	switch (offset) {
+	case DM_CONFSTRPTR0_ADDR_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_CONFSTRPTR0_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_CONFSTRPTR1_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_CONFSTRPTR1_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_CONFSTRPTR1_ADDR_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_CONFSTRPTR1_field_name(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_CONFSTRPTR1_ADDR_OFFSET:
+		return "addr";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_CONFSTRPTR1_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_CONFSTRPTR1_width(context));
+	switch (offset) {
+	case DM_CONFSTRPTR1_ADDR_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_CONFSTRPTR1_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_CONFSTRPTR2_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_CONFSTRPTR2_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_CONFSTRPTR2_ADDR_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_CONFSTRPTR2_field_name(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_CONFSTRPTR2_ADDR_OFFSET:
+		return "addr";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_CONFSTRPTR2_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_CONFSTRPTR2_width(context));
+	switch (offset) {
+	case DM_CONFSTRPTR2_ADDR_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_CONFSTRPTR2_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_CONFSTRPTR3_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_CONFSTRPTR3_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_CONFSTRPTR3_ADDR_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_CONFSTRPTR3_field_name(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_CONFSTRPTR3_ADDR_OFFSET:
+		return "addr";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_CONFSTRPTR3_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_CONFSTRPTR3_width(context));
+	switch (offset) {
+	case DM_CONFSTRPTR3_ADDR_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_CONFSTRPTR3_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_NEXTDM_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_NEXTDM_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_NEXTDM_ADDR_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_NEXTDM_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_NEXTDM_ADDR_OFFSET:
+		return "addr";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_NEXTDM_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_NEXTDM_width(context));
+	switch (offset) {
+	case DM_NEXTDM_ADDR_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_NEXTDM_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_DATA0_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_DATA0_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DATA0_DATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_DATA0_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DATA0_DATA_OFFSET:
+		return "data";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_DATA0_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_DATA0_width(context));
+	switch (offset) {
+	case DM_DATA0_DATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_DATA0_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_PROGBUF0_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_PROGBUF0_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_PROGBUF0_DATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_PROGBUF0_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_PROGBUF0_DATA_OFFSET:
+		return "data";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_PROGBUF0_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_PROGBUF0_width(context));
+	switch (offset) {
+	case DM_PROGBUF0_DATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_PROGBUF0_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_AUTHDATA_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_AUTHDATA_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_AUTHDATA_DATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_AUTHDATA_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_AUTHDATA_DATA_OFFSET:
+		return "data";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_AUTHDATA_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_AUTHDATA_width(context));
+	switch (offset) {
+	case DM_AUTHDATA_DATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_AUTHDATA_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_DMCS2_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_DMCS2_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DMCS2_GROUPTYPE_OFFSET:
+	case DM_DMCS2_DMEXTTRIGGER_OFFSET:
+	case DM_DMCS2_GROUP_OFFSET:
+	case DM_DMCS2_HGWRITE_OFFSET:
+	case DM_DMCS2_HGSELECT_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_DMCS2_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DMCS2_GROUPTYPE_OFFSET:
+		return "grouptype";
+	case DM_DMCS2_DMEXTTRIGGER_OFFSET:
+		return "dmexttrigger";
+	case DM_DMCS2_GROUP_OFFSET:
+		return "group";
+	case DM_DMCS2_HGWRITE_OFFSET:
+		return "hgwrite";
+	case DM_DMCS2_HGSELECT_OFFSET:
+		return "hgselect";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_DMCS2_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_DMCS2_width(context));
+	switch (offset) {
+	case DM_DMCS2_GROUPTYPE_OFFSET:
+	case DM_DMCS2_HGWRITE_OFFSET:
+	case DM_DMCS2_HGSELECT_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case DM_DMCS2_DMEXTTRIGGER_OFFSET:
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	case DM_DMCS2_GROUP_OFFSET:
+		return (value & ((unsigned long long)0x1f << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_DMCS2_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case DM_DMCS2_GROUPTYPE_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "halt";
+		case 1:
+			return "resume";
+		default:
+			return NULL;
+		}
+	case DM_DMCS2_HGSELECT_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "harts";
+		case 1:
+			return "triggers";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int DM_HALTSUM0_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_HALTSUM0_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HALTSUM0_HALTSUM0_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HALTSUM0_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HALTSUM0_HALTSUM0_OFFSET:
+		return "haltsum0";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_HALTSUM0_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_HALTSUM0_width(context));
+	switch (offset) {
+	case DM_HALTSUM0_HALTSUM0_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HALTSUM0_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_HALTSUM1_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_HALTSUM1_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HALTSUM1_HALTSUM1_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HALTSUM1_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HALTSUM1_HALTSUM1_OFFSET:
+		return "haltsum1";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_HALTSUM1_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_HALTSUM1_width(context));
+	switch (offset) {
+	case DM_HALTSUM1_HALTSUM1_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HALTSUM1_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_HALTSUM2_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_HALTSUM2_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HALTSUM2_HALTSUM2_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HALTSUM2_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HALTSUM2_HALTSUM2_OFFSET:
+		return "haltsum2";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_HALTSUM2_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_HALTSUM2_width(context));
+	switch (offset) {
+	case DM_HALTSUM2_HALTSUM2_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HALTSUM2_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_HALTSUM3_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_HALTSUM3_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HALTSUM3_HALTSUM3_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HALTSUM3_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_HALTSUM3_HALTSUM3_OFFSET:
+		return "haltsum3";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_HALTSUM3_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_HALTSUM3_width(context));
+	switch (offset) {
+	case DM_HALTSUM3_HALTSUM3_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_HALTSUM3_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_SBCS_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_SBCS_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBCS_SBVERSION_OFFSET:
+	case DM_SBCS_SBBUSYERROR_OFFSET:
+	case DM_SBCS_SBBUSY_OFFSET:
+	case DM_SBCS_SBREADONADDR_OFFSET:
+	case DM_SBCS_SBACCESS_OFFSET:
+	case DM_SBCS_SBAUTOINCREMENT_OFFSET:
+	case DM_SBCS_SBREADONDATA_OFFSET:
+	case DM_SBCS_SBERROR_OFFSET:
+	case DM_SBCS_SBASIZE_OFFSET:
+	case DM_SBCS_SBACCESS128_OFFSET:
+	case DM_SBCS_SBACCESS64_OFFSET:
+	case DM_SBCS_SBACCESS32_OFFSET:
+	case DM_SBCS_SBACCESS16_OFFSET:
+	case DM_SBCS_SBACCESS8_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBCS_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBCS_SBVERSION_OFFSET:
+		return "sbversion";
+	case DM_SBCS_SBBUSYERROR_OFFSET:
+		return "sbbusyerror";
+	case DM_SBCS_SBBUSY_OFFSET:
+		return "sbbusy";
+	case DM_SBCS_SBREADONADDR_OFFSET:
+		return "sbreadonaddr";
+	case DM_SBCS_SBACCESS_OFFSET:
+		return "sbaccess";
+	case DM_SBCS_SBAUTOINCREMENT_OFFSET:
+		return "sbautoincrement";
+	case DM_SBCS_SBREADONDATA_OFFSET:
+		return "sbreadondata";
+	case DM_SBCS_SBERROR_OFFSET:
+		return "sberror";
+	case DM_SBCS_SBASIZE_OFFSET:
+		return "sbasize";
+	case DM_SBCS_SBACCESS128_OFFSET:
+		return "sbaccess128";
+	case DM_SBCS_SBACCESS64_OFFSET:
+		return "sbaccess64";
+	case DM_SBCS_SBACCESS32_OFFSET:
+		return "sbaccess32";
+	case DM_SBCS_SBACCESS16_OFFSET:
+		return "sbaccess16";
+	case DM_SBCS_SBACCESS8_OFFSET:
+		return "sbaccess8";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_SBCS_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_SBCS_width(context));
+	switch (offset) {
+	case DM_SBCS_SBVERSION_OFFSET:
+	case DM_SBCS_SBACCESS_OFFSET:
+	case DM_SBCS_SBERROR_OFFSET:
+		return (value & ((unsigned long long)7 << offset)) >> offset;
+	case DM_SBCS_SBBUSYERROR_OFFSET:
+	case DM_SBCS_SBBUSY_OFFSET:
+	case DM_SBCS_SBREADONADDR_OFFSET:
+	case DM_SBCS_SBAUTOINCREMENT_OFFSET:
+	case DM_SBCS_SBREADONDATA_OFFSET:
+	case DM_SBCS_SBACCESS128_OFFSET:
+	case DM_SBCS_SBACCESS64_OFFSET:
+	case DM_SBCS_SBACCESS32_OFFSET:
+	case DM_SBCS_SBACCESS16_OFFSET:
+	case DM_SBCS_SBACCESS8_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case DM_SBCS_SBASIZE_OFFSET:
+		return (value & ((unsigned long long)0x7f << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBCS_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBCS_SBVERSION_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "legacy";
+		case 1:
+			return "1.0";
+		default:
+			return NULL;
+		}
+	case DM_SBCS_SBACCESS_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "8bit";
+		case 1:
+			return "16bit";
+		case 2:
+			return "32bit";
+		case 3:
+			return "64bit";
+		case 4:
+			return "128bit";
+		default:
+			return NULL;
+		}
+	case DM_SBCS_SBERROR_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "none";
+		case 1:
+			return "timeout";
+		case 2:
+			return "address";
+		case 3:
+			return "alignment";
+		case 4:
+			return "size";
+		case 7:
+			return "other";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int DM_SBADDRESS0_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_SBADDRESS0_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBADDRESS0_ADDRESS_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBADDRESS0_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBADDRESS0_ADDRESS_OFFSET:
+		return "address";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_SBADDRESS0_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_SBADDRESS0_width(context));
+	switch (offset) {
+	case DM_SBADDRESS0_ADDRESS_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBADDRESS0_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_SBADDRESS1_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_SBADDRESS1_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBADDRESS1_ADDRESS_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBADDRESS1_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBADDRESS1_ADDRESS_OFFSET:
+		return "address";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_SBADDRESS1_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_SBADDRESS1_width(context));
+	switch (offset) {
+	case DM_SBADDRESS1_ADDRESS_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBADDRESS1_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_SBADDRESS2_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_SBADDRESS2_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBADDRESS2_ADDRESS_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBADDRESS2_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBADDRESS2_ADDRESS_OFFSET:
+		return "address";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_SBADDRESS2_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_SBADDRESS2_width(context));
+	switch (offset) {
+	case DM_SBADDRESS2_ADDRESS_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBADDRESS2_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_SBADDRESS3_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_SBADDRESS3_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBADDRESS3_ADDRESS_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBADDRESS3_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBADDRESS3_ADDRESS_OFFSET:
+		return "address";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_SBADDRESS3_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_SBADDRESS3_width(context));
+	switch (offset) {
+	case DM_SBADDRESS3_ADDRESS_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBADDRESS3_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_SBDATA0_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_SBDATA0_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBDATA0_DATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBDATA0_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBDATA0_DATA_OFFSET:
+		return "data";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_SBDATA0_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_SBDATA0_width(context));
+	switch (offset) {
+	case DM_SBDATA0_DATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBDATA0_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_SBDATA1_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_SBDATA1_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBDATA1_DATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBDATA1_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBDATA1_DATA_OFFSET:
+		return "data";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_SBDATA1_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_SBDATA1_width(context));
+	switch (offset) {
+	case DM_SBDATA1_DATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBDATA1_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_SBDATA2_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_SBDATA2_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBDATA2_DATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBDATA2_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBDATA2_DATA_OFFSET:
+		return "data";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_SBDATA2_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_SBDATA2_width(context));
+	switch (offset) {
+	case DM_SBDATA2_DATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBDATA2_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DM_SBDATA3_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DM_SBDATA3_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBDATA3_DATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBDATA3_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DM_SBDATA3_DATA_OFFSET:
+		return "data";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DM_SBDATA3_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DM_SBDATA3_width(context));
+	switch (offset) {
+	case DM_SBDATA3_DATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DM_SBDATA3_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int SHORTNAME_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int SHORTNAME_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case SHORTNAME_FIELD_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *SHORTNAME_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case SHORTNAME_FIELD_OFFSET:
+		return "field";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long SHORTNAME_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < SHORTNAME_width(context));
+	switch (offset) {
+	case SHORTNAME_FIELD_OFFSET:
+		return (value & ((unsigned long long)0xff << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *SHORTNAME_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int AC_ACCESS_REGISTER_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int AC_ACCESS_REGISTER_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case AC_ACCESS_REGISTER_CMDTYPE_OFFSET:
+	case AC_ACCESS_REGISTER_AARSIZE_OFFSET:
+	case AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET:
+	case AC_ACCESS_REGISTER_POSTEXEC_OFFSET:
+	case AC_ACCESS_REGISTER_TRANSFER_OFFSET:
+	case AC_ACCESS_REGISTER_WRITE_OFFSET:
+	case AC_ACCESS_REGISTER_REGNO_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *AC_ACCESS_REGISTER_field_name(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case AC_ACCESS_REGISTER_CMDTYPE_OFFSET:
+		return "cmdtype";
+	case AC_ACCESS_REGISTER_AARSIZE_OFFSET:
+		return "aarsize";
+	case AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET:
+		return "aarpostincrement";
+	case AC_ACCESS_REGISTER_POSTEXEC_OFFSET:
+		return "postexec";
+	case AC_ACCESS_REGISTER_TRANSFER_OFFSET:
+		return "transfer";
+	case AC_ACCESS_REGISTER_WRITE_OFFSET:
+		return "write";
+	case AC_ACCESS_REGISTER_REGNO_OFFSET:
+		return "regno";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long AC_ACCESS_REGISTER_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < AC_ACCESS_REGISTER_width(context));
+	switch (offset) {
+	case AC_ACCESS_REGISTER_CMDTYPE_OFFSET:
+		return (value & ((unsigned long long)0xff << offset)) >> offset;
+	case AC_ACCESS_REGISTER_AARSIZE_OFFSET:
+		return (value & ((unsigned long long)7 << offset)) >> offset;
+	case AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET:
+	case AC_ACCESS_REGISTER_POSTEXEC_OFFSET:
+	case AC_ACCESS_REGISTER_TRANSFER_OFFSET:
+	case AC_ACCESS_REGISTER_WRITE_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case AC_ACCESS_REGISTER_REGNO_OFFSET:
+		return (value & ((unsigned long long)0xffff << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *AC_ACCESS_REGISTER_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case AC_ACCESS_REGISTER_AARSIZE_OFFSET:
+		switch (field_value) {
+		case 2:
+			return "32bit";
+		case 3:
+			return "64bit";
+		case 4:
+			return "128bit";
+		default:
+			return NULL;
+		}
+	case AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET:
+	case AC_ACCESS_REGISTER_POSTEXEC_OFFSET:
+	case AC_ACCESS_REGISTER_TRANSFER_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "disabled";
+		case 1:
+			return "enabled";
+		default:
+			return NULL;
+		}
+	case AC_ACCESS_REGISTER_WRITE_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "arg0";
+		case 1:
+			return "register";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int AC_QUICK_ACCESS_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int AC_QUICK_ACCESS_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case AC_QUICK_ACCESS_CMDTYPE_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *AC_QUICK_ACCESS_field_name(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case AC_QUICK_ACCESS_CMDTYPE_OFFSET:
+		return "cmdtype";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long AC_QUICK_ACCESS_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < AC_QUICK_ACCESS_width(context));
+	switch (offset) {
+	case AC_QUICK_ACCESS_CMDTYPE_OFFSET:
+		return (value & ((unsigned long long)0xff << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *AC_QUICK_ACCESS_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int AC_ACCESS_MEMORY_width(
+		struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int AC_ACCESS_MEMORY_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case AC_ACCESS_MEMORY_CMDTYPE_OFFSET:
+	case AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET:
+	case AC_ACCESS_MEMORY_AAMSIZE_OFFSET:
+	case AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET:
+	case AC_ACCESS_MEMORY_WRITE_OFFSET:
+	case AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *AC_ACCESS_MEMORY_field_name(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case AC_ACCESS_MEMORY_CMDTYPE_OFFSET:
+		return "cmdtype";
+	case AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET:
+		return "aamvirtual";
+	case AC_ACCESS_MEMORY_AAMSIZE_OFFSET:
+		return "aamsize";
+	case AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET:
+		return "aampostincrement";
+	case AC_ACCESS_MEMORY_WRITE_OFFSET:
+		return "write";
+	case AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET:
+		return "target-specific";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long AC_ACCESS_MEMORY_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < AC_ACCESS_MEMORY_width(context));
+	switch (offset) {
+	case AC_ACCESS_MEMORY_CMDTYPE_OFFSET:
+		return (value & ((unsigned long long)0xff << offset)) >> offset;
+	case AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET:
+	case AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET:
+	case AC_ACCESS_MEMORY_WRITE_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case AC_ACCESS_MEMORY_AAMSIZE_OFFSET:
+		return (value & ((unsigned long long)7 << offset)) >> offset;
+	case AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET:
+		return (value & ((unsigned long long)3 << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *AC_ACCESS_MEMORY_decode_field(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long field_value)
+{
+	(void) context;
+	switch (offset) {
+	case AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "physical";
+		case 1:
+			return "virtual";
+		default:
+			return NULL;
+		}
+	case AC_ACCESS_MEMORY_AAMSIZE_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "8bit";
+		case 1:
+			return "16bit";
+		case 2:
+			return "32bit";
+		case 3:
+			return "64bit";
+		case 4:
+			return "128bit";
+		default:
+			return NULL;
+		}
+	case AC_ACCESS_MEMORY_WRITE_OFFSET:
+		switch (field_value) {
+		case 0:
+			return "arg0";
+		case 1:
+			return "memory";
+		default:
+			return NULL;
+		}
+	default:
+		return NULL;
+	}
+}
+static inline unsigned int VIRT_PRIV_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 3;
+}
+
+static unsigned int VIRT_PRIV_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case VIRT_PRIV_V_OFFSET:
+	case VIRT_PRIV_PRV_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *VIRT_PRIV_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case VIRT_PRIV_V_OFFSET:
+		return "v";
+	case VIRT_PRIV_PRV_OFFSET:
+		return "prv";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long VIRT_PRIV_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < VIRT_PRIV_width(context));
+	switch (offset) {
+	case VIRT_PRIV_V_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	case VIRT_PRIV_PRV_OFFSET:
+		return (value & ((unsigned long long)3 << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *VIRT_PRIV_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DMI_SERCS_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DMI_SERCS_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DMI_SERCS_SERIALCOUNT_OFFSET:
+	case DMI_SERCS_SERIAL_OFFSET:
+	case DMI_SERCS_ERROR7_OFFSET:
+	case DMI_SERCS_VALID7_OFFSET:
+	case DMI_SERCS_FULL7_OFFSET:
+	case DMI_SERCS_ERROR6_OFFSET:
+	case DMI_SERCS_VALID6_OFFSET:
+	case DMI_SERCS_FULL6_OFFSET:
+	case DMI_SERCS_ERROR5_OFFSET:
+	case DMI_SERCS_VALID5_OFFSET:
+	case DMI_SERCS_FULL5_OFFSET:
+	case DMI_SERCS_ERROR4_OFFSET:
+	case DMI_SERCS_VALID4_OFFSET:
+	case DMI_SERCS_FULL4_OFFSET:
+	case DMI_SERCS_ERROR3_OFFSET:
+	case DMI_SERCS_VALID3_OFFSET:
+	case DMI_SERCS_FULL3_OFFSET:
+	case DMI_SERCS_ERROR2_OFFSET:
+	case DMI_SERCS_VALID2_OFFSET:
+	case DMI_SERCS_FULL2_OFFSET:
+	case DMI_SERCS_ERROR1_OFFSET:
+	case DMI_SERCS_VALID1_OFFSET:
+	case DMI_SERCS_FULL1_OFFSET:
+	case DMI_SERCS_ERROR0_OFFSET:
+	case DMI_SERCS_VALID0_OFFSET:
+	case DMI_SERCS_FULL0_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DMI_SERCS_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DMI_SERCS_SERIALCOUNT_OFFSET:
+		return "serialcount";
+	case DMI_SERCS_SERIAL_OFFSET:
+		return "serial";
+	case DMI_SERCS_ERROR7_OFFSET:
+		return "error7";
+	case DMI_SERCS_VALID7_OFFSET:
+		return "valid7";
+	case DMI_SERCS_FULL7_OFFSET:
+		return "full7";
+	case DMI_SERCS_ERROR6_OFFSET:
+		return "error6";
+	case DMI_SERCS_VALID6_OFFSET:
+		return "valid6";
+	case DMI_SERCS_FULL6_OFFSET:
+		return "full6";
+	case DMI_SERCS_ERROR5_OFFSET:
+		return "error5";
+	case DMI_SERCS_VALID5_OFFSET:
+		return "valid5";
+	case DMI_SERCS_FULL5_OFFSET:
+		return "full5";
+	case DMI_SERCS_ERROR4_OFFSET:
+		return "error4";
+	case DMI_SERCS_VALID4_OFFSET:
+		return "valid4";
+	case DMI_SERCS_FULL4_OFFSET:
+		return "full4";
+	case DMI_SERCS_ERROR3_OFFSET:
+		return "error3";
+	case DMI_SERCS_VALID3_OFFSET:
+		return "valid3";
+	case DMI_SERCS_FULL3_OFFSET:
+		return "full3";
+	case DMI_SERCS_ERROR2_OFFSET:
+		return "error2";
+	case DMI_SERCS_VALID2_OFFSET:
+		return "valid2";
+	case DMI_SERCS_FULL2_OFFSET:
+		return "full2";
+	case DMI_SERCS_ERROR1_OFFSET:
+		return "error1";
+	case DMI_SERCS_VALID1_OFFSET:
+		return "valid1";
+	case DMI_SERCS_FULL1_OFFSET:
+		return "full1";
+	case DMI_SERCS_ERROR0_OFFSET:
+		return "error0";
+	case DMI_SERCS_VALID0_OFFSET:
+		return "valid0";
+	case DMI_SERCS_FULL0_OFFSET:
+		return "full0";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DMI_SERCS_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DMI_SERCS_width(context));
+	switch (offset) {
+	case DMI_SERCS_SERIALCOUNT_OFFSET:
+		return (value & ((unsigned long long)0xf << offset)) >> offset;
+	case DMI_SERCS_SERIAL_OFFSET:
+		return (value & ((unsigned long long)7 << offset)) >> offset;
+	case DMI_SERCS_ERROR7_OFFSET:
+	case DMI_SERCS_VALID7_OFFSET:
+	case DMI_SERCS_FULL7_OFFSET:
+	case DMI_SERCS_ERROR6_OFFSET:
+	case DMI_SERCS_VALID6_OFFSET:
+	case DMI_SERCS_FULL6_OFFSET:
+	case DMI_SERCS_ERROR5_OFFSET:
+	case DMI_SERCS_VALID5_OFFSET:
+	case DMI_SERCS_FULL5_OFFSET:
+	case DMI_SERCS_ERROR4_OFFSET:
+	case DMI_SERCS_VALID4_OFFSET:
+	case DMI_SERCS_FULL4_OFFSET:
+	case DMI_SERCS_ERROR3_OFFSET:
+	case DMI_SERCS_VALID3_OFFSET:
+	case DMI_SERCS_FULL3_OFFSET:
+	case DMI_SERCS_ERROR2_OFFSET:
+	case DMI_SERCS_VALID2_OFFSET:
+	case DMI_SERCS_FULL2_OFFSET:
+	case DMI_SERCS_ERROR1_OFFSET:
+	case DMI_SERCS_VALID1_OFFSET:
+	case DMI_SERCS_FULL1_OFFSET:
+	case DMI_SERCS_ERROR0_OFFSET:
+	case DMI_SERCS_VALID0_OFFSET:
+	case DMI_SERCS_FULL0_OFFSET:
+		return (value & ((unsigned long long)1 << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DMI_SERCS_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DMI_SERTX_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DMI_SERTX_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DMI_SERTX_DATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DMI_SERTX_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DMI_SERTX_DATA_OFFSET:
+		return "data";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DMI_SERTX_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DMI_SERTX_width(context));
+	switch (offset) {
+	case DMI_SERTX_DATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DMI_SERTX_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+static inline unsigned int DMI_SERRX_width(struct riscv_debug_reg_ctx context)
+{
+	(void) context;
+	return 0x20;
+}
+
+static unsigned int DMI_SERRX_field_is_present(
+		struct riscv_debug_reg_ctx context, unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DMI_SERRX_DATA_OFFSET:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static const char *DMI_SERRX_field_name(struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	(void) context;
+	switch (offset) {
+	case DMI_SERRX_DATA_OFFSET:
+		return "data";
+	default:
+		return NULL;
+	}
+}
+
+static unsigned long long DMI_SERRX_field_value(
+		struct riscv_debug_reg_ctx context, unsigned int offset,
+		unsigned long long value)
+{
+	(void) context;
+	assert(offset < DMI_SERRX_width(context));
+	switch (offset) {
+	case DMI_SERRX_DATA_OFFSET:
+		return (value & ((unsigned long long)0xffffffffU << offset)) >> offset;
+	default:
+		return 0;
+	}
+}
+
+static const char *DMI_SERRX_decode_field(struct riscv_debug_reg_ctx context,
+		unsigned int offset, unsigned long long field_value)
+{
+	(void) context;
+	return NULL;
+}
+unsigned int riscv_debug_reg_width(enum riscv_debug_reg_ordinal reg_ordinal,
+		struct riscv_debug_reg_ctx context)
+{
+	switch (reg_ordinal) {
+	case DTM_IDCODE_ORDINAL:
+		return DTM_IDCODE_width(context);
+	case DTM_DTMCS_ORDINAL:
+		return DTM_DTMCS_width(context);
+	case DTM_DMI_ORDINAL:
+		return DTM_DMI_width(context);
+	case DTM_BYPASS_ORDINAL:
+		return DTM_BYPASS_width(context);
+	case CSR_DCSR_ORDINAL:
+		return CSR_DCSR_width(context);
+	case CSR_DPC_ORDINAL:
+		return CSR_DPC_width(context);
+	case CSR_TSELECT_ORDINAL:
+		return CSR_TSELECT_width(context);
+	case CSR_TDATA1_ORDINAL:
+		return CSR_TDATA1_width(context);
+	case CSR_TDATA2_ORDINAL:
+		return CSR_TDATA2_width(context);
+	case CSR_TDATA3_ORDINAL:
+		return CSR_TDATA3_width(context);
+	case CSR_TINFO_ORDINAL:
+		return CSR_TINFO_width(context);
+	case CSR_TCONTROL_ORDINAL:
+		return CSR_TCONTROL_width(context);
+	case CSR_HCONTEXT_ORDINAL:
+		return CSR_HCONTEXT_width(context);
+	case CSR_SCONTEXT_ORDINAL:
+		return CSR_SCONTEXT_width(context);
+	case CSR_MCONTROL_ORDINAL:
+		return CSR_MCONTROL_width(context);
+	case CSR_MCONTROL6_ORDINAL:
+		return CSR_MCONTROL6_width(context);
+	case CSR_ICOUNT_ORDINAL:
+		return CSR_ICOUNT_width(context);
+	case CSR_ITRIGGER_ORDINAL:
+		return CSR_ITRIGGER_width(context);
+	case CSR_ETRIGGER_ORDINAL:
+		return CSR_ETRIGGER_width(context);
+	case CSR_TMEXTTRIGGER_ORDINAL:
+		return CSR_TMEXTTRIGGER_width(context);
+	case CSR_TEXTRA32_ORDINAL:
+		return CSR_TEXTRA32_width(context);
+	case CSR_TEXTRA64_ORDINAL:
+		return CSR_TEXTRA64_width(context);
+	case DM_DMSTATUS_ORDINAL:
+		return DM_DMSTATUS_width(context);
+	case DM_DMCONTROL_ORDINAL:
+		return DM_DMCONTROL_width(context);
+	case DM_HARTINFO_ORDINAL:
+		return DM_HARTINFO_width(context);
+	case DM_HAWINDOWSEL_ORDINAL:
+		return DM_HAWINDOWSEL_width(context);
+	case DM_HAWINDOW_ORDINAL:
+		return DM_HAWINDOW_width(context);
+	case DM_ABSTRACTCS_ORDINAL:
+		return DM_ABSTRACTCS_width(context);
+	case DM_COMMAND_ORDINAL:
+		return DM_COMMAND_width(context);
+	case DM_ABSTRACTAUTO_ORDINAL:
+		return DM_ABSTRACTAUTO_width(context);
+	case DM_CONFSTRPTR0_ORDINAL:
+		return DM_CONFSTRPTR0_width(context);
+	case DM_CONFSTRPTR1_ORDINAL:
+		return DM_CONFSTRPTR1_width(context);
+	case DM_CONFSTRPTR2_ORDINAL:
+		return DM_CONFSTRPTR2_width(context);
+	case DM_CONFSTRPTR3_ORDINAL:
+		return DM_CONFSTRPTR3_width(context);
+	case DM_NEXTDM_ORDINAL:
+		return DM_NEXTDM_width(context);
+	case DM_DATA0_ORDINAL:
+		return DM_DATA0_width(context);
+	case DM_PROGBUF0_ORDINAL:
+		return DM_PROGBUF0_width(context);
+	case DM_AUTHDATA_ORDINAL:
+		return DM_AUTHDATA_width(context);
+	case DM_DMCS2_ORDINAL:
+		return DM_DMCS2_width(context);
+	case DM_HALTSUM0_ORDINAL:
+		return DM_HALTSUM0_width(context);
+	case DM_HALTSUM1_ORDINAL:
+		return DM_HALTSUM1_width(context);
+	case DM_HALTSUM2_ORDINAL:
+		return DM_HALTSUM2_width(context);
+	case DM_HALTSUM3_ORDINAL:
+		return DM_HALTSUM3_width(context);
+	case DM_SBCS_ORDINAL:
+		return DM_SBCS_width(context);
+	case DM_SBADDRESS0_ORDINAL:
+		return DM_SBADDRESS0_width(context);
+	case DM_SBADDRESS1_ORDINAL:
+		return DM_SBADDRESS1_width(context);
+	case DM_SBADDRESS2_ORDINAL:
+		return DM_SBADDRESS2_width(context);
+	case DM_SBADDRESS3_ORDINAL:
+		return DM_SBADDRESS3_width(context);
+	case DM_SBDATA0_ORDINAL:
+		return DM_SBDATA0_width(context);
+	case DM_SBDATA1_ORDINAL:
+		return DM_SBDATA1_width(context);
+	case DM_SBDATA2_ORDINAL:
+		return DM_SBDATA2_width(context);
+	case DM_SBDATA3_ORDINAL:
+		return DM_SBDATA3_width(context);
+	case SHORTNAME_ORDINAL:
+		return SHORTNAME_width(context);
+	case AC_ACCESS_REGISTER_ORDINAL:
+		return AC_ACCESS_REGISTER_width(context);
+	case AC_QUICK_ACCESS_ORDINAL:
+		return AC_QUICK_ACCESS_width(context);
+	case AC_ACCESS_MEMORY_ORDINAL:
+		return AC_ACCESS_MEMORY_width(context);
+	case VIRT_PRIV_ORDINAL:
+		return VIRT_PRIV_width(context);
+	case DMI_SERCS_ORDINAL:
+		return DMI_SERCS_width(context);
+	case DMI_SERTX_ORDINAL:
+		return DMI_SERTX_width(context);
+	case DMI_SERRX_ORDINAL:
+		return DMI_SERRX_width(context);
+	default:
+		return 0;
+	}
+}
+
+unsigned int riscv_debug_reg_field_is_present(
+		enum riscv_debug_reg_ordinal reg_ordinal, struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	switch (reg_ordinal) {
+	case DTM_IDCODE_ORDINAL:
+		return DTM_IDCODE_field_is_present(context, offset);
+	case DTM_DTMCS_ORDINAL:
+		return DTM_DTMCS_field_is_present(context, offset);
+	case DTM_DMI_ORDINAL:
+		return DTM_DMI_field_is_present(context, offset);
+	case DTM_BYPASS_ORDINAL:
+		return DTM_BYPASS_field_is_present(context, offset);
+	case CSR_DCSR_ORDINAL:
+		return CSR_DCSR_field_is_present(context, offset);
+	case CSR_DPC_ORDINAL:
+		return CSR_DPC_field_is_present(context, offset);
+	case CSR_TSELECT_ORDINAL:
+		return CSR_TSELECT_field_is_present(context, offset);
+	case CSR_TDATA1_ORDINAL:
+		return CSR_TDATA1_field_is_present(context, offset);
+	case CSR_TDATA2_ORDINAL:
+		return CSR_TDATA2_field_is_present(context, offset);
+	case CSR_TDATA3_ORDINAL:
+		return CSR_TDATA3_field_is_present(context, offset);
+	case CSR_TINFO_ORDINAL:
+		return CSR_TINFO_field_is_present(context, offset);
+	case CSR_TCONTROL_ORDINAL:
+		return CSR_TCONTROL_field_is_present(context, offset);
+	case CSR_HCONTEXT_ORDINAL:
+		return CSR_HCONTEXT_field_is_present(context, offset);
+	case CSR_SCONTEXT_ORDINAL:
+		return CSR_SCONTEXT_field_is_present(context, offset);
+	case CSR_MCONTROL_ORDINAL:
+		return CSR_MCONTROL_field_is_present(context, offset);
+	case CSR_MCONTROL6_ORDINAL:
+		return CSR_MCONTROL6_field_is_present(context, offset);
+	case CSR_ICOUNT_ORDINAL:
+		return CSR_ICOUNT_field_is_present(context, offset);
+	case CSR_ITRIGGER_ORDINAL:
+		return CSR_ITRIGGER_field_is_present(context, offset);
+	case CSR_ETRIGGER_ORDINAL:
+		return CSR_ETRIGGER_field_is_present(context, offset);
+	case CSR_TMEXTTRIGGER_ORDINAL:
+		return CSR_TMEXTTRIGGER_field_is_present(context, offset);
+	case CSR_TEXTRA32_ORDINAL:
+		return CSR_TEXTRA32_field_is_present(context, offset);
+	case CSR_TEXTRA64_ORDINAL:
+		return CSR_TEXTRA64_field_is_present(context, offset);
+	case DM_DMSTATUS_ORDINAL:
+		return DM_DMSTATUS_field_is_present(context, offset);
+	case DM_DMCONTROL_ORDINAL:
+		return DM_DMCONTROL_field_is_present(context, offset);
+	case DM_HARTINFO_ORDINAL:
+		return DM_HARTINFO_field_is_present(context, offset);
+	case DM_HAWINDOWSEL_ORDINAL:
+		return DM_HAWINDOWSEL_field_is_present(context, offset);
+	case DM_HAWINDOW_ORDINAL:
+		return DM_HAWINDOW_field_is_present(context, offset);
+	case DM_ABSTRACTCS_ORDINAL:
+		return DM_ABSTRACTCS_field_is_present(context, offset);
+	case DM_COMMAND_ORDINAL:
+		return DM_COMMAND_field_is_present(context, offset);
+	case DM_ABSTRACTAUTO_ORDINAL:
+		return DM_ABSTRACTAUTO_field_is_present(context, offset);
+	case DM_CONFSTRPTR0_ORDINAL:
+		return DM_CONFSTRPTR0_field_is_present(context, offset);
+	case DM_CONFSTRPTR1_ORDINAL:
+		return DM_CONFSTRPTR1_field_is_present(context, offset);
+	case DM_CONFSTRPTR2_ORDINAL:
+		return DM_CONFSTRPTR2_field_is_present(context, offset);
+	case DM_CONFSTRPTR3_ORDINAL:
+		return DM_CONFSTRPTR3_field_is_present(context, offset);
+	case DM_NEXTDM_ORDINAL:
+		return DM_NEXTDM_field_is_present(context, offset);
+	case DM_DATA0_ORDINAL:
+		return DM_DATA0_field_is_present(context, offset);
+	case DM_PROGBUF0_ORDINAL:
+		return DM_PROGBUF0_field_is_present(context, offset);
+	case DM_AUTHDATA_ORDINAL:
+		return DM_AUTHDATA_field_is_present(context, offset);
+	case DM_DMCS2_ORDINAL:
+		return DM_DMCS2_field_is_present(context, offset);
+	case DM_HALTSUM0_ORDINAL:
+		return DM_HALTSUM0_field_is_present(context, offset);
+	case DM_HALTSUM1_ORDINAL:
+		return DM_HALTSUM1_field_is_present(context, offset);
+	case DM_HALTSUM2_ORDINAL:
+		return DM_HALTSUM2_field_is_present(context, offset);
+	case DM_HALTSUM3_ORDINAL:
+		return DM_HALTSUM3_field_is_present(context, offset);
+	case DM_SBCS_ORDINAL:
+		return DM_SBCS_field_is_present(context, offset);
+	case DM_SBADDRESS0_ORDINAL:
+		return DM_SBADDRESS0_field_is_present(context, offset);
+	case DM_SBADDRESS1_ORDINAL:
+		return DM_SBADDRESS1_field_is_present(context, offset);
+	case DM_SBADDRESS2_ORDINAL:
+		return DM_SBADDRESS2_field_is_present(context, offset);
+	case DM_SBADDRESS3_ORDINAL:
+		return DM_SBADDRESS3_field_is_present(context, offset);
+	case DM_SBDATA0_ORDINAL:
+		return DM_SBDATA0_field_is_present(context, offset);
+	case DM_SBDATA1_ORDINAL:
+		return DM_SBDATA1_field_is_present(context, offset);
+	case DM_SBDATA2_ORDINAL:
+		return DM_SBDATA2_field_is_present(context, offset);
+	case DM_SBDATA3_ORDINAL:
+		return DM_SBDATA3_field_is_present(context, offset);
+	case SHORTNAME_ORDINAL:
+		return SHORTNAME_field_is_present(context, offset);
+	case AC_ACCESS_REGISTER_ORDINAL:
+		return AC_ACCESS_REGISTER_field_is_present(context, offset);
+	case AC_QUICK_ACCESS_ORDINAL:
+		return AC_QUICK_ACCESS_field_is_present(context, offset);
+	case AC_ACCESS_MEMORY_ORDINAL:
+		return AC_ACCESS_MEMORY_field_is_present(context, offset);
+	case VIRT_PRIV_ORDINAL:
+		return VIRT_PRIV_field_is_present(context, offset);
+	case DMI_SERCS_ORDINAL:
+		return DMI_SERCS_field_is_present(context, offset);
+	case DMI_SERTX_ORDINAL:
+		return DMI_SERTX_field_is_present(context, offset);
+	case DMI_SERRX_ORDINAL:
+		return DMI_SERRX_field_is_present(context, offset);
+	default:
+		return 0;
+	}
+}
+
+const char *riscv_debug_reg_field_name(
+		enum riscv_debug_reg_ordinal reg_ordinal, struct riscv_debug_reg_ctx context,
+		unsigned int offset)
+{
+	switch (reg_ordinal) {
+	case DTM_IDCODE_ORDINAL:
+		return DTM_IDCODE_field_name(context, offset);
+	case DTM_DTMCS_ORDINAL:
+		return DTM_DTMCS_field_name(context, offset);
+	case DTM_DMI_ORDINAL:
+		return DTM_DMI_field_name(context, offset);
+	case DTM_BYPASS_ORDINAL:
+		return DTM_BYPASS_field_name(context, offset);
+	case CSR_DCSR_ORDINAL:
+		return CSR_DCSR_field_name(context, offset);
+	case CSR_DPC_ORDINAL:
+		return CSR_DPC_field_name(context, offset);
+	case CSR_TSELECT_ORDINAL:
+		return CSR_TSELECT_field_name(context, offset);
+	case CSR_TDATA1_ORDINAL:
+		return CSR_TDATA1_field_name(context, offset);
+	case CSR_TDATA2_ORDINAL:
+		return CSR_TDATA2_field_name(context, offset);
+	case CSR_TDATA3_ORDINAL:
+		return CSR_TDATA3_field_name(context, offset);
+	case CSR_TINFO_ORDINAL:
+		return CSR_TINFO_field_name(context, offset);
+	case CSR_TCONTROL_ORDINAL:
+		return CSR_TCONTROL_field_name(context, offset);
+	case CSR_HCONTEXT_ORDINAL:
+		return CSR_HCONTEXT_field_name(context, offset);
+	case CSR_SCONTEXT_ORDINAL:
+		return CSR_SCONTEXT_field_name(context, offset);
+	case CSR_MCONTROL_ORDINAL:
+		return CSR_MCONTROL_field_name(context, offset);
+	case CSR_MCONTROL6_ORDINAL:
+		return CSR_MCONTROL6_field_name(context, offset);
+	case CSR_ICOUNT_ORDINAL:
+		return CSR_ICOUNT_field_name(context, offset);
+	case CSR_ITRIGGER_ORDINAL:
+		return CSR_ITRIGGER_field_name(context, offset);
+	case CSR_ETRIGGER_ORDINAL:
+		return CSR_ETRIGGER_field_name(context, offset);
+	case CSR_TMEXTTRIGGER_ORDINAL:
+		return CSR_TMEXTTRIGGER_field_name(context, offset);
+	case CSR_TEXTRA32_ORDINAL:
+		return CSR_TEXTRA32_field_name(context, offset);
+	case CSR_TEXTRA64_ORDINAL:
+		return CSR_TEXTRA64_field_name(context, offset);
+	case DM_DMSTATUS_ORDINAL:
+		return DM_DMSTATUS_field_name(context, offset);
+	case DM_DMCONTROL_ORDINAL:
+		return DM_DMCONTROL_field_name(context, offset);
+	case DM_HARTINFO_ORDINAL:
+		return DM_HARTINFO_field_name(context, offset);
+	case DM_HAWINDOWSEL_ORDINAL:
+		return DM_HAWINDOWSEL_field_name(context, offset);
+	case DM_HAWINDOW_ORDINAL:
+		return DM_HAWINDOW_field_name(context, offset);
+	case DM_ABSTRACTCS_ORDINAL:
+		return DM_ABSTRACTCS_field_name(context, offset);
+	case DM_COMMAND_ORDINAL:
+		return DM_COMMAND_field_name(context, offset);
+	case DM_ABSTRACTAUTO_ORDINAL:
+		return DM_ABSTRACTAUTO_field_name(context, offset);
+	case DM_CONFSTRPTR0_ORDINAL:
+		return DM_CONFSTRPTR0_field_name(context, offset);
+	case DM_CONFSTRPTR1_ORDINAL:
+		return DM_CONFSTRPTR1_field_name(context, offset);
+	case DM_CONFSTRPTR2_ORDINAL:
+		return DM_CONFSTRPTR2_field_name(context, offset);
+	case DM_CONFSTRPTR3_ORDINAL:
+		return DM_CONFSTRPTR3_field_name(context, offset);
+	case DM_NEXTDM_ORDINAL:
+		return DM_NEXTDM_field_name(context, offset);
+	case DM_DATA0_ORDINAL:
+		return DM_DATA0_field_name(context, offset);
+	case DM_PROGBUF0_ORDINAL:
+		return DM_PROGBUF0_field_name(context, offset);
+	case DM_AUTHDATA_ORDINAL:
+		return DM_AUTHDATA_field_name(context, offset);
+	case DM_DMCS2_ORDINAL:
+		return DM_DMCS2_field_name(context, offset);
+	case DM_HALTSUM0_ORDINAL:
+		return DM_HALTSUM0_field_name(context, offset);
+	case DM_HALTSUM1_ORDINAL:
+		return DM_HALTSUM1_field_name(context, offset);
+	case DM_HALTSUM2_ORDINAL:
+		return DM_HALTSUM2_field_name(context, offset);
+	case DM_HALTSUM3_ORDINAL:
+		return DM_HALTSUM3_field_name(context, offset);
+	case DM_SBCS_ORDINAL:
+		return DM_SBCS_field_name(context, offset);
+	case DM_SBADDRESS0_ORDINAL:
+		return DM_SBADDRESS0_field_name(context, offset);
+	case DM_SBADDRESS1_ORDINAL:
+		return DM_SBADDRESS1_field_name(context, offset);
+	case DM_SBADDRESS2_ORDINAL:
+		return DM_SBADDRESS2_field_name(context, offset);
+	case DM_SBADDRESS3_ORDINAL:
+		return DM_SBADDRESS3_field_name(context, offset);
+	case DM_SBDATA0_ORDINAL:
+		return DM_SBDATA0_field_name(context, offset);
+	case DM_SBDATA1_ORDINAL:
+		return DM_SBDATA1_field_name(context, offset);
+	case DM_SBDATA2_ORDINAL:
+		return DM_SBDATA2_field_name(context, offset);
+	case DM_SBDATA3_ORDINAL:
+		return DM_SBDATA3_field_name(context, offset);
+	case SHORTNAME_ORDINAL:
+		return SHORTNAME_field_name(context, offset);
+	case AC_ACCESS_REGISTER_ORDINAL:
+		return AC_ACCESS_REGISTER_field_name(context, offset);
+	case AC_QUICK_ACCESS_ORDINAL:
+		return AC_QUICK_ACCESS_field_name(context, offset);
+	case AC_ACCESS_MEMORY_ORDINAL:
+		return AC_ACCESS_MEMORY_field_name(context, offset);
+	case VIRT_PRIV_ORDINAL:
+		return VIRT_PRIV_field_name(context, offset);
+	case DMI_SERCS_ORDINAL:
+		return DMI_SERCS_field_name(context, offset);
+	case DMI_SERTX_ORDINAL:
+		return DMI_SERTX_field_name(context, offset);
+	case DMI_SERRX_ORDINAL:
+		return DMI_SERRX_field_name(context, offset);
+	default:
+		return NULL;
+	}
+}
+
+unsigned long long riscv_debug_reg_field_value(
+		enum riscv_debug_reg_ordinal reg_ordinal, struct riscv_debug_reg_ctx context,
+		unsigned int offset,
+		unsigned long long value)
+{
+	switch (reg_ordinal) {
+	case DTM_IDCODE_ORDINAL:
+		return DTM_IDCODE_field_value(context, offset, value);
+	case DTM_DTMCS_ORDINAL:
+		return DTM_DTMCS_field_value(context, offset, value);
+	case DTM_DMI_ORDINAL:
+		return DTM_DMI_field_value(context, offset, value);
+	case DTM_BYPASS_ORDINAL:
+		return DTM_BYPASS_field_value(context, offset, value);
+	case CSR_DCSR_ORDINAL:
+		return CSR_DCSR_field_value(context, offset, value);
+	case CSR_DPC_ORDINAL:
+		return CSR_DPC_field_value(context, offset, value);
+	case CSR_TSELECT_ORDINAL:
+		return CSR_TSELECT_field_value(context, offset, value);
+	case CSR_TDATA1_ORDINAL:
+		return CSR_TDATA1_field_value(context, offset, value);
+	case CSR_TDATA2_ORDINAL:
+		return CSR_TDATA2_field_value(context, offset, value);
+	case CSR_TDATA3_ORDINAL:
+		return CSR_TDATA3_field_value(context, offset, value);
+	case CSR_TINFO_ORDINAL:
+		return CSR_TINFO_field_value(context, offset, value);
+	case CSR_TCONTROL_ORDINAL:
+		return CSR_TCONTROL_field_value(context, offset, value);
+	case CSR_HCONTEXT_ORDINAL:
+		return CSR_HCONTEXT_field_value(context, offset, value);
+	case CSR_SCONTEXT_ORDINAL:
+		return CSR_SCONTEXT_field_value(context, offset, value);
+	case CSR_MCONTROL_ORDINAL:
+		return CSR_MCONTROL_field_value(context, offset, value);
+	case CSR_MCONTROL6_ORDINAL:
+		return CSR_MCONTROL6_field_value(context, offset, value);
+	case CSR_ICOUNT_ORDINAL:
+		return CSR_ICOUNT_field_value(context, offset, value);
+	case CSR_ITRIGGER_ORDINAL:
+		return CSR_ITRIGGER_field_value(context, offset, value);
+	case CSR_ETRIGGER_ORDINAL:
+		return CSR_ETRIGGER_field_value(context, offset, value);
+	case CSR_TMEXTTRIGGER_ORDINAL:
+		return CSR_TMEXTTRIGGER_field_value(context, offset, value);
+	case CSR_TEXTRA32_ORDINAL:
+		return CSR_TEXTRA32_field_value(context, offset, value);
+	case CSR_TEXTRA64_ORDINAL:
+		return CSR_TEXTRA64_field_value(context, offset, value);
+	case DM_DMSTATUS_ORDINAL:
+		return DM_DMSTATUS_field_value(context, offset, value);
+	case DM_DMCONTROL_ORDINAL:
+		return DM_DMCONTROL_field_value(context, offset, value);
+	case DM_HARTINFO_ORDINAL:
+		return DM_HARTINFO_field_value(context, offset, value);
+	case DM_HAWINDOWSEL_ORDINAL:
+		return DM_HAWINDOWSEL_field_value(context, offset, value);
+	case DM_HAWINDOW_ORDINAL:
+		return DM_HAWINDOW_field_value(context, offset, value);
+	case DM_ABSTRACTCS_ORDINAL:
+		return DM_ABSTRACTCS_field_value(context, offset, value);
+	case DM_COMMAND_ORDINAL:
+		return DM_COMMAND_field_value(context, offset, value);
+	case DM_ABSTRACTAUTO_ORDINAL:
+		return DM_ABSTRACTAUTO_field_value(context, offset, value);
+	case DM_CONFSTRPTR0_ORDINAL:
+		return DM_CONFSTRPTR0_field_value(context, offset, value);
+	case DM_CONFSTRPTR1_ORDINAL:
+		return DM_CONFSTRPTR1_field_value(context, offset, value);
+	case DM_CONFSTRPTR2_ORDINAL:
+		return DM_CONFSTRPTR2_field_value(context, offset, value);
+	case DM_CONFSTRPTR3_ORDINAL:
+		return DM_CONFSTRPTR3_field_value(context, offset, value);
+	case DM_NEXTDM_ORDINAL:
+		return DM_NEXTDM_field_value(context, offset, value);
+	case DM_DATA0_ORDINAL:
+		return DM_DATA0_field_value(context, offset, value);
+	case DM_PROGBUF0_ORDINAL:
+		return DM_PROGBUF0_field_value(context, offset, value);
+	case DM_AUTHDATA_ORDINAL:
+		return DM_AUTHDATA_field_value(context, offset, value);
+	case DM_DMCS2_ORDINAL:
+		return DM_DMCS2_field_value(context, offset, value);
+	case DM_HALTSUM0_ORDINAL:
+		return DM_HALTSUM0_field_value(context, offset, value);
+	case DM_HALTSUM1_ORDINAL:
+		return DM_HALTSUM1_field_value(context, offset, value);
+	case DM_HALTSUM2_ORDINAL:
+		return DM_HALTSUM2_field_value(context, offset, value);
+	case DM_HALTSUM3_ORDINAL:
+		return DM_HALTSUM3_field_value(context, offset, value);
+	case DM_SBCS_ORDINAL:
+		return DM_SBCS_field_value(context, offset, value);
+	case DM_SBADDRESS0_ORDINAL:
+		return DM_SBADDRESS0_field_value(context, offset, value);
+	case DM_SBADDRESS1_ORDINAL:
+		return DM_SBADDRESS1_field_value(context, offset, value);
+	case DM_SBADDRESS2_ORDINAL:
+		return DM_SBADDRESS2_field_value(context, offset, value);
+	case DM_SBADDRESS3_ORDINAL:
+		return DM_SBADDRESS3_field_value(context, offset, value);
+	case DM_SBDATA0_ORDINAL:
+		return DM_SBDATA0_field_value(context, offset, value);
+	case DM_SBDATA1_ORDINAL:
+		return DM_SBDATA1_field_value(context, offset, value);
+	case DM_SBDATA2_ORDINAL:
+		return DM_SBDATA2_field_value(context, offset, value);
+	case DM_SBDATA3_ORDINAL:
+		return DM_SBDATA3_field_value(context, offset, value);
+	case SHORTNAME_ORDINAL:
+		return SHORTNAME_field_value(context, offset, value);
+	case AC_ACCESS_REGISTER_ORDINAL:
+		return AC_ACCESS_REGISTER_field_value(context, offset, value);
+	case AC_QUICK_ACCESS_ORDINAL:
+		return AC_QUICK_ACCESS_field_value(context, offset, value);
+	case AC_ACCESS_MEMORY_ORDINAL:
+		return AC_ACCESS_MEMORY_field_value(context, offset, value);
+	case VIRT_PRIV_ORDINAL:
+		return VIRT_PRIV_field_value(context, offset, value);
+	case DMI_SERCS_ORDINAL:
+		return DMI_SERCS_field_value(context, offset, value);
+	case DMI_SERTX_ORDINAL:
+		return DMI_SERTX_field_value(context, offset, value);
+	case DMI_SERRX_ORDINAL:
+		return DMI_SERRX_field_value(context, offset, value);
+	default:
+		return 0;
+	}
+}
+
+const char *riscv_debug_reg_decode_field(
+		enum riscv_debug_reg_ordinal reg_ordinal, struct riscv_debug_reg_ctx context,
+		unsigned int offset,
+		unsigned long long field_value)
+{
+	switch (reg_ordinal) {
+	case DTM_IDCODE_ORDINAL:
+		return DTM_IDCODE_decode_field(context, offset, field_value);
+	case DTM_DTMCS_ORDINAL:
+		return DTM_DTMCS_decode_field(context, offset, field_value);
+	case DTM_DMI_ORDINAL:
+		return DTM_DMI_decode_field(context, offset, field_value);
+	case DTM_BYPASS_ORDINAL:
+		return DTM_BYPASS_decode_field(context, offset, field_value);
+	case CSR_DCSR_ORDINAL:
+		return CSR_DCSR_decode_field(context, offset, field_value);
+	case CSR_DPC_ORDINAL:
+		return CSR_DPC_decode_field(context, offset, field_value);
+	case CSR_TSELECT_ORDINAL:
+		return CSR_TSELECT_decode_field(context, offset, field_value);
+	case CSR_TDATA1_ORDINAL:
+		return CSR_TDATA1_decode_field(context, offset, field_value);
+	case CSR_TDATA2_ORDINAL:
+		return CSR_TDATA2_decode_field(context, offset, field_value);
+	case CSR_TDATA3_ORDINAL:
+		return CSR_TDATA3_decode_field(context, offset, field_value);
+	case CSR_TINFO_ORDINAL:
+		return CSR_TINFO_decode_field(context, offset, field_value);
+	case CSR_TCONTROL_ORDINAL:
+		return CSR_TCONTROL_decode_field(context, offset, field_value);
+	case CSR_HCONTEXT_ORDINAL:
+		return CSR_HCONTEXT_decode_field(context, offset, field_value);
+	case CSR_SCONTEXT_ORDINAL:
+		return CSR_SCONTEXT_decode_field(context, offset, field_value);
+	case CSR_MCONTROL_ORDINAL:
+		return CSR_MCONTROL_decode_field(context, offset, field_value);
+	case CSR_MCONTROL6_ORDINAL:
+		return CSR_MCONTROL6_decode_field(context, offset, field_value);
+	case CSR_ICOUNT_ORDINAL:
+		return CSR_ICOUNT_decode_field(context, offset, field_value);
+	case CSR_ITRIGGER_ORDINAL:
+		return CSR_ITRIGGER_decode_field(context, offset, field_value);
+	case CSR_ETRIGGER_ORDINAL:
+		return CSR_ETRIGGER_decode_field(context, offset, field_value);
+	case CSR_TMEXTTRIGGER_ORDINAL:
+		return CSR_TMEXTTRIGGER_decode_field(context, offset, field_value);
+	case CSR_TEXTRA32_ORDINAL:
+		return CSR_TEXTRA32_decode_field(context, offset, field_value);
+	case CSR_TEXTRA64_ORDINAL:
+		return CSR_TEXTRA64_decode_field(context, offset, field_value);
+	case DM_DMSTATUS_ORDINAL:
+		return DM_DMSTATUS_decode_field(context, offset, field_value);
+	case DM_DMCONTROL_ORDINAL:
+		return DM_DMCONTROL_decode_field(context, offset, field_value);
+	case DM_HARTINFO_ORDINAL:
+		return DM_HARTINFO_decode_field(context, offset, field_value);
+	case DM_HAWINDOWSEL_ORDINAL:
+		return DM_HAWINDOWSEL_decode_field(context, offset, field_value);
+	case DM_HAWINDOW_ORDINAL:
+		return DM_HAWINDOW_decode_field(context, offset, field_value);
+	case DM_ABSTRACTCS_ORDINAL:
+		return DM_ABSTRACTCS_decode_field(context, offset, field_value);
+	case DM_COMMAND_ORDINAL:
+		return DM_COMMAND_decode_field(context, offset, field_value);
+	case DM_ABSTRACTAUTO_ORDINAL:
+		return DM_ABSTRACTAUTO_decode_field(context, offset, field_value);
+	case DM_CONFSTRPTR0_ORDINAL:
+		return DM_CONFSTRPTR0_decode_field(context, offset, field_value);
+	case DM_CONFSTRPTR1_ORDINAL:
+		return DM_CONFSTRPTR1_decode_field(context, offset, field_value);
+	case DM_CONFSTRPTR2_ORDINAL:
+		return DM_CONFSTRPTR2_decode_field(context, offset, field_value);
+	case DM_CONFSTRPTR3_ORDINAL:
+		return DM_CONFSTRPTR3_decode_field(context, offset, field_value);
+	case DM_NEXTDM_ORDINAL:
+		return DM_NEXTDM_decode_field(context, offset, field_value);
+	case DM_DATA0_ORDINAL:
+		return DM_DATA0_decode_field(context, offset, field_value);
+	case DM_PROGBUF0_ORDINAL:
+		return DM_PROGBUF0_decode_field(context, offset, field_value);
+	case DM_AUTHDATA_ORDINAL:
+		return DM_AUTHDATA_decode_field(context, offset, field_value);
+	case DM_DMCS2_ORDINAL:
+		return DM_DMCS2_decode_field(context, offset, field_value);
+	case DM_HALTSUM0_ORDINAL:
+		return DM_HALTSUM0_decode_field(context, offset, field_value);
+	case DM_HALTSUM1_ORDINAL:
+		return DM_HALTSUM1_decode_field(context, offset, field_value);
+	case DM_HALTSUM2_ORDINAL:
+		return DM_HALTSUM2_decode_field(context, offset, field_value);
+	case DM_HALTSUM3_ORDINAL:
+		return DM_HALTSUM3_decode_field(context, offset, field_value);
+	case DM_SBCS_ORDINAL:
+		return DM_SBCS_decode_field(context, offset, field_value);
+	case DM_SBADDRESS0_ORDINAL:
+		return DM_SBADDRESS0_decode_field(context, offset, field_value);
+	case DM_SBADDRESS1_ORDINAL:
+		return DM_SBADDRESS1_decode_field(context, offset, field_value);
+	case DM_SBADDRESS2_ORDINAL:
+		return DM_SBADDRESS2_decode_field(context, offset, field_value);
+	case DM_SBADDRESS3_ORDINAL:
+		return DM_SBADDRESS3_decode_field(context, offset, field_value);
+	case DM_SBDATA0_ORDINAL:
+		return DM_SBDATA0_decode_field(context, offset, field_value);
+	case DM_SBDATA1_ORDINAL:
+		return DM_SBDATA1_decode_field(context, offset, field_value);
+	case DM_SBDATA2_ORDINAL:
+		return DM_SBDATA2_decode_field(context, offset, field_value);
+	case DM_SBDATA3_ORDINAL:
+		return DM_SBDATA3_decode_field(context, offset, field_value);
+	case SHORTNAME_ORDINAL:
+		return SHORTNAME_decode_field(context, offset, field_value);
+	case AC_ACCESS_REGISTER_ORDINAL:
+		return AC_ACCESS_REGISTER_decode_field(context, offset, field_value);
+	case AC_QUICK_ACCESS_ORDINAL:
+		return AC_QUICK_ACCESS_decode_field(context, offset, field_value);
+	case AC_ACCESS_MEMORY_ORDINAL:
+		return AC_ACCESS_MEMORY_decode_field(context, offset, field_value);
+	case VIRT_PRIV_ORDINAL:
+		return VIRT_PRIV_decode_field(context, offset, field_value);
+	case DMI_SERCS_ORDINAL:
+		return DMI_SERCS_decode_field(context, offset, field_value);
+	case DMI_SERTX_ORDINAL:
+		return DMI_SERTX_decode_field(context, offset, field_value);
+	case DMI_SERRX_ORDINAL:
+		return DMI_SERRX_decode_field(context, offset, field_value);
+	default:
+		return NULL;
+	}
+}
diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h
index 8113d47664..a225b2fd40 100644
--- a/src/target/riscv/debug_defines.h
+++ b/src/target/riscv/debug_defines.h
@@ -1,6 +1,6 @@
 /*
  * This file is auto-generated by running 'make debug_defines.h' in
- * https://github.com/riscv/riscv-debug-spec/ (d749752)
+ * https://github.com/riscv/riscv-debug-spec/ (d749752-dirty)
  */
 
 #define DTM_IDCODE                          0x01
@@ -100,8 +100,8 @@
  * to access the DM over the DMI.
  */
 #define DTM_DMI_ADDRESS_OFFSET              0x22
-#define DTM_DMI_ADDRESS_LENGTH(abits)       abits
-#define DTM_DMI_ADDRESS(abits)              ((0x400000000ULL * (1ULL<<abits)) + -0x400000000ULL)
+#define DTM_DMI_ADDRESS_LENGTH(abits)       (abits)
+#define DTM_DMI_ADDRESS(abits)              ((0x400000000ULL * (1ULL << (abits))) + -0x400000000ULL)
 /*
  * The data to send to the DM over the DMI during Update-DR, and
  * the data returned from the DM as a result of the previous operation.
@@ -407,18 +407,18 @@
 #define CSR_DCSR_PRV                        3
 #define CSR_DPC                             0x7b1
 #define CSR_DPC_DPC_OFFSET                  0
-#define CSR_DPC_DPC_LENGTH(DXLEN)           DXLEN
-#define CSR_DPC_DPC(DXLEN)                  ((1ULL<<DXLEN) + -1)
+#define CSR_DPC_DPC_LENGTH(DXLEN)           (DXLEN)
+#define CSR_DPC_DPC(DXLEN)                  ((1ULL << (DXLEN)) + -1)
 #define CSR_DSCRATCH0                       0x7b2
 #define CSR_DSCRATCH1                       0x7b3
 #define CSR_TSELECT                         0x7a0
 #define CSR_TSELECT_INDEX_OFFSET            0
-#define CSR_TSELECT_INDEX_LENGTH(XLEN)      XLEN
-#define CSR_TSELECT_INDEX(XLEN)             ((1ULL<<XLEN) + -1)
+#define CSR_TSELECT_INDEX_LENGTH(XLEN)      (XLEN)
+#define CSR_TSELECT_INDEX(XLEN)             ((1ULL << (XLEN)) + -1)
 #define CSR_TDATA1                          0x7a1
-#define CSR_TDATA1_TYPE_OFFSET(XLEN)        (XLEN + -4)
+#define CSR_TDATA1_TYPE_OFFSET(XLEN)        ((XLEN) + -4)
 #define CSR_TDATA1_TYPE_LENGTH              4
-#define CSR_TDATA1_TYPE(XLEN)               (0xf * (1ULL<<(XLEN + -4)))
+#define CSR_TDATA1_TYPE(XLEN)               (0xf * (1ULL << ((XLEN) + -4)))
 /*
  * none: There is no trigger at this \RcsrTselect.
  */
@@ -478,9 +478,9 @@
 /*
  * If \FcsrTdataOneType is 0, then this bit is hard-wired to 0.
  */
-#define CSR_TDATA1_DMODE_OFFSET(XLEN)       (XLEN + -5)
+#define CSR_TDATA1_DMODE_OFFSET(XLEN)       ((XLEN) + -5)
 #define CSR_TDATA1_DMODE_LENGTH             1
-#define CSR_TDATA1_DMODE(XLEN)              (1ULL<<(XLEN + -5))
+#define CSR_TDATA1_DMODE(XLEN)              (1ULL << ((XLEN) + -5))
 /*
  * both: Both Debug and M-mode can write the {\tt tdata} registers at the
  * selected \RcsrTselect.
@@ -505,16 +505,16 @@
  * Trigger-specific data.
  */
 #define CSR_TDATA1_DATA_OFFSET              0
-#define CSR_TDATA1_DATA_LENGTH(XLEN)        (XLEN + -5)
-#define CSR_TDATA1_DATA(XLEN)               ((1ULL<<(XLEN + -5)) + -1)
+#define CSR_TDATA1_DATA_LENGTH(XLEN)        ((XLEN) + -5)
+#define CSR_TDATA1_DATA(XLEN)               ((1ULL << ((XLEN) + -5)) + -1)
 #define CSR_TDATA2                          0x7a2
 #define CSR_TDATA2_DATA_OFFSET              0
-#define CSR_TDATA2_DATA_LENGTH(XLEN)        XLEN
-#define CSR_TDATA2_DATA(XLEN)               ((1ULL<<XLEN) + -1)
+#define CSR_TDATA2_DATA_LENGTH(XLEN)        (XLEN)
+#define CSR_TDATA2_DATA(XLEN)               ((1ULL << (XLEN)) + -1)
 #define CSR_TDATA3                          0x7a3
 #define CSR_TDATA3_DATA_OFFSET              0
-#define CSR_TDATA3_DATA_LENGTH(XLEN)        XLEN
-#define CSR_TDATA3_DATA(XLEN)               ((1ULL<<XLEN) + -1)
+#define CSR_TDATA3_DATA_LENGTH(XLEN)        (XLEN)
+#define CSR_TDATA3_DATA(XLEN)               ((1ULL << (XLEN)) + -1)
 #define CSR_TINFO                           0x7a4
 /*
  * One bit for each possible \FcsrTdataOneType enumerated in \RcsrTdataOne. Bit N
@@ -573,8 +573,8 @@
  * and 14 on RV64.
  */
 #define CSR_HCONTEXT_HCONTEXT_OFFSET        0
-#define CSR_HCONTEXT_HCONTEXT_LENGTH(XLEN)  XLEN
-#define CSR_HCONTEXT_HCONTEXT(XLEN)         ((1ULL<<XLEN) + -1)
+#define CSR_HCONTEXT_HCONTEXT_LENGTH(XLEN)  (XLEN)
+#define CSR_HCONTEXT_HCONTEXT(XLEN)         ((1ULL << (XLEN)) + -1)
 #define CSR_SCONTEXT                        0x5a8
 /*
  * Supervisor mode software can write a context number to this
@@ -586,17 +586,17 @@
  * 34 on RV64.
  */
 #define CSR_SCONTEXT_DATA_OFFSET            0
-#define CSR_SCONTEXT_DATA_LENGTH(XLEN)      XLEN
-#define CSR_SCONTEXT_DATA(XLEN)             ((1ULL<<XLEN) + -1)
+#define CSR_SCONTEXT_DATA_LENGTH(XLEN)      (XLEN)
+#define CSR_SCONTEXT_DATA(XLEN)             ((1ULL << (XLEN)) + -1)
 #define CSR_MCONTEXT                        0x7a8
 #define CSR_MSCONTEXT                       0x7aa
 #define CSR_MCONTROL                        0x7a1
-#define CSR_MCONTROL_TYPE_OFFSET(XLEN)      (XLEN + -4)
+#define CSR_MCONTROL_TYPE_OFFSET(XLEN)      ((XLEN) + -4)
 #define CSR_MCONTROL_TYPE_LENGTH            4
-#define CSR_MCONTROL_TYPE(XLEN)             (0xf * (1ULL<<(XLEN + -4)))
-#define CSR_MCONTROL_DMODE_OFFSET(XLEN)     (XLEN + -5)
+#define CSR_MCONTROL_TYPE(XLEN)             (0xf * (1ULL << ((XLEN) + -4)))
+#define CSR_MCONTROL_DMODE_OFFSET(XLEN)     ((XLEN) + -5)
 #define CSR_MCONTROL_DMODE_LENGTH           1
-#define CSR_MCONTROL_DMODE(XLEN)            (1ULL<<(XLEN + -5))
+#define CSR_MCONTROL_DMODE(XLEN)            (1ULL << ((XLEN) + -5))
 /*
  * Specifies the largest naturally aligned powers-of-two (NAPOT) range
  * supported by the hardware when \FcsrMcontrolMatch is 1. The value is the
@@ -605,9 +605,9 @@
  * A value of 63 corresponds to the maximum NAPOT range, which is
  * $2^{63}$ bytes in size.
  */
-#define CSR_MCONTROL_MASKMAX_OFFSET(XLEN)   (XLEN + -0xb)
+#define CSR_MCONTROL_MASKMAX_OFFSET(XLEN)   ((XLEN) + -0xb)
 #define CSR_MCONTROL_MASKMAX_LENGTH         6
-#define CSR_MCONTROL_MASKMAX(XLEN)          (0x3f * (1ULL<<(XLEN + -0xb)))
+#define CSR_MCONTROL_MASKMAX(XLEN)          (0x3f * (1ULL << ((XLEN) + -0xb)))
 /*
  * This field only exists when XLEN is at least 64.
  * It contains the 2 high bits of the access size. The low bits
@@ -946,12 +946,12 @@
 #define CSR_MCONTROL_LOAD_LENGTH            1
 #define CSR_MCONTROL_LOAD                   1
 #define CSR_MCONTROL6                       0x7a1
-#define CSR_MCONTROL6_TYPE_OFFSET(XLEN)     (XLEN + -4)
+#define CSR_MCONTROL6_TYPE_OFFSET(XLEN)     ((XLEN) + -4)
 #define CSR_MCONTROL6_TYPE_LENGTH           4
-#define CSR_MCONTROL6_TYPE(XLEN)            (0xf * (1ULL<<(XLEN + -4)))
-#define CSR_MCONTROL6_DMODE_OFFSET(XLEN)    (XLEN + -5)
+#define CSR_MCONTROL6_TYPE(XLEN)            (0xf * (1ULL << ((XLEN) + -4)))
+#define CSR_MCONTROL6_DMODE_OFFSET(XLEN)    ((XLEN) + -5)
 #define CSR_MCONTROL6_DMODE_LENGTH          1
-#define CSR_MCONTROL6_DMODE(XLEN)           (1ULL<<(XLEN + -5))
+#define CSR_MCONTROL6_DMODE(XLEN)           (1ULL << ((XLEN) + -5))
 /*
  * When set, enable this trigger in VS-mode.
  * This bit is hard-wired to 0 if the hart does not support
@@ -1295,12 +1295,12 @@
 #define CSR_MCONTROL6_LOAD_LENGTH           1
 #define CSR_MCONTROL6_LOAD                  1
 #define CSR_ICOUNT                          0x7a1
-#define CSR_ICOUNT_TYPE_OFFSET(XLEN)        (XLEN + -4)
+#define CSR_ICOUNT_TYPE_OFFSET(XLEN)        ((XLEN) + -4)
 #define CSR_ICOUNT_TYPE_LENGTH              4
-#define CSR_ICOUNT_TYPE(XLEN)               (0xf * (1ULL<<(XLEN + -4)))
-#define CSR_ICOUNT_DMODE_OFFSET(XLEN)       (XLEN + -5)
+#define CSR_ICOUNT_TYPE(XLEN)               (0xf * (1ULL << ((XLEN) + -4)))
+#define CSR_ICOUNT_DMODE_OFFSET(XLEN)       ((XLEN) + -5)
 #define CSR_ICOUNT_DMODE_LENGTH             1
-#define CSR_ICOUNT_DMODE(XLEN)              (1ULL<<(XLEN + -5))
+#define CSR_ICOUNT_DMODE(XLEN)              (1ULL << ((XLEN) + -5))
 /*
  * When set, enable this trigger in VS-mode.
  * This bit is hard-wired to 0 if the hart does not support
@@ -1400,12 +1400,12 @@
  */
 #define CSR_ICOUNT_ACTION_EXTERNAL1         9
 #define CSR_ITRIGGER                        0x7a1
-#define CSR_ITRIGGER_TYPE_OFFSET(XLEN)      (XLEN + -4)
+#define CSR_ITRIGGER_TYPE_OFFSET(XLEN)      ((XLEN) + -4)
 #define CSR_ITRIGGER_TYPE_LENGTH            4
-#define CSR_ITRIGGER_TYPE(XLEN)             (0xf * (1ULL<<(XLEN + -4)))
-#define CSR_ITRIGGER_DMODE_OFFSET(XLEN)     (XLEN + -5)
+#define CSR_ITRIGGER_TYPE(XLEN)             (0xf * (1ULL << ((XLEN) + -4)))
+#define CSR_ITRIGGER_DMODE_OFFSET(XLEN)     ((XLEN) + -5)
 #define CSR_ITRIGGER_DMODE_LENGTH           1
-#define CSR_ITRIGGER_DMODE(XLEN)            (1ULL<<(XLEN + -5))
+#define CSR_ITRIGGER_DMODE(XLEN)            (1ULL << ((XLEN) + -5))
 /*
  * If this bit is implemented, the hardware sets it when this
  * trigger matches. The trigger's user can set or clear it at any
@@ -1413,9 +1413,9 @@
  * trigger(s) matched.  If the bit is not implemented, it is always 0
  * and writing it has no effect.
  */
-#define CSR_ITRIGGER_HIT_OFFSET(XLEN)       (XLEN + -6)
+#define CSR_ITRIGGER_HIT_OFFSET(XLEN)       ((XLEN) + -6)
 #define CSR_ITRIGGER_HIT_LENGTH             1
-#define CSR_ITRIGGER_HIT(XLEN)              (1ULL<<(XLEN + -6))
+#define CSR_ITRIGGER_HIT(XLEN)              (1ULL << ((XLEN) + -6))
 /*
  * When set, enable this trigger for interrupts that are taken from VS
  * mode.
@@ -1502,12 +1502,12 @@
  */
 #define CSR_ITRIGGER_ACTION_EXTERNAL1       9
 #define CSR_ETRIGGER                        0x7a1
-#define CSR_ETRIGGER_TYPE_OFFSET(XLEN)      (XLEN + -4)
+#define CSR_ETRIGGER_TYPE_OFFSET(XLEN)      ((XLEN) + -4)
 #define CSR_ETRIGGER_TYPE_LENGTH            4
-#define CSR_ETRIGGER_TYPE(XLEN)             (0xf * (1ULL<<(XLEN + -4)))
-#define CSR_ETRIGGER_DMODE_OFFSET(XLEN)     (XLEN + -5)
+#define CSR_ETRIGGER_TYPE(XLEN)             (0xf * (1ULL << ((XLEN) + -4)))
+#define CSR_ETRIGGER_DMODE_OFFSET(XLEN)     ((XLEN) + -5)
 #define CSR_ETRIGGER_DMODE_LENGTH           1
-#define CSR_ETRIGGER_DMODE(XLEN)            (1ULL<<(XLEN + -5))
+#define CSR_ETRIGGER_DMODE(XLEN)            (1ULL << ((XLEN) + -5))
 /*
  * If this bit is implemented, the hardware sets it when this
  * trigger matches. The trigger's user can set or clear it at any
@@ -1515,9 +1515,9 @@
  * trigger(s) matched.  If the bit is not implemented, it is always 0
  * and writing it has no effect.
  */
-#define CSR_ETRIGGER_HIT_OFFSET(XLEN)       (XLEN + -6)
+#define CSR_ETRIGGER_HIT_OFFSET(XLEN)       ((XLEN) + -6)
 #define CSR_ETRIGGER_HIT_LENGTH             1
-#define CSR_ETRIGGER_HIT(XLEN)              (1ULL<<(XLEN + -6))
+#define CSR_ETRIGGER_HIT(XLEN)              (1ULL << ((XLEN) + -6))
 /*
  * When set, enable this trigger for exceptions that are taken from VS
  * mode.
@@ -1597,12 +1597,12 @@
  */
 #define CSR_ETRIGGER_ACTION_EXTERNAL1       9
 #define CSR_TMEXTTRIGGER                    0x7a1
-#define CSR_TMEXTTRIGGER_TYPE_OFFSET(XLEN)  (XLEN + -4)
+#define CSR_TMEXTTRIGGER_TYPE_OFFSET(XLEN)  ((XLEN) + -4)
 #define CSR_TMEXTTRIGGER_TYPE_LENGTH        4
-#define CSR_TMEXTTRIGGER_TYPE(XLEN)         (0xf * (1ULL<<(XLEN + -4)))
-#define CSR_TMEXTTRIGGER_DMODE_OFFSET(XLEN) (XLEN + -5)
+#define CSR_TMEXTTRIGGER_TYPE(XLEN)         (0xf * (1ULL << ((XLEN) + -4)))
+#define CSR_TMEXTTRIGGER_DMODE_OFFSET(XLEN) ((XLEN) + -5)
 #define CSR_TMEXTTRIGGER_DMODE_LENGTH       1
-#define CSR_TMEXTTRIGGER_DMODE(XLEN)        (1ULL<<(XLEN + -5))
+#define CSR_TMEXTTRIGGER_DMODE(XLEN)        (1ULL << ((XLEN) + -5))
 /*
  * If this bit is implemented, the hardware sets it when this
  * trigger matches. The trigger's user can set or clear it at any
@@ -1610,9 +1610,9 @@
  * trigger(s) matched.  If the bit is not implemented, it is always 0
  * and writing it has no effect.
  */
-#define CSR_TMEXTTRIGGER_HIT_OFFSET(XLEN)   (XLEN + -6)
+#define CSR_TMEXTTRIGGER_HIT_OFFSET(XLEN)   ((XLEN) + -6)
 #define CSR_TMEXTTRIGGER_HIT_LENGTH         1
-#define CSR_TMEXTTRIGGER_HIT(XLEN)          (1ULL<<(XLEN + -6))
+#define CSR_TMEXTTRIGGER_HIT(XLEN)          (1ULL << ((XLEN) + -6))
 /*
  * This optional bit, when set, causes this trigger to fire whenever an attached
  * interrupt controller signals a trigger.
@@ -3059,3 +3059,95 @@
 #define DMI_SERRX_DATA_OFFSET               0
 #define DMI_SERRX_DATA_LENGTH               0x20
 #define DMI_SERRX_DATA                      0xffffffffU
+#ifndef DEBUG_DEFINES_H
+#define DEBUG_DEFINES_H
+enum riscv_debug_reg_ordinal {
+	DTM_IDCODE_ORDINAL,
+	DTM_DTMCS_ORDINAL,
+	DTM_DMI_ORDINAL,
+	DTM_BYPASS_ORDINAL,
+	CSR_DCSR_ORDINAL,
+	CSR_DPC_ORDINAL,
+	CSR_TSELECT_ORDINAL,
+	CSR_TDATA1_ORDINAL,
+	CSR_TDATA2_ORDINAL,
+	CSR_TDATA3_ORDINAL,
+	CSR_TINFO_ORDINAL,
+	CSR_TCONTROL_ORDINAL,
+	CSR_HCONTEXT_ORDINAL,
+	CSR_SCONTEXT_ORDINAL,
+	CSR_MCONTROL_ORDINAL,
+	CSR_MCONTROL6_ORDINAL,
+	CSR_ICOUNT_ORDINAL,
+	CSR_ITRIGGER_ORDINAL,
+	CSR_ETRIGGER_ORDINAL,
+	CSR_TMEXTTRIGGER_ORDINAL,
+	CSR_TEXTRA32_ORDINAL,
+	CSR_TEXTRA64_ORDINAL,
+	DM_DMSTATUS_ORDINAL,
+	DM_DMCONTROL_ORDINAL,
+	DM_HARTINFO_ORDINAL,
+	DM_HAWINDOWSEL_ORDINAL,
+	DM_HAWINDOW_ORDINAL,
+	DM_ABSTRACTCS_ORDINAL,
+	DM_COMMAND_ORDINAL,
+	DM_ABSTRACTAUTO_ORDINAL,
+	DM_CONFSTRPTR0_ORDINAL,
+	DM_CONFSTRPTR1_ORDINAL,
+	DM_CONFSTRPTR2_ORDINAL,
+	DM_CONFSTRPTR3_ORDINAL,
+	DM_NEXTDM_ORDINAL,
+	DM_DATA0_ORDINAL,
+	DM_PROGBUF0_ORDINAL,
+	DM_AUTHDATA_ORDINAL,
+	DM_DMCS2_ORDINAL,
+	DM_HALTSUM0_ORDINAL,
+	DM_HALTSUM1_ORDINAL,
+	DM_HALTSUM2_ORDINAL,
+	DM_HALTSUM3_ORDINAL,
+	DM_SBCS_ORDINAL,
+	DM_SBADDRESS0_ORDINAL,
+	DM_SBADDRESS1_ORDINAL,
+	DM_SBADDRESS2_ORDINAL,
+	DM_SBADDRESS3_ORDINAL,
+	DM_SBDATA0_ORDINAL,
+	DM_SBDATA1_ORDINAL,
+	DM_SBDATA2_ORDINAL,
+	DM_SBDATA3_ORDINAL,
+	SHORTNAME_ORDINAL,
+	AC_ACCESS_REGISTER_ORDINAL,
+	AC_QUICK_ACCESS_ORDINAL,
+	AC_ACCESS_MEMORY_ORDINAL,
+	VIRT_PRIV_ORDINAL,
+	DMI_SERCS_ORDINAL,
+	DMI_SERTX_ORDINAL,
+	DMI_SERRX_ORDINAL
+};
+struct riscv_debug_reg_ctx {
+	struct {
+		unsigned int value; int is_set;
+	} abits;
+	struct {
+		unsigned int value; int is_set;
+	} DXLEN;
+	struct {
+		unsigned int value; int is_set;
+	} XLEN;
+};
+unsigned int riscv_debug_reg_width(enum riscv_debug_reg_ordinal reg_ordinal,
+		struct riscv_debug_reg_ctx context);
+unsigned int riscv_debug_reg_field_is_present(
+		enum riscv_debug_reg_ordinal reg_ordinal, struct riscv_debug_reg_ctx context,
+		unsigned int offset);
+const char *riscv_debug_reg_field_name(
+		enum riscv_debug_reg_ordinal reg_ordinal, struct riscv_debug_reg_ctx context,
+		unsigned int offset);
+unsigned long long riscv_debug_reg_field_value(
+		enum riscv_debug_reg_ordinal reg_ordinal, struct riscv_debug_reg_ctx context,
+		unsigned int offset,
+		unsigned long long value);
+const char *riscv_debug_reg_decode_field(
+		enum riscv_debug_reg_ordinal reg_ordinal, struct riscv_debug_reg_ctx context,
+		unsigned int offset,
+		unsigned long long field_value);
+#endif
diff --git a/src/target/riscv/debug_register_printers.c b/src/target/riscv/debug_register_printers.c
new file mode 100644
index 0000000000..83419cab44
--- /dev/null
+++ b/src/target/riscv/debug_register_printers.c
@@ -0,0 +1,79 @@
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+#include <stdarg.h>
+
+#include "debug_register_printers.h"
+
+unsigned int get_len_or_sprintf(char *buf, unsigned int curr, const char *format, ...)
+{
+	assert(format);
+	va_list args;
+	int length;
+
+	va_start(args, format);
+	if (buf)
+		length = vsprintf(buf + curr, format, args);
+	else
+		length = vsnprintf(NULL, 0, format, args);
+	va_end(args);
+	assert(length >= 0);
+	return (unsigned int)length;
+}
+
+unsigned int print_value(char *buf, unsigned int curr, uint64_t value)
+{
+	const char * const format = value > 9 ? "0x%" PRIx64 : "%" PRIx64;
+
+	return get_len_or_sprintf(buf, curr, format, value);
+}
+
+unsigned int riscv_debug_reg_field_value_to_s(char *buf, unsigned int curr,
+		enum riscv_debug_reg_ordinal reg_ordinal,
+		struct riscv_debug_reg_ctx context,
+		unsigned int offset, uint64_t field_value)
+{
+	const char * const field_value_name = riscv_debug_reg_decode_field(
+			reg_ordinal, context, offset, field_value);
+
+	if (!field_value_name)
+		return print_value(buf, curr, field_value);
+	return get_len_or_sprintf(buf, curr, "%s", field_value_name);
+}
+
+unsigned int riscv_debug_reg_field_to_s(char *buf, unsigned int curr,
+		enum riscv_debug_reg_ordinal reg_ordinal,
+		struct riscv_debug_reg_ctx context,
+		unsigned int offset, uint64_t field_value)
+{
+	const char * const field_name = riscv_debug_reg_field_name(reg_ordinal,
+			context, offset);
+	assert(field_name);
+	const unsigned int name_len = get_len_or_sprintf(buf, curr, "%s=", field_name);
+
+	return name_len + riscv_debug_reg_field_value_to_s(buf, curr + name_len,
+			reg_ordinal, context, offset, field_value);
+}
+
+unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
+		struct riscv_debug_reg_ctx context, uint64_t value)
+{
+	unsigned int length = 0;
+
+	length += print_value(buf, length, value);
+	length += get_len_or_sprintf(buf, length, " { ");
+
+	const unsigned int width = riscv_debug_reg_width(reg_ordinal, context);
+
+	for (unsigned int offset = 0; offset < width; ++offset) {
+		if (!riscv_debug_reg_field_is_present(reg_ordinal, context, offset))
+			continue;
+		length += riscv_debug_reg_field_to_s(buf, length, reg_ordinal, context, offset,
+				riscv_debug_reg_field_value(reg_ordinal, context, offset, value));
+		length += get_len_or_sprintf(buf, length, ", ");
+	}
+	length += get_len_or_sprintf(buf, length, "}");
+	if (buf)
+		buf[length] = '\0';
+	return length;
+}
diff --git a/src/target/riscv/debug_register_printers.h b/src/target/riscv/debug_register_printers.h
new file mode 100644
index 0000000000..19913f812d
--- /dev/null
+++ b/src/target/riscv/debug_register_printers.h
@@ -0,0 +1,6 @@
+#include <stdbool.h>
+
+#include "debug_defines.h"
+
+unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
+		struct riscv_debug_reg_ctx context, uint64_t value);
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 817d65f6cf..98f7d06c43 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -28,6 +28,7 @@
 #include "program.h"
 #include "asm.h"
 #include "batch.h"
+#include "debug_register_printers.h"
 
 static int riscv013_on_step_or_resume(struct target *target, bool step);
 static int riscv013_step_or_resume_current_hart(struct target *target,
@@ -285,6 +286,31 @@ static dm013_info_t *get_dm(struct target *target)
 	return dm;
 }
 
+static struct riscv_debug_reg_ctx get_riscv_debug_reg_ctx(struct target *target)
+{
+	RISCV_INFO(r);
+	RISCV013_INFO(info);
+	const struct riscv_debug_reg_ctx context = {
+		.XLEN = { .value = r->xlen, .is_set = true },
+		.DXLEN = { .value = r->xlen, .is_set = true },
+		.abits = { .value = info->abits, .is_set = true },
+	};
+	return context;
+}
+
+#define RISCV_LOG_REG(target, reg, value) \
+do {\
+	if (debug_level < LOG_LVL_DEBUG)\
+		break;\
+	typeof(target) _target = (target);\
+	typeof(value) _value = (value);\
+	const enum riscv_debug_reg_ordinal _reg = reg##_ORDINAL;\
+	const struct riscv_debug_reg_ctx _context = get_riscv_debug_reg_ctx(_target);\
+	char buf[riscv_debug_reg_to_s(NULL, _reg, _context, _value) + 1];\
+	riscv_debug_reg_to_s(buf, _reg, _context,  _value);\
+	LOG_TARGET_DEBUG(_target, "%s", buf);\
+} while (false)
+
 static uint32_t set_dmcontrol_hartsel(uint32_t initial, int hart_index)
 {
 	assert(hart_index != HART_INDEX_UNKNOWN);
@@ -306,91 +332,42 @@ static uint32_t set_dmcontrol_hartsel(uint32_t initial, int hart_index)
 	return initial;
 }
 
-static void decode_dm(char *text, unsigned int address, unsigned int data)
+static unsigned int decode_dm(char *text, unsigned int address, unsigned int data)
 {
 	static const struct {
 		unsigned int address;
-		uint64_t mask;
-		const char *name;
+		enum riscv_debug_reg_ordinal ordinal;
 	} description[] = {
-		{ DM_DMCONTROL, DM_DMCONTROL_HALTREQ, "haltreq" },
-		{ DM_DMCONTROL, DM_DMCONTROL_RESUMEREQ, "resumereq" },
-		{ DM_DMCONTROL, DM_DMCONTROL_HARTRESET, "hartreset" },
-		{ DM_DMCONTROL, DM_DMCONTROL_HASEL, "hasel" },
-		{ DM_DMCONTROL, DM_DMCONTROL_HARTSELHI, "hartselhi" },
-		{ DM_DMCONTROL, DM_DMCONTROL_HARTSELLO, "hartsello" },
-		{ DM_DMCONTROL, DM_DMCONTROL_NDMRESET, "ndmreset" },
-		{ DM_DMCONTROL, DM_DMCONTROL_DMACTIVE, "dmactive" },
-		{ DM_DMCONTROL, DM_DMCONTROL_ACKHAVERESET, "ackhavereset" },
-
-		{ DM_DMSTATUS, DM_DMSTATUS_IMPEBREAK, "impebreak" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ALLHAVERESET, "allhavereset" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ANYHAVERESET, "anyhavereset" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ALLRESUMEACK, "allresumeack" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ANYRESUMEACK, "anyresumeack" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ALLNONEXISTENT, "allnonexistent" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ANYNONEXISTENT, "anynonexistent" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ALLUNAVAIL, "allunavail" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ANYUNAVAIL, "anyunavail" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ALLRUNNING, "allrunning" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ANYRUNNING, "anyrunning" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ALLHALTED, "allhalted" },
-		{ DM_DMSTATUS, DM_DMSTATUS_ANYHALTED, "anyhalted" },
-		{ DM_DMSTATUS, DM_DMSTATUS_AUTHENTICATED, "authenticated" },
-		{ DM_DMSTATUS, DM_DMSTATUS_AUTHBUSY, "authbusy" },
-		{ DM_DMSTATUS, DM_DMSTATUS_HASRESETHALTREQ, "hasresethaltreq" },
-		{ DM_DMSTATUS, DM_DMSTATUS_CONFSTRPTRVALID, "confstrptrvalid" },
-		{ DM_DMSTATUS, DM_DMSTATUS_VERSION, "version" },
-
-		{ DM_ABSTRACTCS, DM_ABSTRACTCS_PROGBUFSIZE, "progbufsize" },
-		{ DM_ABSTRACTCS, DM_ABSTRACTCS_BUSY, "busy" },
-		{ DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR, "cmderr" },
-		{ DM_ABSTRACTCS, DM_ABSTRACTCS_DATACOUNT, "datacount" },
-
-		{ DM_COMMAND, DM_COMMAND_CMDTYPE, "cmdtype" },
-
-		{ DM_SBCS, DM_SBCS_SBVERSION, "sbversion" },
-		{ DM_SBCS, DM_SBCS_SBBUSYERROR, "sbbusyerror" },
-		{ DM_SBCS, DM_SBCS_SBBUSY, "sbbusy" },
-		{ DM_SBCS, DM_SBCS_SBREADONADDR, "sbreadonaddr" },
-		{ DM_SBCS, DM_SBCS_SBACCESS, "sbaccess" },
-		{ DM_SBCS, DM_SBCS_SBAUTOINCREMENT, "sbautoincrement" },
-		{ DM_SBCS, DM_SBCS_SBREADONDATA, "sbreadondata" },
-		{ DM_SBCS, DM_SBCS_SBERROR, "sberror" },
-		{ DM_SBCS, DM_SBCS_SBASIZE, "sbasize" },
-		{ DM_SBCS, DM_SBCS_SBACCESS128, "sbaccess128" },
-		{ DM_SBCS, DM_SBCS_SBACCESS64, "sbaccess64" },
-		{ DM_SBCS, DM_SBCS_SBACCESS32, "sbaccess32" },
-		{ DM_SBCS, DM_SBCS_SBACCESS16, "sbaccess16" },
-		{ DM_SBCS, DM_SBCS_SBACCESS8, "sbaccess8" },
+#define DECL_DMI_DESC(ADDR) {ADDR, ADDR##_ORDINAL}
+		DECL_DMI_DESC(DM_DMCONTROL),
+		DECL_DMI_DESC(DM_DMSTATUS),
+		DECL_DMI_DESC(DM_ABSTRACTCS),
+		DECL_DMI_DESC(DM_COMMAND),
+		DECL_DMI_DESC(DM_SBCS)
+#undef DECL_DMI_DESC
 	};
 
-	text[0] = 0;
 	for (unsigned i = 0; i < ARRAY_SIZE(description); i++) {
 		if (description[i].address == address) {
-			uint64_t mask = description[i].mask;
-			unsigned value = get_field(data, mask);
-			if (value) {
-				if (i > 0)
-					*(text++) = ' ';
-				if (mask & (mask >> 1)) {
-					/* If the field is more than 1 bit wide. */
-					sprintf(text, "%s=%d", description[i].name, value);
-				} else {
-					strcpy(text, description[i].name);
-				}
-				text += strlen(text);
-			}
+			const struct riscv_debug_reg_ctx context = {
+				.XLEN = { .value = 0, .is_set = false },
+				.DXLEN = { .value = 0, .is_set = false },
+				.abits = { .value = 0, .is_set = false },
+			};
+			return riscv_debug_reg_to_s(text, description[i].ordinal,
+					context, data);
 		}
 	}
+	return 0;
 }
 
-static void decode_dmi(struct target *target, char *text, unsigned int address, unsigned int data)
+static unsigned int decode_dmi(struct target *target, char *text, unsigned int address,
+		unsigned int data)
 {
 	dm013_info_t *dm = get_dm(target);
 	if (!dm)
-		return;
-	decode_dm(text, address - dm->base, data);
+		return 0;
+	return decode_dm(text, address - dm->base, data);
 }
 
 static void dump_field(struct target *target, int idle, const struct scan_field *field)
@@ -417,13 +394,13 @@ static void dump_field(struct target *target, int idle, const struct scan_field
 			field->num_bits, op_string[out_op], out_data, out_address,
 			status_string[in_op], in_data, in_address, idle);
 
-	char out_text[500];
-	char in_text[500];
-	decode_dmi(target, out_text, out_address, out_data);
-	decode_dmi(target, in_text, in_address, in_data);
+	char out_text[decode_dmi(target, NULL, out_address, out_data) + 1];
+	unsigned int out_len  = decode_dmi(target, out_text, out_address, out_data);
+	char in_text[decode_dmi(target, NULL, in_address, in_data) + 1];
+	unsigned int in_len = decode_dmi(target, in_text, in_address, in_data);
 	if (in_text[0] || out_text[0]) {
-		log_printf_lf(LOG_LVL_DEBUG, __FILE__, __LINE__, "scan", "%s -> %s",
-				out_text, in_text);
+		log_printf_lf(LOG_LVL_DEBUG, __FILE__, __LINE__, "scan", "%.*s -> %.*s",
+				out_len, out_text, in_len, in_text);
 	}
 }
 
@@ -880,14 +857,7 @@ static int execute_abstract_command(struct target *target, uint32_t command)
 	if (debug_level >= LOG_LVL_DEBUG) {
 		switch (get_field(command, DM_COMMAND_CMDTYPE)) {
 			case 0:
-				LOG_TARGET_DEBUG(target, "command=0x%x; access register, size=%d, postexec=%d, "
-						"transfer=%d, write=%d, regno=0x%x",
-						command,
-						8 << get_field(command, AC_ACCESS_REGISTER_AARSIZE),
-						get_field(command, AC_ACCESS_REGISTER_POSTEXEC),
-						get_field(command, AC_ACCESS_REGISTER_TRANSFER),
-						get_field(command, AC_ACCESS_REGISTER_WRITE),
-						get_field(command, AC_ACCESS_REGISTER_REGNO));
+				RISCV_LOG_REG(target, AC_ACCESS_REGISTER, command);
 				break;
 			default:
 				LOG_TARGET_DEBUG(target, "command=0x%x", command);