Zce architecture tests

[jjscheel]

Technical Group

Code Size Reduction TG

ratification-pkg

Code Size

Technical Liaison

Tariq Kurd

Task Category

Arch Tests

Task Sub Category

• gcc
• binutils
• gdb
• intrinsics
• Java
• KVM
• ld
• llvm
• Linux kernel
• QEMU
• Spike

Ratification Target

1Q2023

Statement of Work (SOW)

SOW link

SOW Signoffs: (delete those not needed)

• Task group liaison sign-off date:
• Development partner sign-off date:
• ACT SIG sign-off date (if ACT work):

Waiver

• Freeze
• Ratification

Pull Request Details

No response

[jjscheel]

Per 4/11 email from Prasanna:

Code size reduction: First set of test cases are written, they are being tested against Spike, dei run is in progress until the tests are pass - in progress

[ptprasanna]

No progress made since last Call. Was busy on Zfinx.

[jjscheel]

Ok. Please keep this as a focus item. We need to start showing progress here.

[ptprasanna]

The dry of the tests designed was resumed against SPIKE, still seeing few failures. Fixing/Modifying the tests/frameworks is underway.

[jjscheel]

Glad we are once again making progress!

[jjscheel]

@ptprasanna, any update?

[jjscheel]

@pz9115, raising this to your attention as @ptprasanna is working a possible toolchain issue.

[ptprasanna]

Possibly an issue, but discussing with @Abdulwadoodd to get different point of view, before we conclude the issue with the tool chain. Also discussing with @pz9115 as well.

[jjscheel]

Feed back from @Abdulwadoodd:

Toolchain works fine for Zce.
The error you are getting is because of illegal operands of instructions: The immediate offset of the instructions in the generated tests are incorrect.
If you look at the spec, c.lb* , c.lh* instructions only allowed to have 2-bit unsigned immediate offset (at max) which is not the case for your tests and hence the compilation error.
Do look the reserved lsb of unimm as well

You can try compiling the instruction like:
c.lh x10, 0(x12)
c.lh x8, 2(x13)

And it would work with the toolchain.

I hope this resolves your issue.

[ptprasanna]

Zcf - Tests are generated using CTG, but the execution is not successful. Possibly a tool-chain issue (assuming), or the generated test are wrong. Still investigating.
Zcd - Tests are generated using CTG, but the execution is not successful. Possibly a tool-chain issue (assuming), or the generated test are wrong. Still investigating.
Zcb - Tests are generated, but few cover-points are not meeting up, we are getting them sorted
Zcmp - Yet to start the tests
Zcmt - Yet to start the tests

[jjscheel]

Thanks, @ptprasanna! Will remove from Agenda for this week. Please feel free to reach out if you need technical assistance debugging.

[jjscheel]

@ptprasanna, please update status here.

[anuani21]

Regarding Zcf and Zcd extension, possibly an toolchain issue(assuming) and discussed with @pz9115.

Got a feedback from @pz9115,

1.Since Zce is not upstream yet,need to checkout gcc and binutils into the downstream repo,

Gcc: https://github.com/openhwgroup/corev-gcc/commits/development-08dd5f65b06
Binutils: https://github.com/openhwgroup/corev-binutils-gdb/commits/development-eddf4096b97

2. Use compile args -march= rv32imaf_zcf -mabi=ilp32f.
3. As per specification definition,need to discard zcmb extension.

As per the feedback,I have done all the changes but still I am facing the same issue. @pz9115, Can you give me any suggestions to resolve the issue?

[pz9115]

Regarding Zcf and Zcd extension, possibly an toolchain issue(assuming) and discussed with @pz9115.

Got a feedback from @pz9115,

1.Since Zce is not upstream yet,need to checkout gcc and binutils into the downstream repo,

Gcc: https://github.com/openhwgroup/corev-gcc/commits/development-08dd5f65b06 Binutils: https://github.com/openhwgroup/corev-binutils-gdb/commits/development-eddf4096b97

2. Use compile args -march= rv32imaf_zcf -mabi=ilp32f.
3. As per specification definition,need to discard zcmb extension.

As per the feedback,I have done all the changes but still I am facing the same issue. @pz9115, Can you give me any suggestions to resolve the issue?

Hi @anuani21, Can you provide the error log for me to learn more about the cause of the error, thanks.

[anuani21]

Hi @pz9115,

Here I have attached the error log for your reference.

error-log.odt

[pz9115]

Hi @pz9115,

Here I have attached the error log for your reference.

error-log.odt

Hi @anuani21, I found some compressed instructions that used in the log file, such as:

c.flw f15,-0x4(f15)
c.flw f14,0x0(f13)
c.flw f12,0x28(f11)

Where you use fpr as the second operand. As the instruction defination, it load from memory, computes an effective address by adding the zero-extended as offset scaled by 4.

So you should use gpr instead fpr as the second operand and set the offset positive and multiple it 4, such as:

c.flw f15,0x4(x15)
c.flw f14,0x0(x13)
c.flw f12,0x28(x11)

[Abdulwadoodd]

Hi @ptprasanna, @jjscheel

RISC-V Config PR is merged which adds support of Code size reduction extension to riscv-config tool
PR link: riscv-software-src/riscv-config#129

This was critical because RISCOF and ISAC use riscv config to run tests and generate coverage reports respectively. One can run Zce ACTs using RISCOF by updating the riscv-config version.

[anuani21]

Hi @pz9115,

As per your suggestions,I have done all the changes.Tests are run successfully and got 100% coverage for all instructions in Zcf and Zcd extensions.

[jjscheel]

Great news. How is the coverage coming for other extensions?

[ptprasanna]

Zcb - Completed 100% Coverage
Zcf - Completed 100% Coverage
Zcd - Completed 100% Coverage
Zcmp - @anuani21 is looking for some guidance or help from the community
Zcmt - @anuani21 is looking for some guidance or help from the community

[jjscheel]

@tariqkurd-repo, can you help @anuani21 with their questions on Zcmp and Zcmt?

[tariqkurd-repo]

What are the questions?

[jjscheel]

Ok, thank you!

[anuani21]

@jjscheel,

Restart the work of Zcmp and Zcmt extension by tomorrow.I will make progress on the task before the next meeting.

[anuani21]

@jjscheel,

Updates from IITM,
Zcmp extension:

cm.pop - Test generated and some coverpoints are not hitting.
cm.popret - Generating the test.
cm.popretz- Generating the test.

Zcmt extension:

c.jalt- Generating the test.

[jjscheel]

Thanks, Anusha. Please let me know if you need any assistance locating the gaps.

[anuani21]

@jjscheel,

Updates from IITM,

Zcmp extension:

cm.mvsa01- Completed with 100% coverage(For RV32 and RV64).
cm.mva01s -Completed with 100% coverage(For RV32 and RV64).
cm.push - Test generated for RV32 and RV64. In coverage, some register coverpoints are not met up in RV64 and RV32.
cm.pop - Test generated for RV32 and RV64. In coverage, some register coverpoints are not met up in RV64 and RV32.
cm.popret -Test generated for RV32 and RV64. In coverage, some register coverpoints are not met up in RV64 and RV32.
cm.popretz - Test generated for RV32 and RV64. In coverage, some register coverpoints are not met up in RV64 and RV32.

Zcmt extension:
cm.jt -Completed and 100% coverage for RV32.

Pending work in Zcmp - I have to fix the register coverpoint issue.(I will fix the issue before next meeting).
Pending work in Zcmt -  Cm.jalt instruction  for RV32 and RV64,cm.jt instruction for RV64.

[anuani21]

@jjscheel,

Zcmt extension- Generating test cases for cm.jalt instruction in RV32 and RV64.

Pending work in Zcmp - I have to fix the register coverpoint issue.

[anuani21]

@jjscheel,

No progress made since last call.

[anuani21]

@jjscheel,

Updates from IITM,

Zcmt extension:
cm.jt -Completed with 100%coverage for RV32 and RV64.
cm.jalt - Completed with 100%coverage for RV32 and RV64

Pending work in Zcmp - I have to fix the register coverpoint issue.I will fix this issue before next meeting.

[anuani21]

@jjscheel,

Updates from IITM,
In Zcmp extension:
cm.push- Completed with 100%coverage for RV32.
cm.pop - Completed with 100%coverage for RV32.
cm.popret -Need to fix the register coverpoints.
cmpopretz- Need to fix the register coverpoints.

[anuani21]

@jjscheel,

No progress made since last Call. Was busy on Debug ACT for Native Triggers.

[anuani21]

@jjscheel,

Updates from IITM,

• There are five sub-extensions in Zce

1. Zcb -it is already merged.

2. Zcf -Raised a PR.

3. Zcd - Raised a PR.
   - Riscv-ctg : Add support for Zcf and Zcd extension riscv-software-src/riscv-ctg#122
   - Riscv-isac: Add support for Zcf and Zcd extension riscv-software-src/riscv-isac#100
   - Riscv-arch-test: Add support for Zcf and Zcd extension riscv-non-isa/riscv-arch-test#497

4. Zcmp - popret and popretz instructions are pending.
   5.. Zcmt- completed. Need to raise a Pr along with zcmp extension

• We will complete Zcmp and raise a PR for Zcmp and Zcmt extension together before the next meeting.

[jjscheel]

Great. THANKS!!!

[anuani21]

@jjscheel,

Updates from IITM,

1. Zcf&Zcd extension:
   Re-submiited the PR in riscv-ctg and riscv-isac into riscv-arch-test Add support for Zcf and Zcd extension riscv-non-isa/riscv-arch-test#497

2. Zcmp and Zcmt extension: We will raise a PR within this week.

[JAYANTH-IITM]

Update :
I am currently working on ACT for Zcmp and Zcmt .

While running the test I am encounter this assembler error which is saying "Zcm* is not compatible with C extension" .
I have raised the same issue in arch-test repo (riscv-non-isa/riscv-arch-test#543) in which allen suggested to include c in ISA ( RV32ICZicsr_Zca_Zcmp ) , but even after that the error was not resolved .

I asked tariq sir also about this error , to which sir suggested it might be toolchain bug.

@pz9115 sir can you please help me here . I have attched ss of the error
Image

[pz9115]

Update : I am currently working on ACT for Zcmp and Zcmt .

While running the test I am encounter this assembler error which is saying "Zcm* is not compatible with C extension" . I have raised the same issue in arch-test repo (riscv-non-isa/riscv-arch-test#543) in which allen suggested to include c in ISA ( RV32ICZicsr_Zca_Zcmp ) , but even after that the error was not resolved .

I asked tariq sir also about this error , to which sir suggested it might be toolchain bug.

@pz9115 sir can you please help me here . I have attched ss of the error Image

@JAYANTH-IITM I think this is cause by the toolchain version issue, we'd better update both gcc and binutils to the latest upstream line.
There is no release version of riscv-gnu-toolchain yet, which means we need to build it manually, here is the steps:

First, use git clone get the riscv-gnu-toolchain

git clone https://github.com/riscv-collab/riscv-gnu-toolchain.git

Then we need to prepare the environment, On Ubuntu, executing the following command should suffice:

$ sudo apt-get install autoconf automake autotools-dev curl python3 python3-pip libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev ninja-build git cmake libglib2.0-dev libslirp-dev

The next step, go into subdir gcc and binutils, update the code to the upstream version:

cd gcc
git fetch origin
git checkout origin/trunk
cd ../binutils
git fetch origin
git checkout origin/trunk

After this, we need to set the toolchain installation directory(in --prefix=, like /opt/riscv) and build it(the time cost based on your CPU performance, usually it takes about half an hour）

./configure --prefix=/opt/riscv --with-arch=rv32ic_zicsr_zca_zcmp --with-abi=ilp32
make -j$(nproc)

If you meet any problems in toolchain, please feel free to ask me at anytime.

[IC41558-IITM]

Thank you sir . will update the toolchain and redo the tests .