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Priv 1.12 ACT - Miscellaneous Missing Tests and Coverage additions #26
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I don’t think that’s the right SOW? |
@jrtc27, that's the one I intended (and that I was given), but it is indeed new and it could be that our title doesn't make sense. Look for updates after our next meeting where will indeed be discussing. THANKS! |
@UmerShahidengr, can you review this item in the context of @jrtc27's question. I'm pretty sure I've linked the SOW you sent me. Perhaps my title is too ambiguous. |
Actually, at reviewing things more, I think this is a duplicate of #13. I'm going to close it for now. |
I don't think this is a duplicate at all. This increases coverage for a
bunch of different cases; #13 is only about CSRRW/RC/RS[I] ops for all the
various CSRs.
On the other hand, a prerequisite is that Sail can configure CSR accesses
from YAML
…On Fri, Mar 17, 2023 at 10:14 AM Jeff Scheel ***@***.***> wrote:
Closed #26 <#26> as not
planned.
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Ok, let's re-open and continue looking at this next meeting. |
The SOW has the following requirements:
None of those are part of the privileged spec. |
The SOW is correct, and is different from the #13; the title of this shouldn't be "legacy corner case" IMHO, but rather |
Yes, exactly. The SOW is correct, the title is wrong.
…On Fri, Mar 17, 2023 at 4:00 PM Jessica Clarke ***@***.***> wrote:
The SOW has the following requirements:
Generate tests for M-extension
Divide/Remainder tests (issue#300)
Specifically tests of the most negative integer divided by -1.
This should include all forms of *signed* DIV and REM only
Add better test generator coverage conditions and regenerate non-FP op
tests (issue #306)
rs1 == rd != rs2; rd != x0
rs1 == rd != rs2; rd == x0
rs1 == x0 != rd
rd == x0 != rs1
Generate tests that use unsupported, legal encodings for Fence and Fencei
ops (issue#119)
Specifically that any reserved bits defined to be ignored do not cause
traps.
Generate tests for c.flw and c.fsw for RV64 (issue#289) currently missing
entirely
Delete #ifdef rvtest_mtrap_routine, and matching #endif lines from all
tests (issue #292)
Remove TEST_RRI_OP macro from test_macros.h
None of those are part of the privileged spec.
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Thanks, @allenjbaum and @jrtc27 |
@UmerShahidengr, another item needing an update:
Thanks! |
Our trainees (which are recruited last month) will be working on this project. Each trainee will work on one issue as part of the training. I will assign one trainee from the current batch to be the collaborator, then this SoW can be assigned to him. This SoW has not been started yet but it will be completed in 2023Q2. |
Thanks, I will set projected date to end of 2Q and mark it for discussion in next meeting. |
Update May 7th, 2023 ⇾ Not much update on this task yet. |
Ok. Thanks. Setting next update to next meeting and dropping from this Agenda. |
Update May 23rd, 2023 => Not much update on this task yet. |
Update ⇾ June 12th, 2023: |
Thanks, @UmerShahidengr. I've removed from agenda. |
Update:
|
After transferring Issue#289 to Prassanna, and resolving Issue#306, this SoW will be completed. |
@jjscheel Yes, as part of Zcc we are covering up Zcf and Zcd (Compressed instruction of floating single and double) |
So, @UmerShahidengr, if I read all the issues correctly, only the first has a PR and while it's been submitted, it has yet to be accepted. If correct, we need 2 things to occur before we can close this out:
|
@jjscheel Issue 300 and Issue 306 both have PRs in place, there is just some mandatory checklist which needs to be completed. I will get those all sorted out by next week hopefully. And yes your two points are correct. |
Thanks, @alitariq4589! I've updated the summary in the first comment. |
Update ⇾ Aug 15th, 2023 |
Issue#300 has been resolved. Its PR has been merged. @jjscheel FYI |
Update ⇾ September 12th, 2023 |
@UmerShahidengr, this sounds like positive status. Does this mean all work has been submitted as PRs and all PRs are accepted? |
All work has been submitted. The most recent PR hasn't been meeged yet. |
Update Sept 26th, 2023: |
Update ⇾ October 10th, 2023: |
All PRs merged means we just have to sign-off on SOW. @allenjbaum, can you please confirm that all is complete from your perspective as Task contact and ACT contact? |
I tried to approve the merge, and got 318 conflicts. There were two separate versions of these tests.
|
There's a merge conflict on PR#368; it looks like something needed to be
rebased before pushing iit.
…On Tue, Oct 10, 2023 at 5:21 AM Jeff Scheel ***@***.***> wrote:
All PRs merged means we just have to sign-off on SOW. @allenjbaum
<https://github.com/allenjbaum>, can you please confirm that all is
complete from your perspective as Task contact and ACT contact?
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@allenjbaum The issue#306 of arch-test needed some changes in the source code of riscv-ctg. So, the initially created PR#368 (which was created by me) did not generate all cases and I forgot to close the PR#368. In PR#385, MuhammadHammad001 changed the source code of RISC-V CTG and generated all required assembly tests resolving the issue#306. So I will close the PR#368 now. |
I'm quite confused as to which PRs were merged as part of this These test cases are fixed in div.s : The SOW says that the TEST_RRI_OP macro should be removed from test.h; it hasn't been So, this doesn't look complete at all. Am I missing something here? or is there some reason those were removed from the SOW? |
@allenjbaum You got that right regarding rem and div that the test condition is not there. But I added the condition in I will generate the tests and will create another PR for rem/div for the case As far as issue#292 and TEST_RPI_OP labels are concerned, issue#292 was closed on Mar 27, 2023 (as completed) so the label should have been removed from the PR because I did not add it explicitly and the latest commit in the branch from which I created PR was of May 8, 2023 which implies that the label should not have been there. But I will see to it that it is removed when I create PR for rem and div |
Let me explain this whole scenerio, there were two issues to be solved as part of this SoW:
Issue#292 was already closed when we started working on it, so nobody worked on it from our side. |
RRI: That appears to be a mistyping; it is TEST_RI_OP that should be
removed ! IT is a duplicate of RRI_OP and misnamed on top of it.
regarding #ifdef rvtest_mtrap_routine: Let's make this a separate work
item, as it affects all tests (if we want to do it).
Removing them means that the trap signature area is always instantiating,
which increases signature size by some tiny amount.
The reason for it was to simplify writing tests, and there are several new
macros that are defined (RVTEST_TSIG_BEGIN and RVTEST_DATA_END
specifically)
that define mtrap_sigptr - conditionally (as it is done in the tests) or
unconditionally.
But, if tests aren't using those macros (yet), it doesn't matter, and I
think there are conflicting definitions in those macros that need to get
sorted out.
So, tests for all of DIVREM and DIVW/REMW need the maxneg/-1 cases, the 4
cross conditions, (and maybe divide by zero (value and X0) cases if they're
not there, though I suspect they are)
…On Thu, Oct 12, 2023 at 1:28 AM Umer Shahid ***@***.***> wrote:
Let me explain this whole scenerio, there were two issues to be solved as
part of this SoW:
1. Issue#300
<riscv-non-isa/riscv-arch-test#300>:
- It required some updates in CTG which were merged here
<riscv-software-src/riscv-ctg#65>.
- The generated tests were merged here
<riscv-non-isa/riscv-arch-test#365>. The PR#365
<riscv-non-isa/riscv-arch-test#365> only had
divw and remw tests on the updated conditions for the proof of concept, div
and rem tests were not changed as coverpoint of dividing by -1 was hit for
division and reminder operations by divw and remw.
1. Issue#306
<riscv-non-isa/riscv-arch-test#306>:
- This issue also required modifications in CTG, changes were merged
here <riscv-software-src/riscv-ctg#79>.
- The generated tests based on the updated conditions were merged here
<riscv-non-isa/riscv-arch-test#385>.
Issue#292 <riscv-non-isa/riscv-arch-test#292>was
already closed when we started working on it, so nobody worked on it from
our side.
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Update ⇾ October 24th, 2023 |
I have added the PR in riscv-arch-test for solving issue#300 (most negative number divided by -1). This PR contains tests for both RV32IM as well as RV64IM for rem* and div*. The relevant riscv-ctg PR is also mentioned in the checklist. |
Update ⇾ November 28th, 2023 |
@allenjbaum, please review and confirm that we can consider this done. Thanks! |
If it's been merged, it can be considered done. |
Update ⇾ December 12th, 2023 |
Closed. Thanks to all who completed this work! |
Technical Group
Architecture Test SIG
ratification-pkg
Priv 1.11, Priv 1.12
Technical Liaison
Allen Baum
Task Category
Arch Tests
65
Task Sub Category
Ratification Target
2021
Statement of Work (SOW)
SOW: link
SOW Signoffs:
Waiver
Pull Request Details
The text was updated successfully, but these errors were encountered: