From f0be9a42c064926438c3f376342fd109d1240c19 Mon Sep 17 00:00:00 2001 From: Manuel Eggimann Date: Thu, 17 Mar 2022 14:29:49 +0100 Subject: [PATCH] Add optional parameter to tc_clk_gating to flag functional gates (#22) * Add optional parameter to tc_clk_gating to flag functional gates * Update changelog --- CHANGELOG.md | 3 +++ src/rtl/tc_clk.sv | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 04d2a7c..73fb061 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,6 +5,9 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html). ## Unreleased +### Changed +- Added optional `IS_FUNCTIONAL` flag to `tc_clk_gating` cell to optionally mark them as *not required for functionality*. + ## 0.2.4 - 2021-02-04 - Add `deprecated/pulp_clk_cells_xilinx.sv` to `Bender.yml` diff --git a/src/rtl/tc_clk.sv b/src/rtl/tc_clk.sv index bf0c1a8..e6aa1fd 100644 --- a/src/rtl/tc_clk.sv +++ b/src/rtl/tc_clk.sv @@ -28,7 +28,14 @@ module tc_clk_buffer ( endmodule // Description: Behavioral model of an integrated clock-gating cell (ICG) -module tc_clk_gating ( +module tc_clk_gating #( + /// This paramaeter is a hint for tool/technology specific mappings of this + /// tech_cell. It indicates wether this particular clk gate instance is + /// required for functional correctness or just instantiated for power + /// savings. If IS_FUNCTIONAL == 0, technology specific mappings might + /// replace this cell with a feedthrough connection without any gating. + parameter bit IS_FUNCTIONAL = 1'b1 +)( input logic clk_i, input logic en_i, input logic test_en_i,