From 8ed192c7be993bc8daba5467284a76539e5cfac6 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Mon, 4 Oct 2021 17:46:06 +0200 Subject: [PATCH] Fix bender, add xilinx pads (#16) * Add override targets to Bender.yml * Patch Bender file for fpga target. Looks like `not(synthesys)` automatically overrides the `fpga` target. To have the xilinx-specific cells linked by Bender to Vivado, we need to modify `synthesis` into `asic`. Fixed typo in sram cells. * Fix bender fpga files, add pad_functional_xilinx * remove unneeded files Co-authored-by: Manuel Eggimann Co-authored-by: Luca Valente --- Bender.yml | 34 +++++----- src/deprecated/cluster_clk_cells_xilinx.sv | 75 --------------------- src/deprecated/pulp_clk_cells_xilinx.sv | 78 ---------------------- src/fpga/pad_functional_xilinx.sv | 48 +++++++++++++ src/fpga/tc_sram_xilinx.sv | 2 +- src/rtl/tc_sram.sv | 2 +- 6 files changed, 68 insertions(+), 171 deletions(-) delete mode 100644 src/deprecated/cluster_clk_cells_xilinx.sv delete mode 100644 src/deprecated/pulp_clk_cells_xilinx.sv create mode 100644 src/fpga/pad_functional_xilinx.sv diff --git a/Bender.yml b/Bender.yml index 4efe945..7077953 100644 --- a/Bender.yml +++ b/Bender.yml @@ -6,28 +6,23 @@ dependencies: common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } sources: - # These simply wrap tc_* cells and are fine to use in any case - - src/deprecated/cluster_clk_cells.sv - - src/deprecated/pulp_clk_cells.sv - - - target: all(rtl, not(synthesis)) + - target: all(any(all(not(asic), not(fpga)), tech_cells_generic_include_tc_sram), not(tech_cells_generic_exclude_tc_sram)) files: - # level 0 + # Level 0 - src/rtl/tc_sram.sv - - target: all(all(fpga, xilinx), not(synthesis)) - files: - - src/deprecated/cluster_clk_cells_xilinx.sv - - src/deprecated/pulp_clk_cells_xilinx.sv - - src/fpga/tc_clk_xilinx.sv - - src/fpga/tc_sram_xilinx.sv - - - target: all(not(all(fpga, xilinx)), not(synthesis)) + - target: all(any(all(not(asic), not(fpga)), tech_cells_generic_include_tc_clk), not(tech_cells_generic_exclude_tc_clk)) files: # Level 0 - src/rtl/tc_clk.sv - - target: not(synthesis) + - target: all(any(fpga, tech_cells_generic_include_xilinx_xpm), not(tech_cells_generic_exclude_xilinx_xpm)) + files: + - src/fpga/pad_functional_xilinx.sv + - src/fpga/tc_clk_xilinx.sv + - src/fpga/tc_sram_xilinx.sv + + - target: all(any(not(synthesis), tech_cells_generic_include_deprecated), not(tech_cells_generic_exclude_deprecated)) files: - src/deprecated/cluster_pwr_cells.sv - src/deprecated/generic_memory.sv @@ -35,9 +30,16 @@ sources: - src/deprecated/pad_functional.sv - src/deprecated/pulp_buffer.sv - src/deprecated/pulp_pwr_cells.sv + + - target: all(any(not(synthesis), tech_cells_generic_include_pwr_cells), not(tech_cells_generic_exclude_pwr_cells)) + files: - src/tc_pwr.sv - - target: test + - target: all(any(test, tech_cells_generic_include_tb_cells), not(tech_cells_generic_exclude_tb_cells)) files: - test/tb_tc_sram.sv - src/deprecated/pulp_clock_gating_async.sv + + # These simply wrap tc_* cells and are fine to use in any case + - src/deprecated/cluster_clk_cells.sv + - src/deprecated/pulp_clk_cells.sv diff --git a/src/deprecated/cluster_clk_cells_xilinx.sv b/src/deprecated/cluster_clk_cells_xilinx.sv deleted file mode 100644 index 0aa7cb5..0000000 --- a/src/deprecated/cluster_clk_cells_xilinx.sv +++ /dev/null @@ -1,75 +0,0 @@ -// Copyright 2019 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_clock_and2 ( - input logic clk0_i, - input logic clk1_i, - output logic clk_o -); - - assign clk_o = clk0_i & clk1_i; - -endmodule - -module cluster_clock_buffer ( - input logic clk_i, - output logic clk_o -); - - assign clk_o = clk_i; - -endmodule - -// Disable clock gating on FPGA as it behaves differently than expected -module cluster_clock_gating ( - input logic clk_i, - input logic en_i, - input logic test_en_i, - output logic clk_o -); - - assign clk_o = clk_i; - -endmodule - -module cluster_clock_inverter ( - input logic clk_i, - output logic clk_o -); - - assign clk_o = ~clk_i; - -endmodule - -module pulp_clock_mux2 ( - input logic clk0_i, - input logic clk1_i, - input logic clk_sel_i, - output logic clk_o -); - - BUFGMUX i_BUFGMUX ( - .S ( clk_sel_i ), - .I0 ( clk0_i ), - .I1 ( clk1_i ), - .O ( clk_o ) - ); - -endmodule - -module cluster_clock_xor2 ( - input logic clk0_i, - input logic clk1_i, - output logic clk_o -); - - assign clk_o = clk0_i ^ clk1_i; - -endmodule diff --git a/src/deprecated/pulp_clk_cells_xilinx.sv b/src/deprecated/pulp_clk_cells_xilinx.sv deleted file mode 100644 index 7c82c49..0000000 --- a/src/deprecated/pulp_clk_cells_xilinx.sv +++ /dev/null @@ -1,78 +0,0 @@ -// Copyright 2019 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -// Cells to be used for Xilinx FPGA mappings - -module pulp_clock_and2 ( - input logic clk0_i, - input logic clk1_i, - output logic clk_o -); - - assign clk_o = clk0_i & clk1_i; - -endmodule - -module pulp_clock_buffer ( - input logic clk_i, - output logic clk_o -); - - assign clk_o = clk_i; - -endmodule - -// Disable clock gating on FPGA as it behaves differently than expected -module pulp_clock_gating ( - input logic clk_i, - input logic en_i, - input logic test_en_i, - output logic clk_o -); - - assign clk_o = clk_i; - -endmodule - -module pulp_clock_inverter ( - input logic clk_i, - output logic clk_o -); - - assign clk_o = ~clk_i; - -endmodule - -module pulp_clock_mux2 ( - input logic clk0_i, - input logic clk1_i, - input logic clk_sel_i, - output logic clk_o -); - - BUFGMUX i_BUFGMUX ( - .S ( clk_sel_i ), - .I0 ( clk0_i ), - .I1 ( clk1_i ), - .O ( clk_o ) - ); - -endmodule - -module pulp_clock_xor2 ( - input logic clk0_i, - input logic clk1_i, - output logic clk_o -); - - assign clk_o = clk0_i ^ clk1_i; - -endmodule - diff --git a/src/fpga/pad_functional_xilinx.sv b/src/fpga/pad_functional_xilinx.sv new file mode 100644 index 0000000..665c113 --- /dev/null +++ b/src/fpga/pad_functional_xilinx.sv @@ -0,0 +1,48 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + + +module pad_functional_pd +( + input logic OEN, + input logic I, + output logic O, + input logic PEN, + inout logic PAD +); + + (* PULLDOWN = "YES" *) + IOBUF iobuf_i ( + .T ( OEN ), + .I ( I ), + .O ( O ), + .IO( PAD ) + ); + +endmodule + +module pad_functional_pu +( + input logic OEN, + input logic I, + output logic O, + input logic PEN, + inout logic PAD +); + + (* PULLUP = "YES" *) + IOBUF iobuf_i ( + .T ( OEN ), + .I ( I ), + .O ( O ), + .IO( PAD ) + ); + +endmodule diff --git a/src/fpga/tc_sram_xilinx.sv b/src/fpga/tc_sram_xilinx.sv index c706802..7c50e64 100644 --- a/src/fpga/tc_sram_xilinx.sv +++ b/src/fpga/tc_sram_xilinx.sv @@ -168,7 +168,7 @@ module tc_sram #( // Validate parameters. // pragma translate_off `ifndef VERILATOR -`ifndef TARGET_SYNTHESYS +`ifndef TARGET_SYNTHESIS initial begin: p_assertions assert (SimInit == "zeros") else $fatal(1, "The Xilinx `tc_sram` has fixed SimInit: zeros"); assert ($bits(addr_i) == NumPorts * AddrWidth) else $fatal(1, "AddrWidth problem on `addr_i`"); diff --git a/src/rtl/tc_sram.sv b/src/rtl/tc_sram.sv index 53530e0..98298d6 100644 --- a/src/rtl/tc_sram.sv +++ b/src/rtl/tc_sram.sv @@ -167,7 +167,7 @@ module tc_sram #( // Validate parameters. // pragma translate_off `ifndef VERILATOR -`ifndef TARGET_SYNTHESYS +`ifndef TARGET_SYNTHESIS initial begin: p_assertions assert ($bits(addr_i) == NumPorts * AddrWidth) else $fatal(1, "AddrWidth problem on `addr_i`"); assert ($bits(wdata_i) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `wdata_i`");