diff --git a/Bender.yml b/Bender.yml index 2721800..6287a98 100644 --- a/Bender.yml +++ b/Bender.yml @@ -5,39 +5,21 @@ package: sources: - target: all(fpga, xilinx) files: - - src/cluster_clock_gating_xilinx.sv - - src/pulp_clock_gating_xilinx.sv - - src/pulp_clock_mux2_xilinx.sv + - src/deprecated/cluster_clk_cells_xilinx.sv + - src/fpga/tc_clk_xilinx.sv - target: not(all(fpga, xilinx)) files: - - src/cluster_clock_gating.sv - - src/pulp_clock_gating.sv - - src/pulp_clock_mux2.sv + - src/deprecated/cluster_clk_cells.sv + - src/deprecated/pulp_clk_cells.sv + - src/rtl/tc_clk.sv - target: not(synthesis) files: - - src/cluster_clock_and2.sv - - src/cluster_clock_buffer.sv - - src/cluster_clock_inverter.sv - - src/cluster_clock_mux2.sv - - src/cluster_clock_xor2.sv - - src/cluster_level_shifter_in.sv - - src/cluster_level_shifter_in_clamp.sv - - src/cluster_level_shifter_inout.sv - - src/cluster_level_shifter_out.sv - - src/cluster_level_shifter_out_clamp.sv - - src/generic_memory.sv - - src/generic_rom.sv - - src/pad_functional.sv - - src/pulp_buffer.sv - - src/pulp_clock_and2.sv - - src/pulp_clock_buffer.sv - - src/pulp_clock_gating_async.sv - - src/pulp_clock_inverter.sv - - src/pulp_clock_xor2.sv - - src/pulp_level_shifter_in.sv - - src/pulp_level_shifter_in_clamp.sv - - src/pulp_level_shifter_out.sv - - src/pulp_level_shifter_out_clamp.sv - - src/pulp_power_gating.sv + - src/deprecated/cluster_pwr_cells.sv + - src/deprecated/generic_memory.sv + - src/deprecated/generic_rom.sv + - src/deprecated/pad_functional.sv + - src/deprecated/pulp_buffer.sv + - src/deprecated/pulp_pwr_cells.sv + - src/tc_pwr.sv diff --git a/CHANGELOG.md b/CHANGELOG.md index 483a7b3..d726be8 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,15 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## Unreleased +## 0.1.6 - 2019-11-18 +### Added +- Add Readme +- Add Contribution Guide + +### Changed +- Move modules of similar topic to a single file. This makes it easier to add new modules. +- Move separation between `cluster` and `pulp` to `deprecated` folder. There should be a single solution to a tech-cell. + ## 0.1.1 - 2018-09-12 ### Changed - Polish release @@ -14,4 +23,4 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## 0.1.0 - 2018-09-12 ### Added -- Initial commit. \ No newline at end of file +- Initial commit. diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 0000000..a2ded4e --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,3 @@ +# Contributing + +See [our style and contribution guidelines](https://github.com/pulp-platform/style-guidelines). \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 0000000..f96e6a7 --- /dev/null +++ b/README.md @@ -0,0 +1,54 @@ +# Generic Technology Cells (API to Cell Library) + +Maintainer: Florian Zaruba + +This repository contains technology related cells like SRAMs, clock-gating cells, power management cells. The description here are: + +- **Behavioral**: Meant for RTL simulation only. +- **FPGA**: Meant for FPGA implementation. Currently we only support Xilinx FPGAs. But we are happy to accept patches for Altera or other devices. + +It is the purpose of your technology specific file to include the cells with correct drive strength. We do not make the assumption in the front-end anymore. + +> As this layer needs to be re-implemented for every new technology keep it thin! + +## Cell Contents + +If you want to get started in your own technology (either an unsupported FPGA or an ASIC technology) please provide implementations for the cells in this repository. + +### Clock Cells + +Clock cells usually are care-fully designed cells which do not exhibit any glitches. Therefore they need to be manually instantiated in ASIC designs. All clock cells can be found in `tc_clk.sv`. + +| Name | Description | Status | Xilinx | +|-------------------|------------------------------|--------|--------------------| +| `tc_clk_and2` | Clock and gate | active | :white_check_mark: | +| `tc_clk_buffer` | Clock buffer | active | :white_check_mark: | +| `tc_clk_gating` | Integrated clock gating cell | active | :white_check_mark: | +| `tc_clk_inverter` | Clock inverter | active | :white_check_mark: | +| `tc_clk_mux2` | Clock Mux with two inputs | active | :white_check_mark: | +| `tc_clk_xor2` | Clock Xor | active | :white_check_mark: | +| `tc_clk_delay` | Programmable clock-delay | active | | + +### Memory + +| Name | Description | Status | Xilinx | +|-----------|----------------------------------------------------------|--------|--------------------| +| `sp_sram` | Single-ported SRAM with bit-error injection capabilities | active | :white_check_mark: | +| `dp_sram` | Dual-ported SRAM with bit-error injection capabilities | active | :white_check_mark: | +| `mp_sram` | Multi-ported SRAM with bit-error injection capabilities | active | | + +### Power Cells + +Power cells are mostly used for advanced power gating features and not used in any of our open-source IPs. However, feel-free to re-use them. All clock cells can be found in `tc_pwr.sv`. + +| Name | Description | Status | +|-------------------------------------|--------------------------------------|--------| +| `tc_pwr_level_shifter_in` | Level Shifter | active | +| `tc_pwr_level_shifter_in_clamp_lo` | Level Shifter w/ clamp to `1'b0` | active | +| `tc_pwr_level_shifter_in_clamp_hi` | Level Shifter w/ clamp to `1'b1` | active | +| `tc_pwr_level_shifter_out` | Level Shifter | active | +| `tc_pwr_level_shifter_out_clamp_lo` | Level Shifter w/ clamp to `1'b0` | active | +| `tc_pwr_level_shifter_out_clamp_hi` | Level Shifter w/ clamp to `1'b1` | active | +| `tc_pwr_power_gating` | Power Gate with ctrl and status pins | active | +| `tc_pwr_isolation_lo` | Isolation Cell w/ isolate to `1'b0` | active | +| `tc_pwr_isolation_hi` | Isolation Cell w/ isolate to `1'b1` | active | diff --git a/src/cluster_clock_and2.sv b/src/cluster_clock_and2.sv deleted file mode 100644 index 2505a5f..0000000 --- a/src/cluster_clock_and2.sv +++ /dev/null @@ -1,20 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_clock_and2 -( - input logic clk0_i, - input logic clk1_i, - output logic clk_o -); - - assign clk_o = clk0_i & clk1_i; - -endmodule diff --git a/src/cluster_clock_buffer.sv b/src/cluster_clock_buffer.sv deleted file mode 100644 index 57f603e..0000000 --- a/src/cluster_clock_buffer.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_clock_buffer - ( - input logic clk_i, - output logic clk_o - ); - - assign clk_o = clk_i; - -endmodule diff --git a/src/cluster_clock_gating.sv b/src/cluster_clock_gating.sv deleted file mode 100644 index 3c48d22..0000000 --- a/src/cluster_clock_gating.sv +++ /dev/null @@ -1,29 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_clock_gating - ( - input logic clk_i, - input logic en_i, - input logic test_en_i, - output logic clk_o - ); - - logic clk_en; - - always_latch - begin - if (clk_i == 1'b0) - clk_en <= en_i | test_en_i; - end - - assign clk_o = clk_i & clk_en; - -endmodule diff --git a/src/cluster_clock_gating_xilinx.sv b/src/cluster_clock_gating_xilinx.sv deleted file mode 100644 index 7ec477f..0000000 --- a/src/cluster_clock_gating_xilinx.sv +++ /dev/null @@ -1,21 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_clock_gating - ( - input logic clk_i, - input logic en_i, - input logic test_en_i, - output logic clk_o - ); - - assign clk_o = clk_i; - -endmodule diff --git a/src/cluster_clock_inverter.sv b/src/cluster_clock_inverter.sv deleted file mode 100644 index ffde563..0000000 --- a/src/cluster_clock_inverter.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_clock_inverter - ( - input logic clk_i, - output logic clk_o - ); - - assign clk_o = ~clk_i; - -endmodule diff --git a/src/cluster_clock_mux2.sv b/src/cluster_clock_mux2.sv deleted file mode 100644 index e817e6a..0000000 --- a/src/cluster_clock_mux2.sv +++ /dev/null @@ -1,27 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_clock_mux2 - ( - input logic clk0_i, - input logic clk1_i, - input logic clk_sel_i, - output logic clk_o - ); - - always_comb - begin - if (clk_sel_i == 1'b0) - clk_o = clk0_i; - else - clk_o = clk1_i; - end - -endmodule diff --git a/src/cluster_clock_xor2.sv b/src/cluster_clock_xor2.sv deleted file mode 100644 index 9071f3f..0000000 --- a/src/cluster_clock_xor2.sv +++ /dev/null @@ -1,20 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_clock_xor2 - ( - input logic clk0_i, - input logic clk1_i, - output logic clk_o - ); - - assign clk_o = clk0_i ^ clk1_i; - -endmodule diff --git a/src/cluster_level_shifter_in.sv b/src/cluster_level_shifter_in.sv deleted file mode 100644 index 35cd1ff..0000000 --- a/src/cluster_level_shifter_in.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_level_shifter_in -( - input logic in_i, - output logic out_o -); - -assign out_o = in_i; - -endmodule diff --git a/src/cluster_level_shifter_in_clamp.sv b/src/cluster_level_shifter_in_clamp.sv deleted file mode 100644 index 7ed45f0..0000000 --- a/src/cluster_level_shifter_in_clamp.sv +++ /dev/null @@ -1,20 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_level_shifter_in_clamp -( - input logic in_i, - output logic out_o, - input logic clamp_i -); - -assign out_o = clamp_i ? 1'b0 : in_i; - -endmodule diff --git a/src/cluster_level_shifter_inout.sv b/src/cluster_level_shifter_inout.sv deleted file mode 100644 index a4ad782..0000000 --- a/src/cluster_level_shifter_inout.sv +++ /dev/null @@ -1,8 +0,0 @@ -module cluster_level_shifter_inout ( - input logic data_i, - output logic data_o -); - - assign data_o = data_i; - -endmodule \ No newline at end of file diff --git a/src/cluster_level_shifter_out.sv b/src/cluster_level_shifter_out.sv deleted file mode 100644 index 3f9969b..0000000 --- a/src/cluster_level_shifter_out.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_level_shifter_out - ( - input logic in_i, - output logic out_o - ); - - assign out_o = in_i; - -endmodule diff --git a/src/cluster_level_shifter_out_clamp.sv b/src/cluster_level_shifter_out_clamp.sv deleted file mode 100644 index c6a6d91..0000000 --- a/src/cluster_level_shifter_out_clamp.sv +++ /dev/null @@ -1,20 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module cluster_level_shifter_out_clamp -( - input logic in_i, - output logic out_o, - input logic clamp_i -); - - assign out_o = clamp_i ? 1'b0 : in_i; - -endmodule diff --git a/src/deprecated/cluster_clk_cells.sv b/src/deprecated/cluster_clk_cells.sv new file mode 100644 index 0000000..ab0d821 --- /dev/null +++ b/src/deprecated/cluster_clk_cells.sv @@ -0,0 +1,76 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module cluster_clock_and2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i & clk1_i; + +endmodule + +module cluster_clock_buffer ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +// Description: Behavioral model of an integrated clock-gating cell (ICG) +module cluster_clock_gating ( + input logic clk_i, + input logic en_i, + input logic test_en_i, + output logic clk_o +); + + logic clk_en; + + always_latch begin + if (clk_i == 1'b0) clk_en <= en_i | test_en_i; + end + + assign clk_o = clk_i & clk_en; + +endmodule + +module cluster_clock_inverter ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = ~clk_i; + +endmodule + +module cluster_clock_mux2 ( + input logic clk0_i, + input logic clk1_i, + input logic clk_sel_i, + output logic clk_o +); + + assign clk_o = (clk_sel_i) ? clk1_i : clk0_i; + +endmodule + +module cluster_clock_xor2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i ^ clk1_i; + +endmodule diff --git a/src/deprecated/cluster_clk_cells_xilinx.sv b/src/deprecated/cluster_clk_cells_xilinx.sv new file mode 100644 index 0000000..0aa7cb5 --- /dev/null +++ b/src/deprecated/cluster_clk_cells_xilinx.sv @@ -0,0 +1,75 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module cluster_clock_and2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i & clk1_i; + +endmodule + +module cluster_clock_buffer ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +// Disable clock gating on FPGA as it behaves differently than expected +module cluster_clock_gating ( + input logic clk_i, + input logic en_i, + input logic test_en_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +module cluster_clock_inverter ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = ~clk_i; + +endmodule + +module pulp_clock_mux2 ( + input logic clk0_i, + input logic clk1_i, + input logic clk_sel_i, + output logic clk_o +); + + BUFGMUX i_BUFGMUX ( + .S ( clk_sel_i ), + .I0 ( clk0_i ), + .I1 ( clk1_i ), + .O ( clk_o ) + ); + +endmodule + +module cluster_clock_xor2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i ^ clk1_i; + +endmodule diff --git a/src/deprecated/cluster_pwr_cells.sv b/src/deprecated/cluster_pwr_cells.sv new file mode 100644 index 0000000..b085faa --- /dev/null +++ b/src/deprecated/cluster_pwr_cells.sv @@ -0,0 +1,59 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Description: This file contains power-related cells +// Mainly shifters at the moment. + +module cluster_level_shifter_in ( + input logic in_i, + output logic out_o +); + + assign out_o = in_i; + +endmodule + +module cluster_level_shifter_in_clamp ( + input logic in_i, + output logic out_o, + input logic clamp_i +); + + assign out_o = clamp_i ? 1'b0 : in_i; + +endmodule + +module cluster_level_shifter_inout ( + input logic data_i, + output logic data_o +); + + assign data_o = data_i; + +endmodule + +module cluster_level_shifter_out ( + input logic in_i, + output logic out_o +); + + assign out_o = in_i; + +endmodule + +module cluster_level_shifter_out_clamp ( + input logic in_i, + output logic out_o, + input logic clamp_i +); + + assign out_o = clamp_i ? 1'b0 : in_i; + +endmodule diff --git a/src/generic_memory.sv b/src/deprecated/generic_memory.sv similarity index 100% rename from src/generic_memory.sv rename to src/deprecated/generic_memory.sv diff --git a/src/generic_rom.sv b/src/deprecated/generic_rom.sv similarity index 100% rename from src/generic_rom.sv rename to src/deprecated/generic_rom.sv diff --git a/src/pad_functional.sv b/src/deprecated/pad_functional.sv similarity index 80% rename from src/pad_functional.sv rename to src/deprecated/pad_functional.sv index d81598a..720b332 100644 --- a/src/pad_functional.sv +++ b/src/deprecated/pad_functional.sv @@ -9,13 +9,12 @@ // specific language governing permissions and limitations under the License. -module pad_functional_pd -( - input logic OEN, - input logic I, - output logic O, - input logic PEN, - inout wire PAD +module pad_functional_pd ( + input logic OEN, + input logic I, + output logic O, + input logic PEN, + inout wire PAD ); /* @@ -46,13 +45,12 @@ module pad_functional_pd endmodule -module pad_functional_pu -( - input logic OEN, - input logic I, - output logic O, - input logic PEN, - inout wire PAD +module pad_functional_pu ( + input logic OEN, + input logic I, + output logic O, + input logic PEN, + inout wire PAD ); /* diff --git a/src/pulp_buffer.sv b/src/deprecated/pulp_buffer.sv similarity index 100% rename from src/pulp_buffer.sv rename to src/deprecated/pulp_buffer.sv diff --git a/src/deprecated/pulp_clk_cells.sv b/src/deprecated/pulp_clk_cells.sv new file mode 100644 index 0000000..1451d2f --- /dev/null +++ b/src/deprecated/pulp_clk_cells.sv @@ -0,0 +1,89 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module pulp_clock_and2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i & clk1_i; + +endmodule + +module pulp_clock_buffer ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +// Description: Behavioral model of an integrated clock-gating cell (ICG) +module pulp_clock_gating ( + input logic clk_i, + input logic en_i, + input logic test_en_i, + output logic clk_o +); + + logic clk_en; + + always_latch begin + if (clk_i == 1'b0) clk_en <= en_i | test_en_i; + end + + assign clk_o = clk_i & clk_en; + +endmodule + +module pulp_clock_inverter ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = ~clk_i; + +endmodule + +module pulp_clock_mux2 ( + input logic clk0_i, + input logic clk1_i, + input logic clk_sel_i, + output logic clk_o +); + + assign clk_o = (clk_sel_i) ? clk1_i : clk0_i; + +endmodule + +module pulp_clock_xor2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i ^ clk1_i; + +endmodule + +`ifndef SYNTHESIS +module pulp_clock_delay( + input logic in_i, + output logic out_o +); + + assign #(300ps) out_o = in_i; + +endmodule +`endif + + diff --git a/src/deprecated/pulp_clk_cells_xilinx.sv b/src/deprecated/pulp_clk_cells_xilinx.sv new file mode 100644 index 0000000..7c82c49 --- /dev/null +++ b/src/deprecated/pulp_clk_cells_xilinx.sv @@ -0,0 +1,78 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Cells to be used for Xilinx FPGA mappings + +module pulp_clock_and2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i & clk1_i; + +endmodule + +module pulp_clock_buffer ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +// Disable clock gating on FPGA as it behaves differently than expected +module pulp_clock_gating ( + input logic clk_i, + input logic en_i, + input logic test_en_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +module pulp_clock_inverter ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = ~clk_i; + +endmodule + +module pulp_clock_mux2 ( + input logic clk0_i, + input logic clk1_i, + input logic clk_sel_i, + output logic clk_o +); + + BUFGMUX i_BUFGMUX ( + .S ( clk_sel_i ), + .I0 ( clk0_i ), + .I1 ( clk1_i ), + .O ( clk_o ) + ); + +endmodule + +module pulp_clock_xor2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i ^ clk1_i; + +endmodule + diff --git a/src/deprecated/pulp_clock_gating_async.sv b/src/deprecated/pulp_clock_gating_async.sv new file mode 100644 index 0000000..5c95b55 --- /dev/null +++ b/src/deprecated/pulp_clock_gating_async.sv @@ -0,0 +1,44 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// TODO(zarubaf): This is not really a tech cell - move it to common cells + +module pulp_clock_gating_async #( + parameter int unsigned STAGES = 2 +) ( + input logic clk_i, + input logic rstn_i, + input logic en_async_i, + output logic en_ack_o, + input logic test_en_i, + output logic clk_o +); + + logic [STAGES-1:0] r_reg; + + assign en_ack_o = r_reg[STAGES-1]; + + // synchronize enable signal + always_ff @ (posedge clk_i or negedge rstn_i) begin + if (!rstn_i) begin + r_reg <= '0; + end else begin + r_reg <= {r_reg[STAGES-2:0], en_async_i}; + end + end + + pulp_clock_gating i_clk_gate ( + .clk_i, + .en_i ( r_reg[STAGES-1] ), + .test_en_i, + .clk_o + ); + +endmodule \ No newline at end of file diff --git a/src/deprecated/pulp_pwr_cells.sv b/src/deprecated/pulp_pwr_cells.sv new file mode 100644 index 0000000..58c3ee2 --- /dev/null +++ b/src/deprecated/pulp_pwr_cells.sv @@ -0,0 +1,88 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Description: This file contains power-related cells +// Mainly shifters at the moment. + +module pulp_level_shifter_in ( + input logic in_i, + output logic out_o +); + + assign out_o = in_i; + +endmodule + +module pulp_level_shifter_in_clamp ( + input logic in_i, + output logic out_o, + input logic clamp_i +); + + assign out_o = clamp_i ? 1'b0 : in_i; + +endmodule + +module pulp_level_shifter_inout ( + input logic data_i, + output logic data_o +); + + assign data_o = data_i; + +endmodule + +module pulp_level_shifter_out ( + input logic in_i, + output logic out_o +); + + assign out_o = in_i; + +endmodule + +module pulp_level_shifter_out_clamp ( + input logic in_i, + output logic out_o, + input logic clamp_i +); + + assign out_o = clamp_i ? 1'b0 : in_i; + +endmodule + +module pulp_power_gating ( + input logic sleep_i, + output logic sleepout_o +); + + assign sleepout_o = sleep_i; + +endmodule + +module pulp_isolation_0 ( + input logic data_i, + input logic ena_i, + output logic data_o +); + + assign data_o = ena_i ? data_i : 1'b0; + +endmodule + +module pulp_isolation_1 ( + input logic data_i, + input logic ena_i, + output logic data_o +); + + assign data_o = ena_i ? data_i : 1'b1; + +endmodule diff --git a/src/fpga/tc_clk_xilinx.sv b/src/fpga/tc_clk_xilinx.sv new file mode 100644 index 0000000..d8e5e96 --- /dev/null +++ b/src/fpga/tc_clk_xilinx.sv @@ -0,0 +1,78 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Cells to be used for Xilinx FPGA mappings + +module tc_clk_and2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i & clk1_i; + +endmodule + +module tc_clk_buffer ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +// Disable clock gating on FPGA as it behaves differently than expected +module tc_clk_gating ( + input logic clk_i, + input logic en_i, + input logic test_en_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +module tc_clk_inverter ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = ~clk_i; + +endmodule + +module tc_clk_mux2 ( + input logic clk0_i, + input logic clk1_i, + input logic clk_sel_i, + output logic clk_o +); + + BUFGMUX i_BUFGMUX ( + .S ( clk_sel_i ), + .I0 ( clk0_i ), + .I1 ( clk1_i ), + .O ( clk_o ) + ); + +endmodule + +module tc_clk_xor2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i ^ clk1_i; + +endmodule + diff --git a/src/pulp_clock_and2.sv b/src/pulp_clock_and2.sv deleted file mode 100644 index 77caee0..0000000 --- a/src/pulp_clock_and2.sv +++ /dev/null @@ -1,20 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_clock_and2 -( - input logic clk0_i, - input logic clk1_i, - output logic clk_o -); - - assign clk_o = clk0_i & clk1_i; - -endmodule diff --git a/src/pulp_clock_buffer.sv b/src/pulp_clock_buffer.sv deleted file mode 100644 index e6fd775..0000000 --- a/src/pulp_clock_buffer.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_clock_buffer - ( - input logic clk_i, - output logic clk_o - ); - - assign clk_o = clk_i; - -endmodule diff --git a/src/pulp_clock_delay.sv b/src/pulp_clock_delay.sv deleted file mode 100644 index 583dc09..0000000 --- a/src/pulp_clock_delay.sv +++ /dev/null @@ -1,11 +0,0 @@ -`timescale 1ns/1ps -module pulp_clock_delay -( - input logic in_i, - output logic out_o -); - - -assign #(0.300) out_o = in_i; - -endmodule // pulp_clock_delay diff --git a/src/pulp_clock_gating.sv b/src/pulp_clock_gating.sv deleted file mode 100644 index 372a2fb..0000000 --- a/src/pulp_clock_gating.sv +++ /dev/null @@ -1,29 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_clock_gating -( - input logic clk_i, - input logic en_i, - input logic test_en_i, - output logic clk_o -); - - logic clk_en; - - always_latch - begin - if (clk_i == 1'b0) - clk_en <= en_i | test_en_i; - end - - assign clk_o = clk_i & clk_en; - -endmodule diff --git a/src/pulp_clock_gating_async.sv b/src/pulp_clock_gating_async.sv deleted file mode 100644 index 6845347..0000000 --- a/src/pulp_clock_gating_async.sv +++ /dev/null @@ -1,38 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_clock_gating_async -( - input logic clk_i, - input logic rstn_i, - input logic en_async_i, - output logic en_ack_o, - input logic test_en_i, - output logic clk_o -); - - pulp_sync #( .STAGES(2) ) i_pulp_sync - ( - .clk_i ( clk_i ), - .rstn_i ( rstn_i ), - .serial_i ( en_async_i ), - .serial_o ( en_ack_o ) - ); - - - pulp_clock_gating i_clk_gate - ( - .clk_i ( clk_i ), - .en_i ( en_ack_o ), - .test_en_i( test_en_i ), - .clk_o ( clk_o ) - ); - -endmodule diff --git a/src/pulp_clock_gating_xilinx.sv b/src/pulp_clock_gating_xilinx.sv deleted file mode 100644 index 1e2db2d..0000000 --- a/src/pulp_clock_gating_xilinx.sv +++ /dev/null @@ -1,21 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_clock_gating - ( - input logic clk_i, - input logic en_i, - input logic test_en_i, - output logic clk_o - ); - - assign clk_o = clk_i; - -endmodule diff --git a/src/pulp_clock_inverter.sv b/src/pulp_clock_inverter.sv deleted file mode 100644 index 7522828..0000000 --- a/src/pulp_clock_inverter.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_clock_inverter - ( - input logic clk_i, - output logic clk_o - ); - - assign clk_o = ~clk_i; - -endmodule diff --git a/src/pulp_clock_mux2.sv b/src/pulp_clock_mux2.sv deleted file mode 100644 index a6ef73e..0000000 --- a/src/pulp_clock_mux2.sv +++ /dev/null @@ -1,27 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_clock_mux2 - ( - input logic clk0_i, - input logic clk1_i, - input logic clk_sel_i, - output logic clk_o - ); - - always_comb - begin - if (clk_sel_i == 1'b0) - clk_o = clk0_i; - else - clk_o = clk1_i; - end - -endmodule diff --git a/src/pulp_clock_mux2_xilinx.sv b/src/pulp_clock_mux2_xilinx.sv deleted file mode 100644 index 19f064a..0000000 --- a/src/pulp_clock_mux2_xilinx.sv +++ /dev/null @@ -1,26 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_clock_mux2 - ( - input logic clk0_i, - input logic clk1_i, - input logic clk_sel_i, - output logic clk_o - ); - - BUFGMUX bufgmux_i ( - .S(clk_sel_i), - .I0(clk0_i), - .I1(clk1_i), - .O(clk_o) - ); - -endmodule diff --git a/src/pulp_clock_xor2.sv b/src/pulp_clock_xor2.sv deleted file mode 100644 index ec6813c..0000000 --- a/src/pulp_clock_xor2.sv +++ /dev/null @@ -1,20 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_clock_xor2 - ( - input logic clk0_i, - input logic clk1_i, - output logic clk_o - ); - - assign clk_o = clk0_i ^ clk1_i; - -endmodule diff --git a/src/pulp_isolation_0.sv b/src/pulp_isolation_0.sv deleted file mode 100644 index 2a6efdc..0000000 --- a/src/pulp_isolation_0.sv +++ /dev/null @@ -1,10 +0,0 @@ -module pulp_isolation_0 -( - input logic data_i, - input logic ena_i, - output logic data_o -); - - assign data_o = ena_i ? data_i : 1'b0; - -endmodule \ No newline at end of file diff --git a/src/pulp_level_shifter_in.sv b/src/pulp_level_shifter_in.sv deleted file mode 100644 index 3b652ba..0000000 --- a/src/pulp_level_shifter_in.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_level_shifter_in -( - input logic in_i, - output logic out_o -); - - assign out_o = in_i; - -endmodule diff --git a/src/pulp_level_shifter_in_clamp.sv b/src/pulp_level_shifter_in_clamp.sv deleted file mode 100644 index d159899..0000000 --- a/src/pulp_level_shifter_in_clamp.sv +++ /dev/null @@ -1,20 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_level_shifter_in_clamp -( - input logic in_i, - output logic out_o, - input logic clamp_i -); - -assign out_o = clamp_i ? 1'b0 : in_i; - -endmodule diff --git a/src/pulp_level_shifter_inout.sv b/src/pulp_level_shifter_inout.sv deleted file mode 100644 index f8b336e..0000000 --- a/src/pulp_level_shifter_inout.sv +++ /dev/null @@ -1,8 +0,0 @@ -module pulp_level_shifter_inout ( - input logic data_i, - output logic data_o -); - - assign data_o = data_i; - -endmodule \ No newline at end of file diff --git a/src/pulp_level_shifter_out.sv b/src/pulp_level_shifter_out.sv deleted file mode 100644 index 34341eb..0000000 --- a/src/pulp_level_shifter_out.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_level_shifter_out -( - input logic in_i, - output logic out_o -); - -assign out_o = in_i; - -endmodule diff --git a/src/pulp_level_shifter_out_clamp.sv b/src/pulp_level_shifter_out_clamp.sv deleted file mode 100644 index 84514b1..0000000 --- a/src/pulp_level_shifter_out_clamp.sv +++ /dev/null @@ -1,21 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_level_shifter_clamp_out -( - input logic in_i, - output logic out_o, - input logic clamp_i -); - - - assign out_o = clamp_i ? 1'b0 : in_i; - -endmodule diff --git a/src/pulp_power_gating.sv b/src/pulp_power_gating.sv deleted file mode 100644 index fe0f791..0000000 --- a/src/pulp_power_gating.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module pulp_power_gating - ( - input logic sleep_i, - output logic sleepout_o - ); - - assign sleepout_o = sleep_i; - -endmodule diff --git a/src/pulp_sync.sv b/src/pulp_sync.sv deleted file mode 100644 index ef3c7a6..0000000 --- a/src/pulp_sync.sv +++ /dev/null @@ -1,36 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -// Antonio Pullini - -module pulp_sync -#( - parameter STAGES = 2 -) -( - input logic clk_i, - input logic rstn_i, - input logic serial_i, - output logic serial_o -); - - logic [STAGES-1:0] r_bf_synch; - - always_ff @(posedge clk_i, negedge rstn_i) - begin - if(!rstn_i) - r_bf_synch <= '0; - else - r_bf_synch <= {r_bf_synch[STAGES-2:0], serial_i}; - end - - assign serial_o = r_bf_synch[STAGES-1]; - -endmodule diff --git a/src/rtl/tc_clk.sv b/src/rtl/tc_clk.sv new file mode 100644 index 0000000..fdbbd36 --- /dev/null +++ b/src/rtl/tc_clk.sv @@ -0,0 +1,91 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module tc_clk_and2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i & clk1_i; + +endmodule + +module tc_clk_buffer ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +// Description: Behavioral model of an integrated clock-gating cell (ICG) +module tc_clk_gating ( + input logic clk_i, + input logic en_i, + input logic test_en_i, + output logic clk_o +); + + logic clk_en; + + always_latch begin + if (clk_i == 1'b0) clk_en <= en_i | test_en_i; + end + + assign clk_o = clk_i & clk_en; + +endmodule + +module tc_clk_inverter ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = ~clk_i; + +endmodule + +module tc_clk_mux2 ( + input logic clk0_i, + input logic clk1_i, + input logic clk_sel_i, + output logic clk_o +); + + assign clk_o = (clk_sel_i) ? clk1_i : clk0_i; + +endmodule + +module tc_clk_xor2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i ^ clk1_i; + +endmodule + +`ifndef SYNTHESIS +module tc_clk_delay #( + parameter int unsigned Delay = 300ps +) ( + input logic in_i, + output logic out_o +); + + assign #(Delay) out_o = in_i; + +endmodule +`endif + + diff --git a/src/tc_pwr.sv b/src/tc_pwr.sv new file mode 100644 index 0000000..460c994 --- /dev/null +++ b/src/tc_pwr.sv @@ -0,0 +1,100 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Description: This file contains power-related cells +// Mainly shifters at the moment. + + +module tc_pwr_level_shifter_in ( + input logic in_i, + output logic out_o +); + + assign out_o = in_i; + +endmodule + +module tc_pwr_level_shifter_in_clamp_lo ( + input logic in_i, + output logic out_o, + input logic clamp_i +); + + assign out_o = clamp_i ? 1'b0 : in_i; + +endmodule + +module tc_pwr_level_shifter_in_clamp_hi ( + input logic in_i, + output logic out_o, + input logic clamp_i +); + + assign out_o = clamp_i ? 1'b1 : in_i; + +endmodule + +module tc_pwr_level_shifter_out ( + input logic in_i, + output logic out_o +); + + assign out_o = in_i; + +endmodule + +module tc_pwr_level_shifter_out_clamp_lo ( + input logic in_i, + output logic out_o, + input logic clamp_i +); + + assign out_o = clamp_i ? 1'b0 : in_i; + +endmodule + +module tc_pwr_level_shifter_out_clamp_hi ( + input logic in_i, + output logic out_o, + input logic clamp_i +); + + assign out_o = clamp_i ? 1'b1 : in_i; + +endmodule + +module tc_pwr_power_gating ( + input logic sleep_i, + output logic sleepout_o +); + + assign sleepout_o = sleep_i; + +endmodule + +module tc_pwr_isolation_lo ( + input logic data_i, + input logic ena_i, + output logic data_o +); + + assign data_o = ena_i ? data_i : 1'b0; + +endmodule + +module tc_pwr_isolation_hi ( + input logic data_i, + input logic ena_i, + output logic data_o +); + + assign data_o = ena_i ? data_i : 1'b1; + +endmodule diff --git a/src_files.yml b/src_files.yml index eee8411..ea73fb8 100644 --- a/src_files.yml +++ b/src_files.yml @@ -3,38 +3,21 @@ tech_cells_rtl: skip_synthesis, ] files: [ - src/cluster_clock_gating.sv, - src/pulp_clock_gating.sv, - src/pulp_clock_mux2.sv, - src/pulp_clock_buffer.sv, - src/pulp_clock_inverter.sv, - src/pulp_clock_xor2.sv, - src/pulp_clock_delay.sv, - src/pulp_buffer.sv, - src/pulp_level_shifter_in.sv, - src/pulp_level_shifter_in_clamp.sv, - src/pulp_level_shifter_out.sv, - src/pulp_level_shifter_out_clamp.sv, - src/pulp_clock_and2.sv, - src/cluster_clock_buffer.sv, - src/cluster_clock_inverter.sv, - src/cluster_clock_mux2.sv, - src/cluster_clock_xor2.sv, - src/cluster_level_shifter_in.sv, - src/cluster_level_shifter_in_clamp.sv, - src/cluster_level_shifter_out.sv, - src/cluster_level_shifter_out_clamp.sv, - src/cluster_clock_and2.sv, - src/pulp_power_gating.sv, - src/generic_rom.sv, - src/generic_memory.sv, - src/pad_functional.sv, + src/deprecated/cluster_clk_cells.sv, + src/deprecated/cluster_pwr_cells.sv, + src/deprecated/generic_memory.sv, + src/deprecated/generic_rom.sv, + src/deprecated/pad_functional.sv, + src/deprecated/pulp_buffer.sv, + src/deprecated/pulp_clk_cells.sv, + src/deprecated/pulp_pwr_cells.sv, + src/rtl/tc_clk.sv, + src/tc_pwr.sv, ] tech_cells_rtl_synth: files: [ - src/pulp_sync.sv, - src/pulp_clock_gating_async.sv, + src/deprecated/pulp_clock_gating_async.sv, ] tech_cells_fpga: @@ -42,27 +25,11 @@ tech_cells_fpga: xilinx, ] files: [ - src/cluster_clock_gating_xilinx.sv, - src/pulp_clock_gating_xilinx.sv, - src/pulp_clock_mux2_xilinx.sv, - src/pulp_clock_buffer.sv, - src/pulp_clock_inverter.sv, - src/pulp_clock_xor2.sv, - src/pulp_clock_delay.sv, - src/pulp_buffer.sv, - src/pulp_level_shifter_in.sv, - src/pulp_level_shifter_in_clamp.sv, - src/pulp_level_shifter_out.sv, - src/pulp_level_shifter_out_clamp.sv, - src/pulp_clock_and2.sv, - src/cluster_clock_buffer.sv, - src/cluster_clock_inverter.sv, - src/cluster_clock_mux2.sv, - src/cluster_clock_xor2.sv, - src/cluster_level_shifter_in.sv, - src/cluster_level_shifter_in_clamp.sv, - src/cluster_level_shifter_out.sv, - src/cluster_level_shifter_out_clamp.sv, - src/cluster_clock_and2.sv, - src/pulp_power_gating.sv, + src/deprecated/cluster_clk_cells_xilinx.sv, + src/deprecated/cluster_pwr_cells.sv, + src/deprecated/pulp_clk_cells_xilinx.sv, + src/deprecated/pulp_pwr_cells.sv, + src/deprecated/pulp_buffer.sv, + src/fpga/tc_clk_xilinx.sv, + src/tc_pwr.sv, ]