diff --git a/.github/verible.waiver b/.github/verible.waiver index 6c8339f3..7da6b29d 100644 --- a/.github/verible.waiver +++ b/.github/verible.waiver @@ -4,10 +4,3 @@ # Authors: # - Thomas Benz - -# Fix this ... -waive --rule=line-length --location="src/frontend/desc64/idma_desc64.sv" - -# Declare zero-based big-endian unpacked dimensions sized as [N] -> legacy PULP code :S -waive --rule=unpacked-dimensions-range-ordering --location="src/systems/pulpopen/dmac_wrap.sv" -waive --rule=line-length --location="src/systems/pulpopen/dmac_wrap.sv" diff --git a/Bender.yml b/Bender.yml index 991b30d3..342c867b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -7,8 +7,8 @@ package: authors: - "Thomas Benz " # current maintainer - "Michael Rogenmoser " - - "Tobias Senti " - - "Axel Vanoni " + - "Tobias Senti " + - "Axel Vanoni " dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } @@ -67,18 +67,15 @@ sources: - src/frontend/desc64/idma_desc64_reg_wrapper.sv # Level 2 - src/frontend/desc64/idma_desc64_top.sv - - src/frontend/desc64/idma_desc64_cva6_wrap.sv # Synthesis wrappers - target: synth files: # Level 0 - src/frontend/desc64/idma_desc64_synth_pkg.sv - - src/frontend/desc64/idma_desc64_cva6_synth_pkg.sv - src/synth/idma_nd_backend_synth.sv # Level 1 - src/frontend/desc64/idma_desc64_synth.sv - - src/frontend/desc64/idma_desc64_cva6_synth.sv # Testbenches - target: test diff --git a/src/frontend/desc64/idma_desc64_cva6_synth.sv b/src/frontend/desc64/idma_desc64_cva6_synth.sv deleted file mode 100644 index 397011f2..00000000 --- a/src/frontend/desc64/idma_desc64_cva6_synth.sv +++ /dev/null @@ -1,67 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Authors: -// - Axel Vanoni - -/// Synthesis wrapper for the descriptor-based frontend -module idma_desc64_cva6_synth #( - parameter int AxiAddrWidth = idma_desc64_cva6_synth_pkg::AxiAddrWidth, - parameter int AxiDataWidth = idma_desc64_cva6_synth_pkg::AxiDataWidth, - parameter int AxiUserWidth = idma_desc64_cva6_synth_pkg::AxiUserWidth, - parameter int AxiIdWidth = idma_desc64_cva6_synth_pkg::AxiIdWidth, - parameter int AxiSlvIdWidth = idma_desc64_cva6_synth_pkg::AxiSlvIdWidth, - parameter int NSpeculation = idma_desc64_cva6_synth_pkg::NSpeculation, - parameter int PendingFifoDepth = idma_desc64_cva6_synth_pkg::PendingFifoDepth, - parameter int InputFifoDepth = idma_desc64_cva6_synth_pkg::InputFifoDepth, - parameter type mst_aw_chan_t = idma_desc64_cva6_synth_pkg::mst_aw_chan_t, - parameter type mst_w_chan_t = idma_desc64_cva6_synth_pkg::mst_w_chan_t, - parameter type mst_b_chan_t = idma_desc64_cva6_synth_pkg::mst_b_chan_t, - parameter type mst_ar_chan_t = idma_desc64_cva6_synth_pkg::mst_ar_chan_t, - parameter type mst_r_chan_t = idma_desc64_cva6_synth_pkg::mst_r_chan_t, - parameter type axi_mst_req_t = idma_desc64_cva6_synth_pkg::axi_mst_req_t, - parameter type axi_mst_rsp_t = idma_desc64_cva6_synth_pkg::axi_mst_rsp_t, - parameter type axi_slv_req_t = idma_desc64_cva6_synth_pkg::axi_slv_req_t, - parameter type axi_slv_rsp_t = idma_desc64_cva6_synth_pkg::axi_slv_rsp_t -)( - input logic clk_i, - input logic rst_ni, - input logic testmode_i, - output logic irq_o, - output axi_mst_req_t axi_master_req_o, - input axi_mst_rsp_t axi_master_rsp_i, - input axi_slv_req_t axi_slave_req_i, - output axi_slv_rsp_t axi_slave_rsp_o -); - -idma_desc64_cva6_wrap #( - .AxiAddrWidth (AxiAddrWidth ), - .AxiDataWidth (AxiDataWidth ), - .AxiUserWidth (AxiUserWidth ), - .AxiIdWidth (AxiIdWidth ), - .AxiSlvIdWidth (AxiSlvIdWidth), - .NSpeculation (NSpeculation), - .PendingFifoDepth(PendingFifoDepth), - .InputFifoDepth(InputFifoDepth), - .mst_aw_chan_t (mst_aw_chan_t), - .mst_w_chan_t (mst_w_chan_t ), - .mst_b_chan_t (mst_b_chan_t ), - .mst_ar_chan_t (mst_ar_chan_t), - .mst_r_chan_t (mst_r_chan_t ), - .axi_mst_req_t (axi_mst_req_t), - .axi_mst_rsp_t (axi_mst_rsp_t), - .axi_slv_req_t (axi_slv_req_t), - .axi_slv_rsp_t (axi_slv_rsp_t) -) i_idma_desc64_cva6_wrap ( - .clk_i, - .rst_ni, - .testmode_i, - .irq_o, - .axi_master_req_o, - .axi_master_rsp_i, - .axi_slave_req_i, - .axi_slave_rsp_o -); - -endmodule diff --git a/src/frontend/desc64/idma_desc64_cva6_synth_pkg.sv b/src/frontend/desc64/idma_desc64_cva6_synth_pkg.sv deleted file mode 100644 index e889c0c9..00000000 --- a/src/frontend/desc64/idma_desc64_cva6_synth_pkg.sv +++ /dev/null @@ -1,30 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Authors: -// - Axel Vanoni - -`include "axi/typedef.svh" - -/// Synthesis package for the descriptor-based frontend -package idma_desc64_cva6_synth_pkg; - `AXI_TYPEDEF_ALL(axi, logic [63:0], logic [2:0], logic [63:0], logic [7:0], logic) - parameter int AxiAddrWidth = 64; - parameter int AxiDataWidth = 64; - parameter int AxiUserWidth = 1; - parameter int AxiIdWidth = 3; - parameter int AxiSlvIdWidth = 3; - parameter int NSpeculation = 4; - parameter int PendingFifoDepth = 4; - parameter int InputFifoDepth = 1; - parameter type mst_aw_chan_t = axi_aw_chan_t; // AW Channel Type, master port - parameter type mst_w_chan_t = axi_w_chan_t; // W Channel Type, all ports - parameter type mst_b_chan_t = axi_b_chan_t; // B Channel Type, master port - parameter type mst_ar_chan_t = axi_ar_chan_t; // AR Channel Type, master port - parameter type mst_r_chan_t = axi_r_chan_t; // R Channel Type, master port - parameter type axi_mst_req_t = axi_req_t; - parameter type axi_mst_rsp_t = axi_resp_t; - parameter type axi_slv_req_t = axi_req_t; - parameter type axi_slv_rsp_t = axi_resp_t; -endpackage diff --git a/src/frontend/desc64/idma_desc64_cva6_wrap.sv b/src/frontend/desc64/idma_desc64_cva6_wrap.sv deleted file mode 100644 index 7d808a56..00000000 --- a/src/frontend/desc64/idma_desc64_cva6_wrap.sv +++ /dev/null @@ -1,334 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Authors: -// - Axel Vanoni - -`include "axi/assign.svh" -`include "axi/typedef.svh" -`include "idma/guard.svh" -`include "idma/typedef.svh" -`include "idma/tracer.svh" -`include "register_interface/typedef.svh" -`include "common_cells/registers.svh" - -/// Wrapper for the iDMA -module idma_desc64_cva6_wrap #( - parameter int AxiAddrWidth = 64, - parameter int AxiDataWidth = 64, - parameter int AxiUserWidth = -1, - parameter int AxiIdWidth = -1, - parameter int AxiSlvIdWidth = -1, - parameter int NSpeculation = 4, - parameter int PendingFifoDepth = 4, - parameter int InputFifoDepth = 1, - parameter type mst_aw_chan_t = logic, // AW Channel Type, master port - parameter type mst_w_chan_t = logic, // W Channel Type, all ports - parameter type mst_b_chan_t = logic, // B Channel Type, master port - parameter type mst_ar_chan_t = logic, // AR Channel Type, master port - parameter type mst_r_chan_t = logic, // R Channel Type, master port - parameter type axi_mst_req_t = logic, - parameter type axi_mst_rsp_t = logic, - parameter type axi_slv_req_t = logic, - parameter type axi_slv_rsp_t = logic -) ( - input logic clk_i, - input logic rst_ni, - input logic testmode_i, - output logic irq_o, - output axi_mst_req_t axi_master_req_o, - input axi_mst_rsp_t axi_master_rsp_i, - input axi_slv_req_t axi_slave_req_i, - output axi_slv_rsp_t axi_slave_rsp_o -); - import axi_pkg::*; - - typedef logic [AxiAddrWidth-1:0] addr_t; - typedef logic [AxiDataWidth-1:0] data_t; - typedef logic [(AxiDataWidth/8)-1:0] strb_t; - typedef logic [AxiUserWidth-1:0] user_t; - // has one less bit for the mux not to error - typedef logic [AxiIdWidth-2:0] post_mux_id_t; - - localparam int unsigned NumAxInFlight = NSpeculation < 3 ? 3 : NSpeculation; - localparam int unsigned BufferDepth = 3; - - axi_slv_req_t axi_slv_req; - axi_slv_rsp_t axi_slv_rsp; - - `AXI_TYPEDEF_ALL(dma_axi_mst_post_mux, addr_t, post_mux_id_t, data_t, strb_t, user_t) - dma_axi_mst_post_mux_req_t axi_fe_mst_req; - dma_axi_mst_post_mux_resp_t axi_fe_mst_rsp; - dma_axi_mst_post_mux_req_t axi_read_req, axi_write_req, axi_be_mst_req; - dma_axi_mst_post_mux_resp_t axi_read_rsp, axi_write_rsp, axi_be_mst_rsp; - - `REG_BUS_TYPEDEF_ALL(dma_reg, addr_t, data_t, strb_t) - dma_reg_req_t dma_reg_slv_req; - dma_reg_rsp_t dma_reg_slv_rsp; - - // iDMA struct definitions - localparam int unsigned TFLenWidth = 32; - typedef logic [TFLenWidth-1:0] tf_len_t; - - // iDMA request / response types - `IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, post_mux_id_t, addr_t, tf_len_t) - `IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t) - - typedef struct packed { - dma_axi_mst_post_mux_ar_chan_t ar_chan; - } axi_read_meta_channel_t; - - typedef struct packed { - axi_read_meta_channel_t axi; - } read_meta_channel_t; - - typedef struct packed { - dma_axi_mst_post_mux_aw_chan_t aw_chan; - } axi_write_meta_channel_t; - - typedef struct packed { - axi_write_meta_channel_t axi; - } write_meta_channel_t; - - idma_req_t idma_req; - logic idma_req_valid; - logic idma_req_ready; - - idma_rsp_t idma_rsp; - logic idma_rsp_valid; - logic idma_rsp_ready; - idma_pkg::idma_busy_t idma_busy; - - idma_desc64_top #( - .AddrWidth ( AxiAddrWidth ), - .DataWidth ( AxiDataWidth ), - .AxiIdWidth ( AxiIdWidth - 1 ), - .idma_req_t ( idma_req_t ), - .idma_rsp_t ( idma_rsp_t ), - .axi_req_t ( dma_axi_mst_post_mux_req_t ), - .axi_rsp_t ( dma_axi_mst_post_mux_resp_t ), - .axi_ar_chan_t ( dma_axi_mst_post_mux_ar_chan_t ), - .axi_r_chan_t ( dma_axi_mst_post_mux_r_chan_t ), - .reg_req_t ( dma_reg_req_t ), - .reg_rsp_t ( dma_reg_rsp_t ), - .InputFifoDepth ( InputFifoDepth ), - .PendingFifoDepth ( PendingFifoDepth ), - .BackendDepth ( NumAxInFlight + BufferDepth ), - .NSpeculation ( NSpeculation ) - ) i_dma_desc64 ( - .clk_i, - .rst_ni, - .master_req_o ( axi_fe_mst_req ), - .master_rsp_i ( axi_fe_mst_rsp ), - .axi_ar_id_i ( '1 ), - .axi_aw_id_i ( '1 ), - .slave_req_i ( dma_reg_slv_req ), - .slave_rsp_o ( dma_reg_slv_rsp ), - .idma_req_o ( idma_req ), - .idma_req_valid_o ( idma_req_valid ), - .idma_req_ready_i ( idma_req_ready ), - .idma_rsp_i ( idma_rsp ), - .idma_rsp_valid_i ( idma_rsp_valid ), - .idma_rsp_ready_o ( idma_rsp_ready ), - .idma_busy_i ( |idma_busy ), - .irq_o ( irq_o ) - ); - - idma_backend_rw_axi #( - .DataWidth ( AxiDataWidth ), - .AddrWidth ( AxiAddrWidth ), - .AxiIdWidth ( AxiIdWidth-1 ), - .UserWidth ( AxiUserWidth ), - .TFLenWidth ( TFLenWidth ), - .MaskInvalidData ( 1'b1 ), - .BufferDepth ( BufferDepth ), - .RAWCouplingAvail ( 1'b1 ), - .HardwareLegalizer ( 1'b1 ), - .RejectZeroTransfers ( 1'b1 ), - .ErrorCap ( idma_pkg::NO_ERROR_HANDLING ), - .CombinedShifter ( 1'b0 ), - .PrintFifoInfo ( 1'b0 ), - .NumAxInFlight ( NumAxInFlight ), - .MemSysDepth ( 32'd0 ), - .idma_req_t ( idma_req_t ), - .idma_rsp_t ( idma_rsp_t ), - .idma_eh_req_t ( idma_pkg::idma_eh_req_t ), - .idma_busy_t ( idma_pkg::idma_busy_t ), - .axi_req_t ( dma_axi_mst_post_mux_req_t ), - .axi_rsp_t ( dma_axi_mst_post_mux_resp_t ), - .write_meta_channel_t ( write_meta_channel_t ), - .read_meta_channel_t ( read_meta_channel_t ) - ) i_idma_backend ( - .clk_i, - .rst_ni, - .testmode_i, - .idma_req_i ( idma_req ), - .req_valid_i ( idma_req_valid ), - .req_ready_o ( idma_req_ready ), - .idma_rsp_o ( idma_rsp ), - .rsp_valid_o ( idma_rsp_valid ), - .rsp_ready_i ( idma_rsp_ready ), - .idma_eh_req_i ( '0 ), - .eh_req_valid_i ( 1'b1 ), - .eh_req_ready_o ( /*NOT CONNECTED*/ ), - .axi_read_req_o ( axi_read_req ), - .axi_read_rsp_i ( axi_read_rsp ), - .axi_write_req_o ( axi_write_req ), - .axi_write_rsp_i ( axi_write_rsp ), - .busy_o ( idma_busy ) - ); - - // Read Write Join - axi_rw_join #( - .axi_req_t ( dma_axi_mst_post_mux_req_t ), - .axi_resp_t ( dma_axi_mst_post_mux_resp_t ) - ) i_axi_rw_join ( - .clk_i, - .rst_ni, - .slv_read_req_i ( axi_read_req ), - .slv_read_resp_o ( axi_read_rsp ), - .slv_write_req_i ( axi_write_req ), - .slv_write_resp_o ( axi_write_rsp ), - .mst_req_o ( axi_be_mst_req ), - .mst_resp_i ( axi_be_mst_rsp ) - ); - - `IDMA_NONSYNTH_BLOCK( - string trace_file; - initial begin - void'($value$plusargs("trace_file=%s", trace_file)); - end - initial begin : inital_tracer - automatic bit first_iter = 1; - automatic integer tf; - automatic `IDMA_TRACER_MAX_TYPE cnst [string]; - automatic `IDMA_TRACER_MAX_TYPE meta [string]; - automatic `IDMA_TRACER_MAX_TYPE busy [string]; - automatic `IDMA_TRACER_MAX_TYPE axib [string]; - automatic string trace; - #0; - tf = $fopen(trace_file, "w"); - $display("[Tracer] Logging iDMA backend %s to %s", "i_idma_backend", trace_file); - forever begin - @(posedge i_idma_backend.clk_i); - if (i_idma_backend.rst_ni & |i_idma_backend.busy_o) begin - break; - end - end - forever begin - @(posedge i_idma_backend.clk_i); - /* Trace */ - trace = "{"; - /* Constants */ - cnst = '{ - "inst" : "i_idma_backend", - "data_width" : i_idma_backend.DataWidth, - "addr_width" : i_idma_backend.AddrWidth, - "user_width" : i_idma_backend.UserWidth, - "axi_id_width" : i_idma_backend.AxiIdWidth, - "num_ax_in_flight" : i_idma_backend.NumAxInFlight, - "buffer_depth" : i_idma_backend.BufferDepth, - "tf_len_width" : i_idma_backend.TFLenWidth, - "mem_sys_depth" : i_idma_backend.MemSysDepth, - "rw_coupling_avail" : i_idma_backend.RAWCouplingAvail, - "mask_invalid_data" : i_idma_backend.MaskInvalidData, - "hardware_legalizer" : i_idma_backend.HardwareLegalizer, - "reject_zero_transfers" : i_idma_backend.RejectZeroTransfers, - "error_cap" : i_idma_backend.ErrorCap, - "print_fifo_info" : i_idma_backend.PrintFifoInfo - }; - meta = '{ - "time" : $time() - }; - busy = '{ - "buffer" : i_idma_backend.busy_o.buffer_busy, - "r_dp" : i_idma_backend.busy_o.r_dp_busy, - "w_dp" : i_idma_backend.busy_o.w_dp_busy, - "r_leg" : i_idma_backend.busy_o.r_leg_busy, - "w_leg" : i_idma_backend.busy_o.w_leg_busy, - "eh_fsm" : i_idma_backend.busy_o.eh_fsm_busy, - "eh_cnt" : i_idma_backend.busy_o.eh_cnt_busy, - "raw_coupler" : i_idma_backend.busy_o.raw_coupler_busy - }; - axib = '{ - "w_valid" : i_idma_backend.protocol_req_o.w_valid, - "w_ready" : axi_be_mst_rsp.w_ready, - "w_strb" : i_idma_backend.protocol_req_o.w.strb, - "r_valid" : axi_be_mst_rsp.r_valid, - "r_ready" : i_idma_backend.protocol_req_o.r_ready - }; - if ($isunknown(axib["w_ready"]) || $isunknown(axib["r_valid"])) begin - $fatal("UNKNOWN AXI STATE, THIS SHOULD NEVER HAPPEN!"); - end - /* Assembly */ - `IDMA_TRACER_STR_ASSEMBLY(cnst, first_iter); - `IDMA_TRACER_STR_ASSEMBLY(meta, 1); - `IDMA_TRACER_STR_ASSEMBLY(busy, 1); - `IDMA_TRACER_STR_ASSEMBLY(axib, 1); - `IDMA_TRACER_CLEAR_COND(first_iter); - /* Commit */ - $fwrite(tf, $sformatf("%s}\n", trace)); - end - end - ) - - axi_mux #( - .SlvAxiIDWidth(AxiIdWidth - 1), - .slv_aw_chan_t(dma_axi_mst_post_mux_aw_chan_t), - .mst_aw_chan_t(mst_aw_chan_t), - .w_chan_t (mst_w_chan_t), // same channel type for master+slave - .slv_b_chan_t (dma_axi_mst_post_mux_b_chan_t), - .mst_b_chan_t (mst_b_chan_t), - .slv_ar_chan_t(dma_axi_mst_post_mux_ar_chan_t), - .mst_ar_chan_t(mst_ar_chan_t), - .slv_r_chan_t (dma_axi_mst_post_mux_r_chan_t), - .mst_r_chan_t (mst_r_chan_t), - .slv_req_t (dma_axi_mst_post_mux_req_t), - .slv_resp_t (dma_axi_mst_post_mux_resp_t), - .mst_req_t (axi_mst_req_t), - .mst_resp_t (axi_mst_rsp_t), - .NoSlvPorts ('d2), - .MaxWTrans ('d2), - .FallThrough ('0), - .SpillAw ('b0), - .SpillW ('0), - .SpillB ('0), - .SpillAr ('b0), - .SpillR ('0) - ) i_axi_mux ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .test_i (1'b0), - .slv_reqs_i ({axi_fe_mst_req, axi_be_mst_req}), - .slv_resps_o ({axi_fe_mst_rsp, axi_be_mst_rsp}), - .mst_req_o (axi_master_req_o), - .mst_resp_i (axi_master_rsp_i) - ); - - axi_to_reg #( - .ADDR_WIDTH (AxiAddrWidth), - .DATA_WIDTH (AxiDataWidth), - .ID_WIDTH (AxiSlvIdWidth), - .USER_WIDTH (AxiUserWidth), - .AXI_MAX_WRITE_TXNS(32'd1), - .AXI_MAX_READ_TXNS (32'd1), - .DECOUPLE_W (1'b1), - .axi_req_t (axi_slv_req_t), - .axi_rsp_t (axi_slv_rsp_t), - .reg_req_t (dma_reg_req_t), - .reg_rsp_t (dma_reg_rsp_t) - ) i_axi_to_reg ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .testmode_i(testmode_i), - .axi_req_i (axi_slv_req), - .axi_rsp_o (axi_slv_rsp), - .reg_req_o (dma_reg_slv_req), - .reg_rsp_i (dma_reg_slv_rsp) - ); - - assign axi_slv_req = axi_slave_req_i; - assign axi_slave_rsp_o = axi_slv_rsp; - -endmodule diff --git a/src/systems/cva6_reg/dma_core_wrap.sv b/src/systems/cva6_reg/dma_core_wrap.sv deleted file mode 100644 index 320b962d..00000000 --- a/src/systems/cva6_reg/dma_core_wrap.sv +++ /dev/null @@ -1,332 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Authors: -// - Thomas Benz -// - Andreas Kuster -// - Paul Scheffler - -`include "axi/assign.svh" -`include "axi/typedef.svh" -`include "idma/typedef.svh" -`include "register_interface/typedef.svh" - -/// DMA core wrapper for the CVA6 integration -module dma_core_wrap #( - parameter int unsigned AxiAddrWidth = 32'd0, - parameter int unsigned AxiDataWidth = 32'd0, - parameter int unsigned AxiIdWidth = 32'd0, - parameter int unsigned AxiUserWidth = 32'd0, - parameter int unsigned AxiSlvIdWidth = 32'd0, - parameter int unsigned NumAxInFlight = 32'd0, - parameter int unsigned MemSysDepth = 32'd0, - parameter int unsigned JobFifoDepth = 32'd0, - parameter bit RAWCouplingAvail = 32'd0, - parameter bit IsTwoD = 32'd0, - parameter type axi_mst_req_t = logic, - parameter type axi_mst_rsp_t = logic, - parameter type axi_slv_req_t = logic, - parameter type axi_slv_rsp_t = logic -) ( - input logic clk_i, - input logic rst_ni, - input logic testmode_i, - output axi_mst_req_t axi_mst_req_o, - input axi_mst_rsp_t axi_mst_rsp_i, - input axi_slv_req_t axi_slv_req_i, - output axi_slv_rsp_t axi_slv_rsp_o -); - - // local params - localparam int unsigned DmaRegisterWidth = 32'd64; - localparam int unsigned NumDim = 32'd2; - localparam int unsigned TFLenWidth = AxiAddrWidth; - - typedef logic [AxiDataWidth-1:0] data_t; - typedef logic [AxiDataWidth/8-1:0] strb_t; - typedef logic [AxiAddrWidth-1:0] addr_t; - typedef logic [AxiIdWidth-1:0] axi_id_t; - typedef logic [AxiSlvIdWidth-1:0] axi_slv_id_t; - typedef logic [AxiUserWidth-1:0] axi_user_t; - - // iDMA struct definitions - typedef logic [TFLenWidth-1:0] tf_len_t; - - // iDMA request / response types - `IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, axi_slv_id_t, addr_t, tf_len_t) - `IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t) - - `REG_BUS_TYPEDEF_ALL(dma_regs, addr_t, data_t, strb_t) - - idma_req_t burst_req, burst_req_d; - logic be_valid, be_valid_d; - logic be_ready, be_ready_d; - logic be_trans_complete; - idma_pkg::idma_busy_t idma_busy; - - idma_rsp_t idma_rsp; - logic idma_rsp_valid; - logic idma_rsp_ready; - - logic twod_trans_complete; - logic twod_busy; - - dma_regs_req_t dma_regs_req; - dma_regs_rsp_t dma_regs_rsp; - - axi_to_reg #( - .ADDR_WIDTH( AxiAddrWidth ), - .DATA_WIDTH( AxiDataWidth ), - .ID_WIDTH ( AxiSlvIdWidth ), - .USER_WIDTH( AxiUserWidth ), - .axi_req_t ( axi_slv_req_t ), - .axi_rsp_t ( axi_slv_rsp_t ), - .reg_req_t ( dma_regs_req_t ), - .reg_rsp_t ( dma_regs_rsp_t ) - ) i_axi_translate ( - .clk_i, - .rst_ni, - .testmode_i ( 1'b0 ), - .axi_req_i ( axi_slv_req_i ), - .axi_rsp_o ( axi_slv_rsp_o ), - .reg_req_o ( dma_regs_req ), - .reg_rsp_i ( dma_regs_rsp ) - ); - - - if (!IsTwoD) begin : gen_one_d - /* - * DMA Frontend - */ - idma_reg64_frontend #( - .dma_regs_req_t ( dma_regs_req_t ), - .dma_regs_rsp_t ( dma_regs_rsp_t ), - .burst_req_t ( idma_req_t ) - ) i_dma_frontend ( - .clk_i, - .rst_ni, - // AXI slave: control port - .dma_ctrl_req_i ( dma_regs_req ), - .dma_ctrl_rsp_o ( dma_regs_rsp ), - // Backend control - .burst_req_o ( burst_req_d ), - .valid_o ( be_valid_d ), - .ready_i ( be_ready_d ), - .backend_idle_i ( ~|idma_busy ), - .trans_complete_i ( be_trans_complete ) - ); - - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( AxiDataWidth ), - .DEPTH ( JobFifoDepth ), - .T ( idma_req_t ) - ) i_stream_fifo_jobs_oned ( - .clk_i, - .rst_ni, - .testmode_i, - .flush_i ( 1'b0 ), - .usage_o ( /* NOT CONNECTED */ ), - .data_i ( burst_req_d ), - .valid_i ( be_valid_d ), - .ready_o ( be_ready_d ), - .data_o ( burst_req ), - .valid_o ( be_valid ), - .ready_i ( be_ready ) - ); - - - assign be_trans_complete = idma_rsp_valid; - assign idma_rsp_ready = 1'b1; - - end else begin : gen_two_d - - `IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, tf_len_t, tf_len_t) - - idma_nd_req_t idma_nd_req, idma_nd_req_d; - logic idma_nd_req_valid, idma_nd_req_valid_d; - logic idma_nd_req_ready, idma_nd_req_ready_d; - - // 2D frontend - idma_reg64_2d_frontend #( - .dma_regs_req_t ( dma_regs_req_t ), - .dma_regs_rsp_t ( dma_regs_rsp_t ), - .burst_req_t ( idma_req_t ), - .idma_nd_req_t ( idma_nd_req_t ) - - ) i_dma_2d_frontend ( - .clk_i, - .rst_ni, - // AXI slave: control port - .dma_ctrl_req_i ( dma_regs_req ), - .dma_ctrl_rsp_o ( dma_regs_rsp ), - // Backend control - .idma_nd_req_o ( idma_nd_req_d ), - .valid_o ( idma_nd_req_valid_d ), - .ready_i ( idma_nd_req_ready_d ), - .backend_idle_i ( ~|idma_busy & !twod_busy ), - .trans_complete_i ( twod_trans_complete ) - ); - - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( AxiDataWidth ), - .DEPTH ( JobFifoDepth ), - .T ( idma_nd_req_t ) - ) i_stream_fifo_jobs_twod ( - .clk_i, - .rst_ni, - .testmode_i, - .flush_i ( 1'b0 ), - .usage_o ( /* NOT CONNECTED */ ), - .data_i ( idma_nd_req_d ), - .valid_i ( idma_nd_req_valid_d ), - .ready_o ( idma_nd_req_ready_d ), - .data_o ( idma_nd_req ), - .valid_o ( idma_nd_req_valid ), - .ready_i ( idma_nd_req_ready ) - ); - - // Midend - idma_nd_midend #( - .NumDim ( NumDim ), - .addr_t ( addr_t ), - .idma_req_t ( idma_req_t ), - .idma_rsp_t ( idma_rsp_t ), - .idma_nd_req_t ( idma_nd_req_t ), - .RepWidths ( {AxiAddrWidth, AxiAddrWidth} ) - ) i_idma_nd_midend ( - .clk_i, - .rst_ni, - .nd_req_i ( idma_nd_req ), - .nd_req_valid_i ( idma_nd_req_valid ), - .nd_req_ready_o ( idma_nd_req_ready ), - .nd_rsp_o ( /* NOT CONECTED */ ), - .nd_rsp_valid_o ( twod_trans_complete ), - .nd_rsp_ready_i ( 1'b1 ), - .burst_req_o ( burst_req ), - .burst_req_valid_o( be_valid ), - .burst_req_ready_i( be_ready ), - .burst_rsp_i ( idma_rsp ), - .burst_rsp_valid_i( idma_rsp_valid ), - .burst_rsp_ready_o( idma_rsp_ready ), - .busy_o ( twod_busy ) - ); - end - - `AXI_TYPEDEF_AW_CHAN_T(axi_mst_aw_chan_t, addr_t, axi_id_t, axi_user_t) - `AXI_TYPEDEF_AR_CHAN_T(axi_mst_ar_chan_t, addr_t, axi_id_t, axi_user_t) - - idma_backend #( - .DataWidth ( AxiDataWidth ), - .AddrWidth ( AxiAddrWidth ), - .UserWidth ( AxiUserWidth ), - .AxiIdWidth ( AxiIdWidth ), - .NumAxInFlight ( NumAxInFlight ), - .BufferDepth ( 3 ), - .TFLenWidth ( TFLenWidth ), - .RAWCouplingAvail ( RAWCouplingAvail ), - .MaskInvalidData ( 1'b0 ), - .HardwareLegalizer ( 1'b1 ), - .RejectZeroTransfers ( 1'b1 ), - .MemSysDepth ( MemSysDepth ), - .ErrorCap ( idma_pkg::NO_ERROR_HANDLING ), - .idma_req_t ( idma_req_t ), - .idma_rsp_t ( idma_rsp_t ), - .idma_eh_req_t ( idma_pkg::idma_eh_req_t ), - .idma_busy_t ( idma_pkg::idma_busy_t ), - .protocol_req_t ( axi_mst_req_t ), - .protocol_rsp_t ( axi_mst_rsp_t ), - .aw_chan_t ( axi_mst_aw_chan_t ), - .ar_chan_t ( axi_mst_ar_chan_t ) - ) i_idma_backend ( - .clk_i, - .rst_ni, - .testmode_i, - - .idma_req_i ( burst_req ), - .req_valid_i ( be_valid ), - .req_ready_o ( be_ready ), - - .idma_rsp_o ( idma_rsp ), - .rsp_valid_o ( idma_rsp_valid ), - .rsp_ready_i ( idma_rsp_ready ), - - .idma_eh_req_i ( '0 ), // No error handling - .eh_req_valid_i( 1'b1 ), - .eh_req_ready_o( /*NOT CONNECTED*/ ), - - .protocol_req_o( axi_mst_req_o ), - .protocol_rsp_i( axi_mst_rsp_i ), - .busy_o ( idma_busy ) - ); - -endmodule : dma_core_wrap - - - -module dma_core_wrap_intf #( - parameter int unsigned AXI_ADDR_WIDTH = 32'd0, - parameter int unsigned AXI_DATA_WIDTH = 32'd0, - parameter int unsigned AXI_USER_WIDTH = 32'd0, - parameter int unsigned AXI_ID_WIDTH = 32'd0, - parameter int unsigned AXI_SLV_ID_WIDTH = 32'd0, - parameter int unsigned JOB_FIFO_DEPTH = 32'd0, - parameter int unsigned NUM_AX_IN_FLIGHT = 32'd0, - parameter int unsigned MEM_SYS_DEPTH = 32'd0, - parameter bit RAW_COUPLING_AVAIL = 1'b0, - parameter bit IS_TWO_D = 1'b0 -) ( - input logic clk_i, - input logic rst_ni, - input logic testmode_i, - AXI_BUS.Master axi_master, - AXI_BUS.Slave axi_slave -); - - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [(AXI_DATA_WIDTH/8)-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - typedef logic [AXI_ID_WIDTH-1:0] axi_id_t; - typedef logic [AXI_SLV_ID_WIDTH-1:0] axi_slv_id_t; - - `AXI_TYPEDEF_ALL(axi_mst, addr_t, axi_id_t, data_t, strb_t, user_t) - axi_mst_req_t axi_mst_req; - axi_mst_resp_t axi_mst_resp; - `AXI_ASSIGN_FROM_REQ(axi_master, axi_mst_req) - `AXI_ASSIGN_TO_RESP(axi_mst_resp, axi_master) - - `AXI_TYPEDEF_ALL(axi_slv, addr_t, axi_slv_id_t, data_t, strb_t, user_t) - axi_slv_req_t axi_slv_req; - axi_slv_resp_t axi_slv_resp; - `AXI_ASSIGN_TO_REQ(axi_slv_req, axi_slave) - `AXI_ASSIGN_FROM_RESP(axi_slave, axi_slv_resp) - - dma_core_wrap #( - .AxiAddrWidth ( AXI_ADDR_WIDTH ), - .AxiDataWidth ( AXI_DATA_WIDTH ), - .AxiIdWidth ( AXI_USER_WIDTH ), - .AxiUserWidth ( AXI_ID_WIDTH ), - .AxiSlvIdWidth ( AXI_SLV_ID_WIDTH ), - .JobFifoDepth ( JOB_FIFO_DEPTH ), - .NumAxInFlight ( NUM_AX_IN_FLIGHT ), - .MemSysDepth ( MEM_SYS_DEPTH ), - .RAWCouplingAvail ( RAW_COUPLING_AVAIL ), - .IsTwoD ( IS_TWO_D ), - .axi_mst_req_t ( axi_mst_req_t ), - .axi_mst_rsp_t ( axi_mst_resp_t ), - .axi_slv_req_t ( axi_slv_req_t ), - .axi_slv_rsp_t ( axi_slv_resp_t ) - ) i_dma_core_wrap ( - .clk_i, - .rst_ni, - .testmode_i, - .axi_mst_req_o ( axi_mst_req ), - .axi_mst_rsp_i ( axi_mst_resp ), - .axi_slv_req_i ( axi_slv_req ), - .axi_slv_rsp_o ( axi_slv_resp ) - ); - -endmodule : dma_core_wrap_intf diff --git a/src/systems/pulpopen/dmac_wrap.sv b/src/systems/pulpopen/dmac_wrap.sv deleted file mode 100644 index a48e33a9..00000000 --- a/src/systems/pulpopen/dmac_wrap.sv +++ /dev/null @@ -1,593 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Authors: -// - Thomas Benz -// - Michael Rogenmoser -// - Tobias Senti - -`include "axi/assign.svh" -`include "axi/typedef.svh" -`include "idma/typedef.svh" -`include "register_interface/typedef.svh" - -/// DMA Core wrapper -module dmac_wrap #( - parameter int unsigned NB_CORES = 4, - parameter int unsigned AXI_ADDR_WIDTH = 32, - parameter int unsigned AXI_DATA_WIDTH = 64, - parameter int unsigned AXI_USER_WIDTH = 6, - parameter int unsigned AXI_ID_WIDTH = 4, - parameter int unsigned PE_ID_WIDTH = 1, - parameter int unsigned NB_PE_PORTS = 1, - parameter int unsigned DATA_WIDTH = 32, - parameter int unsigned ADDR_WIDTH = 32, - parameter int unsigned BE_WIDTH = DATA_WIDTH/8, - parameter int unsigned NB_OUTSND_BURSTS = 8, - parameter int unsigned GLOBAL_QUEUE_DEPTH = 16 -) ( - input logic clk_i, - input logic rst_ni, - input logic test_mode_i, - XBAR_PERIPH_BUS.Slave pe_ctrl_slave[NB_PE_PORTS-1:0], - XBAR_TCDM_BUS.Slave ctrl_slave[NB_CORES-1:0], - hci_core_intf.master tcdm_master[3:0], - AXI_BUS.Master ext_master, - output logic [NB_CORES-1:0] term_event_o, - output logic [NB_CORES-1:0] term_irq_o, - output logic [NB_PE_PORTS-1:0] term_event_pe_o, - output logic [NB_PE_PORTS-1:0] term_irq_pe_o, - output logic busy_o -); - - localparam int unsigned NumRegs = NB_CORES + NB_PE_PORTS; - localparam int unsigned MstIdxWidth = AXI_ID_WIDTH; - localparam int unsigned SlvIdxWidth = AXI_ID_WIDTH - $clog2(NUM_STREAMS); - - // CORE --> MCHAN CTRL INTERFACE BUS SIGNALS - logic [NumRegs-1:0][DATA_WIDTH-1:0] config_wdata; - logic [NumRegs-1:0][ADDR_WIDTH-1:0] config_add; - logic [NumRegs-1:0] config_req; - logic [NumRegs-1:0] config_wen; - logic [NumRegs-1:0][BE_WIDTH-1:0] config_be; - logic [NumRegs-1:0][PE_ID_WIDTH-1:0] config_id; - logic [NumRegs-1:0] config_gnt; - logic [NumRegs-1:0][DATA_WIDTH-1:0] config_r_rdata; - logic [NumRegs-1:0] config_r_valid; - logic [NumRegs-1:0] config_r_opc; - logic [NumRegs-1:0][PE_ID_WIDTH-1:0] config_r_id; - - // tie-off pe control ports - for (genvar i = 0; i < NB_CORES; i++) begin : gen_ctrl_registers - assign config_add[i] = ctrl_slave[i].add; - assign config_req[i] = ctrl_slave[i].req; - assign config_wdata[i] = ctrl_slave[i].wdata; - assign config_wen[i] = ctrl_slave[i].wen; - assign config_be[i] = ctrl_slave[i].be; - assign config_id[i] = '0; - assign ctrl_slave[i].gnt = config_gnt[i]; - assign ctrl_slave[i].r_opc = config_r_opc[i]; - assign ctrl_slave[i].r_valid = config_r_valid[i]; - assign ctrl_slave[i].r_rdata = config_r_rdata[i]; - end - - for (genvar i = 0; i < NB_PE_PORTS; i++) begin : gen_pe_ctrl_registers - assign config_add[NB_CORES+i] = pe_ctrl_slave[i].add; - assign config_req[NB_CORES+i] = pe_ctrl_slave[i].req; - assign config_wdata[NB_CORES+i] = pe_ctrl_slave[i].wdata; - assign config_wen[NB_CORES+i] = pe_ctrl_slave[i].wen; - assign config_be[NB_CORES+i] = pe_ctrl_slave[i].be; - assign config_id[NB_CORES+i] = pe_ctrl_slave[i].id; - assign pe_ctrl_slave[i].gnt = config_gnt[NB_CORES+i]; - assign pe_ctrl_slave[i].r_opc = config_r_opc[NB_CORES+i]; - assign pe_ctrl_slave[i].r_valid = config_r_valid[NB_CORES+i]; - assign pe_ctrl_slave[i].r_rdata = config_r_rdata[NB_CORES+i]; - assign pe_ctrl_slave[i].r_id = config_r_id[NB_CORES+i]; - end - - // AXI4+ATOP types - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [MstIdxWidth-1:0] mst_id_t; - typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - - // AXI4+ATOP channels typedefs - `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, mst_id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, mst_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, mst_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, data_t, mst_id_t, user_t) - `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_chan_t, axi_w_chan_t, axi_ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_rsp_t, axi_b_chan_t, axi_r_chan_t) - - // OBI channels typedefs - `IDMA_OBI_TYPEDEF_A_CHAN_T(obi_a_chan_t, addr_t, data_t, strb_t, mst_id_t) - `IDMA_OBI_TYPEDEF_R_CHAN_T(obi_r_chan_t, data_t, mst_id_t) - `IDMA_OBI_TYPEDEF_REQ_T(obi_req_t, obi_a_chan_t) - `IDMA_OBI_TYPEDEF_RESP_T(obi_rsp_t, obi_r_chan_t) - - // Calculate padding (keep it static for now!) - localparam int unsigned ObiAChanWidth = AXI_ADDR_WIDTH + AXI_DATA_WIDTH + AXI_DATA_WIDTH/8 + 32'd1; - localparam int unsigned AxiAwChanWidth = axi_pkg::aw_width(AXI_ADDR_WIDTH, MstIdxWidth, AXI_USER_WIDTH); - localparam int unsigned AxiArChanWidth = axi_pkg::ar_width(AXI_ADDR_WIDTH, MstIdxWidth, AXI_USER_WIDTH); - localparam int unsigned ArMetaPadWidth = ObiAChanWidth - AxiArChanWidth; - localparam int unsigned AwMetaPadWidth = ObiAChanWidth - AxiAwChanWidth; - - - // DMA Meta Channels - typedef struct packed { - axi_ar_chan_t ar_chan; - logic [ArMetaPadWidth-1:0] padding; - } axi_read_ar_chan_padded_t; - - typedef struct packed { - obi_a_chan_t a_chan; - } obi_read_a_chan_padded_t; - - typedef union packed { - axi_read_ar_chan_padded_t axi; - obi_read_a_chan_padded_t obi; - } read_meta_channel_t; - - typedef struct packed { - axi_aw_chan_t aw_chan; - logic [AwMetaPadWidth-1:0] padding; - } axi_write_aw_chan_padded_t; - - typedef struct packed { - obi_a_chan_t a_chan; - } obi_write_a_chan_padded_t; - - typedef union packed { - axi_write_aw_chan_padded_t axi; - obi_write_a_chan_padded_t obi; - } write_meta_channel_t; - - // BUS definitions - axi_req_t axi_read_req, axi_write_req, soc_req; - axi_rsp_t axi_read_rsp, axi_write_rsp, soc_rsp; - - obi_req_t obi_read_req, obi_write_req; - obi_rsp_t obi_read_rsp, obi_write_rsp; - - // interface to structs - `AXI_ASSIGN_FROM_REQ(ext_master, soc_req) - `AXI_ASSIGN_TO_RESP(soc_rsp, ext_master) - - // Register BUS definitions - `REG_BUS_TYPEDEF_ALL(dma_regs, logic[9:0], logic[31:0], logic[3:0]) - dma_regs_req_t [NumRegs-1:0] dma_regs_req; - dma_regs_rsp_t [NumRegs-1:0] dma_regs_rsp; - - // iDMA struct definitions - localparam int unsigned TFLenWidth = AXI_ADDR_WIDTH; - localparam int unsigned NumDim = 3; - localparam int unsigned RepWidth = 32; - localparam int unsigned StrideWidth = 32; - typedef logic [TFLenWidth-1:0] tf_len_t; - typedef logic [RepWidth-1:0] reps_t; - typedef logic [StrideWidth-1:0] strides_t; - - // iDMA request / response types - `IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, mst_id_t, addr_t, tf_len_t) - `IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t) - - // iDMA ND request - `IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, reps_t, strides_t) - - // ND rep parameter - localparam logic [2:0][31:0] RepWidths = '{default: 32'd32}; - - // fifo types - typedef struct packed { - idma_nd_req_t nd_req; - logic stream; - } fifo_t; - - // transfer id type - typedef logic [31:0] tf_id_t; - - fifo_t fifo_in, fifo_out; - logic stream_idx, stream_idx_queue; - - logic [1:0] twod_queue_valid_demux; - logic [1:0] twod_queue_ready_demux; - - logic [1:0] trans_complete_demux; - idma_req_t [1:0] burst_req_demux; - logic [1:0] be_valid_demux; - logic [1:0] be_ready_demux; - - idma_rsp_t [1:0] idma_rsp_demux; - logic [1:0] be_rsp_valid_demux; - logic [1:0] be_rsp_ready_demux; - - tf_id_t [1:0] done_id; - tf_id_t [1:0] next_id_demux; - tf_id_t next_id; - - logic [1:0] midend_busy; - idma_pkg::idma_busy_t [1:0] be_busy; - - idma_nd_req_t nd_req, nd_req_queue; - - logic fe_valid, twod_queue_valid; - logic fe_ready, twod_queue_ready; - // logic trans_complete, midend_busy; - // idma_pkg::idma_busy_t idma_busy; - - - // ------------------------------------------------------ - // FRONTEND - // ------------------------------------------------------ - for (genvar i = 0; i < NumRegs; i++) begin : gen_core_regs - periph_to_reg #( - .AW ( 10 ), - .DW ( 32 ), - .BW ( 8 ), - .IW ( PE_ID_WIDTH ), - .req_t ( dma_regs_req_t ), - .rsp_t ( dma_regs_rsp_t ) - ) i_pe_translate ( - .clk_i, - .rst_ni, - .req_i ( config_req [i] ), - .add_i ( config_add [i][9:0] ), - .wen_i ( config_wen [i] ), - .wdata_i ( config_wdata [i] ), - .be_i ( config_be [i] ), - .id_i ( config_id [i] ), - .gnt_o ( config_gnt [i] ), - .r_rdata_o ( config_r_rdata [i] ), - .r_opc_o ( config_r_opc [i] ), - .r_id_o ( config_r_id [i] ), - .r_valid_o ( config_r_valid [i] ), - .reg_req_o ( dma_regs_req [i] ), - .reg_rsp_i ( dma_regs_rsp [i] ) - ); - end - - idma_reg32_3d #( - .NumRegs ( NumRegs ), - .NumStreams ( 32'd2 ), - .IdCounterWidth ( 32'd32 ), - .reg_req_t ( dma_regs_req_t ), - .reg_rsp_t ( dma_regs_rsp_t ), - .dma_req_t ( idma_nd_req_t ) - ) i_idma_reg32_3d ( - .clk_i, - .rst_ni, - .dma_ctrl_req_i ( dma_regs_req ), - .dma_ctrl_rsp_o ( dma_regs_rsp ), - .dma_req_o ( nd_req ), - .req_valid_o ( fe_valid ), - .req_ready_i ( fe_ready ), - .next_id_i ( next_id ), - .done_id_i ( done_id ), - .stream_idx_o ( stream_idx ), - .busy_i ( be_busy ), - .midend_busy_i ( midend_busy ) - ); - - for (genvar i = 0; i < 2; i++) begin : gen_id_cnts - logic issue; - assign issue = fe_valid & fe_ready & (stream_idx == i); - - idma_transfer_id_gen #( - .IdWidth(32'd32) - ) i_idma_transfer_id_gen ( - .clk_i, - .rst_ni, - .issue_i ( issue ), - .retire_i ( trans_complete_demux[i] ), - .next_o ( done_id[i] ), - .completed_o( next_id_demux[i] ) - ); - end - - // give proper id - assign next_id = next_id_demux[stream_idx]; - - // interrupts and events (currently broadcast tx_cplt event only) - assign term_event_pe_o = |trans_complete_demux; - assign term_irq_pe_o = |trans_complete_demux; - assign term_event_o = |trans_complete_demux; - assign term_irq_o = |trans_complete_demux; - assign busy_o = midend_busy | (|be_busy); - - - // ------------------------------------------------------ - // MIDEND - // ------------------------------------------------------ - // global (3D) request FIFO - stream_fifo #( - .DEPTH ( GLOBAL_QUEUE_DEPTH ), - .T ( idma_nd_req_t ) - ) i_stream_fifo ( - .clk_i, - .rst_ni, - .flush_i ( 1'b0 ), - .testmode_i ( test_mode_i ), - .usage_o (/*NOT CONNECTED*/ ), - .data_i ( fifo_in ), - .valid_i ( fe_valid ), - .ready_o ( fe_ready ), - .data_o ( fifo_out ), - .valid_o ( twod_queue_valid ), - .ready_i ( twod_queue_ready ) - ); - - assign fifo_in.nd_req = nd_req; - assign fifo_in.stream = stream_idx; - assign nd_req_queue = fifo_out.nd_req; - assign stream_idx_queue = fifo_out.stream; - - stream_demux #( - .N_OUP ( 2 ) - ) i_stream_demux ( - .inp_valid_i ( twod_queue_valid ), - .inp_ready_o ( twod_queue_ready ), - .oup_sel_i ( stream_idx_queue ), - .oup_valid_o ( twod_queue_valid_demux ), - .oup_ready_i ( twod_queue_ready_demux ) - ); - - idma_nd_midend #( - .NumDim ( NumDim ), - .addr_t ( addr_t ), - .idma_req_t ( idma_req_t ), - .idma_rsp_t ( idma_rsp_t ), - .idma_nd_req_t( idma_nd_req_t ), - .RepWidths ( RepWidths ) - ) i_idma_nd_midend_axi_to_obi ( - .clk_i, - .rst_ni, - .nd_req_i ( nd_req_queue ), - .nd_req_valid_i ( twod_queue_valid_demux[0] ), - .nd_req_ready_o ( twod_queue_ready_demux[0] ), - .nd_rsp_o (/*NOT CONNECTED*/ ), - .nd_rsp_valid_o ( trans_complete_demux[0] ), - .nd_rsp_ready_i ( 1'b1 ), - .burst_req_o ( burst_req_demux[0] ), - .burst_req_valid_o( be_valid_demux[0] ), - .burst_req_ready_i( be_ready_demux[0] ), - .burst_rsp_i ( idma_rsp_demux[0] ), - .burst_rsp_valid_i( be_rsp_valid_demux[0] ), - .burst_rsp_ready_o( be_rsp_ready_demux[0] ), - .busy_o ( midend_busy[0] ) - ); - - idma_nd_midend #( - .NumDim ( NumDim ), - .addr_t ( addr_t ), - .idma_req_t ( idma_req_t ), - .idma_rsp_t ( idma_rsp_t ), - .idma_nd_req_t( idma_nd_req_t ), - .RepWidths ( RepWidths ) - ) i_idma_nd_midend_obi_to_axi ( - .clk_i, - .rst_ni, - .nd_req_i ( nd_req_queue ), - .nd_req_valid_i ( twod_queue_valid_demux[1] ), - .nd_req_ready_o ( twod_queue_ready_demux[1] ), - .nd_rsp_o (/*NOT CONNECTED*/ ), - .nd_rsp_valid_o ( trans_complete_demux[1] ), - .nd_rsp_ready_i ( 1'b1 ), - .burst_req_o ( burst_req_demux[1] ), - .burst_req_valid_o( be_valid_demux[1] ), - .burst_req_ready_i( be_ready_demux[1] ), - .burst_rsp_i ( idma_rsp_demux[1] ), - .burst_rsp_valid_i( be_rsp_valid_demux[1] ), - .burst_rsp_ready_o( be_rsp_ready_demux[1] ), - .busy_o ( midend_busy[1] ) - ); - - - // ------------------------------------------------------ - // BACKEND - // ------------------------------------------------------ - idma_backend_r_axi_w_obi #( - .DataWidth ( AXI_DATA_WIDTH ), - .AddrWidth ( AXI_ADDR_WIDTH ), - .AxiIdWidth ( AXI_ID_WIDTH ), - .UserWidth ( AXI_USER_WIDTH ), - .TFLenWidth ( TFLenWidth ), - .MaskInvalidData ( 1'b1 ), - .BufferDepth ( 3 ), - .RAWCouplingAvail ( 1'b0 ), - .HardwareLegalizer ( 1'b1 ), - .RejectZeroTransfers ( 1'b1 ), - .ErrorCap ( idma_pkg::NO_ERROR_HANDLING ), - .PrintFifoInfo ( 1'b0 ), - .NumAxInFlight ( NB_OUTSND_BURSTS ), - .MemSysDepth ( 32'd0 ), - .idma_req_t ( idma_req_t ), - .idma_rsp_t ( idma_rsp_t ), - .idma_eh_req_t ( idma_pkg::idma_eh_req_t ), - .idma_busy_t ( idma_pkg::idma_busy_t ), - .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ), - .obi_req_t ( obi_req_t ), - .obi_rsp_t ( obi_rsp_t ), - .write_meta_channel_t ( write_meta_channel_t ), - .read_meta_channel_t ( read_meta_channel_t ) - ) i_idma_backend_axi_to_obi ( - .clk_i, - .rst_ni, - .testmode_i ( test_mode_i ), - .idma_req_i ( burst_req_demux[0] ), - .req_valid_i ( be_valid_demux[0] ), - .req_ready_o ( be_ready_demux[0] ), - .idma_rsp_o ( idma_rsp_demux[0] ), - .rsp_valid_o ( be_rsp_valid_demux[0] ), - .rsp_ready_i ( be_rsp_ready_demux[0] ), - .idma_eh_req_i ( '0 ), - .eh_req_valid_i ( 1'b1 ), - .eh_req_ready_o ( /* NOT CONNECTED */ ), - .axi_read_req_o ( axi_read_req ), - .axi_read_rsp_i ( axi_read_rsp ), - .obi_write_req_o ( obi_write_req ), - .obi_write_rsp_i ( obi_write_rsp ), - .busy_o ( be_busy[0] ) - ); - - idma_backend_w_axi_r_obi #( - .DataWidth ( AXI_DATA_WIDTH ), - .AddrWidth ( AXI_ADDR_WIDTH ), - .AxiIdWidth ( AXI_ID_WIDTH ), - .UserWidth ( AXI_USER_WIDTH ), - .TFLenWidth ( TFLenWidth ), - .MaskInvalidData ( 1'b1 ), - .BufferDepth ( 3 ), - .RAWCouplingAvail ( 1'b0 ), - .HardwareLegalizer ( 1'b1 ), - .RejectZeroTransfers ( 1'b1 ), - .ErrorCap ( idma_pkg::NO_ERROR_HANDLING ), - .PrintFifoInfo ( 1'b0 ), - .NumAxInFlight ( NB_OUTSND_BURSTS ), - .MemSysDepth ( 32'd0 ), - .idma_req_t ( idma_req_t ), - .idma_rsp_t ( idma_rsp_t ), - .idma_eh_req_t ( idma_pkg::idma_eh_req_t ), - .idma_busy_t ( idma_pkg::idma_busy_t ), - .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ), - .obi_req_t ( obi_req_t ), - .obi_rsp_t ( obi_rsp_t ), - .write_meta_channel_t ( write_meta_channel_t ), - .read_meta_channel_t ( read_meta_channel_t ) - ) i_idma_backend_obi_to_axi ( - .clk_i, - .rst_ni, - .testmode_i ( test_mode_i ), - .idma_req_i ( burst_req_demux[1] ), - .req_valid_i ( be_valid_demux[1] ), - .req_ready_o ( be_ready_demux[1] ), - .idma_rsp_o ( idma_rsp_demux[1] ), - .rsp_valid_o ( be_rsp_valid_demux[1] ), - .rsp_ready_i ( be_rsp_ready_demux[1] ), - .idma_eh_req_i ( '0 ), - .eh_req_valid_i ( 1'b1 ), - .eh_req_ready_o ( /* NOT CONNECTED */ ), - .axi_write_req_o ( axi_write_req ), - .axi_write_rsp_i ( axi_write_rsp ), - .obi_read_req_o ( obi_read_req ), - .obi_read_rsp_i ( obi_read_rsp ), - .busy_o ( be_busy[1] ) - ); - - - // ------------------------------------------------------ - // AXI RW Join - // ------------------------------------------------------ - axi_rw_join #( - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_rsp_t ) - ) i_axi_soc_rw_join ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_read_req_i ( axi_read_req ), - .slv_read_resp_o ( axi_read_rsp ), - .slv_write_req_i ( axi_write_req ), - .slv_write_resp_o ( axi_write_rsp ), - .mst_req_o ( soc_req ), - .mst_resp_i ( soc_rsp ) - ); - - // ------------------------------------------------------ - // TCDM Bank Split - // ------------------------------------------------------ - - logic tcdm_master_we_0; - logic tcdm_master_we_1; - logic tcdm_master_we_2; - logic tcdm_master_we_3; - - mem_to_banks #( - .AddrWidth( AXI_ADDR_WIDTH ), - .DataWidth( AXI_DATA_WIDTH ), - .NumBanks ( 2 ), - .HideStrb ( 1'b1 ), - .MaxTrans ( 32'd1 ) - ) i_mem_to_banks_write ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .req_i ( obi_write_req.a_req ), - .addr_i ( obi_write_req.a.addr ), - .wdata_i ( obi_write_req.a.wdata ), - .strb_i ( obi_write_req.a.be ), - .atop_i ( '0 ), - .we_i ( !obi_write_req.a.we ), - - .gnt_o ( obi_write_rsp.a_gnt ), - .rvalid_o ( obi_write_rsp.r_valid ), - .rdata_o ( obi_write_rsp.r.rdata ), - - .bank_req_o ( { tcdm_master[0].req, tcdm_master[1].req } ), - .bank_gnt_i ( { tcdm_master[0].gnt, tcdm_master[1].gnt } ), - .bank_addr_o ( { tcdm_master[0].add, tcdm_master[1].add } ), - .bank_wdata_o ( { tcdm_master[0].data, tcdm_master[1].data } ), - .bank_strb_o ( { tcdm_master[0].be, tcdm_master[1].be } ), - .bank_atop_o ( /* NOT CONNECTED */ ), - .bank_we_o ( { tcdm_master_we_0, tcdm_master_we_1 } ), - .bank_rvalid_i ( { tcdm_master[0].r_valid, tcdm_master[1].r_valid } ), - .bank_rdata_i ( { tcdm_master[0].r_data, tcdm_master[1].r_data } ) - ); - - mem_to_banks #( - .AddrWidth( AXI_ADDR_WIDTH ), - .DataWidth( AXI_DATA_WIDTH ), - .NumBanks ( 2 ), - .HideStrb ( 1'b1 ), - .MaxTrans ( 32'd1 ) - ) i_mem_to_banks_read ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .req_i ( obi_read_req.a_req ), - .addr_i ( obi_read_req.a.addr ), - .wdata_i ( obi_read_req.a.wdata ), - .strb_i ( obi_read_req.a.be ), - .atop_i ( '0 ), - .we_i ( !obi_read_req.a.we ), - - .gnt_o ( obi_read_rsp.a_gnt ), - .rvalid_o ( obi_read_rsp.r_valid ), - .rdata_o ( obi_read_rsp.r.rdata ), - - .bank_req_o ( { tcdm_master[2].req, tcdm_master[3].req } ), - .bank_gnt_i ( { tcdm_master[2].gnt, tcdm_master[3].gnt } ), - .bank_addr_o ( { tcdm_master[2].add, tcdm_master[3].add } ), - .bank_wdata_o ( { tcdm_master[2].data, tcdm_master[3].data } ), - .bank_strb_o ( { tcdm_master[2].be, tcdm_master[3].be } ), - .bank_atop_o ( /* NOT CONNECTED */ ), - .bank_we_o ( { tcdm_master_we_2, tcdm_master_we_3 } ), - .bank_rvalid_i ( { tcdm_master[2].r_valid, tcdm_master[3].r_valid } ), - .bank_rdata_i ( { tcdm_master[2].r_data, tcdm_master[3].r_data } ) - ); - - // flip we polarity - assign tcdm_master[0].wen = !tcdm_master_we_0; - assign tcdm_master[1].wen = !tcdm_master_we_1; - assign tcdm_master[2].wen = !tcdm_master_we_2; - assign tcdm_master[3].wen = !tcdm_master_we_3; - - assign tcdm_master[0].boffs = '0; - assign tcdm_master[1].boffs = '0; - assign tcdm_master[2].boffs = '0; - assign tcdm_master[3].boffs = '0; - - assign tcdm_master[0].lrdy = '1; - assign tcdm_master[1].lrdy = '1; - assign tcdm_master[2].lrdy = '1; - assign tcdm_master[3].lrdy = '1; - - assign tcdm_master[0].user = '0; - assign tcdm_master[1].user = '0; - assign tcdm_master[2].user = '0; - assign tcdm_master[3].user = '0; - -endmodule : dmac_wrap diff --git a/src/systems/pulpopen/dmac_wrap_synth.sv b/src/systems/pulpopen/dmac_wrap_synth.sv deleted file mode 100644 index e30c6d12..00000000 --- a/src/systems/pulpopen/dmac_wrap_synth.sv +++ /dev/null @@ -1,429 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Authors: -// - Thomas Benz -// - Michael Rogenmoser -// - Tobias Senti - -/// Synthesis wrapper for DMAC -module dmac_wrap_synth #( - parameter int unsigned NumAx = 2, - parameter int unsigned FifoDepth = 2 -)( - input logic clk_i, - input logic rst_ni, - input logic test_mode_i, - - output logic [31:0] data_master_aw_addr_o, - output logic [2:0] data_master_aw_prot_o, - output logic [3:0] data_master_aw_region_o, - output logic [7:0] data_master_aw_len_o, - output logic [2:0] data_master_aw_size_o, - output logic [1:0] data_master_aw_burst_o, - output logic data_master_aw_lock_o, - output logic [5:0] data_master_aw_atop_o, - output logic [3:0] data_master_aw_cache_o, - output logic [3:0] data_master_aw_qos_o, - output logic [5:0] data_master_aw_id_o, - output logic [0:0] data_master_aw_user_o, - output logic data_master_aw_valid_o, - input logic data_master_aw_ready_i, - - output logic [31:0] data_master_ar_addr_o, - output logic [2:0] data_master_ar_prot_o, - output logic [3:0] data_master_ar_region_o, - output logic [7:0] data_master_ar_len_o, - output logic [2:0] data_master_ar_size_o, - output logic [1:0] data_master_ar_burst_o, - output logic data_master_ar_lock_o, - output logic [3:0] data_master_ar_cache_o, - output logic [3:0] data_master_ar_qos_o, - output logic [5:0] data_master_ar_id_o, - output logic [0:0] data_master_ar_user_o, - output logic data_master_ar_valid_o, - input logic data_master_ar_ready_i, - - output logic [63:0] data_master_w_data_o, - output logic [7:0] data_master_w_strb_o, - output logic [3:0] data_master_w_user_o, - output logic data_master_w_last_o, - output logic data_master_w_valid_o, - input logic data_master_w_ready_i, - - input logic [63:0] data_master_r_data_i, - input logic [1:0] data_master_r_resp_i, - input logic data_master_r_last_i, - input logic [5:0] data_master_r_id_i, - input logic [0:0] data_master_r_user_i, - input logic data_master_r_valid_i, - output logic data_master_r_ready_o, - - input logic [1:0] data_master_b_resp_i, - input logic [5:0] data_master_b_id_i, - input logic [0:0] data_master_b_user_i, - input logic data_master_b_valid_i, - output logic data_master_b_ready_o, - - input logic ctrl_0_req, - input logic [31:0] ctrl_0_add, - input logic ctrl_0_wen, - input logic [31:0] ctrl_0_wdata, - input logic [3:0] ctrl_0_be, - output logic ctrl_0_gnt, - // output logic ctrl_0_r_opc, - output logic [31:0] ctrl_0_r_rdata, - output logic ctrl_0_r_valid, - - input logic ctrl_1_req, - input logic [31:0] ctrl_1_add, - input logic ctrl_1_wen, - input logic [31:0] ctrl_1_wdata, - input logic [3:0] ctrl_1_be, - output logic ctrl_1_gnt, - // output logic ctrl_1_r_opc, - output logic [31:0] ctrl_1_r_rdata, - output logic ctrl_1_r_valid, - - input logic ctrl_2_req, - input logic [31:0] ctrl_2_add, - input logic ctrl_2_wen, - input logic [31:0] ctrl_2_wdata, - input logic [3:0] ctrl_2_be, - output logic ctrl_2_gnt, - // output logic ctrl_2_r_opc, - output logic [31:0] ctrl_2_r_rdata, - output logic ctrl_2_r_valid, - - input logic ctrl_3_req, - input logic [31:0] ctrl_3_add, - input logic ctrl_3_wen, - input logic [31:0] ctrl_3_wdata, - input logic [3:0] ctrl_3_be, - output logic ctrl_3_gnt, - // output logic ctrl_3_r_opc, - output logic [31:0] ctrl_3_r_rdata, - output logic ctrl_3_r_valid, - - input logic ctrl_4_req, - input logic [31:0] ctrl_4_add, - input logic ctrl_4_wen, - input logic [31:0] ctrl_4_wdata, - input logic [3:0] ctrl_4_be, - output logic ctrl_4_gnt, - // output logic ctrl_4_r_opc, - output logic [31:0] ctrl_4_r_rdata, - output logic ctrl_4_r_valid, - - input logic ctrl_5_req, - input logic [31:0] ctrl_5_add, - input logic ctrl_5_wen, - input logic [31:0] ctrl_5_wdata, - input logic [3:0] ctrl_5_be, - output logic ctrl_5_gnt, - // output logic ctrl_5_r_opc, - output logic [31:0] ctrl_5_r_rdata, - output logic ctrl_5_r_valid, - - input logic ctrl_6_req, - input logic [31:0] ctrl_6_add, - input logic ctrl_6_wen, - input logic [31:0] ctrl_6_wdata, - input logic [3:0] ctrl_6_be, - output logic ctrl_6_gnt, - // output logic ctrl_6_r_opc, - output logic [31:0] ctrl_6_r_rdata, - output logic ctrl_6_r_valid, - - input logic ctrl_7_req, - input logic [31:0] ctrl_7_add, - input logic ctrl_7_wen, - input logic [31:0] ctrl_7_wdata, - input logic [3:0] ctrl_7_be, - output logic ctrl_7_gnt, - // output logic ctrl_7_r_opc, - output logic [31:0] ctrl_7_r_rdata, - output logic ctrl_7_r_valid, - - output logic tcdm_0_req, - output logic [31:0] tcdm_0_add, - output logic tcdm_0_wen, - output logic [31:0] tcdm_0_wdata, - output logic [3:0] tcdm_0_be, - input logic tcdm_0_gnt, - // input logic tcdm_0_r_opc, - input logic [31:0] tcdm_0_r_rdata, - input logic tcdm_0_r_valid, - - output logic tcdm_1_req, - output logic [31:0] tcdm_1_add, - output logic tcdm_1_wen, - output logic [31:0] tcdm_1_wdata, - output logic [3:0] tcdm_1_be, - input logic tcdm_1_gnt, - // input logic tcdm_1_r_opc, - input logic [31:0] tcdm_1_r_rdata, - input logic tcdm_1_r_valid, - - output logic tcdm_2_req, - output logic [31:0] tcdm_2_add, - output logic tcdm_2_wen, - output logic [31:0] tcdm_2_wdata, - output logic [3:0] tcdm_2_be, - input logic tcdm_2_gnt, - // input logic tcdm_2_r_opc, - input logic [31:0] tcdm_2_r_rdata, - input logic tcdm_2_r_valid, - - output logic tcdm_3_req, - output logic [31:0] tcdm_3_add, - output logic tcdm_3_wen, - output logic [31:0] tcdm_3_wdata, - output logic [3:0] tcdm_3_be, - input logic tcdm_3_gnt, - // input logic tcdm_3_r_opc, - input logic [31:0] tcdm_3_r_rdata, - input logic tcdm_3_r_valid, - - input logic pe_ctrl_req, - input logic [31:0] pe_ctrl_add, - input logic pe_ctrl_wen, - input logic [31:0] pe_ctrl_wdata, - input logic [3:0] pe_ctrl_be, - output logic pe_ctrl_gnt, - input logic [8:0] pe_ctrl_id, - output logic pe_ctrl_r_valid, - // output logic pe_ctrl_r_opc, - output logic [8:0] pe_ctrl_r_id, - output logic [31:0] pe_ctrl_r_rdata, - - output logic [7:0] term_event_o, - output logic [7:0] term_irq_o, - output logic term_event_pe_o, - output logic term_irq_pe_o, - output logic busy_o -); - - XBAR_TCDM_BUS ctrl_slave[7:0](); - XBAR_PERIPH_BUS pe_ctrl_slave[0:0](); - hci_core_intf tcdm_master[3:0](.clk()); - AXI_BUS #( - .AXI_ADDR_WIDTH ( 32 ), - .AXI_DATA_WIDTH ( 64 ), - .AXI_ID_WIDTH ( 6 ), - .AXI_USER_WIDTH ( 1 ) - ) ext_master(); - - dmac_wrap #( - .NB_CORES ( 8 ), - .AXI_ADDR_WIDTH ( 32 ), - .AXI_DATA_WIDTH ( 64 ), - .AXI_USER_WIDTH ( 1 ), - .AXI_ID_WIDTH ( 6 ), - .PE_ID_WIDTH ( 8 ), - .NB_PE_PORTS ( 1 ), - .DATA_WIDTH ( 32 ), - .ADDR_WIDTH ( 32 ), - .BE_WIDTH ( 4 ), - .NB_OUTSND_BURSTS ( NumAx ), - .GLOBAL_QUEUE_DEPTH ( FifoDepth ) - ) i_dmac_wrap ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_mode_i ( test_mode_i ), - .pe_ctrl_slave ( pe_ctrl_slave ), - .ctrl_slave ( ctrl_slave ), - .tcdm_master ( tcdm_master ), - .ext_master ( ext_master ), - .term_event_o ( term_event_o ), - .term_irq_o ( term_irq_o ), - .term_event_pe_o ( term_event_pe_o ), - .term_irq_pe_o ( term_irq_pe_o ), - .busy_o ( busy_o ) - ); - - assign data_master_aw_valid_o = ext_master.aw_valid; - assign data_master_aw_addr_o = ext_master.aw_addr; - assign data_master_aw_prot_o = ext_master.aw_prot; - assign data_master_aw_region_o = ext_master.aw_region; - assign data_master_aw_len_o = ext_master.aw_len; - assign data_master_aw_size_o = ext_master.aw_size; - assign data_master_aw_burst_o = ext_master.aw_burst; - assign data_master_aw_lock_o = ext_master.aw_lock; - assign data_master_aw_atop_o = ext_master.aw_atop; - assign data_master_aw_cache_o = ext_master.aw_cache; - assign data_master_aw_qos_o = ext_master.aw_qos; - assign data_master_aw_id_o = ext_master.aw_id; - assign data_master_aw_user_o = ext_master.aw_user; - assign ext_master.aw_ready = data_master_aw_ready_i; - - assign data_master_ar_valid_o = ext_master.ar_valid; - assign data_master_ar_addr_o = ext_master.ar_addr; - assign data_master_ar_prot_o = ext_master.ar_prot; - assign data_master_ar_region_o = ext_master.ar_region; - assign data_master_ar_len_o = ext_master.ar_len; - assign data_master_ar_size_o = ext_master.ar_size; - assign data_master_ar_burst_o = ext_master.ar_burst; - assign data_master_ar_lock_o = ext_master.ar_lock; - assign data_master_ar_cache_o = ext_master.ar_cache; - assign data_master_ar_qos_o = ext_master.ar_qos; - assign data_master_ar_id_o = ext_master.ar_id; - assign data_master_ar_user_o = ext_master.ar_user; - assign ext_master.ar_ready = data_master_ar_ready_i; - - assign data_master_w_valid_o = ext_master.w_valid; - assign data_master_w_data_o = ext_master.w_data; - assign data_master_w_strb_o = ext_master.w_strb; - assign data_master_w_user_o = ext_master.w_user; - assign data_master_w_last_o = ext_master.w_last; - assign ext_master.w_ready = data_master_w_ready_i; - - assign ext_master.r_valid = data_master_r_valid_i; - assign ext_master.r_data = data_master_r_data_i; - assign ext_master.r_resp = data_master_r_resp_i; - assign ext_master.r_last = data_master_r_last_i; - assign ext_master.r_id = data_master_r_id_i; - assign ext_master.r_user = data_master_r_user_i; - assign data_master_r_ready_o = ext_master.r_ready; - - assign ext_master.b_valid = data_master_b_valid_i; - assign ext_master.b_resp = data_master_b_resp_i; - assign ext_master.b_id = data_master_b_id_i; - assign ext_master.b_user = data_master_b_user_i; - assign data_master_b_ready_o = ext_master.b_ready; - - assign ctrl_slave[0].req = ctrl_0_req; - assign ctrl_slave[0].add = ctrl_0_add; - assign ctrl_slave[0].wen = ctrl_0_wen; - assign ctrl_slave[0].wdata = ctrl_0_wdata; - assign ctrl_slave[0].be = ctrl_0_be; - assign ctrl_0_gnt = ctrl_slave[0].gnt; - // assign ctrl_0_r_opc = ctrl_slave[0].r_opc; - assign ctrl_0_r_rdata = ctrl_slave[0].r_rdata; - assign ctrl_0_r_valid = ctrl_slave[0].r_valid; - - assign ctrl_slave[1].req = ctrl_1_req; - assign ctrl_slave[1].add = ctrl_1_add; - assign ctrl_slave[1].wen = ctrl_1_wen; - assign ctrl_slave[1].wdata = ctrl_1_wdata; - assign ctrl_slave[1].be = ctrl_1_be; - assign ctrl_1_gnt = ctrl_slave[1].gnt; - // assign ctrl_1_r_opc = ctrl_slave[1].r_opc; - assign ctrl_1_r_rdata = ctrl_slave[1].r_rdata; - assign ctrl_1_r_valid = ctrl_slave[1].r_valid; - - assign ctrl_slave[2].req = ctrl_2_req; - assign ctrl_slave[2].add = ctrl_2_add; - assign ctrl_slave[2].wen = ctrl_2_wen; - assign ctrl_slave[2].wdata = ctrl_2_wdata; - assign ctrl_slave[2].be = ctrl_2_be; - assign ctrl_2_gnt = ctrl_slave[2].gnt; - // assign ctrl_2_r_opc = ctrl_slave[2].r_opc; - assign ctrl_2_r_rdata = ctrl_slave[2].r_rdata; - assign ctrl_2_r_valid = ctrl_slave[2].r_valid; - - assign ctrl_slave[3].req = ctrl_3_req; - assign ctrl_slave[3].add = ctrl_3_add; - assign ctrl_slave[3].wen = ctrl_3_wen; - assign ctrl_slave[3].wdata = ctrl_3_wdata; - assign ctrl_slave[3].be = ctrl_3_be; - assign ctrl_3_gnt = ctrl_slave[3].gnt; - // assign ctrl_3_r_opc = ctrl_slave[3].r_opc; - assign ctrl_3_r_rdata = ctrl_slave[3].r_rdata; - assign ctrl_3_r_valid = ctrl_slave[3].r_valid; - - assign ctrl_slave[4].req = ctrl_4_req; - assign ctrl_slave[4].add = ctrl_4_add; - assign ctrl_slave[4].wen = ctrl_4_wen; - assign ctrl_slave[4].wdata = ctrl_4_wdata; - assign ctrl_slave[4].be = ctrl_4_be; - assign ctrl_4_gnt = ctrl_slave[4].gnt; - // assign ctrl_4_r_opc = ctrl_slave[4].r_opc; - assign ctrl_4_r_rdata = ctrl_slave[4].r_rdata; - assign ctrl_4_r_valid = ctrl_slave[4].r_valid; - - assign ctrl_slave[5].req = ctrl_5_req; - assign ctrl_slave[5].add = ctrl_5_add; - assign ctrl_slave[5].wen = ctrl_5_wen; - assign ctrl_slave[5].wdata = ctrl_5_wdata; - assign ctrl_slave[5].be = ctrl_5_be; - assign ctrl_5_gnt = ctrl_slave[5].gnt; - // assign ctrl_5_r_opc = ctrl_slave[5].r_opc; - assign ctrl_5_r_rdata = ctrl_slave[5].r_rdata; - assign ctrl_5_r_valid = ctrl_slave[5].r_valid; - - assign ctrl_slave[6].req = ctrl_6_req; - assign ctrl_slave[6].add = ctrl_6_add; - assign ctrl_slave[6].wen = ctrl_6_wen; - assign ctrl_slave[6].wdata = ctrl_6_wdata; - assign ctrl_slave[6].be = ctrl_6_be; - assign ctrl_6_gnt = ctrl_slave[6].gnt; - // assign ctrl_6_r_opc = ctrl_slave[6].r_opc; - assign ctrl_6_r_rdata = ctrl_slave[6].r_rdata; - assign ctrl_6_r_valid = ctrl_slave[6].r_valid; - - assign ctrl_slave[7].req = ctrl_7_req; - assign ctrl_slave[7].add = ctrl_7_add; - assign ctrl_slave[7].wen = ctrl_7_wen; - assign ctrl_slave[7].wdata = ctrl_7_wdata; - assign ctrl_slave[7].be = ctrl_7_be; - assign ctrl_7_gnt = ctrl_slave[7].gnt; - // assign ctrl_7_r_opc = ctrl_slave[7].r_opc; - assign ctrl_7_r_rdata = ctrl_slave[7].r_rdata; - assign ctrl_7_r_valid = ctrl_slave[7].r_valid; - - assign tcdm_0_req = tcdm_master[0].req; - assign tcdm_0_add = tcdm_master[0].add; - assign tcdm_0_wen = tcdm_master[0].wen; - assign tcdm_0_wdata = tcdm_master[0].data; - assign tcdm_0_be = tcdm_master[0].be; - assign tcdm_master[0].gnt = tcdm_0_gnt; - // assign tcdm_master[0].r_opc = tcdm_0_r_opc; - assign tcdm_master[0].r_data = tcdm_0_r_rdata; - assign tcdm_master[0].r_valid = tcdm_0_r_valid; - - assign tcdm_1_req = tcdm_master[1].req; - assign tcdm_1_add = tcdm_master[1].add; - assign tcdm_1_wen = tcdm_master[1].wen; - assign tcdm_1_wdata = tcdm_master[1].data; - assign tcdm_1_be = tcdm_master[1].be; - assign tcdm_master[1].gnt = tcdm_1_gnt; - // assign tcdm_master[1].r_opc = tcdm_1_r_opc; - assign tcdm_master[1].r_data = tcdm_1_r_rdata; - assign tcdm_master[1].r_valid = tcdm_1_r_valid; - - assign tcdm_2_req = tcdm_master[2].req; - assign tcdm_2_add = tcdm_master[2].add; - assign tcdm_2_wen = tcdm_master[2].wen; - assign tcdm_2_wdata = tcdm_master[2].data; - assign tcdm_2_be = tcdm_master[2].be; - assign tcdm_master[2].gnt = tcdm_2_gnt; - // assign tcdm_master[2].r_opc = tcdm_2_r_opc; - assign tcdm_master[2].r_data = tcdm_2_r_rdata; - assign tcdm_master[2].r_valid = tcdm_2_r_valid; - - assign tcdm_3_req = tcdm_master[3].req; - assign tcdm_3_add = tcdm_master[3].add; - assign tcdm_3_wen = tcdm_master[3].wen; - assign tcdm_3_wdata = tcdm_master[3].data; - assign tcdm_3_be = tcdm_master[3].be; - assign tcdm_master[3].gnt = tcdm_3_gnt; - // assign tcdm_master[3].r_opc = tcdm_3_r_opc; - assign tcdm_master[3].r_data = tcdm_3_r_rdata; - assign tcdm_master[3].r_valid = tcdm_3_r_valid; - - assign pe_ctrl_slave[0].req = pe_ctrl_req; - assign pe_ctrl_slave[0].add = pe_ctrl_add; - assign pe_ctrl_slave[0].wen = pe_ctrl_wen; - assign pe_ctrl_slave[0].wdata = pe_ctrl_wdata; - assign pe_ctrl_slave[0].be = pe_ctrl_be; - assign pe_ctrl_gnt = pe_ctrl_slave[0].gnt; - assign pe_ctrl_slave[0].id = pe_ctrl_id; - assign pe_ctrl_r_valid = pe_ctrl_slave[0].r_valid; - // assign pe_ctrl_r_opc = pe_ctrl_slave[0].r_opc; - assign pe_ctrl_r_id = pe_ctrl_slave[0].r_id; - assign pe_ctrl_r_rdata = pe_ctrl_slave[0].r_rdata; - - -endmodule