diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index fa61ea7..d501d5b 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -521,9 +521,9 @@ module idma_inst64_top #( // We need to schedule the assignment into a safe region, otherwise // `hart_id_i` won't have a value assigned at the beginning of the first // delta cycle. - /* verilator lint_off STMTDLY */ +`ifndef VERILATOR #0; - /* verilator lint_on STMTDLY */ +`endif $sformat(trace_file, "dma_trace_%05x_%05x.log", hart_id_i, c); end // attach the tracer diff --git a/util/mario/tracer.py b/util/mario/tracer.py index 96e0ea5..ce83f26 100644 --- a/util/mario/tracer.py +++ b/util/mario/tracer.py @@ -15,7 +15,6 @@ // The tracer for the ${identifier} iDMA `define IDMA_TRACER_${identifier_cap}(__backend_inst, __out_f) <%text>\\ `ifndef SYNTHESIS <%text>\\ -`ifndef VERILATOR <%text>\\ initial begin : inital_tracer_${identifier} <%text>\\ automatic bit first_iter = 1; <%text>\\ automatic integer tf; <%text>\\ @@ -25,7 +24,9 @@ automatic `IDMA_TRACER_MAX_TYPE busy [string]; <%text>\\ automatic `IDMA_TRACER_MAX_TYPE bus [string]; <%text>\\ automatic string trace; <%text>\\ +`ifndef VERILATOR <%text>\\ #0; <%text>\\ +`endif <%text>\\ tf = $fopen(__out_f, "w"); <%text>\\ $display("[iDMA Tracer] Logging %s to %s", `"__backend_inst`", __out_f); <%text>\\ forever begin <%text>\\ @@ -90,7 +91,6 @@ end <%text>\\ end <%text>\\ end <%text>\\ -`endif <%text>\\ `endif '''