From 9e57482836082c316c2946eeeebd7dc9ac0f40bb Mon Sep 17 00:00:00 2001
From: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Date: Fri, 30 Jun 2023 10:43:19 +0200
Subject: [PATCH] Add CI

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
---
 .github/verible-lint-matcher.json | 16 +++++++++++++
 .github/workflows/gitlab-ci.yml   | 23 +++++++++++++++++++
 .github/workflows/lint.yml        | 22 ++++++++++++++++++
 .gitlab-ci.yml                    | 38 +++++++++++++++++++++++++++++++
 4 files changed, 99 insertions(+)
 create mode 100644 .github/verible-lint-matcher.json
 create mode 100644 .github/workflows/gitlab-ci.yml
 create mode 100644 .github/workflows/lint.yml
 create mode 100644 .gitlab-ci.yml

diff --git a/.github/verible-lint-matcher.json b/.github/verible-lint-matcher.json
new file mode 100644
index 0000000..e5bfee9
--- /dev/null
+++ b/.github/verible-lint-matcher.json
@@ -0,0 +1,16 @@
+{
+  "problemMatcher": [
+    {
+      "owner": "verible-lint-matcher",
+      "pattern": [
+        {
+          "regexp": "^(.+):(\\d+):(\\d+):\\s(.+)$",
+          "file": 1,
+          "line": 2,
+          "column": 3,
+          "message": 4
+        }
+      ]
+    }
+  ]
+}
diff --git a/.github/workflows/gitlab-ci.yml b/.github/workflows/gitlab-ci.yml
new file mode 100644
index 0000000..30abd63
--- /dev/null
+++ b/.github/workflows/gitlab-ci.yml
@@ -0,0 +1,23 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Based on https://github.com/pulp-platform/pulp-actions/tree/main/gitlab-ci#action-usage
+
+# Author: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+
+name: gitlab-ci
+
+on: [ push, pull_request, workflow_dispatch ]
+
+jobs:
+  gitlab-ci:
+    runs-on: ubuntu-latest
+    if: github.repository == 'pulp-platform/axi_riscv_atomics' && (github.event_name != 'pull_request' || github.event.pull_request.head.repo.full_name == github.repository)
+    steps:
+      - name: Check Gitlab CI
+        uses: pulp-platform/pulp-actions/gitlab-ci@v2
+        with:
+          domain: iis-git.ee.ethz.ch
+          repo: github-mirror/axi_riscv_atomics
+          token: ${{ secrets.GITLAB_TOKEN }}
diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml
new file mode 100644
index 0000000..0798445
--- /dev/null
+++ b/.github/workflows/lint.yml
@@ -0,0 +1,22 @@
+name: lint
+on: [ push, pull_request, workflow_dispatch ]
+
+jobs:
+  ################
+  # Verible Lint #
+  ################
+  verilog:
+    name: Verilog Sources
+    # This job runs on Linux (fixed ubuntu version)
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - uses: chipsalliance/verible-linter-action@main
+        with:
+          paths: |
+            ./src
+          exclude_paths: |
+            ./src/deprecated
+          extra_args: "--waiver_files lint/common_cells.style.waiver --rules=-interface-name-style --lint_fatal"
+          github_token: ${{ secrets.GITHUB_TOKEN }}
+          reviewdog_reporter: github-check
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
new file mode 100644
index 0000000..2a721bb
--- /dev/null
+++ b/.gitlab-ci.yml
@@ -0,0 +1,38 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Author: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+
+variables:
+  VSIM: questa-2022.3 vsim -64
+  VLIB: questa-2022.3 vlib
+  VMAP: questa-2022.3 vmap
+  VCOM: questa-2022.3 vcom -64
+  VLOG: questa-2022.3 vlog -64
+  VOPT: questa-2022.3 vopt -64
+
+stages:
+  - test
+
+.test-tpl:
+  stage: test
+  needs:
+  variables:
+    TOPLEVEL: ""
+    PARAM1: ""
+    PARAM2: ""
+  timeout: 10min
+  script:
+    - bender script vsim -t test > compile.tcl
+    - $VSIM -c -quiet -do 'source compile.tcl; quit'
+    - $VSIM -c $TOPLEVEL -do "run -all"
+    - (! grep -n "Error:" transcript)
+
+tests:
+  extends: .test-tpl
+  parallel:
+    matrix:
+      - TOPLEVEL:
+          - axi_riscv_atomics_tb
+          - axi_riscv_lrsc_tb