From c8707071cd1dc75e03679860b2a4035d99a3ee6e Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Thu, 20 Jan 2022 19:51:32 +0100 Subject: [PATCH] Align req and rsp types to #153 --- doc/axi_lite_mailbox.md | 2 +- doc/axi_lite_xbar.md | 2 +- doc/axi_xbar.md | 2 +- include/axi/typedef.svh | 20 ++--- scripts/axi_intercon_gen.py | 4 +- src/axi_atop_filter.sv | 22 +++--- src/axi_burst_splitter.sv | 22 +++--- src/axi_cdc.sv | 70 ++++++++--------- src/axi_cdc_dst.sv | 40 +++++----- src/axi_cdc_src.sv | 40 +++++----- src/axi_cut.sv | 74 +++++++++--------- src/axi_delayer.sv | 34 ++++---- src/axi_demux.sv | 30 ++++---- src/axi_dw_converter.sv | 60 +++++++-------- src/axi_dw_downsizer.sv | 56 +++++++------- src/axi_dw_upsizer.sv | 56 +++++++------- src/axi_err_slv.sv | 18 ++--- src/axi_id_remap.sv | 44 +++++------ src/axi_id_serialize.sv | 116 ++++++++++++++-------------- src/axi_isolate.sv | 26 +++---- src/axi_iw_converter.sv | 60 +++++++-------- src/axi_lite_demux.sv | 90 +++++++++++----------- src/axi_lite_mailbox.sv | 132 +++++++++++++++---------------- src/axi_lite_mux.sv | 52 ++++++------- src/axi_lite_regs.sv | 28 +++---- src/axi_lite_to_apb.sv | 32 ++++---- src/axi_lite_to_axi.sv | 12 +-- src/axi_lite_xbar.sv | 150 ++++++++++++++++++------------------ src/axi_modify_address.sv | 34 ++++---- src/axi_multicut.sv | 90 +++++++++++----------- src/axi_mux.sv | 118 ++++++++++++++-------------- src/axi_serializer.sv | 22 +++--- src/axi_sim_mem.sv | 10 +-- src/axi_to_axi_lite.sv | 64 +++++++-------- src/axi_xbar.sv | 132 +++++++++++++++---------------- test/axi_synth_bench.sv | 50 ++++++------ test/tb_axi_lite_to_apb.sv | 16 ++-- test/tb_axi_sim_mem.sv | 6 +- test/tb_axi_xbar.sv | 12 +-- 39 files changed, 924 insertions(+), 924 deletions(-) diff --git a/doc/axi_lite_mailbox.md b/doc/axi_lite_mailbox.md index 7d5e2de52..ee6f0d4e6 100644 --- a/doc/axi_lite_mailbox.md +++ b/doc/axi_lite_mailbox.md @@ -16,7 +16,7 @@ This table describes the parameters of the module. | `AxiAddrWidth` | `int unsigned` | The AXI4-Lite address width on the AW and AR channels | | `AxiDataWidth` | `int unsigned` | The AXI4-Lite data width on the W and R channels | | `req_lite_t` | `type` | In accordance with the `AXI_LITE_TYPEDEF_REQ_T` macro | -| `resp_lite_t` | `type` | In accordance with the `AXI_LITE_TYPEDEF_RESP_T` macro | +| `rsp_lite_t` | `type` | In accordance with the `AXI_LITE_TYPEDEF_RSP_T` macro | ## Module Ports diff --git a/doc/axi_lite_xbar.md b/doc/axi_lite_xbar.md index 047b3966d..98d3ad0ec 100644 --- a/doc/axi_lite_xbar.md +++ b/doc/axi_lite_xbar.md @@ -40,7 +40,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg | `AxiDataWidth` | `int unsigned` | The AXI4-Lite data width. | | `NoAddrRules` | `int unsigned` | The number of address map rules. | -The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_resp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses. +The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_rsp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses. ### Pipelining and Latency diff --git a/doc/axi_xbar.md b/doc/axi_xbar.md index ca0c12108..535bceaaa 100644 --- a/doc/axi_xbar.md +++ b/doc/axi_xbar.md @@ -54,7 +54,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg | `AxiDataWidth` | `int unsigned` | The AXI data width. | | `NoAddrRules` | `int unsigned` | The number of address map rules. | -The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_resp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses. +The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_rsp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses. ### Pipelining and Latency diff --git a/include/axi/typedef.svh b/include/axi/typedef.svh index a2a860e50..f97539759 100644 --- a/include/axi/typedef.svh +++ b/include/axi/typedef.svh @@ -29,7 +29,7 @@ // `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_user_t) // `AXI_TYPEDEF_R_CHAN_T(axi_r_t, axi_data_t, axi_id_t, axi_user_t) // `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_t, axi_w_t, axi_ar_t) -// `AXI_TYPEDEF_RESP_T(axi_resp_t, axi_b_t, axi_r_t) +// `AXI_TYPEDEF_RSP_T(axi_rsp_t, axi_b_t, axi_r_t) `define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) \ typedef struct packed { \ id_t id; \ @@ -91,7 +91,7 @@ logic ar_valid; \ logic r_ready; \ } req_t; -`define AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) \ +`define AXI_TYPEDEF_RSP_T(rsp_t, b_chan_t, r_chan_t) \ typedef struct packed { \ logic aw_ready; \ logic ar_ready; \ @@ -100,7 +100,7 @@ b_chan_t b; \ logic r_valid; \ r_chan_t r; \ - } resp_t; + } rsp_t; //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -113,7 +113,7 @@ // Usage Example: // `AXI_TYPEDEF_ALL(axi, addr_t, id_t, data_t, strb_t, user_t) // -// This defines `axi_req_t` and `axi_resp_t` request/response structs as well as `axi_aw_chan_t`, +// This defines `axi_req_t` and `axi_rsp_t` request/response structs as well as `axi_aw_chan_t`, // `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs. `define AXI_TYPEDEF_ALL(__name, __addr_t, __id_t, __data_t, __strb_t, __user_t) \ `AXI_TYPEDEF_AW_CHAN_T(__name``_aw_chan_t, __addr_t, __id_t, __user_t) \ @@ -122,7 +122,7 @@ `AXI_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t, __id_t, __user_t) \ `AXI_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t, __id_t, __user_t) \ `AXI_TYPEDEF_REQ_T(__name``_req_t, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \ - `AXI_TYPEDEF_RESP_T(__name``_resp_t, __name``_b_chan_t, __name``_r_chan_t) + `AXI_TYPEDEF_RSP_T(__name``_rsp_t, __name``_b_chan_t, __name``_r_chan_t) //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -136,7 +136,7 @@ // `AXI_LITE_TYPEDEF_AR_CHAN_T(axi_lite_ar_t, axi_lite_addr_t) // `AXI_LITE_TYPEDEF_R_CHAN_T(axi_lite_r_t, axi_lite_data_t) // `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, axi_lite_aw_t, axi_lite_w_t, axi_lite_ar_t) -// `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, axi_lite_b_t, axi_lite_r_t) +// `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, axi_lite_b_t, axi_lite_r_t) `define AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t) \ typedef struct packed { \ addr_t addr; \ @@ -172,7 +172,7 @@ logic ar_valid; \ logic r_ready; \ } req_lite_t; -`define AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t) \ +`define AXI_LITE_TYPEDEF_RSP_T(rsp_lite_t, b_chan_lite_t, r_chan_lite_t) \ typedef struct packed { \ logic aw_ready; \ logic w_ready; \ @@ -181,7 +181,7 @@ logic ar_ready; \ r_chan_lite_t r; \ logic r_valid; \ - } resp_lite_t; + } rsp_lite_t; //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -194,7 +194,7 @@ // Usage Example: // `AXI_LITE_TYPEDEF_ALL(axi_lite, addr_t, data_t, strb_t) // -// This defines `axi_lite_req_t` and `axi_lite_resp_t` request/response structs as well as +// This defines `axi_lite_req_t` and `axi_lite_rsp_t` request/response structs as well as // `axi_lite_aw_chan_t`, `axi_lite_w_chan_t`, `axi_lite_b_chan_t`, `axi_lite_ar_chan_t`, and // `axi_lite_r_chan_t` channel structs. `define AXI_LITE_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t) \ @@ -204,7 +204,7 @@ `AXI_LITE_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t) \ `AXI_LITE_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t) \ `AXI_LITE_TYPEDEF_REQ_T(__name``_req_t, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \ - `AXI_LITE_TYPEDEF_RESP_T(__name``_resp_t, __name``_b_chan_t, __name``_r_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(__name``_rsp_t, __name``_b_chan_t, __name``_r_chan_t) //////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/scripts/axi_intercon_gen.py b/scripts/axi_intercon_gen.py index af5b3a209..49666c2e3 100644 --- a/scripts/axi_intercon_gen.py +++ b/scripts/axi_intercon_gen.py @@ -378,9 +378,9 @@ def write(self): `AXI_TYPEDEF_R_CHAN_T(r_chan_slv_t, data_t, id_slv_t, user_t) `AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t) - `AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_mst_t, r_chan_mst_t) + `AXI_TYPEDEF_RSP_T(slv_rsp_t, b_chan_mst_t, r_chan_mst_t) `AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t) - `AXI_TYPEDEF_RESP_T(mst_resp_t, b_chan_slv_t, r_chan_slv_t) + `AXI_TYPEDEF_RSP_T(mst_rsp_t, b_chan_slv_t, r_chan_slv_t) """ diff --git a/src/axi_atop_filter.sv b/src/axi_atop_filter.sv index ec28a8ebd..12a4dee86 100644 --- a/src/axi_atop_filter.sv +++ b/src/axi_atop_filter.sv @@ -40,22 +40,22 @@ module axi_atop_filter #( /// Maximum number of in-flight AXI write transactions parameter int unsigned AxiMaxWriteTxns = 0, /// AXI request type - parameter type axi_req_t = logic, + parameter type axi_req_t = logic, /// AXI response type - parameter type axi_resp_t = logic + parameter type axi_rsp_t = logic ) ( /// Rising-edge clock of both ports - input logic clk_i, + input logic clk_i, /// Asynchronous reset, active low - input logic rst_ni, + input logic rst_ni, /// Slave port request - input axi_req_t slv_req_i, + input axi_req_t slv_req_i, /// Slave port response - output axi_resp_t slv_resp_o, + output axi_rsp_t slv_resp_o, /// Master port request - output axi_req_t mst_req_o, + output axi_req_t mst_req_o, /// Master port response - input axi_resp_t mst_resp_i + input axi_rsp_t mst_resp_i ); // Minimum counter width is 2 to detect underflows. @@ -406,10 +406,10 @@ module axi_atop_filter_intf #( `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) axi_req_t slv_req, mst_req; - axi_resp_t slv_resp, mst_resp; + axi_rsp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -423,7 +423,7 @@ module axi_atop_filter_intf #( .AxiMaxWriteTxns ( AXI_MAX_WRITE_TXNS ), // AXI request & response type .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) + .axi_rsp_t ( axi_rsp_t ) ) i_axi_atop_filter ( .clk_i, .rst_ni, diff --git a/src/axi_burst_splitter.sv b/src/axi_burst_splitter.sv index ad086ed99..482f77124 100644 --- a/src/axi_burst_splitter.sv +++ b/src/axi_burst_splitter.sv @@ -36,18 +36,18 @@ module axi_burst_splitter #( parameter int unsigned IdWidth = 32'd0, parameter int unsigned UserWidth = 32'd0, parameter type axi_req_t = logic, - parameter type axi_resp_t = logic + parameter type axi_rsp_t = logic ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // Input / Slave Port - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_rsp_t slv_resp_o, // Output / Master Port - output axi_req_t mst_req_o, - input axi_resp_t mst_resp_i + output axi_req_t mst_req_o, + input axi_rsp_t mst_resp_i ); typedef logic [AddrWidth-1:0] addr_t; @@ -62,8 +62,8 @@ module axi_burst_splitter #( `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) // Demultiplex between supported and unsupported transactions. - axi_req_t act_req, unsupported_req; - axi_resp_t act_resp, unsupported_resp; + axi_req_t act_req, unsupported_req; + axi_rsp_t act_resp, unsupported_resp; logic sel_aw_unsupported, sel_ar_unsupported; localparam int unsigned MaxTxns = (MaxReadTxns > MaxWriteTxns) ? MaxReadTxns : MaxWriteTxns; axi_demux #( @@ -74,7 +74,7 @@ module axi_burst_splitter #( .ar_chan_t ( ar_chan_t ), .r_chan_t ( r_chan_t ), .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), + .axi_rsp_t ( axi_rsp_t ), .NoMstPorts ( 2 ), .MaxTrans ( MaxTxns ), .AxiLookBits ( IdWidth ), @@ -120,7 +120,7 @@ module axi_burst_splitter #( axi_err_slv #( .AxiIdWidth ( IdWidth ), .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), + .axi_rsp_t ( axi_rsp_t ), .Resp ( axi_pkg::RESP_SLVERR ), .ATOPs ( 1'b0 ), // The burst splitter does not support ATOPs. .MaxTrans ( 1 ) // Splitting bursts implies a low-performance bus. diff --git a/src/axi_cdc.sv b/src/axi_cdc.sv index 1e422ed72..94da26c98 100644 --- a/src/axi_cdc.sv +++ b/src/axi_cdc.sv @@ -24,26 +24,26 @@ /// ports are in separate clock domains. IMPORTANT: For each AXI channel, you MUST properly /// constrain three paths through the FIFO; see the header of `cdc_fifo_gray` for instructions. module axi_cdc #( - parameter type aw_chan_t = logic, // AW Channel Type - parameter type w_chan_t = logic, // W Channel Type - parameter type b_chan_t = logic, // B Channel Type - parameter type ar_chan_t = logic, // AR Channel Type - parameter type r_chan_t = logic, // R Channel Type - parameter type axi_req_t = logic, // encapsulates request channels - parameter type axi_resp_t = logic, // encapsulates request channels + parameter type aw_chan_t = logic, // AW Channel Type + parameter type w_chan_t = logic, // W Channel Type + parameter type b_chan_t = logic, // B Channel Type + parameter type ar_chan_t = logic, // AR Channel Type + parameter type r_chan_t = logic, // R Channel Type + parameter type axi_req_t = logic, // encapsulates request channels + parameter type axi_rsp_t = logic, // encapsulates request channels /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. parameter int unsigned LogDepth = 1 ) ( // slave side - clocked by `src_clk_i` - input logic src_clk_i, - input logic src_rst_ni, - input axi_req_t src_req_i, - output axi_resp_t src_resp_o, + input logic src_clk_i, + input logic src_rst_ni, + input axi_req_t src_req_i, + output axi_rsp_t src_resp_o, // master side - clocked by `dst_clk_i` - input logic dst_clk_i, - input logic dst_rst_ni, - output axi_req_t dst_req_o, - input axi_resp_t dst_resp_i + input logic dst_clk_i, + input logic dst_rst_ni, + output axi_req_t dst_req_o, + input axi_rsp_t dst_resp_i ); aw_chan_t [2**LogDepth-1:0] async_data_aw_data; @@ -64,7 +64,7 @@ module axi_cdc #( .ar_chan_t ( ar_chan_t ), .r_chan_t ( r_chan_t ), .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), + .axi_rsp_t ( axi_rsp_t ), .LogDepth ( LogDepth ) ) i_axi_cdc_src ( .src_clk_i, @@ -95,7 +95,7 @@ module axi_cdc #( .ar_chan_t ( ar_chan_t ), .r_chan_t ( r_chan_t ), .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), + .axi_rsp_t ( axi_rsp_t ), .LogDepth ( LogDepth ) ) i_axi_cdc_dst ( .dst_clk_i, @@ -153,11 +153,11 @@ module axi_cdc_intf #( `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - req_t src_req, dst_req; - resp_t src_resp, dst_resp; + axi_req_t src_req, dst_req; + axi_rsp_t src_resp, dst_resp; `AXI_ASSIGN_TO_REQ(src_req, src) `AXI_ASSIGN_FROM_RESP(src, src_resp) @@ -171,8 +171,8 @@ module axi_cdc_intf #( .b_chan_t ( b_chan_t ), .ar_chan_t ( ar_chan_t ), .r_chan_t ( r_chan_t ), - .axi_req_t ( req_t ), - .axi_resp_t ( resp_t ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), .LogDepth ( LOG_DEPTH ) ) i_axi_cdc ( .src_clk_i, @@ -211,11 +211,11 @@ module axi_lite_cdc_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - req_t src_req, dst_req; - resp_t src_resp, dst_resp; + axi_lite_req_t src_req, dst_req; + axi_lite_rsp_t src_resp, dst_resp; `AXI_LITE_ASSIGN_TO_REQ(src_req, src) `AXI_LITE_ASSIGN_FROM_RESP(src, src_resp) @@ -224,14 +224,14 @@ module axi_lite_cdc_intf #( `AXI_LITE_ASSIGN_TO_RESP(dst_resp, dst) axi_cdc #( - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_req_t ( req_t ), - .axi_resp_t ( resp_t ), - .LogDepth ( LOG_DEPTH ) + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_lite_req_t ), + .axi_rsp_t ( axi_lite_rsp_t ), + .LogDepth ( LOG_DEPTH ) ) i_axi_cdc ( .src_clk_i, .src_rst_ni, diff --git a/src/axi_cdc_dst.sv b/src/axi_cdc_dst.sv index d365156ce..15b5329e3 100644 --- a/src/axi_cdc_dst.sv +++ b/src/axi_cdc_dst.sv @@ -32,7 +32,7 @@ module axi_cdc_dst #( parameter type ar_chan_t = logic, parameter type r_chan_t = logic, parameter type axi_req_t = logic, - parameter type axi_resp_t = logic + parameter type axi_rsp_t = logic ) ( // asynchronous slave port input aw_chan_t [2**LogDepth-1:0] async_data_slave_aw_data_i, @@ -54,7 +54,7 @@ module axi_cdc_dst #( input logic dst_clk_i, input logic dst_rst_ni, output axi_req_t dst_req_o, - input axi_resp_t dst_resp_i + input axi_rsp_t dst_resp_i ); cdc_fifo_gray_dst #( @@ -156,11 +156,11 @@ module axi_cdc_dst_intf #( `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - req_t dst_req; - resp_t dst_resp; + axi_req_t dst_req; + axi_rsp_t dst_resp; axi_cdc_dst #( .aw_chan_t ( aw_chan_t ), @@ -168,8 +168,8 @@ module axi_cdc_dst_intf #( .b_chan_t ( b_chan_t ), .ar_chan_t ( ar_chan_t ), .r_chan_t ( r_chan_t ), - .axi_req_t ( req_t ), - .axi_resp_t ( resp_t ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), .LogDepth ( LOG_DEPTH ) ) i_axi_cdc_dst ( .async_data_slave_aw_data_i ( src.aw_data ), @@ -221,21 +221,21 @@ module axi_lite_cdc_dst_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - req_t dst_req; - resp_t dst_resp; + axi_lite_req_t dst_req; + axi_lite_rsp_t dst_resp; axi_cdc_dst #( - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_req_t ( req_t ), - .axi_resp_t ( resp_t ), - .LogDepth ( LOG_DEPTH ) + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_lite_req_t ), + .axi_rsp_t ( axi_lite_rsp_t ), + .LogDepth ( LOG_DEPTH ) ) i_axi_cdc_dst ( .async_data_slave_aw_data_i ( src.aw_data ), .async_data_slave_aw_wptr_i ( src.aw_wptr ), diff --git a/src/axi_cdc_src.sv b/src/axi_cdc_src.sv index 0f93ae82b..be9a2506a 100644 --- a/src/axi_cdc_src.sv +++ b/src/axi_cdc_src.sv @@ -32,13 +32,13 @@ module axi_cdc_src #( parameter type ar_chan_t = logic, parameter type r_chan_t = logic, parameter type axi_req_t = logic, - parameter type axi_resp_t = logic + parameter type axi_rsp_t = logic ) ( // synchronous slave port - clocked by `src_clk_i` input logic src_clk_i, input logic src_rst_ni, input axi_req_t src_req_i, - output axi_resp_t src_resp_o, + output axi_rsp_t src_resp_o, // asynchronous master port output aw_chan_t [2**LogDepth-1:0] async_data_master_aw_data_o, output logic [LogDepth:0] async_data_master_aw_wptr_o, @@ -156,11 +156,11 @@ module axi_cdc_src_intf #( `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - req_t src_req; - resp_t src_resp; + axi_req_t src_req; + axi_rsp_t src_resp; `AXI_ASSIGN_TO_REQ(src_req, src) `AXI_ASSIGN_FROM_RESP(src, src_resp) @@ -171,8 +171,8 @@ module axi_cdc_src_intf #( .b_chan_t ( b_chan_t ), .ar_chan_t ( ar_chan_t ), .r_chan_t ( r_chan_t ), - .axi_req_t ( req_t ), - .axi_resp_t ( resp_t ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), .LogDepth ( LOG_DEPTH ) ) i_axi_cdc_src ( .src_clk_i, @@ -221,24 +221,24 @@ module axi_lite_cdc_src_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - req_t src_req; - resp_t src_resp; + axi_lite_req_t src_req; + axi_lite_rsp_t src_resp; `AXI_LITE_ASSIGN_TO_REQ(src_req, src) `AXI_LITE_ASSIGN_FROM_RESP(src, src_resp) axi_cdc_src #( - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_req_t ( req_t ), - .axi_resp_t ( resp_t ), - .LogDepth ( LOG_DEPTH ) + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_lite_req_t ), + .axi_rsp_t ( axi_lite_rsp_t ), + .LogDepth ( LOG_DEPTH ) ) i_axi_cdc_src ( .src_clk_i, .src_rst_ni, diff --git a/src/axi_cut.sv b/src/axi_cut.sv index 34278ca62..b1a0a0acc 100644 --- a/src/axi_cut.sv +++ b/src/axi_cut.sv @@ -19,25 +19,25 @@ /// Breaks all combinatorial paths between its input and output. module axi_cut #( // bypass enable - parameter bit Bypass = 1'b0, + parameter bit Bypass = 1'b0, // AXI channel structs - parameter type aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type r_chan_t = logic, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, // AXI request & response structs - parameter type axi_req_t = logic, - parameter type axi_resp_t = logic + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // salve port - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_rsp_t slv_resp_o, // master port - output axi_req_t mst_req_o, - input axi_resp_t mst_resp_i + output axi_req_t mst_req_o, + input axi_rsp_t mst_resp_i ); // a spill register for each channel @@ -146,10 +146,10 @@ module axi_cut_intf #( `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_rsp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, in) `AXI_ASSIGN_FROM_RESP(in, slv_resp) @@ -158,14 +158,14 @@ module axi_cut_intf #( `AXI_ASSIGN_TO_RESP(mst_resp, out) axi_cut #( - .Bypass ( BYPASS ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) + .Bypass ( BYPASS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ) ) i_axi_cut ( .clk_i, .rst_ni, @@ -219,11 +219,11 @@ module axi_lite_cut_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_resp_t slv_resp, mst_resp; + axi_lite_req_t slv_req, mst_req; + axi_lite_rsp_t slv_resp, mst_resp; `AXI_LITE_ASSIGN_TO_REQ(slv_req, in) `AXI_LITE_ASSIGN_FROM_RESP(in, slv_resp) @@ -232,14 +232,14 @@ module axi_lite_cut_intf #( `AXI_LITE_ASSIGN_TO_RESP(mst_resp, out) axi_cut #( - .Bypass ( BYPASS ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) + .Bypass ( BYPASS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_lite_req_t ), + .axi_rsp_t ( axi_lite_rsp_t ) ) i_axi_cut ( .clk_i, .rst_ni, diff --git a/src/axi_delayer.sv b/src/axi_delayer.sv index 8d217d14e..08e198793 100644 --- a/src/axi_delayer.sv +++ b/src/axi_delayer.sv @@ -16,28 +16,28 @@ /// Synthesizable module that (randomly) delays AXI channels. module axi_delayer #( // AXI channel types - parameter type aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type r_chan_t = logic, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, // AXI request & response types - parameter type axi_req_t = logic, - parameter type axi_resp_t = logic, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic, // delay parameters parameter bit StallRandomInput = 0, parameter bit StallRandomOutput = 0, parameter int unsigned FixedDelayInput = 1, parameter int unsigned FixedDelayOutput = 1 ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low // slave port - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_rsp_t slv_resp_o, // master port - output axi_req_t mst_req_o, - input axi_resp_t mst_resp_i + output axi_req_t mst_req_o, + input axi_rsp_t mst_resp_i ); // AW stream_delay #( @@ -153,10 +153,10 @@ module axi_delayer_intf #( `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_rsp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -171,7 +171,7 @@ module axi_delayer_intf #( .ar_chan_t ( ar_chan_t ), .r_chan_t ( r_chan_t ), .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), + .axi_rsp_t ( axi_rsp_t ), .StallRandomInput ( STALL_RANDOM_INPUT ), .StallRandomOutput ( STALL_RANDOM_OUTPUT ), .FixedDelayInput ( FIXED_DELAY_INPUT ), diff --git a/src/axi_demux.sv b/src/axi_demux.sv index b0d6b4202..dcf238ec6 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -24,7 +24,7 @@ module axi_demux #( parameter type ar_chan_t = logic, parameter type r_chan_t = logic, parameter type axi_req_t = logic, - parameter type axi_resp_t = logic, + parameter type axi_rsp_t = logic, parameter int unsigned NoMstPorts = 32'd0, parameter int unsigned MaxTrans = 32'd8, parameter int unsigned AxiLookBits = 32'd3, @@ -46,10 +46,10 @@ module axi_demux #( input axi_req_t slv_req_i, input select_t slv_aw_select_i, input select_t slv_ar_select_i, - output axi_resp_t slv_resp_o, + output axi_rsp_t slv_resp_o, // Master Ports output axi_req_t [NoMstPorts-1:0] mst_reqs_o, - input axi_resp_t [NoMstPorts-1:0] mst_resps_i + input axi_rsp_t [NoMstPorts-1:0] mst_resps_i ); localparam int unsigned IdCounterWidth = MaxTrans > 1 ? $clog2(MaxTrans) : 1; @@ -736,12 +736,12 @@ module axi_demux_intf #( `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req; - axi_resp_t slv_resp; - axi_req_t [NO_MST_PORTS-1:0] mst_req; - axi_resp_t [NO_MST_PORTS-1:0] mst_resp; + axi_req_t slv_req; + axi_rsp_t slv_resp; + axi_req_t [NO_MST_PORTS-1:0] mst_req; + axi_rsp_t [NO_MST_PORTS-1:0] mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -753,13 +753,13 @@ module axi_demux_intf #( axi_demux #( .AxiIdWidth ( AXI_ID_WIDTH ), // ID Width - .aw_chan_t ( aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( b_chan_t ), // B Channel Type - .ar_chan_t ( ar_chan_t ), // AR Channel Type - .r_chan_t ( r_chan_t ), // R Channel Type - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), .NoMstPorts ( NO_MST_PORTS ), .MaxTrans ( MAX_TRANS ), .AxiLookBits ( AXI_LOOK_BITS ), diff --git a/src/axi_dw_converter.sv b/src/axi_dw_converter.sv index 7e6f6dad3..03642056b 100644 --- a/src/axi_dw_converter.sv +++ b/src/axi_dw_converter.sv @@ -28,19 +28,19 @@ module axi_dw_converter #( parameter type ar_chan_t = logic, // AR Channel Type parameter type mst_r_chan_t = logic, // R Channel Type for the mst port parameter type slv_r_chan_t = logic, // R Channel Type for the slv port - parameter type axi_mst_req_t = logic, // AXI Request Type for mst ports - parameter type axi_mst_resp_t = logic, // AXI Response Type for mst ports - parameter type axi_slv_req_t = logic, // AXI Request Type for slv ports - parameter type axi_slv_resp_t = logic // AXI Response Type for slv ports + parameter type mst_port_axi_req_t = logic, // AXI Request Type for mst ports + parameter type mst_port_axi_rsp_t = logic, // AXI Response Type for mst ports + parameter type slv_port_axi_req_t = logic, // AXI Request Type for slv ports + parameter type slv_port_axi_rsp_t = logic // AXI Response Type for slv ports ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // Slave interface - input axi_slv_req_t slv_req_i, - output axi_slv_resp_t slv_resp_o, + input slv_port_axi_req_t slv_req_i, + output slv_port_axi_rsp_t slv_resp_o, // Master interface - output axi_mst_req_t mst_req_o, - input axi_mst_resp_t mst_resp_i + output mst_port_axi_req_t mst_req_o, + input mst_port_axi_rsp_t mst_resp_i ); if (AxiMstPortDataWidth == AxiSlvPortDataWidth) begin: gen_no_dw_conversion @@ -62,10 +62,10 @@ module axi_dw_converter #( .ar_chan_t (ar_chan_t ), .mst_r_chan_t (mst_r_chan_t ), .slv_r_chan_t (slv_r_chan_t ), - .axi_mst_req_t (axi_mst_req_t ), - .axi_mst_resp_t (axi_mst_resp_t ), - .axi_slv_req_t (axi_slv_req_t ), - .axi_slv_resp_t (axi_slv_resp_t ) + .mst_port_axi_req_t (mst_port_axi_req_t ), + .mst_port_axi_rsp_t (mst_port_axi_rsp_t ), + .slv_port_axi_req_t (slv_port_axi_req_t ), + .slv_port_axi_rsp_t (slv_port_axi_rsp_t ) ) i_axi_dw_upsizer ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -92,10 +92,10 @@ module axi_dw_converter #( .ar_chan_t (ar_chan_t ), .mst_r_chan_t (mst_r_chan_t ), .slv_r_chan_t (slv_r_chan_t ), - .axi_mst_req_t (axi_mst_req_t ), - .axi_mst_resp_t (axi_mst_resp_t ), - .axi_slv_req_t (axi_slv_req_t ), - .axi_slv_resp_t (axi_slv_resp_t ) + .mst_port_axi_req_t (mst_port_axi_req_t ), + .mst_port_axi_rsp_t (mst_port_axi_rsp_t ), + .slv_port_axi_req_t (slv_port_axi_req_t ), + .slv_port_axi_rsp_t (slv_port_axi_rsp_t ) ) i_axi_dw_downsizer ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -143,15 +143,15 @@ module axi_dw_converter_intf #( `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, mst_data_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, slv_data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_t, mst_w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(mst_resp_t, b_chan_t, mst_r_chan_t) - `AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_t, slv_w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, aw_chan_t, mst_w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, aw_chan_t, slv_w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, b_chan_t, slv_r_chan_t) - slv_req_t slv_req; - slv_resp_t slv_resp; - mst_req_t mst_req; - mst_resp_t mst_resp; + slv_port_axi_req_t slv_req; + slv_port_axi_rsp_t slv_resp; + mst_port_axi_req_t mst_req; + mst_port_axi_rsp_t mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -172,10 +172,10 @@ module axi_dw_converter_intf #( .ar_chan_t ( ar_chan_t ), .mst_r_chan_t ( mst_r_chan_t ), .slv_r_chan_t ( slv_r_chan_t ), - .axi_mst_req_t ( mst_req_t ), - .axi_mst_resp_t ( mst_resp_t ), - .axi_slv_req_t ( slv_req_t ), - .axi_slv_resp_t ( slv_resp_t ) + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ) ) i_axi_dw_converter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/src/axi_dw_downsizer.sv b/src/axi_dw_downsizer.sv index 6e467552e..f7e01a8c6 100644 --- a/src/axi_dw_downsizer.sv +++ b/src/axi_dw_downsizer.sv @@ -32,19 +32,19 @@ module axi_dw_downsizer #( parameter type ar_chan_t = logic, // AR Channel Type parameter type mst_r_chan_t = logic, // R Channel Type for mst port parameter type slv_r_chan_t = logic, // R Channel Type for slv port - parameter type axi_mst_req_t = logic, // AXI Request Type for mst ports - parameter type axi_mst_resp_t = logic, // AXI Response Type for mst ports - parameter type axi_slv_req_t = logic, // AXI Request Type for slv ports - parameter type axi_slv_resp_t = logic // AXI Response Type for slv ports + parameter type mst_port_axi_req_t = logic, // AXI Request Type for mst ports + parameter type mst_port_axi_rsp_t = logic, // AXI Response Type for mst ports + parameter type slv_port_axi_req_t = logic, // AXI Request Type for slv ports + parameter type slv_port_axi_rsp_t = logic // AXI Response Type for slv ports ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // Slave interface - input axi_slv_req_t slv_req_i, - output axi_slv_resp_t slv_resp_o, + input slv_port_axi_req_t slv_req_i, + output slv_port_axi_rsp_t slv_resp_o, // Master interface - output axi_mst_req_t mst_req_o, - input axi_mst_resp_t mst_resp_i + output mst_port_axi_req_t mst_req_o, + input mst_port_axi_rsp_t mst_resp_i ); /***************** @@ -83,8 +83,8 @@ module axi_dw_downsizer #( typedef logic [$clog2(AxiSlvPortStrbWidth/AxiMstPortStrbWidth) + 7:0] burst_len_t; // Internal AXI bus - axi_mst_req_t mst_req; - axi_mst_resp_t mst_resp; + mst_port_axi_req_t mst_req; + mst_port_axi_rsp_t mst_resp; /************** * ARBITERS * @@ -182,14 +182,14 @@ module axi_dw_downsizer #( * ERROR SLAVE * *****************/ - axi_mst_req_t axi_err_req; - axi_mst_resp_t axi_err_resp; + mst_port_axi_req_t axi_err_req; + mst_port_axi_rsp_t axi_err_resp; axi_err_slv #( .AxiIdWidth(AxiIdWidth ), .Resp (axi_pkg::RESP_SLVERR), - .axi_req_t (axi_mst_req_t ), - .axi_resp_t(axi_mst_resp_t ) + .axi_req_t (mst_port_axi_req_t ), + .axi_rsp_t (mst_port_axi_rsp_t ) ) i_axi_err_slv ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -209,18 +209,18 @@ module axi_dw_downsizer #( logic mst_req_aw_err; axi_demux #( - .AxiIdWidth (AxiIdWidth ), - .AxiLookBits(AxiIdWidth ), - .aw_chan_t (aw_chan_t ), - .w_chan_t (mst_w_chan_t ), - .b_chan_t (b_chan_t ), - .ar_chan_t (ar_chan_t ), - .r_chan_t (mst_r_chan_t ), - .axi_req_t (axi_mst_req_t ), - .axi_resp_t (axi_mst_resp_t), - .NoMstPorts (2 ), - .MaxTrans (AxiMaxReads ), - .SpillAw (1'b1 ) // Required to break dependency between AW and W channels + .AxiIdWidth (AxiIdWidth ), + .AxiLookBits(AxiIdWidth ), + .aw_chan_t (aw_chan_t ), + .w_chan_t (mst_w_chan_t ), + .b_chan_t (b_chan_t ), + .ar_chan_t (ar_chan_t ), + .r_chan_t (mst_r_chan_t ), + .axi_req_t (mst_port_axi_req_t), + .axi_rsp_t (mst_port_axi_rsp_t), + .NoMstPorts (2 ), + .MaxTrans (AxiMaxReads ), + .SpillAw (1'b1 ) // Required to break dependency between AW and W channels ) i_axi_demux ( .clk_i (clk_i ), .rst_ni (rst_ni ), diff --git a/src/axi_dw_upsizer.sv b/src/axi_dw_upsizer.sv index d7bb021f3..9fbace8db 100644 --- a/src/axi_dw_upsizer.sv +++ b/src/axi_dw_upsizer.sv @@ -31,19 +31,19 @@ module axi_dw_upsizer #( parameter type ar_chan_t = logic, // AR Channel Type parameter type mst_r_chan_t = logic, // R Channel Type for mst port parameter type slv_r_chan_t = logic, // R Channel Type for slv port - parameter type axi_mst_req_t = logic, // AXI Request Type for mst ports - parameter type axi_mst_resp_t = logic, // AXI Response Type for mst ports - parameter type axi_slv_req_t = logic, // AXI Request Type for slv ports - parameter type axi_slv_resp_t = logic // AXI Response Type for slv ports + parameter type mst_port_axi_req_t = logic, // AXI Request Type for mst ports + parameter type mst_port_axi_rsp_t = logic, // AXI Response Type for mst ports + parameter type slv_port_axi_req_t = logic, // AXI Request Type for slv ports + parameter type slv_port_axi_rsp_t = logic // AXI Response Type for slv ports ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // Slave interface - input axi_slv_req_t slv_req_i, - output axi_slv_resp_t slv_resp_o, + input slv_port_axi_req_t slv_req_i, + output slv_port_axi_rsp_t slv_resp_o, // Master interface - output axi_mst_req_t mst_req_o, - input axi_mst_resp_t mst_resp_i + output mst_port_axi_req_t mst_req_o, + input mst_port_axi_rsp_t mst_resp_i ); /***************** @@ -80,8 +80,8 @@ module axi_dw_upsizer #( typedef logic [$clog2(AxiMstPortStrbWidth/AxiSlvPortStrbWidth) + 7:0] burst_len_t; // Internal AXI bus - axi_mst_req_t mst_req; - axi_mst_resp_t mst_resp; + mst_port_axi_req_t mst_req; + mst_port_axi_rsp_t mst_resp; /************** * ARBITERS * @@ -179,14 +179,14 @@ module axi_dw_upsizer #( * ERROR SLAVE * *****************/ - axi_mst_req_t axi_err_req; - axi_mst_resp_t axi_err_resp; + mst_port_axi_req_t axi_err_req; + mst_port_axi_rsp_t axi_err_resp; axi_err_slv #( .AxiIdWidth(AxiIdWidth ), .Resp (axi_pkg::RESP_SLVERR), - .axi_req_t (axi_mst_req_t ), - .axi_resp_t(axi_mst_resp_t ) + .axi_req_t (mst_port_axi_req_t ), + .axi_rsp_t (mst_port_axi_rsp_t ) ) i_axi_err_slv ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -206,18 +206,18 @@ module axi_dw_upsizer #( logic mst_req_aw_err; axi_demux #( - .AxiIdWidth (AxiIdWidth ), - .AxiLookBits(AxiIdWidth ), - .aw_chan_t (aw_chan_t ), - .w_chan_t (mst_w_chan_t ), - .b_chan_t (b_chan_t ), - .ar_chan_t (ar_chan_t ), - .r_chan_t (mst_r_chan_t ), - .axi_req_t (axi_mst_req_t ), - .axi_resp_t (axi_mst_resp_t), - .NoMstPorts (2 ), - .MaxTrans (AxiMaxReads ), - .SpillAw (1'b1 ) // Required to break dependency between AW and W channels + .AxiIdWidth (AxiIdWidth ), + .AxiLookBits(AxiIdWidth ), + .aw_chan_t (aw_chan_t ), + .w_chan_t (mst_w_chan_t ), + .b_chan_t (b_chan_t ), + .ar_chan_t (ar_chan_t ), + .r_chan_t (mst_r_chan_t ), + .axi_req_t (mst_port_axi_req_t), + .axi_rsp_t (mst_port_axi_rsp_t), + .NoMstPorts (2 ), + .MaxTrans (AxiMaxReads ), + .SpillAw (1'b1 ) // Required to break dependency between AW and W channels ) i_axi_demux ( .clk_i (clk_i ), .rst_ni (rst_ni ), diff --git a/src/axi_err_slv.sv b/src/axi_err_slv.sv index e7719c429..8b9e5799d 100644 --- a/src/axi_err_slv.sv +++ b/src/axi_err_slv.sv @@ -19,19 +19,19 @@ module axi_err_slv #( parameter int unsigned AxiIdWidth = 0, // AXI ID Width parameter type axi_req_t = logic, // AXI 4 request struct, with atop field - parameter type axi_resp_t = logic, // AXI 4 response struct + parameter type axi_rsp_t = logic, // AXI 4 response struct parameter axi_pkg::resp_t Resp = axi_pkg::RESP_DECERR, // Error generated by this slave. parameter int unsigned RespWidth = 32'd64, // Data response width, gets zero extended or truncated to r.data. parameter logic [RespWidth-1:0] RespData = 64'hCA11AB1EBADCAB1E, // Hexvalue for data return value parameter bit ATOPs = 1'b1, // Activate support for ATOPs. Set to 1 if this slave could ever get an atomic AXI transaction. parameter int unsigned MaxTrans = 1 // Maximum # of accepted transactions before stalling ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable // slave port - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o + input axi_req_t slv_req_i, + output axi_rsp_t slv_resp_o ); typedef logic [AxiIdWidth-1:0] id_t; typedef struct packed { @@ -39,15 +39,15 @@ module axi_err_slv #( axi_pkg::len_t len; } r_data_t; - axi_req_t err_req; - axi_resp_t err_resp; + axi_req_t err_req; + axi_rsp_t err_resp; if (ATOPs) begin axi_atop_filter #( .AxiIdWidth ( AxiIdWidth ), .AxiMaxWriteTxns ( MaxTrans ), .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) + .axi_rsp_t ( axi_rsp_t ) ) i_atop_filter ( .clk_i, .rst_ni, diff --git a/src/axi_id_remap.sv b/src/axi_id_remap.sv index 44da60878..edd44c18a 100644 --- a/src/axi_id_remap.sv +++ b/src/axi_id_remap.sv @@ -57,32 +57,32 @@ module axi_id_remap #( /// Request struct type of the AXI4+ATOP slave port. /// /// The width of all IDs in this struct must match `AxiSlvPortIdWidth`. - parameter type slv_req_t = logic, + parameter type slv_port_axi_req_t = logic, /// Response struct type of the AXI4+ATOP slave port. /// /// The width of all IDs in this struct must match `AxiSlvPortIdWidth`. - parameter type slv_resp_t = logic, + parameter type slv_port_axi_rsp_t = logic, /// Request struct type of the AXI4+ATOP master port /// /// The width of all IDs in this struct must match `AxiMstPortIdWidth`. - parameter type mst_req_t = logic, + parameter type mst_port_axi_req_t = logic, /// Response struct type of the AXI4+ATOP master port /// /// The width of all IDs in this struct must match `AxiMstPortIdWidth`. - parameter type mst_resp_t = logic + parameter type mst_port_axi_rsp_t = logic ) ( /// Rising-edge clock of all ports - input logic clk_i, + input logic clk_i, /// Asynchronous reset, active low - input logic rst_ni, + input logic rst_ni, /// Slave port request - input slv_req_t slv_req_i, + input slv_port_axi_req_t slv_req_i, /// Slave port response - output slv_resp_t slv_resp_o, + output slv_port_axi_rsp_t slv_resp_o, /// Master port request - output mst_req_t mst_req_o, + output mst_port_axi_req_t mst_req_o, /// Master port response - input mst_resp_t mst_resp_i + input mst_port_axi_rsp_t mst_resp_i ); // Feed all signals that are not ID or flow control of AW and AR through. @@ -602,21 +602,21 @@ module axi_id_remap_intf #( `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_user_t) `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_user_t) `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_chan_t, slv_r_chan_t) `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, axi_addr_t, mst_id_t, axi_user_t) `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, axi_user_t) `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, axi_addr_t, mst_id_t, axi_user_t) `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, axi_data_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, mst_w_chan_t, mst_ar_chan_t) - `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_chan_t, mst_w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_chan_t, mst_r_chan_t) - slv_req_t slv_req; - slv_resp_t slv_resp; - mst_req_t mst_req; - mst_resp_t mst_resp; + slv_port_axi_req_t slv_req; + slv_port_axi_rsp_t slv_resp; + mst_port_axi_req_t mst_req; + mst_port_axi_rsp_t mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -628,10 +628,10 @@ module axi_id_remap_intf #( .AxiSlvPortMaxUniqIds ( AXI_SLV_PORT_MAX_UNIQ_IDS ), .AxiMaxTxnsPerId ( AXI_MAX_TXNS_PER_ID ), .AxiMstPortIdWidth ( AXI_MST_PORT_ID_WIDTH ), - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ) + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ) ) i_axi_id_remap ( .clk_i, .rst_ni, diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv index 4e81a9017..c5b4d49c0 100644 --- a/src/axi_id_serialize.sv +++ b/src/axi_id_serialize.sv @@ -48,26 +48,26 @@ module axi_id_serialize #( /// User width of both AXI4+ATOP ports parameter int unsigned AxiUserWidth = 32'd0, /// Request struct type of the AXI4+ATOP slave port - parameter type slv_req_t = logic, + parameter type slv_port_axi_req_t = logic, /// Response struct type of the AXI4+ATOP slave port - parameter type slv_resp_t = logic, + parameter type slv_port_axi_rsp_t = logic, /// Request struct type of the AXI4+ATOP master port - parameter type mst_req_t = logic, + parameter type mst_port_axi_req_t = logic, /// Response struct type of the AXI4+ATOP master port - parameter type mst_resp_t = logic + parameter type mst_port_axi_rsp_t = logic ) ( /// Rising-edge clock of both ports - input logic clk_i, + input logic clk_i, /// Asynchronous reset, active low - input logic rst_ni, + input logic rst_ni, /// Slave port request - input slv_req_t slv_req_i, + input slv_port_axi_req_t slv_req_i, /// Slave port response - output slv_resp_t slv_resp_o, + output slv_port_axi_rsp_t slv_resp_o, /// Master port request - output mst_req_t mst_req_o, + output mst_port_axi_req_t mst_req_o, /// Master port response - input mst_resp_t mst_resp_i + input mst_port_axi_rsp_t mst_resp_i ); /// Number of bits of the slave port ID that determine the mapping to the master port ID @@ -118,7 +118,7 @@ module axi_id_serialize #( /// AXI Requests from serializer `AXI_TYPEDEF_REQ_T(ser_req_t, ser_aw_t, w_t, ser_ar_t) /// AXI responses to serializer - `AXI_TYPEDEF_RESP_T(ser_resp_t, ser_b_t, ser_r_t) + `AXI_TYPEDEF_RSP_T(ser_rsp_t, ser_b_t, ser_r_t) /// AW channel after the multiplexer `AXI_TYPEDEF_AW_CHAN_T(mux_aw_t, addr_t, mux_id_t, user_t) @@ -131,7 +131,7 @@ module axi_id_serialize #( /// AXI requests from the multiplexer `AXI_TYPEDEF_REQ_T(mux_req_t, mux_aw_t, w_t, mux_ar_t) /// AXI responses to the multiplexer - `AXI_TYPEDEF_RESP_T(mux_resp_t, mux_b_t, mux_r_t) + `AXI_TYPEDEF_RSP_T(mux_rsp_t, mux_b_t, mux_r_t) /// AW channel at master port `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, user_t) @@ -146,8 +146,8 @@ module axi_id_serialize #( assign slv_aw_select = select_t'(slv_req_i.aw.id % AxiMstPortMaxUniqIds); // TODO: customizable base assign slv_ar_select = select_t'(slv_req_i.ar.id % AxiMstPortMaxUniqIds); - slv_req_t [AxiMstPortMaxUniqIds-1:0] to_serializer_reqs; - slv_resp_t [AxiMstPortMaxUniqIds-1:0] to_serializer_resps; + slv_port_axi_req_t [AxiMstPortMaxUniqIds-1:0] to_serializer_reqs; + slv_port_axi_rsp_t [AxiMstPortMaxUniqIds-1:0] to_serializer_resps; axi_demux #( .AxiIdWidth ( AxiSlvPortIdWidth ), @@ -156,8 +156,8 @@ module axi_id_serialize #( .b_chan_t ( slv_b_t ), .ar_chan_t ( slv_ar_t ), .r_chan_t ( slv_r_t ), - .axi_req_t ( slv_req_t ), - .axi_resp_t ( slv_resp_t ), + .axi_req_t ( slv_port_axi_req_t ), + .axi_rsp_t ( slv_port_axi_rsp_t ), .NoMstPorts ( AxiMstPortMaxUniqIds ), .MaxTrans ( AxiSlvPortMaxTxns ), .AxiLookBits ( AxiSlvPortIdWidth ), @@ -179,18 +179,18 @@ module axi_id_serialize #( .mst_resps_i ( to_serializer_resps ) ); - slv_req_t [AxiMstPortMaxUniqIds-1:0] tmp_serializer_reqs; - slv_resp_t [AxiMstPortMaxUniqIds-1:0] tmp_serializer_resps; - ser_req_t [AxiMstPortMaxUniqIds-1:0] from_serializer_reqs; - ser_resp_t [AxiMstPortMaxUniqIds-1:0] from_serializer_resps; + slv_port_axi_req_t [AxiMstPortMaxUniqIds-1:0] tmp_serializer_reqs; + slv_port_axi_rsp_t [AxiMstPortMaxUniqIds-1:0] tmp_serializer_resps; + ser_req_t [AxiMstPortMaxUniqIds-1:0] from_serializer_reqs; + ser_rsp_t [AxiMstPortMaxUniqIds-1:0] from_serializer_resps; for (genvar i = 0; i < AxiMstPortMaxUniqIds; i++) begin : gen_serializers axi_serializer #( .MaxReadTxns ( AxiMstPortMaxTxnsPerId ), .MaxWriteTxns ( AxiMstPortMaxTxnsPerId ), .AxiIdWidth ( AxiSlvPortIdWidth ), - .axi_req_t ( slv_req_t ), - .axi_resp_t ( slv_resp_t ) + .axi_req_t ( slv_port_axi_req_t ), + .axi_rsp_t ( slv_port_axi_rsp_t ) ) i_axi_serializer ( .clk_i, .rst_ni, @@ -211,32 +211,32 @@ module axi_id_serialize #( end end - mux_req_t axi_mux_req; - mux_resp_t axi_mux_resp; + mux_req_t axi_mux_req; + mux_rsp_t axi_mux_resp; axi_mux #( - .SlvAxiIDWidth ( 32'd1 ), - .slv_aw_chan_t ( ser_aw_t ), - .mst_aw_chan_t ( mux_aw_t ), - .w_chan_t ( w_t ), - .slv_b_chan_t ( ser_b_t ), - .mst_b_chan_t ( mux_b_t ), - .slv_ar_chan_t ( ser_ar_t ), - .mst_ar_chan_t ( mux_ar_t ), - .slv_r_chan_t ( ser_r_t ), - .mst_r_chan_t ( mux_r_t ), - .slv_req_t ( ser_req_t ), - .slv_resp_t ( ser_resp_t ), - .mst_req_t ( mux_req_t ), - .mst_resp_t ( mux_resp_t ), - .NoSlvPorts ( AxiMstPortMaxUniqIds ), - .MaxWTrans ( AxiMstPortMaxTxnsPerId ), - .FallThrough ( 1'b0 ), - .SpillAw ( 1'b1 ), - .SpillW ( 1'b0 ), - .SpillB ( 1'b0 ), - .SpillAr ( 1'b1 ), - .SpillR ( 1'b0 ) + .SlvAxiIDWidth ( 32'd1 ), + .slv_aw_chan_t ( ser_aw_t ), + .mst_aw_chan_t ( mux_aw_t ), + .w_chan_t ( w_t ), + .slv_b_chan_t ( ser_b_t ), + .mst_b_chan_t ( mux_b_t ), + .slv_ar_chan_t ( ser_ar_t ), + .mst_ar_chan_t ( mux_ar_t ), + .slv_r_chan_t ( ser_r_t ), + .mst_r_chan_t ( mux_r_t ), + .slv_port_axi_req_t ( ser_req_t ), + .slv_port_axi_rsp_t ( ser_rsp_t ), + .mst_port_axi_req_t ( mux_req_t ), + .mst_port_axi_rsp_t ( mux_rsp_t ), + .NoSlvPorts ( AxiMstPortMaxUniqIds ), + .MaxWTrans ( AxiMstPortMaxTxnsPerId ), + .FallThrough ( 1'b0 ), + .SpillAw ( 1'b1 ), + .SpillW ( 1'b0 ), + .SpillB ( 1'b0 ), + .SpillAr ( 1'b1 ), + .SpillR ( 1'b0 ) ) i_axi_mux ( .clk_i, .rst_ni, @@ -365,20 +365,20 @@ module axi_id_serialize_intf #( `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, user_t) - `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_t, w_t, slv_ar_t) - `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_t, slv_r_t) + `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_t, w_t, slv_ar_t) + `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_t, slv_r_t) `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, user_t) `AXI_TYPEDEF_B_CHAN_T(mst_b_t, mst_id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(mst_ar_t, addr_t, mst_id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, user_t) - `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_t, w_t, mst_ar_t) - `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_t, mst_r_t) + `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_t, w_t, mst_ar_t) + `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_t, mst_r_t) - slv_req_t slv_req; - slv_resp_t slv_resp; - mst_req_t mst_req; - mst_resp_t mst_resp; + slv_port_axi_req_t slv_req; + slv_port_axi_rsp_t slv_resp; + mst_port_axi_req_t mst_req; + mst_port_axi_rsp_t mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -394,10 +394,10 @@ module axi_id_serialize_intf #( .AxiAddrWidth ( AXI_ADDR_WIDTH ), .AxiDataWidth ( AXI_DATA_WIDTH ), .AxiUserWidth ( AXI_USER_WIDTH ), - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ) + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ) ) i_axi_id_serialize ( .clk_i, .rst_ni, diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv index 008cbdfa3..4c5c330c9 100644 --- a/src/axi_isolate.sv +++ b/src/axi_isolate.sv @@ -33,16 +33,16 @@ module axi_isolate #( parameter int unsigned NumPending = 32'd16, // Number of pending requests per channel parameter type axi_req_t = logic, // AXI request struct definition - parameter type axi_resp_t = logic // AXI response struct definition + parameter type axi_rsp_t = logic // AXI response struct definition ) ( - input logic clk_i, // clock - input logic rst_ni, // reset - input axi_req_t slv_req_i, // slave port request struct - output axi_resp_t slv_resp_o, // slave port response struct - output axi_req_t mst_req_o, // master port request struct - input axi_resp_t mst_resp_i, // master port response struct - input logic isolate_i, // isolate master port from slave port - output logic isolated_o // master port is isolated from slave port + input logic clk_i, // clock + input logic rst_ni, // reset + input axi_req_t slv_req_i, // slave port request struct + output axi_rsp_t slv_resp_o, // slave port response struct + output axi_req_t mst_req_o, // master port request struct + input axi_rsp_t mst_resp_i, // master port response struct + input logic isolate_i, // isolate master port from slave port + output logic isolated_o // master port is isolated from slave port ); // plus 1 in clog for accouning no open transaction, plus one bit for atomic injection localparam int unsigned CounterWidth = $clog2(NumPending + 32'd1) + 32'd1; @@ -306,10 +306,10 @@ module axi_isolate_intf #( `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_rsp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -320,7 +320,7 @@ module axi_isolate_intf #( axi_isolate #( .NumPending ( NUM_PENDING ), // Number of pending requests per channel .axi_req_t ( axi_req_t ), // AXI request struct definition - .axi_resp_t ( axi_resp_t ) // AXI response struct definition + .axi_rsp_t ( axi_rsp_t ) // AXI response struct definition ) i_axi_isolate ( .clk_i, // clock .rst_ni, // reset diff --git a/src/axi_iw_converter.sv b/src/axi_iw_converter.sv index e9c5ebb82..3eaed63ad 100644 --- a/src/axi_iw_converter.sv +++ b/src/axi_iw_converter.sv @@ -86,26 +86,26 @@ module axi_iw_converter #( /// User signal width of both AXI4+ATOP ports parameter int unsigned AxiUserWidth = 32'd0, /// Request struct type of the AXI4+ATOP slave port - parameter type slv_req_t = logic, + parameter type slv_port_axi_req_t = logic, /// Response struct type of the AXI4+ATOP slave port - parameter type slv_resp_t = logic, + parameter type slv_port_axi_rsp_t = logic, /// Request struct type of the AXI4+ATOP master port - parameter type mst_req_t = logic, + parameter type mst_port_axi_req_t = logic, /// Response struct type of the AXI4+ATOP master port - parameter type mst_resp_t = logic + parameter type mst_port_axi_rsp_t = logic ) ( /// Rising-edge clock of both ports - input logic clk_i, + input logic clk_i, /// Asynchronous reset, active low - input logic rst_ni, + input logic rst_ni, /// Slave port request - input slv_req_t slv_req_i, + input slv_port_axi_req_t slv_req_i, /// Slave port response - output slv_resp_t slv_resp_o, + output slv_port_axi_rsp_t slv_resp_o, /// Master port request - output mst_req_t mst_req_o, + output mst_port_axi_req_t mst_req_o, /// Master port response - input mst_resp_t mst_resp_i + input mst_port_axi_rsp_t mst_resp_i ); typedef logic [AxiAddrWidth-1:0] addr_t; @@ -131,10 +131,10 @@ module axi_iw_converter #( .AxiMstPortIdWidth ( AxiMstPortIdWidth ), .AxiSlvPortMaxUniqIds ( AxiSlvPortMaxUniqIds ), .AxiMaxTxnsPerId ( AxiSlvPortMaxTxnsPerId ), - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ) + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ) ) i_axi_id_remap ( .clk_i, .rst_ni, @@ -153,10 +153,10 @@ module axi_iw_converter #( .AxiAddrWidth ( AxiAddrWidth ), .AxiDataWidth ( AxiDataWidth ), .AxiUserWidth ( AxiUserWidth ), - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ) + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ) ) i_axi_id_serialize ( .clk_i, .rst_ni, @@ -289,21 +289,21 @@ module axi_iw_converter_intf #( `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_user_t) `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_user_t) `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_chan_t, slv_r_chan_t) `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, axi_addr_t, mst_id_t, axi_user_t) `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, axi_user_t) `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, axi_addr_t, mst_id_t, axi_user_t) `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, axi_data_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, mst_w_chan_t, mst_ar_chan_t) - `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_chan_t, mst_w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_chan_t, mst_r_chan_t) - slv_req_t slv_req; - slv_resp_t slv_resp; - mst_req_t mst_req; - mst_resp_t mst_resp; + slv_port_axi_req_t slv_req; + slv_port_axi_rsp_t slv_resp; + mst_port_axi_req_t mst_req; + mst_port_axi_rsp_t mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -321,10 +321,10 @@ module axi_iw_converter_intf #( .AxiAddrWidth ( AXI_ADDR_WIDTH ), .AxiDataWidth ( AXI_DATA_WIDTH ), .AxiUserWidth ( AXI_USER_WIDTH ), - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ) + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ) ) i_axi_iw_converter ( .clk_i, .rst_ni, diff --git a/src/axi_lite_demux.sv b/src/axi_lite_demux.sv index 7aa047c2d..2587a5afe 100644 --- a/src/axi_lite_demux.sv +++ b/src/axi_lite_demux.sv @@ -19,35 +19,35 @@ // stability rules as the corresponding AXI4-Lite channel. module axi_lite_demux #( - parameter type aw_chan_t = logic, // AXI4-Lite AW channel - parameter type w_chan_t = logic, // AXI4-Lite W channel - parameter type b_chan_t = logic, // AXI4-Lite B channel - parameter type ar_chan_t = logic, // AXI4-Lite AR channel - parameter type r_chan_t = logic, // AXI4-Lite R channel - parameter type axi_lite_req_t = logic, // AXI4-Lite request struct - parameter type axi_lite_resp_t = logic, // AXI4-Lite response struct - parameter int unsigned NoMstPorts = 32'd0, // Number of instantiated ports - parameter int unsigned MaxTrans = 32'd0, // Maximum number of open transactions per channel - parameter bit FallThrough = 1'b0, // FIFOs are in fall through mode - parameter bit SpillAw = 1'b1, // insert one cycle latency on slave AW - parameter bit SpillW = 1'b0, // insert one cycle latency on slave W - parameter bit SpillB = 1'b0, // insert one cycle latency on slave B - parameter bit SpillAr = 1'b1, // insert one cycle latency on slave AR - parameter bit SpillR = 1'b0, // insert one cycle latency on slave R + parameter type aw_chan_t = logic, // AXI4-Lite AW channel + parameter type w_chan_t = logic, // AXI4-Lite W channel + parameter type b_chan_t = logic, // AXI4-Lite B channel + parameter type ar_chan_t = logic, // AXI4-Lite AR channel + parameter type r_chan_t = logic, // AXI4-Lite R channel + parameter type axi_lite_req_t = logic, // AXI4-Lite request struct + parameter type axi_lite_rsp_t = logic, // AXI4-Lite response struct + parameter int unsigned NoMstPorts = 32'd0, // Number of instantiated ports + parameter int unsigned MaxTrans = 32'd0, // Maximum number of open transactions per channel + parameter bit FallThrough = 1'b0, // FIFOs are in fall through mode + parameter bit SpillAw = 1'b1, // insert one cycle latency on slave AW + parameter bit SpillW = 1'b0, // insert one cycle latency on slave W + parameter bit SpillB = 1'b0, // insert one cycle latency on slave B + parameter bit SpillAr = 1'b1, // insert one cycle latency on slave AR + parameter bit SpillR = 1'b0, // insert one cycle latency on slave R // Dependent parameters, DO NOT OVERRIDE! - parameter type select_t = logic [$clog2(NoMstPorts)-1:0] + parameter type select_t = logic [$clog2(NoMstPorts)-1:0] ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, + input logic clk_i, + input logic rst_ni, + input logic test_i, // slave port (AXI4-Lite input), connect master module here - input axi_lite_req_t slv_req_i, - input select_t slv_aw_select_i, - input select_t slv_ar_select_i, - output axi_lite_resp_t slv_resp_o, + input axi_lite_req_t slv_req_i, + input select_t slv_aw_select_i, + input select_t slv_ar_select_i, + output axi_lite_rsp_t slv_resp_o, // master ports (AXI4-Lite outputs), connect slave modules here - output axi_lite_req_t [NoMstPorts-1:0] mst_reqs_o, - input axi_lite_resp_t [NoMstPorts-1:0] mst_resps_i + output axi_lite_req_t [NoMstPorts-1:0] mst_reqs_o, + input axi_lite_rsp_t [NoMstPorts-1:0] mst_resps_i ); //-------------------------------------- @@ -426,12 +426,12 @@ module axi_lite_demux_intf #( `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - axi_lite_req_t slv_req; - axi_lite_resp_t slv_resp; - axi_lite_req_t [NoMstPorts-1:0] mst_reqs; - axi_lite_resp_t [NoMstPorts-1:0] mst_resps; + axi_lite_req_t slv_req; + axi_lite_rsp_t slv_resp; + axi_lite_req_t [NoMstPorts-1:0] mst_reqs; + axi_lite_rsp_t [NoMstPorts-1:0] mst_resps; `AXI_LITE_ASSIGN_TO_REQ(slv_req, slv) `AXI_LITE_ASSIGN_FROM_RESP(slv, slv_resp) @@ -442,21 +442,21 @@ module axi_lite_demux_intf #( end axi_lite_demux #( - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ), - .NoMstPorts ( NoMstPorts ), - .MaxTrans ( MaxTrans ), - .FallThrough ( FallThrough ), - .SpillAw ( SpillAw ), - .SpillW ( SpillW ), - .SpillB ( SpillB ), - .SpillAr ( SpillAr ), - .SpillR ( SpillR ) + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), + .NoMstPorts ( NoMstPorts ), + .MaxTrans ( MaxTrans ), + .FallThrough ( FallThrough ), + .SpillAw ( SpillAw ), + .SpillW ( SpillW ), + .SpillB ( SpillB ), + .SpillAr ( SpillAr ), + .SpillR ( SpillR ) ) i_axi_demux ( .clk_i, .rst_ni, diff --git a/src/axi_lite_mailbox.sv b/src/axi_lite_mailbox.sv index 63fc63889..f9d341697 100644 --- a/src/axi_lite_mailbox.sv +++ b/src/axi_lite_mailbox.sv @@ -19,24 +19,24 @@ `include "common_cells/registers.svh" module axi_lite_mailbox #( - parameter int unsigned MailboxDepth = 32'd0, - parameter bit unsigned IrqEdgeTrig = 1'b0, - parameter bit unsigned IrqActHigh = 1'b1, - parameter int unsigned AxiAddrWidth = 32'd0, - parameter int unsigned AxiDataWidth = 32'd0, - parameter type axi_lite_req_t = logic, - parameter type axi_lite_resp_t = logic, + parameter int unsigned MailboxDepth = 32'd0, + parameter bit unsigned IrqEdgeTrig = 1'b0, + parameter bit unsigned IrqActHigh = 1'b1, + parameter int unsigned AxiAddrWidth = 32'd0, + parameter int unsigned AxiDataWidth = 32'd0, + parameter type axi_lite_req_t = logic, + parameter type axi_lite_rsp_t = logic, // DEPENDENT PARAMETERS, DO NOT OVERRIDE! - parameter type addr_t = logic [AxiAddrWidth-1:0] + parameter type addr_t = logic [AxiAddrWidth-1:0] ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable // slave ports [1:0] - input axi_lite_req_t [1:0] slv_reqs_i, - output axi_lite_resp_t [1:0] slv_resps_o, - output logic [1:0] irq_o, // interrupt output for each port - input addr_t [1:0] base_addr_i // base address for each port + input axi_lite_req_t [1:0] slv_reqs_i, + output axi_lite_rsp_t [1:0] slv_resps_o, + output logic [1:0] irq_o, // interrupt output for each port + input addr_t [1:0] base_addr_i // base address for each port ); localparam int unsigned FifoUsageWidth = $clog2(MailboxDepth); typedef logic [AxiDataWidth-1:0] data_t; @@ -55,14 +55,14 @@ module axi_lite_mailbox #( logic [1:0] clear_irq; axi_lite_mailbox_slave #( - .MailboxDepth ( MailboxDepth ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ), - .addr_t ( addr_t ), - .data_t ( data_t ), - .usage_t ( usage_t ) // fill pointer from MBOX FIFO + .MailboxDepth ( MailboxDepth ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), + .addr_t ( addr_t ), + .data_t ( data_t ), + .usage_t ( usage_t ) // fill pointer from MBOX FIFO ) i_slv_port_0 ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low @@ -88,14 +88,14 @@ module axi_lite_mailbox #( ); axi_lite_mailbox_slave #( - .MailboxDepth ( MailboxDepth ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ), - .addr_t ( addr_t ), - .data_t ( data_t ), - .usage_t ( usage_t ) // fill pointer from MBOX FIFO + .MailboxDepth ( MailboxDepth ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), + .addr_t ( addr_t ), + .data_t ( data_t ), + .usage_t ( usage_t ) // fill pointer from MBOX FIFO ) i_slv_port_1 ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low @@ -202,36 +202,36 @@ endmodule // slave port module module axi_lite_mailbox_slave #( - parameter int unsigned MailboxDepth = 32'd16, - parameter int unsigned AxiAddrWidth = 32'd32, - parameter int unsigned AxiDataWidth = 32'd32, - parameter type axi_lite_req_t = logic, - parameter type axi_lite_resp_t = logic, - parameter type addr_t = logic [AxiAddrWidth-1:0], - parameter type data_t = logic [AxiDataWidth-1:0], - parameter type usage_t = logic // fill pointer from MBOX FIFO + parameter int unsigned MailboxDepth = 32'd16, + parameter int unsigned AxiAddrWidth = 32'd32, + parameter int unsigned AxiDataWidth = 32'd32, + parameter type axi_lite_req_t = logic, + parameter type axi_lite_rsp_t = logic, + parameter type addr_t = logic [AxiAddrWidth-1:0], + parameter type data_t = logic [AxiDataWidth-1:0], + parameter type usage_t = logic // fill pointer from MBOX FIFO ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low // slave port - input axi_lite_req_t slv_req_i, - output axi_lite_resp_t slv_resp_o, - input addr_t base_addr_i, // base address for the slave port + input axi_lite_req_t slv_req_i, + output axi_lite_rsp_t slv_resp_o, + input addr_t base_addr_i, // base address for the slave port // write FIFO port - output data_t mbox_w_data_o, - input logic mbox_w_full_i, - output logic mbox_w_push_o, - output logic mbox_w_flush_o, - input usage_t mbox_w_usage_i, + output data_t mbox_w_data_o, + input logic mbox_w_full_i, + output logic mbox_w_push_o, + output logic mbox_w_flush_o, + input usage_t mbox_w_usage_i, // read FIFO port - input data_t mbox_r_data_i, - input logic mbox_r_empty_i, - output logic mbox_r_pop_o, - output logic mbox_r_flush_o, - input usage_t mbox_r_usage_i, + input data_t mbox_r_data_i, + input logic mbox_r_empty_i, + output logic mbox_r_pop_o, + output logic mbox_r_flush_o, + input usage_t mbox_r_usage_i, // interrupt output, level triggered, active high, conversion in top - output logic irq_o, - output logic clear_irq_o // clear the edge trigger irq register in `axi_lite_mailbox` + output logic irq_o, + output logic clear_irq_o // clear the edge trigger irq register in `axi_lite_mailbox` ); `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t) @@ -579,10 +579,10 @@ module axi_lite_mailbox_intf #( `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_lite_t, r_chan_lite_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_lite_t, r_chan_lite_t) - axi_lite_req_t [1:0] slv_reqs; - axi_lite_resp_t [1:0] slv_resps; + axi_lite_req_t [1:0] slv_reqs; + axi_lite_rsp_t [1:0] slv_resps; for (genvar i = 0; i < 2; i++) begin : gen_port_assign `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) @@ -590,13 +590,13 @@ module axi_lite_mailbox_intf #( end axi_lite_mailbox #( - .MailboxDepth ( MAILBOX_DEPTH ), - .IrqEdgeTrig ( IRQ_EDGE_TRIG ), - .IrqActHigh ( IRQ_ACT_HIGH ), - .AxiAddrWidth ( AXI_ADDR_WIDTH ), - .AxiDataWidth ( AXI_DATA_WIDTH ), - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ) + .MailboxDepth ( MAILBOX_DEPTH ), + .IrqEdgeTrig ( IRQ_EDGE_TRIG ), + .IrqActHigh ( IRQ_ACT_HIGH ), + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .AxiDataWidth ( AXI_DATA_WIDTH ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ) ) i_axi_lite_mailbox ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low diff --git a/src/axi_lite_mux.sv b/src/axi_lite_mux.sv index 31389ef49..26777f3ac 100644 --- a/src/axi_lite_mux.sv +++ b/src/axi_lite_mux.sv @@ -28,7 +28,7 @@ module axi_lite_mux #( parameter type ar_chan_t = logic, // AR LITE Channel Type parameter type r_chan_t = logic, // R LITE Channel Type parameter type axi_lite_req_t = logic, // AXI4-Lite request type - parameter type axi_lite_resp_t = logic, // AXI4-Lite response type + parameter type axi_lite_rsp_t = logic, // AXI4-Lite response type parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports // Maximum number of outstanding transactions per write or read parameter int unsigned MaxTrans = 32'd0, @@ -42,15 +42,15 @@ module axi_lite_mux #( parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0 ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Test Mode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Test Mode enable // slave ports (AXI4-Lite inputs), connect master modules here - input axi_lite_req_t [NoSlvPorts-1:0] slv_reqs_i, - output axi_lite_resp_t [NoSlvPorts-1:0] slv_resps_o, + input axi_lite_req_t [NoSlvPorts-1:0] slv_reqs_i, + output axi_lite_rsp_t [NoSlvPorts-1:0] slv_resps_o, // master port (AXI4-Lite output), connect slave module here - output axi_lite_req_t mst_req_o, - input axi_lite_resp_t mst_resp_i + output axi_lite_req_t mst_req_o, + input axi_lite_rsp_t mst_resp_i ); // pass through if only one slave port if (NoSlvPorts == 32'h1) begin : gen_no_mux @@ -423,12 +423,12 @@ module axi_lite_mux_intf #( `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) axi_lite_req_t [NoSlvPorts-1:0] slv_reqs; - axi_lite_resp_t [NoSlvPorts-1:0] slv_resps; + axi_lite_rsp_t [NoSlvPorts-1:0] slv_resps; axi_lite_req_t mst_req; - axi_lite_resp_t mst_resp; + axi_lite_rsp_t mst_resp; for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_assign_slv_ports `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) @@ -439,21 +439,21 @@ module axi_lite_mux_intf #( `AXI_LITE_ASSIGN_TO_RESP(mst_resp, mst) axi_lite_mux #( - .aw_chan_t ( aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( b_chan_t ), // B Channel Type - .ar_chan_t ( ar_chan_t ), // AR Channel Type - .r_chan_t ( r_chan_t ), // R Channel Type - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ), - .NoSlvPorts ( NoSlvPorts ), // Number of slave ports - .MaxTrans ( MaxTrans ), - .FallThrough ( FallThrough ), - .SpillAw ( SpillAw ), - .SpillW ( SpillW ), - .SpillB ( SpillB ), - .SpillAr ( SpillAr ), - .SpillR ( SpillR ) + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), + .NoSlvPorts ( NoSlvPorts ), // Number of slave ports + .MaxTrans ( MaxTrans ), + .FallThrough ( FallThrough ), + .SpillAw ( SpillAw ), + .SpillW ( SpillW ), + .SpillB ( SpillB ), + .SpillAr ( SpillAr ), + .SpillR ( SpillR ) ) i_axi_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low diff --git a/src/axi_lite_regs.sv b/src/axi_lite_regs.sv index 406e4b7f6..a3c39431b 100644 --- a/src/axi_lite_regs.sv +++ b/src/axi_lite_regs.sv @@ -94,7 +94,7 @@ module axi_lite_regs #( /// Request struct of the AXI4-Lite port. parameter type axi_lite_req_t = logic, /// Response struct of the AXI4-Lite port. - parameter type axi_lite_resp_t = logic + parameter type axi_lite_rsp_t = logic ) ( /// Rising-edge clock of all ports input logic clk_i, @@ -103,7 +103,7 @@ module axi_lite_regs #( /// AXI4-Lite slave request input axi_lite_req_t axi_req_i, /// AXI4-Lite slave response - output axi_lite_resp_t axi_resp_o, + output axi_lite_rsp_t axi_resp_o, /// Signals that a byte is being written from the AXI4-Lite port in the current clock cycle. This /// signal is asserted regardless of the value of `AxiReadOnly` and can therefore be used by /// surrounding logic to react to write-on-read-only-byte errors. @@ -439,24 +439,24 @@ module axi_lite_regs_intf #( `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_lite_t, r_chan_lite_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_lite_t, r_chan_lite_t) - axi_lite_req_t axi_lite_req; - axi_lite_resp_t axi_lite_resp; + axi_lite_req_t axi_lite_req; + axi_lite_rsp_t axi_lite_resp; `AXI_LITE_ASSIGN_TO_REQ(axi_lite_req, slv) `AXI_LITE_ASSIGN_FROM_RESP(slv, axi_lite_resp) axi_lite_regs #( - .RegNumBytes ( REG_NUM_BYTES ), - .AxiAddrWidth ( AXI_ADDR_WIDTH ), - .AxiDataWidth ( AXI_DATA_WIDTH ), - .PrivProtOnly ( PRIV_PROT_ONLY ), - .SecuProtOnly ( SECU_PROT_ONLY ), - .AxiReadOnly ( AXI_READ_ONLY ), - .RegRstVal ( REG_RST_VAL ), - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ) + .RegNumBytes ( REG_NUM_BYTES ), + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .AxiDataWidth ( AXI_DATA_WIDTH ), + .PrivProtOnly ( PRIV_PROT_ONLY ), + .SecuProtOnly ( SECU_PROT_ONLY ), + .AxiReadOnly ( AXI_READ_ONLY ), + .RegRstVal ( REG_RST_VAL ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ) ) i_axi_lite_regs ( .clk_i, .rst_ni, diff --git a/src/axi_lite_to_apb.sv b/src/axi_lite_to_apb.sv index c2d6f0621..1d8262e3f 100644 --- a/src/axi_lite_to_apb.sv +++ b/src/axi_lite_to_apb.sv @@ -40,7 +40,7 @@ // logic pready; // slave signals that it is ready // data_t prdata; // read data, connects to R channel // logic pslverr; // gets translated into either `axi_pkg::RESP_OK` or `axi_pkg::RESP_SLVERR` -// } apb_resp_t; +// } apb_rsp_t; // Each connected `apb_resp`, has to be connected to the corresponding port index. The module // routes the response depending on the `apb_req.psel` bit and `apb_req.pwrite` either to the // AXI4Lite B channel for writes and to the R channel for reads. @@ -55,21 +55,21 @@ module axi_lite_to_apb #( parameter bit PipelineRequest = 1'b0, // Pipeline request path parameter bit PipelineResponse = 1'b0, // Pipeline response path parameter type axi_lite_req_t = logic, // AXI4-Lite request struct - parameter type axi_lite_resp_t = logic, // AXI4-Lite response sruct + parameter type axi_lite_rsp_t = logic, // AXI4-Lite response sruct parameter type apb_req_t = logic, // APB4 request struct - parameter type apb_resp_t = logic, // APB4 response struct + parameter type apb_rsp_t = logic, // APB4 response struct parameter type rule_t = logic // Address Decoder rule from `common_cells` ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low // AXI LITE slave port - input axi_lite_req_t axi_lite_req_i, - output axi_lite_resp_t axi_lite_resp_o, + input axi_lite_req_t axi_lite_req_i, + output axi_lite_rsp_t axi_lite_resp_o, // APB master port - output apb_req_t [NoApbSlaves-1:0] apb_req_o, - input apb_resp_t [NoApbSlaves-1:0] apb_resp_i, + output apb_req_t [NoApbSlaves-1:0] apb_req_o, + input apb_rsp_t [NoApbSlaves-1:0] apb_resp_i, // APB Slave Address Map - input rule_t [NoRules-1:0] addr_map_i + input rule_t [NoRules-1:0] addr_map_i ); localparam logic RD = 1'b0; // Encode index of a read request localparam logic WR = 1'b1; // Encode index of a write request @@ -428,7 +428,7 @@ module axi_lite_to_apb_intf #( logic pready; // slave signals that it is ready data_t prdata; // read data, connects to R channel logic pslverr; // gets translated into either `axi_pkg::RESP_OK` or `axi_pkg::RESP_SLVERR` - } apb_resp_t; + } apb_rsp_t; `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t) `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t) @@ -436,12 +436,12 @@ module axi_lite_to_apb_intf #( `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) axi_req_t axi_req; - axi_resp_t axi_resp; + axi_rsp_t axi_resp; apb_req_t [NoApbSlaves-1:0] apb_req; - apb_resp_t [NoApbSlaves-1:0] apb_resp; + apb_rsp_t [NoApbSlaves-1:0] apb_resp; logic [SelIdxWidth-1:0] apb_sel; `AXI_LITE_ASSIGN_TO_REQ(axi_req, slv) @@ -475,9 +475,9 @@ module axi_lite_to_apb_intf #( .PipelineRequest ( PipelineRequest ), .PipelineResponse ( PipelineResponse ), .axi_lite_req_t ( axi_req_t ), - .axi_lite_resp_t ( axi_resp_t ), + .axi_lite_rsp_t ( axi_rsp_t ), .apb_req_t ( apb_req_t ), - .apb_resp_t ( apb_resp_t ), + .apb_rsp_t ( apb_rsp_t ), .rule_t ( rule_t ) ) i_axi_lite_to_apb ( .clk_i, // Clock diff --git a/src/axi_lite_to_axi.sv b/src/axi_lite_to_axi.sv index c1319d83b..7c54d52f7 100644 --- a/src/axi_lite_to_axi.sv +++ b/src/axi_lite_to_axi.sv @@ -18,20 +18,20 @@ module axi_lite_to_axi #( parameter int unsigned AxiDataWidth = 32'd0, // LITE AXI structs - parameter type axi_lite_req_t = logic, - parameter type axi_lite_resp_t = logic, + parameter type axi_lite_req_t = logic, + parameter type axi_lite_rsp_t = logic, // FULL AXI structs - parameter type axi_req_t = logic, - parameter type axi_resp_t = logic + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic ) ( // Slave AXI LITE port input axi_lite_req_t slv_req_lite_i, - output axi_lite_resp_t slv_resp_lite_o, + output axi_lite_rsp_t slv_resp_lite_o, input axi_pkg::cache_t slv_aw_cache_i, input axi_pkg::cache_t slv_ar_cache_i, // Master AXI port output axi_req_t mst_req_o, - input axi_resp_t mst_resp_i + input axi_rsp_t mst_resp_i ); localparam int unsigned AxiSize = axi_pkg::size_t'($unsigned($clog2(AxiDataWidth/8))); diff --git a/src/axi_lite_xbar.sv b/src/axi_lite_xbar.sv index fb5b8d822..ebb2cece0 100644 --- a/src/axi_lite_xbar.sv +++ b/src/axi_lite_xbar.sv @@ -21,27 +21,27 @@ module axi_lite_xbar #( parameter axi_pkg::xbar_cfg_t Cfg = '0, - parameter type aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type r_chan_t = logic, - parameter type axi_lite_req_t = logic, - parameter type axi_lite_resp_t = logic, - parameter type rule_t = axi_pkg::xbar_rule_64_t, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + parameter type axi_lite_req_t = logic, + parameter type axi_lite_rsp_t = logic, + parameter type rule_t = axi_pkg::xbar_rule_64_t, // DEPENDENT PARAMETERS, DO NOT OVERWRITE! parameter int unsigned MstIdxWidth = (Cfg.NoMstPorts > 32'd1) ? $clog2(Cfg.NoMstPorts) : 32'd1 ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, - input axi_lite_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, - output axi_lite_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, - output axi_lite_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, - input axi_lite_resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i, - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NoSlvPorts-1:0][MstIdxWidth-1:0] default_mst_port_i + input logic clk_i, + input logic rst_ni, + input logic test_i, + input axi_lite_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, + output axi_lite_rsp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, + output axi_lite_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, + input axi_lite_rsp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i, + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NoSlvPorts-1:0][MstIdxWidth-1:0] default_mst_port_i ); typedef logic [Cfg.AxiAddrWidth-1:0] addr_t; @@ -57,15 +57,15 @@ module axi_lite_xbar #( `AXI_TYPEDEF_AR_CHAN_T(full_ar_chan_t, addr_t, logic, logic) `AXI_TYPEDEF_R_CHAN_T(full_r_chan_t, data_t, logic, logic) `AXI_TYPEDEF_REQ_T(full_req_t, full_aw_chan_t, full_w_chan_t, full_ar_chan_t) - `AXI_TYPEDEF_RESP_T(full_resp_t, full_b_chan_t, full_r_chan_t) + `AXI_TYPEDEF_RSP_T(full_rsp_t, full_b_chan_t, full_r_chan_t) // signals from the axi_lite_demuxes, one index more for decode error routing - axi_lite_req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; - axi_lite_resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps; + axi_lite_req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; + axi_lite_rsp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps; // signals into the axi_lite_muxes, are of type slave as the multiplexer extends the ID - axi_lite_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; - axi_lite_resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; + axi_lite_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; + axi_lite_rsp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux logic [MstIdxWidth-1:0] dec_aw, dec_ar; @@ -73,8 +73,8 @@ module axi_lite_xbar #( logic dec_aw_error; logic dec_ar_error; - full_req_t decerr_req; - full_resp_t decerr_resp; + full_req_t decerr_req; + full_rsp_t decerr_resp; addr_decode #( .NoIndices ( Cfg.NoMstPorts ), @@ -138,21 +138,21 @@ module axi_lite_xbar #( `endif // pragma translate_on axi_lite_demux #( - .aw_chan_t ( aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( b_chan_t ), // B Channel Type - .ar_chan_t ( ar_chan_t ), // AR Channel Type - .r_chan_t ( r_chan_t ), // R Channel Type - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ), - .NoMstPorts ( Cfg.NoMstPorts + 1 ), - .MaxTrans ( Cfg.MaxMstTrans ), - .FallThrough ( Cfg.FallThrough ), - .SpillAw ( Cfg.LatencyMode[9] ), - .SpillW ( Cfg.LatencyMode[8] ), - .SpillB ( Cfg.LatencyMode[7] ), - .SpillAr ( Cfg.LatencyMode[6] ), - .SpillR ( Cfg.LatencyMode[5] ) + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), + .NoMstPorts ( Cfg.NoMstPorts + 1 ), + .MaxTrans ( Cfg.MaxMstTrans ), + .FallThrough ( Cfg.FallThrough ), + .SpillAw ( Cfg.LatencyMode[9] ), + .SpillW ( Cfg.LatencyMode[8] ), + .SpillB ( Cfg.LatencyMode[7] ), + .SpillAr ( Cfg.LatencyMode[6] ), + .SpillR ( Cfg.LatencyMode[5] ) ) i_axi_lite_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low @@ -168,11 +168,11 @@ module axi_lite_xbar #( // connect the decode error module to the last index of the demux master port // typedef as the decode error slave uses full axi axi_lite_to_axi #( - .AxiDataWidth ( Cfg.AxiDataWidth ), - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ), - .axi_req_t ( full_req_t ), - .axi_resp_t ( full_resp_t ) + .AxiDataWidth ( Cfg.AxiDataWidth ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), + .axi_req_t ( full_req_t ), + .axi_rsp_t ( full_rsp_t ) ) i_dec_err_conv ( .slv_req_lite_i ( slv_reqs[i][Cfg.NoMstPorts] ), .slv_resp_lite_o ( slv_resps[i][Cfg.NoMstPorts] ), @@ -185,7 +185,7 @@ module axi_lite_xbar #( axi_err_slv #( .AxiIdWidth ( 32'd1 ), // ID width is one as defined as logic above .axi_req_t ( full_req_t ), // AXI request struct - .axi_resp_t ( full_resp_t ), // AXI response struct + .axi_rsp_t ( full_rsp_t ), // AXI response struct .Resp ( axi_pkg::RESP_DECERR ), .ATOPs ( 1'b0 ), // no ATOPs in AXI4-Lite .MaxTrans ( 1 ) // Transactions terminate at this slave, and AXI4-Lite @@ -210,21 +210,21 @@ module axi_lite_xbar #( for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_mst_port_mux axi_lite_mux #( - .aw_chan_t ( aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( b_chan_t ), // B Channel Type - .ar_chan_t ( ar_chan_t ), // AR Channel Type - .r_chan_t ( r_chan_t ), // R Channel Type - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ), - .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module - .MaxTrans ( Cfg.MaxSlvTrans ), - .FallThrough ( Cfg.FallThrough ), - .SpillAw ( Cfg.LatencyMode[4] ), - .SpillW ( Cfg.LatencyMode[3] ), - .SpillB ( Cfg.LatencyMode[2] ), - .SpillAr ( Cfg.LatencyMode[1] ), - .SpillR ( Cfg.LatencyMode[0] ) + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), + .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module + .MaxTrans ( Cfg.MaxSlvTrans ), + .FallThrough ( Cfg.FallThrough ), + .SpillAw ( Cfg.LatencyMode[4] ), + .SpillW ( Cfg.LatencyMode[3] ), + .SpillB ( Cfg.LatencyMode[2] ), + .SpillAr ( Cfg.LatencyMode[1] ), + .SpillR ( Cfg.LatencyMode[0] ) ) i_axi_lite_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low @@ -262,12 +262,12 @@ module axi_lite_xbar_intf #( `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - axi_lite_req_t [Cfg.NoMstPorts-1:0] mst_reqs; - axi_lite_resp_t [Cfg.NoMstPorts-1:0] mst_resps; - axi_lite_req_t [Cfg.NoSlvPorts-1:0] slv_reqs; - axi_lite_resp_t [Cfg.NoSlvPorts-1:0] slv_resps; + axi_lite_req_t [Cfg.NoMstPorts-1:0] mst_reqs; + axi_lite_rsp_t [Cfg.NoMstPorts-1:0] mst_resps; + axi_lite_req_t [Cfg.NoSlvPorts-1:0] slv_reqs; + axi_lite_rsp_t [Cfg.NoSlvPorts-1:0] slv_resps; for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst `AXI_LITE_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) @@ -280,15 +280,15 @@ module axi_lite_xbar_intf #( end axi_lite_xbar #( - .Cfg ( Cfg ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ), - .rule_t ( rule_t ) + .Cfg ( Cfg ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), + .rule_t ( rule_t ) ) i_xbar ( .clk_i, .rst_ni, diff --git a/src/axi_modify_address.sv b/src/axi_modify_address.sv index 2a9b96229..cc58eae51 100644 --- a/src/axi_modify_address.sv +++ b/src/axi_modify_address.sv @@ -17,26 +17,26 @@ /// Modify addresses on an AXI4 bus module axi_modify_address #( /// Request type of the slave port - parameter type slv_req_t = logic, + parameter type slv_port_axi_req_t = logic, /// Address type of the master port parameter type mst_addr_t = logic, /// Request type of the master port - parameter type mst_req_t = logic, + parameter type mst_port_axi_req_t = logic, /// Response type of slave and master port - parameter type axi_resp_t = logic + parameter type axi_rsp_t = logic ) ( /// Slave port request - input slv_req_t slv_req_i, + input slv_port_axi_req_t slv_req_i, /// Slave port response - output axi_resp_t slv_resp_o, + output axi_rsp_t slv_resp_o, /// AW address on master port; must remain stable while an AW handshake is pending. input mst_addr_t mst_aw_addr_i, /// AR address on master port; must remain stable while an AR handshake is pending. input mst_addr_t mst_ar_addr_i, /// Master port request - output mst_req_t mst_req_o, + output mst_port_axi_req_t mst_req_o, /// Master port response - input axi_resp_t mst_resp_i + input axi_rsp_t mst_resp_i ); assign mst_req_o = '{ @@ -123,13 +123,13 @@ module axi_modify_address_intf #( `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, slv_addr_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, mst_addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - slv_req_t slv_req; - mst_req_t mst_req; - axi_resp_t slv_resp, mst_resp; + slv_port_axi_req_t slv_req; + mst_port_axi_req_t mst_req; + axi_rsp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -138,10 +138,10 @@ module axi_modify_address_intf #( `AXI_ASSIGN_TO_RESP(mst_resp, mst) axi_modify_address #( - .slv_req_t ( slv_req_t ), - .mst_addr_t ( mst_addr_t ), - .mst_req_t ( mst_req_t ), - .axi_resp_t ( axi_resp_t ) + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .mst_addr_t ( mst_addr_t ), + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .axi_rsp_t ( axi_rsp_t ) ) i_axi_modify_address ( .slv_req_i ( slv_req ), .slv_resp_o ( slv_resp ), diff --git a/src/axi_multicut.sv b/src/axi_multicut.sv index 1e42c2da5..e023a36f5 100644 --- a/src/axi_multicut.sv +++ b/src/axi_multicut.sv @@ -21,23 +21,23 @@ module axi_multicut #( parameter int unsigned NoCuts = 32'd1, // Number of cuts. // AXI channel structs - parameter type aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type r_chan_t = logic, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, // AXI request & response structs - parameter type axi_req_t = logic, - parameter type axi_resp_t = logic + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low // slave port - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_rsp_t slv_resp_o, // master port - output axi_req_t mst_req_o, - input axi_resp_t mst_resp_i + output axi_req_t mst_req_o, + input axi_rsp_t mst_resp_i ); if (NoCuts == '0) begin : gen_no_cut @@ -46,8 +46,8 @@ module axi_multicut #( assign slv_resp_o = mst_resp_i; end else begin : gen_axi_cut // instantiate all needed cuts - axi_req_t [NoCuts:0] cut_req; - axi_resp_t [NoCuts:0] cut_resp; + axi_req_t [NoCuts:0] cut_req; + axi_rsp_t [NoCuts:0] cut_resp; // connect slave to the lowest index assign cut_req[0] = slv_req_i; @@ -56,14 +56,14 @@ module axi_multicut #( // AXI cuts for (genvar i = 0; i < NoCuts; i++) begin : gen_axi_cuts axi_cut #( - .Bypass ( 1'b0 ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) + .Bypass ( 1'b0 ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ) ) i_cut ( .clk_i, .rst_ni, @@ -118,10 +118,10 @@ module axi_multicut_intf #( `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_rsp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, in) `AXI_ASSIGN_FROM_RESP(in, slv_resp) @@ -130,14 +130,14 @@ module axi_multicut_intf #( `AXI_ASSIGN_TO_RESP(mst_resp, out) axi_multicut #( - .NoCuts ( NUM_CUTS ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) + .NoCuts ( NUM_CUTS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ) ) i_axi_multicut ( .clk_i, .rst_ni, @@ -192,10 +192,10 @@ module axi_lite_multicut_intf #( `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_rsp_t slv_resp, mst_resp; `AXI_LITE_ASSIGN_TO_REQ(slv_req, in) `AXI_LITE_ASSIGN_FROM_RESP(in, slv_resp) @@ -204,14 +204,14 @@ module axi_lite_multicut_intf #( `AXI_LITE_ASSIGN_TO_RESP(mst_resp, out) axi_multicut #( - .NoCuts ( NUM_CUTS ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) + .NoCuts ( NUM_CUTS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ) ) i_axi_multicut ( .clk_i, .rst_ni, diff --git a/src/axi_mux.sv b/src/axi_mux.sv index 59ee3ec46..d6bc59d22 100644 --- a/src/axi_mux.sv +++ b/src/axi_mux.sv @@ -26,42 +26,42 @@ module axi_mux #( // AXI parameter and channel types - parameter int unsigned SlvAxiIDWidth = 32'd0, // AXI ID width, slave ports - parameter type slv_aw_chan_t = logic, // AW Channel Type, slave ports - parameter type mst_aw_chan_t = logic, // AW Channel Type, master port - parameter type w_chan_t = logic, // W Channel Type, all ports - parameter type slv_b_chan_t = logic, // B Channel Type, slave ports - parameter type mst_b_chan_t = logic, // B Channel Type, master port - parameter type slv_ar_chan_t = logic, // AR Channel Type, slave ports - parameter type mst_ar_chan_t = logic, // AR Channel Type, master port - parameter type slv_r_chan_t = logic, // R Channel Type, slave ports - parameter type mst_r_chan_t = logic, // R Channel Type, master port - parameter type slv_req_t = logic, // Slave port request type - parameter type slv_resp_t = logic, // Slave port response type - parameter type mst_req_t = logic, // Master ports request type - parameter type mst_resp_t = logic, // Master ports response type - parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports + parameter int unsigned SlvAxiIDWidth = 32'd0, // AXI ID width, slave ports + parameter type slv_aw_chan_t = logic, // AW Channel Type, slave ports + parameter type mst_aw_chan_t = logic, // AW Channel Type, master port + parameter type w_chan_t = logic, // W Channel Type, all ports + parameter type slv_b_chan_t = logic, // B Channel Type, slave ports + parameter type mst_b_chan_t = logic, // B Channel Type, master port + parameter type slv_ar_chan_t = logic, // AR Channel Type, slave ports + parameter type mst_ar_chan_t = logic, // AR Channel Type, master port + parameter type slv_r_chan_t = logic, // R Channel Type, slave ports + parameter type mst_r_chan_t = logic, // R Channel Type, master port + parameter type slv_port_axi_req_t = logic, // Slave port request type + parameter type slv_port_axi_rsp_t = logic, // Slave port response type + parameter type mst_port_axi_req_t = logic, // Master ports request type + parameter type mst_port_axi_rsp_t = logic, // Master ports response type + parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports // Maximum number of outstanding transactions per write - parameter int unsigned MaxWTrans = 32'd8, + parameter int unsigned MaxWTrans = 32'd8, // If enabled, this multiplexer is purely combinatorial - parameter bit FallThrough = 1'b0, + parameter bit FallThrough = 1'b0, // add spill register on write master ports, adds a cycle latency on write channels - parameter bit SpillAw = 1'b1, - parameter bit SpillW = 1'b0, - parameter bit SpillB = 1'b0, + parameter bit SpillAw = 1'b1, + parameter bit SpillW = 1'b0, + parameter bit SpillB = 1'b0, // add spill register on read master ports, adds a cycle latency on read channels - parameter bit SpillAr = 1'b1, - parameter bit SpillR = 1'b0 + parameter bit SpillAr = 1'b1, + parameter bit SpillR = 1'b0 ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Test Mode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Test Mode enable // slave ports (AXI inputs), connect master modules here - input slv_req_t [NoSlvPorts-1:0] slv_reqs_i, - output slv_resp_t [NoSlvPorts-1:0] slv_resps_o, + input slv_port_axi_req_t [NoSlvPorts-1:0] slv_reqs_i, + output slv_port_axi_rsp_t [NoSlvPorts-1:0] slv_resps_o, // master port (AXI outputs), connect slave modules here - output mst_req_t mst_req_o, - input mst_resp_t mst_resp_i + output mst_port_axi_req_t mst_req_o, + input mst_port_axi_rsp_t mst_resp_i ); localparam int unsigned MstIdxBits = $clog2(NoSlvPorts); @@ -468,16 +468,16 @@ module axi_mux_intf #( `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, user_t) - `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_chan_t, slv_r_chan_t) - `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) - `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_chan_t, mst_r_chan_t) - slv_req_t [NO_SLV_PORTS-1:0] slv_reqs; - slv_resp_t [NO_SLV_PORTS-1:0] slv_resps; - mst_req_t mst_req; - mst_resp_t mst_resp; + slv_port_axi_req_t [NO_SLV_PORTS-1:0] slv_reqs; + slv_port_axi_rsp_t [NO_SLV_PORTS-1:0] slv_resps; + mst_port_axi_req_t mst_req; + mst_port_axi_rsp_t mst_resp; for (genvar i = 0; i < NO_SLV_PORTS; i++) begin : gen_assign_slv_ports `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) @@ -488,28 +488,28 @@ module axi_mux_intf #( `AXI_ASSIGN_TO_RESP(mst_resp, mst) axi_mux #( - .SlvAxiIDWidth ( SLV_AXI_ID_WIDTH ), - .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports - .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port - .w_chan_t ( w_chan_t ), // W Channel Type, all ports - .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports - .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port - .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports - .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port - .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports - .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ), - .NoSlvPorts ( NO_SLV_PORTS ), // Number of slave ports - .MaxWTrans ( MAX_W_TRANS ), - .FallThrough ( FALL_THROUGH ), - .SpillAw ( SPILL_AW ), - .SpillW ( SPILL_W ), - .SpillB ( SPILL_B ), - .SpillAr ( SPILL_AR ), - .SpillR ( SPILL_R ) + .SlvAxiIDWidth ( SLV_AXI_ID_WIDTH ), + .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports + .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port + .w_chan_t ( w_chan_t ), // W Channel Type, all ports + .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports + .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port + .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports + .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port + .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports + .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), + .NoSlvPorts ( NO_SLV_PORTS ), // Number of slave ports + .MaxWTrans ( MAX_W_TRANS ), + .FallThrough ( FALL_THROUGH ), + .SpillAw ( SPILL_AW ), + .SpillW ( SPILL_W ), + .SpillB ( SPILL_B ), + .SpillAr ( SPILL_AR ), + .SpillR ( SPILL_R ) ) i_axi_mux ( .clk_i ( clk_i ), // Clock .rst_ni ( rst_ni ), // Asynchronous reset active low diff --git a/src/axi_serializer.sv b/src/axi_serializer.sv index 0b064f29e..260358fba 100644 --- a/src/axi_serializer.sv +++ b/src/axi_serializer.sv @@ -29,20 +29,20 @@ module axi_serializer #( /// AXI4+ATOP request struct definition. parameter type axi_req_t = logic, /// AXI4+ATOP response struct definition. - parameter type axi_resp_t = logic + parameter type axi_rsp_t = logic ) ( /// Clock - input logic clk_i, + input logic clk_i, /// Asynchronous reset, active low - input logic rst_ni, + input logic rst_ni, /// Slave port request - input axi_req_t slv_req_i, + input axi_req_t slv_req_i, /// Slave port response - output axi_resp_t slv_resp_o, + output axi_rsp_t slv_resp_o, /// Master port request - output axi_req_t mst_req_o, + output axi_req_t mst_req_o, /// Master port response - input axi_resp_t mst_resp_i + input axi_rsp_t mst_resp_i ); typedef logic [AxiIdWidth-1:0] id_t; @@ -255,9 +255,9 @@ module axi_serializer_intf #( `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_resp_t slv_resp, mst_resp; + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) + axi_req_t slv_req, mst_req; + axi_rsp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) `AXI_ASSIGN_FROM_REQ(mst, mst_req) @@ -268,7 +268,7 @@ module axi_serializer_intf #( .MaxWriteTxns ( MAX_WRITE_TXNS ), .AxiIdWidth ( AXI_ID_WIDTH ), .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) + .axi_rsp_t ( axi_rsp_t ) ) i_axi_serializer ( .clk_i, .rst_ni, diff --git a/src/axi_sim_mem.sv b/src/axi_sim_mem.sv index 77bd09a17..5da595035 100644 --- a/src/axi_sim_mem.sv +++ b/src/axi_sim_mem.sv @@ -31,7 +31,7 @@ module axi_sim_mem #( /// AXI4 request struct definition parameter type axi_req_t = logic, /// AXI4 response struct definition - parameter type axi_resp_t = logic, + parameter type axi_rsp_t = logic, /// Warn on accesses to uninitialized bytes parameter bit WarnUninitialized = 1'b0, /// Application delay (measured after rising clock edge) @@ -40,13 +40,13 @@ module axi_sim_mem #( parameter time AcqDelay = 0ps ) ( /// Rising-edge clock - input logic clk_i, + input logic clk_i, /// Active-low reset - input logic rst_ni, + input logic rst_ni, /// AXI4 request struct - input axi_req_t axi_req_i, + input axi_req_t axi_req_i, /// AXI4 response struct - output axi_resp_t axi_rsp_o + output axi_rsp_t axi_rsp_o ); localparam int unsigned StrbWidth = DataWidth / 8; diff --git a/src/axi_to_axi_lite.sv b/src/axi_to_axi_lite.sv index 29571bf5b..7ac83066e 100644 --- a/src/axi_to_axi_lite.sv +++ b/src/axi_to_axi_lite.sv @@ -25,30 +25,30 @@ module axi_to_axi_lite #( parameter int unsigned AxiMaxReadTxns = 32'd0, parameter bit FallThrough = 1'b1, // FIFOs in Fall through mode in ID reflect parameter type axi_req_t = logic, - parameter type axi_resp_t = logic, + parameter type axi_rsp_t = logic, parameter type axi_lite_req_t = logic, - parameter type axi_lite_resp_t = logic + parameter type axi_lite_rsp_t = logic ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable // slave port full AXI4+ATOP - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_rsp_t slv_resp_o, // master port AXI4-Lite - output axi_lite_req_t mst_req_o, - input axi_lite_resp_t mst_resp_i + output axi_lite_req_t mst_req_o, + input axi_lite_rsp_t mst_resp_i ); // full bus declarations - axi_req_t filtered_req, splitted_req; - axi_resp_t filtered_resp, splitted_resp; + axi_req_t filtered_req, splitted_req; + axi_rsp_t filtered_resp, splitted_resp; // atomics adapter so that atomics can be resolved axi_atop_filter #( .AxiIdWidth ( AxiIdWidth ), .AxiMaxWriteTxns ( AxiMaxWriteTxns ), .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) + .axi_rsp_t ( axi_rsp_t ) ) i_axi_atop_filter( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -67,7 +67,7 @@ module axi_to_axi_lite #( .IdWidth ( AxiIdWidth ), .UserWidth ( AxiUserWidth ), .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) + .axi_rsp_t ( axi_rsp_t ) ) i_axi_burst_splitter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -84,9 +84,9 @@ module axi_to_axi_lite #( .AxiMaxReadTxns ( AxiMaxReadTxns ), .FallThrough ( FallThrough ), .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), + .axi_rsp_t ( axi_rsp_t ), .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ) + .axi_lite_rsp_t ( axi_lite_rsp_t ) ) i_axi_to_axi_lite_id_reflect ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -120,19 +120,19 @@ module axi_to_axi_lite_id_reflect #( parameter int unsigned AxiMaxReadTxns = 32'd0, parameter bit FallThrough = 1'b1, // FIFOs in fall through mode parameter type axi_req_t = logic, - parameter type axi_resp_t = logic, + parameter type axi_rsp_t = logic, parameter type axi_lite_req_t = logic, - parameter type axi_lite_resp_t = logic + parameter type axi_lite_rsp_t = logic ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable // slave port full AXI - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_rsp_t slv_resp_o, // master port AXI LITE - output axi_lite_req_t mst_req_o, - input axi_lite_resp_t mst_resp_i + output axi_lite_req_t mst_req_o, + input axi_lite_rsp_t mst_resp_i ); typedef logic [AxiIdWidth-1:0] id_t; @@ -276,7 +276,7 @@ module axi_to_axi_lite_intf #( `AXI_TYPEDEF_AR_CHAN_T(full_ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(full_r_chan_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, full_aw_chan_t, full_w_chan_t, full_ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_resp_t, full_b_chan_t, full_r_chan_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, full_b_chan_t, full_r_chan_t) // LITE channels typedef `AXI_LITE_TYPEDEF_AW_CHAN_T(lite_aw_chan_t, addr_t) `AXI_LITE_TYPEDEF_W_CHAN_T(lite_w_chan_t, data_t, strb_t) @@ -284,12 +284,12 @@ module axi_to_axi_lite_intf #( `AXI_LITE_TYPEDEF_AR_CHAN_T(lite_ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T (lite_r_chan_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, lite_aw_chan_t, lite_w_chan_t, lite_ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, lite_b_chan_t, lite_r_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, lite_b_chan_t, lite_r_chan_t) - axi_req_t full_req; - axi_resp_t full_resp; - axi_lite_req_t lite_req; - axi_lite_resp_t lite_resp; + axi_req_t full_req; + axi_rsp_t full_resp; + axi_lite_req_t lite_req; + axi_lite_rsp_t lite_resp; `AXI_ASSIGN_TO_REQ(full_req, slv) `AXI_ASSIGN_FROM_RESP(slv, full_resp) @@ -306,9 +306,9 @@ module axi_to_axi_lite_intf #( .AxiMaxReadTxns ( AXI_MAX_READ_TXNS ), .FallThrough ( FALL_THROUGH ), // FIFOs in Fall through mode in ID reflect .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), + .axi_rsp_t ( axi_rsp_t ), .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ) + .axi_lite_rsp_t ( axi_lite_rsp_t ) ) i_axi_to_axi_lite ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv index 6124d90a7..8a1cc3e95 100644 --- a/src/axi_xbar.sv +++ b/src/axi_xbar.sv @@ -29,22 +29,22 @@ import cf_math_pkg::idx_width; parameter type mst_ar_chan_t = logic, parameter type slv_r_chan_t = logic, parameter type mst_r_chan_t = logic, - parameter type slv_req_t = logic, - parameter type slv_resp_t = logic, - parameter type mst_req_t = logic, - parameter type mst_resp_t = logic, + parameter type slv_port_axi_req_t = logic, + parameter type slv_port_axi_rsp_t = logic, + parameter type mst_port_axi_req_t = logic, + parameter type mst_port_axi_rsp_t = logic, parameter type rule_t = axi_pkg::xbar_rule_64_t ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, - input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, - output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, - output mst_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, - input mst_resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i, - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i + input logic clk_i, + input logic rst_ni, + input logic test_i, + input slv_port_axi_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, + output slv_port_axi_rsp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, + output mst_port_axi_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, + input mst_port_axi_rsp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i, + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i ); typedef logic [Cfg.AxiAddrWidth-1:0] addr_t; @@ -52,15 +52,15 @@ import cf_math_pkg::idx_width; typedef logic [idx_width(Cfg.NoMstPorts + 1)-1:0] mst_port_idx_t; // signals from the axi_demuxes, one index more for decode error - slv_req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; - slv_resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps; + slv_port_axi_req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; + slv_port_axi_rsp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps; // workaround for issue #133 (problem with vsim 10.6c) localparam int unsigned cfg_NoMstPorts = Cfg.NoMstPorts; // signals into the axi_muxes, are of type slave as the multiplexer extends the ID - slv_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; - slv_resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; + slv_port_axi_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; + slv_port_axi_rsp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux logic [idx_width(Cfg.NoMstPorts)-1:0] dec_aw, dec_ar; @@ -138,8 +138,8 @@ import cf_math_pkg::idx_width; .b_chan_t ( slv_b_chan_t ), // B Channel Type .ar_chan_t ( slv_ar_chan_t ), // AR Channel Type .r_chan_t ( slv_r_chan_t ), // R Channel Type - .axi_req_t ( slv_req_t ), - .axi_resp_t ( slv_resp_t ), + .axi_req_t ( slv_port_axi_req_t ), + .axi_rsp_t ( slv_port_axi_rsp_t ), .NoMstPorts ( Cfg.NoMstPorts + 1 ), .MaxTrans ( Cfg.MaxMstTrans ), .AxiLookBits ( Cfg.AxiIdUsedSlvPorts ), @@ -164,8 +164,8 @@ import cf_math_pkg::idx_width; axi_err_slv #( .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), - .axi_req_t ( slv_req_t ), - .axi_resp_t ( slv_resp_t ), + .axi_req_t ( slv_port_axi_req_t ), + .axi_rsp_t ( slv_port_axi_rsp_t ), .Resp ( axi_pkg::RESP_DECERR ), .ATOPs ( ATOPs ), .MaxTrans ( 4 ) // Transactions terminate at this slave, so minimize @@ -191,28 +191,28 @@ import cf_math_pkg::idx_width; for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_mst_port_mux axi_mux #( - .SlvAxiIDWidth ( Cfg.AxiIdWidthSlvPorts ), // ID width of the slave ports - .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports - .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port - .w_chan_t ( w_chan_t ), // W Channel Type, all ports - .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports - .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port - .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports - .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port - .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports - .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ), - .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module - .MaxWTrans ( Cfg.MaxSlvTrans ), - .FallThrough ( Cfg.FallThrough ), - .SpillAw ( Cfg.LatencyMode[4] ), - .SpillW ( Cfg.LatencyMode[3] ), - .SpillB ( Cfg.LatencyMode[2] ), - .SpillAr ( Cfg.LatencyMode[1] ), - .SpillR ( Cfg.LatencyMode[0] ) + .SlvAxiIDWidth ( Cfg.AxiIdWidthSlvPorts ), // ID width of the slave ports + .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports + .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port + .w_chan_t ( w_chan_t ), // W Channel Type, all ports + .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports + .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port + .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports + .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port + .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports + .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), + .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module + .MaxWTrans ( Cfg.MaxSlvTrans ), + .FallThrough ( Cfg.FallThrough ), + .SpillAw ( Cfg.LatencyMode[4] ), + .SpillW ( Cfg.LatencyMode[3] ), + .SpillB ( Cfg.LatencyMode[2] ), + .SpillAr ( Cfg.LatencyMode[1] ), + .SpillR ( Cfg.LatencyMode[0] ) ) i_axi_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low @@ -276,15 +276,15 @@ import cf_math_pkg::idx_width; `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, id_slv_t, user_t) `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, id_mst_t, user_t) `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, id_slv_t, user_t) - `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) - `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) - `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_chan_t, slv_r_chan_t) - mst_req_t [Cfg.NoMstPorts-1:0] mst_reqs; - mst_resp_t [Cfg.NoMstPorts-1:0] mst_resps; - slv_req_t [Cfg.NoSlvPorts-1:0] slv_reqs; - slv_resp_t [Cfg.NoSlvPorts-1:0] slv_resps; + mst_port_axi_req_t [Cfg.NoMstPorts-1:0] mst_reqs; + mst_port_axi_rsp_t [Cfg.NoMstPorts-1:0] mst_resps; + slv_port_axi_req_t [Cfg.NoSlvPorts-1:0] slv_reqs; + slv_port_axi_rsp_t [Cfg.NoSlvPorts-1:0] slv_resps; for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) @@ -298,20 +298,20 @@ import cf_math_pkg::idx_width; axi_xbar #( .Cfg (Cfg), - .slv_aw_chan_t ( slv_aw_chan_t ), - .mst_aw_chan_t ( mst_aw_chan_t ), - .w_chan_t ( w_chan_t ), - .slv_b_chan_t ( slv_b_chan_t ), - .mst_b_chan_t ( mst_b_chan_t ), - .slv_ar_chan_t ( slv_ar_chan_t ), - .mst_ar_chan_t ( mst_ar_chan_t ), - .slv_r_chan_t ( slv_r_chan_t ), - .mst_r_chan_t ( mst_r_chan_t ), - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ), - .rule_t ( rule_t ) + .slv_aw_chan_t ( slv_aw_chan_t ), + .mst_aw_chan_t ( mst_aw_chan_t ), + .w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slv_b_chan_t ), + .mst_b_chan_t ( mst_b_chan_t ), + .slv_ar_chan_t ( slv_ar_chan_t ), + .mst_ar_chan_t ( mst_ar_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ), + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), + .rule_t ( rule_t ) ) i_xbar ( .clk_i, .rst_ni, diff --git a/test/axi_synth_bench.sv b/test/axi_synth_bench.sv index 9cb255890..ac4081809 100644 --- a/test/axi_synth_bench.sv +++ b/test/axi_synth_bench.sv @@ -290,7 +290,7 @@ module synth_axi_lite_to_apb #( logic pready; // slave signals that it is ready data_t prdata; // read data, connects to R channel logic pslverr; // gets translated into either `axi_pkg::RESP_OK` or `axi_pkg::RESP_SLVERR` - } apb_resp_t; + } apb_rsp_t; `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t) `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t) @@ -298,25 +298,25 @@ module synth_axi_lite_to_apb #( `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t axi_req; - axi_resp_t axi_resp; - apb_req_t [NoApbSlaves-1:0] apb_req; - apb_resp_t [NoApbSlaves-1:0] apb_resp; + axi_req_t axi_req; + axi_rsp_t axi_resp; + apb_req_t [NoApbSlaves-1:0] apb_req; + apb_rsp_t [NoApbSlaves-1:0] apb_resp; axi_pkg::xbar_rule_32_t [NoApbSlaves-1:0] addr_map; axi_lite_to_apb #( - .NoApbSlaves ( NoApbSlaves ), - .NoRules ( NoApbSlaves ), - .AddrWidth ( 32'd32 ), - .DataWidth ( DataWidth ), - .axi_lite_req_t ( axi_req_t ), - .axi_lite_resp_t ( axi_resp_t ), - .apb_req_t ( apb_req_t ), - .apb_resp_t ( apb_resp_t ), - .rule_t ( axi_pkg::xbar_rule_32_t ) + .NoApbSlaves ( NoApbSlaves ), + .NoRules ( NoApbSlaves ), + .AddrWidth ( 32'd32 ), + .DataWidth ( DataWidth ), + .axi_lite_req_t ( axi_req_t ), + .axi_lite_rsp_t ( axi_rsp_t ), + .apb_req_t ( apb_req_t ), + .apb_rsp_t ( apb_rsp_t ), + .rule_t ( axi_pkg::xbar_rule_32_t ) ) i_axi_lite_to_apb_dut ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -388,7 +388,7 @@ module synth_axi_lite_xbar #( `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_(axi_lite_rsp_t, b_chan_t, r_chan_t) localparam axi_pkg::xbar_cfg_t XbarCfg = '{ NoSlvPorts: NoSlvMst, NoMstPorts: NoSlvMst, @@ -404,18 +404,18 @@ module synth_axi_lite_xbar #( axi_pkg::xbar_rule_32_t [NoSlvMst-1:0] addr_map; logic test; - axi_lite_req_t [NoSlvMst-1:0] mst_reqs, slv_reqs; - axi_lite_resp_t [NoSlvMst-1:0] mst_resps, slv_resps; + axi_lite_req_t [NoSlvMst-1:0] mst_reqs, slv_reqs; + axi_lite_rsp_t [NoSlvMst-1:0] mst_resps, slv_resps; axi_lite_xbar #( .Cfg ( XbarCfg ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), .rule_t ( axi_pkg::xbar_rule_32_t ) ) i_xbar_dut ( .clk_i ( clk_i ), diff --git a/test/tb_axi_lite_to_apb.sv b/test/tb_axi_lite_to_apb.sv index fdf7349a7..967acb977 100644 --- a/test/tb_axi_lite_to_apb.sv +++ b/test/tb_axi_lite_to_apb.sv @@ -51,7 +51,7 @@ module tb_axi_lite_to_apb #( `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) typedef logic [NoApbSlaves-1:0] sel_t; @@ -69,7 +69,7 @@ module tb_axi_lite_to_apb #( logic pready; data_t prdata; logic pslverr; - } apb_resp_t; + } apb_rsp_t; localparam rule_t [NoAddrRules-1:0] AddrMap = '{ '{idx: 32'd7, start_addr: 32'h0001_0000, end_addr: 32'h0001_1000}, @@ -113,12 +113,12 @@ module tb_axi_lite_to_apb #( logic end_of_sim; // master structs - axi_lite_req_t axi_req; - axi_lite_resp_t axi_resp; + axi_lite_req_t axi_req; + axi_lite_rsp_t axi_resp; // slave structs - apb_req_t [NoApbSlaves-1:0] apb_req; - apb_resp_t [NoApbSlaves-1:0] apb_resps; + apb_req_t [NoApbSlaves-1:0] apb_req; + apb_rsp_t [NoApbSlaves-1:0] apb_resps; // ------------------------------- // AXI Interfaces @@ -235,9 +235,9 @@ module tb_axi_lite_to_apb #( .PipelineRequest ( TbPipelineRequest ), .PipelineResponse ( TbPipelineResponse ), .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_resp_t ( axi_lite_resp_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), .apb_req_t ( apb_req_t ), - .apb_resp_t ( apb_resp_t ), + .apb_rsp_t ( apb_rsp_t ), .rule_t ( rule_t ) ) i_axi_lite_to_apb_dut ( .clk_i ( clk ), diff --git a/test/tb_axi_sim_mem.sv b/test/tb_axi_sim_mem.sv index 7383a9b31..726c25765 100644 --- a/test/tb_axi_sim_mem.sv +++ b/test/tb_axi_sim_mem.sv @@ -43,17 +43,17 @@ module tb_axi_sim_mem #( `AXI_TYPEDEF_AR_CHAN_T(ar_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_t, w_t, ar_t) - `AXI_TYPEDEF_RESP_T(axi_resp_t, b_t, r_t) + `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_t, r_t) axi_req_t req; - axi_resp_t rsp; + axi_rsp_t rsp; axi_sim_mem #( .AddrWidth (TbAddrWidth), .DataWidth (TbDataWidth), .IdWidth (TbIdWidth), .UserWidth (TbUserWidth), .axi_req_t (axi_req_t), - .axi_resp_t (axi_resp_t), + .axi_rsp_t (axi_rsp_t), .WarnUninitialized (TbWarnUninitialized), .ApplDelay (TbApplDelay), .AcqDelay (TbAcqDelay) diff --git a/test/tb_axi_xbar.sv b/test/tb_axi_xbar.sv index 736e2a265..b5c857b26 100644 --- a/test/tb_axi_xbar.sv +++ b/test/tb_axi_xbar.sv @@ -80,9 +80,9 @@ module tb_axi_xbar #( `AXI_TYPEDEF_R_CHAN_T(r_chan_slv_t, data_t, id_slv_t, user_t) `AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t) - `AXI_TYPEDEF_RESP_T(mst_resp_t, b_chan_mst_t, r_chan_mst_t) + `AXI_TYPEDEF_RSP_T(mst_rsp_t, b_chan_mst_t, r_chan_mst_t) `AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t) - `AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_slv_t, r_chan_slv_t) + `AXI_TYPEDEF_RSP_T(slv_rsp_t, b_chan_slv_t, r_chan_slv_t) localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = '{ '{idx: 32'd7 % TbNumSlv, start_addr: 32'h0001_0000, end_addr: 32'h0001_1000}, @@ -131,12 +131,12 @@ module tb_axi_xbar #( logic [TbNumMst-1:0] end_of_sim; // master structs - mst_req_t [TbNumMst-1:0] masters_req; - mst_resp_t [TbNumMst-1:0] masters_resp; + mst_req_t [TbNumMst-1:0] masters_req; + mst_rsp_t [TbNumMst-1:0] masters_resp; // slave structs - slv_req_t [TbNumSlv-1:0] slaves_req; - slv_resp_t [TbNumSlv-1:0] slaves_resp; + slv_req_t [TbNumSlv-1:0] slaves_req; + slv_rsp_t [TbNumSlv-1:0] slaves_resp; // ------------------------------- // AXI Interfaces