diff --git a/.ci/Memora.yml b/.ci/Memora.yml index 176afb4ff..f5171beb0 100644 --- a/.ci/Memora.yml +++ b/.ci/Memora.yml @@ -209,7 +209,7 @@ artifacts: - src/axi_pkg.sv - src/axi_intf.sv - src/axi_test.sv - - src/axi_err_slv.sv + - src/axi_err_sbr.sv - src/axi_lite_demux.sv - src/axi_lite_mux.sv - src/axi_lite_to_axi.sv @@ -296,7 +296,7 @@ artifacts: - src/axi_intf.sv - src/axi_test.sv - src/axi_demux.sv - - src/axi_err_slv.sv + - src/axi_err_sbr.sv - src/axi_mux.sv - src/axi_xbar.sv - test/tb_axi_xbar.sv diff --git a/Bender.yml b/Bender.yml index 7a348ac14..c7486f757 100644 --- a/Bender.yml +++ b/Bender.yml @@ -62,12 +62,12 @@ sources: - src/axi_rw_join.sv - src/axi_rw_split.sv - src/axi_serializer.sv - - src/axi_slave_compare.sv + - src/axi_subordinate_compare.sv - src/axi_throttle.sv - src/axi_to_mem.sv # Level 3 - src/axi_cdc.sv - - src/axi_err_slv.sv + - src/axi_err_sbr.sv - src/axi_dw_converter.sv - src/axi_from_mem.sv - src/axi_id_serialize.sv @@ -119,7 +119,7 @@ sources: - test/tb_axi_modify_address.sv - test/tb_axi_serializer.sv - test/tb_axi_sim_mem.sv - - test/tb_axi_slave_compare.sv + - test/tb_axi_subordinate_compare.sv - test/tb_axi_to_axi_lite.sv - test/tb_axi_to_mem_banked.sv - test/tb_axi_xbar.sv diff --git a/README.md b/README.md index 012703744..6642faad9 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # AXI SystemVerilog Modules for High-Performance On-Chip Communication -[![CI status](https://akurth.net/usrv/ig/shields/pipeline/akurth/axi/master.svg)](https://iis-git.ee.ethz.ch/akurth/axi/commits/master) +[![CI status](https://akurth.net/usrv/ig/shields/pipeline/akurth/axi/manager.svg)](https://iis-git.ee.ethz.ch/akurth/axi/commits/manager) [![GitHub tag (latest SemVer)](https://img.shields.io/github/v/tag/pulp-platform/axi?color=blue&label=current&sort=semver)](CHANGELOG.md) [![SHL-0.51 license](https://img.shields.io/badge/license-SHL--0.51-green)](LICENSE) @@ -26,44 +26,44 @@ In addition to the documents linked in the following table, we are setting up [d | [`axi_cdc`](src/axi_cdc.sv) | AXI clock domain crossing based on a Gray FIFO implementation. | | | [`axi_cut`](src/axi_cut.sv) | Breaks all combinatorial paths between its input and output. | | | [`axi_delayer`](src/axi_delayer.sv) | Synthesizable module which can (randomly) delays AXI channels. | | -| [`axi_demux`](src/axi_demux.sv) | Demultiplexes an AXI bus from one slave port to multiple master ports. | [Doc](doc/axi_demux.md) | +| [`axi_demux`](src/axi_demux.sv) | Demultiplexes an AXI bus from one subordinate port to multiple manager ports. | [Doc](doc/axi_demux.md) | | [`axi_dw_converter`](src/axi_dw_converter.sv) | A data width converter between AXI interfaces of any data width. | | -| [`axi_dw_downsizer`](src/axi_dw_downsizer.sv) | A data width converter between a wide AXI master and a narrower AXI slave. | | -| [`axi_dw_upsizer`](src/axi_dw_upsizer.sv) | A data width converter between a narrow AXI master and a wider AXI slave. | | -| [`axi_err_slv`](src/axi_err_slv.sv) | Always responds with an AXI decode/slave error for transactions which are sent to it. | | +| [`axi_dw_downsizer`](src/axi_dw_downsizer.sv) | A data width converter between a wide AXI manager and a narrower AXI subordinate. | | +| [`axi_dw_upsizer`](src/axi_dw_upsizer.sv) | A data width converter between a narrow AXI manager and a wider AXI subordinate. | | +| [`axi_err_sbr`](src/axi_err_sbr.sv) | Always responds with an AXI decode/subordinate error for transactions which are sent to it. | | | [`axi_fifo`](src/axi_fifo.sv) | A Fifo for each AXI4 channel to buffer requests. | | | [`axi_from_mem`](src/axi_from_mem.sv) | This module acts like an SRAM and makes AXI4 requests downstream. | | | [`axi_id_prepend`](src/axi_id_prepend.sv) | This module prepends/strips the MSB from the AXI IDs. | | -| [`axi_id_remap`](src/axi_id_remap.sv) | Remap AXI IDs from wide IDs at the slave port to narrower IDs at the master port. | [Doc][doc.axi_id_remap] | +| [`axi_id_remap`](src/axi_id_remap.sv) | Remap AXI IDs from wide IDs at the subordinate port to narrower IDs at the manager port. | [Doc][doc.axi_id_remap] | | [`axi_id_serialize`](src/axi_id_serialize.sv) | Reduce AXI IDs by serializing transactions when necessary. | [Doc][doc.axi_id_serialize] | | [`axi_intf`](src/axi_intf.sv) | This file defines the interfaces we support. | | -| [`axi_isolate`](src/axi_isolate.sv) | A module that can isolate downstream slaves from receiving new AXI4 transactions. | | +| [`axi_isolate`](src/axi_isolate.sv) | A module that can isolate downstream subordinates from receiving new AXI4 transactions. | | | [`axi_iw_converter`](src/axi_iw_converter.sv) | Convert between any two AXI ID widths. | [Doc][doc.axi_iw_converter] | | [`axi_join`](src/axi_join.sv) | A connector that joins two AXI interfaces. | | | [`axi_lfsr`](src/axi_lfsr.sv) | AXI4-attached LFSR; read returns pseudo-random data, writes are compressed into a checksum. | | -| [`axi_lite_demux`](src/axi_lite_demux.sv) | Demultiplexes an AXI4-Lite bus from one slave port to multiple master ports. | [Doc](doc/axi_lite_demux.md) | +| [`axi_lite_demux`](src/axi_lite_demux.sv) | Demultiplexes an AXI4-Lite bus from one subordinate port to multiple manager ports. | [Doc](doc/axi_lite_demux.md) | | [`axi_lite_from_mem`](src/axi_lite_from_mem.sv) | This module acts like an SRAM and makes AXI4-Lite requests downstream. | | | [`axi_lite_join`](src/axi_lite_join.sv) | A connector that joins two AXI-Lite interfaces. | | | [`axi_lite_lfsr`](src/axi_lite_lfsr.sv) | AXI4-Lite-attached LFSR; read returns pseudo-random data, writes are compressed into a checksum. | | -| [`axi_lite_mailbox`](src/axi_lite_mailbox.sv) | A AXI4-Lite Mailbox with two slave ports and usage triggered irq. | [Doc](doc/axi_lite_mailbox.md) | -| [`axi_lite_mux`](src/axi_lite_mux.sv) | Multiplexes AXI4-Lite slave ports down to one master port. | [Doc](doc/axi_lite_mux.md) | +| [`axi_lite_mailbox`](src/axi_lite_mailbox.sv) | A AXI4-Lite Mailbox with two subordinate ports and usage triggered irq. | [Doc](doc/axi_lite_mailbox.md) | +| [`axi_lite_mux`](src/axi_lite_mux.sv) | Multiplexes AXI4-Lite subordinate ports down to one manager port. | [Doc](doc/axi_lite_mux.md) | | [`axi_lite_regs`](src/axi_lite_regs.sv) | AXI4-Lite registers with optional read-only and protection features. | [Doc][doc.axi_lite_regs] | | [`axi_lite_to_apb`](src/axi_lite_to_apb.sv) | AXI4-Lite to APB4 protocol converter. | | | [`axi_lite_to_axi`](src/axi_lite_to_axi.sv) | AXI4-Lite to AXI4 protocol converter. | | -| [`axi_lite_xbar`](src/axi_lite_xbar.sv) | Fully-connected AXI4-Lite crossbar with an arbitrary number of slave and master ports. | [Doc](doc/axi_lite_xbar.md) | +| [`axi_lite_xbar`](src/axi_lite_xbar.sv) | Fully-connected AXI4-Lite crossbar with an arbitrary number of subordinate and manager ports. | [Doc](doc/axi_lite_xbar.md) | | [`axi_modify_address`](src/axi_modify_address.sv) | A connector that allows addresses of AXI requests to be changed. | | | [`axi_multicut`](src/axi_multicut.sv) | AXI register which can be used to relax timing pressure on long AXI buses. | | -| [`axi_mux`](src/axi_mux.sv) | Multiplexes the AXI4 slave ports down to one master port. | [Doc](doc/axi_mux.md) | +| [`axi_mux`](src/axi_mux.sv) | Multiplexes the AXI4 subordinate ports down to one manager port. | [Doc](doc/axi_mux.md) | | [`axi_pkg`](src/axi_pkg.sv) | Contains AXI definitions, common structs, and useful helper functions. | | -| [`axi_rw_join`](src/axi_rw_join.sv) | Joins a read and a write slave into one single read / write master. | | -| [`axi_rw_split`](src/axi_rw_split.sv) | Splits a single read / write slave into one read and one write master. | | +| [`axi_rw_join`](src/axi_rw_join.sv) | Joins a read and a write subordinate into one single read / write manager. | | +| [`axi_rw_split`](src/axi_rw_split.sv) | Splits a single read / write subordinate into one read and one write manager. | | | [`axi_serializer`](src/axi_serializer.sv) | Serializes transactions with different IDs to the same ID. | | | [`axi_throttle`](src/axi_throttle.sv) | Limits the maximum number of outstanding transfers sent to the downstream logic. | | | [`axi_test`](src/axi_test.sv) | A set of testbench utilities for AXI interfaces. | | | [`axi_to_axi_lite`](src/axi_to_axi_lite.sv) | AXI4 to AXI4-Lite protocol converter. | | | [`axi_to_mem`](src/axi_to_mem.sv) | AXI4 to memory protocol (req, gnt, rvalid) converter. Additional banked, interleaved, split variant. | | -| [`axi_xbar`](src/axi_xbar.sv) | Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. | [Doc](doc/axi_xbar.md) | -| [`axi_xp`](src/axi_xp.sv) | AXI Crosspoint (XP) with homomorphous slave and master ports. | | +| [`axi_xbar`](src/axi_xbar.sv) | Fully-connected AXI4+ATOP crossbar with an arbitrary number of subordinate and manager ports. | [Doc](doc/axi_xbar.md) | +| [`axi_xp`](src/axi_xp.sv) | AXI Crosspoint (XP) with homomorphous subordinate and manager ports. | | ## Synthesizable Verification Modules @@ -72,7 +72,7 @@ The following modules are meant to be used for verification purposes only but ar | Name | Description | |------------------------------------------------------|---------------------------------------------------------------------------------------------------------| | [`axi_bus_compare`](src/axi_bus_compare.sv) | Compares two buses of the same type (and in the same clock domain), returns events on mismatch. | -| [`axi_slave_compare`](src/axi_slave_compare.sv) | Compares two slave devices of the same type (and in the same clock domain), returns events on mismatch. | +| [`axi_subordinate_compare`](src/axi_subordinate_compare.sv) | Compares two subordinate devices of the same type (and in the same clock domain), returns events on mismatch. | ### Simulation-Only Modules @@ -85,12 +85,12 @@ In addition to the modules above, which are available in synthesis and simulatio | [`axi_driver`](src/axi_test.sv) | Low-level driver for AXI4(+ATOPs) that can send and receive individual beats on any channel. | | [`axi_dumper`](src/axi_dumper.sv) | Dumps log to file to be interpreted by `axi_dumper_interpret` script for debugging purposes. | | [`axi_lite_driver`](src/axi_test.sv) | Low-level driver for AXI4-Lite that can send and receive individual beats on any channel. | -| [`axi_lite_rand_master`](src/axi_test.sv) | AXI4-Lite master component that issues random transactions within user-defined constraints. | -| [`axi_lite_rand_slave`](src/axi_test.sv) | AXI4-Lite slave component that responds to transactions with constrainable random delays and data. | -| [`axi_rand_master`](src/axi_test.sv) | AXI4(+ATOPs) master component that issues random transactions within user-defined constraints. | -| [`axi_rand_slave`](src/axi_test.sv) | AXI4(+ATOPs) slave component that responds to transactions with constrainable random delays and data. | +| [`axi_lite_rand_manager`](src/axi_test.sv) | AXI4-Lite manager component that issues random transactions within user-defined constraints. | +| [`axi_lite_rand_subordinate`](src/axi_test.sv) | AXI4-Lite subordinate component that responds to transactions with constrainable random delays and data. | +| [`axi_rand_manager`](src/axi_test.sv) | AXI4(+ATOPs) manager component that issues random transactions within user-defined constraints. | +| [`axi_rand_subordinate`](src/axi_test.sv) | AXI4(+ATOPs) subordinate component that responds to transactions with constrainable random delays and data. | | [`axi_scoreboard`](src/axi_test.sv) | Scoreboard that models a memory that only gets changed by the monitored AXI4(+ATOPs) port. | -| [`axi_sim_mem`](src/axi_sim_mem.sv) | Infinite memory with AXI4 slave port. | +| [`axi_sim_mem`](src/axi_sim_mem.sv) | Infinite memory with AXI4 subordinate port. | @@ -98,14 +98,14 @@ In addition to the modules above, which are available in synthesis and simulatio AXI4+ATOPs means the full AXI4 specification plus atomic operations (ATOPs) as defined in Section E1.1 of the [AMBA 5 specification][AMBA 5 Spec]. This has the following implications for modules that do not implement ATOPs and systems that include such modules: -- Masters that do not issue ATOPs must set `aw_atop` to `'0`. -- Slaves that do not support ATOPs must specify this in their interface documentation and can ignore the `aw_atop` signal. +- Managers that do not issue ATOPs must set `aw_atop` to `'0`. +- Subordinates that do not support ATOPs must specify this in their interface documentation and can ignore the `aw_atop` signal. - System designers are responsible for ensuring that - 1. slaves that do not support ATOPs are behind an [`axi_atop_filter`](src/axi_atop_filter.sv) if any master could issue an ATOP to such slaves and + 1. subordinates that do not support ATOPs are behind an [`axi_atop_filter`](src/axi_atop_filter.sv) if any manager could issue an ATOP to such subordinates and 2. the `aw_atop` signal is well-defined at the input of any (non-AXI4-Lite) module in this repository. -Masters and slaves that do support ATOPs must adhere to Section E1.1 of the [AMBA 5 specification][AMBA 5 Spec]. In particular: -- ATOPs that have the `aw_atop[axi_pkg::ATOP_R_RESP]` bit set generate a write response (B channel) beat and at least one read response (R channel) beat. All modules for which the `aw_atop[axi_pkg::ATOP_R_RESP]` bit could be set at their master port must be able to handle both B and R beats (in any order and without requiring a simultaneous handshake) for each such ATOP request. All modules for which the `aw_atop[axi_pkg::ATOP_R_RESP]` bit could be set at their slave port must respond with the appropriate number of B and R beats for each such ATOP request. +Managers and subordinates that do support ATOPs must adhere to Section E1.1 of the [AMBA 5 specification][AMBA 5 Spec]. In particular: +- ATOPs that have the `aw_atop[axi_pkg::ATOP_R_RESP]` bit set generate a write response (B channel) beat and at least one read response (R channel) beat. All modules for which the `aw_atop[axi_pkg::ATOP_R_RESP]` bit could be set at their manager port must be able to handle both B and R beats (in any order and without requiring a simultaneous handshake) for each such ATOP request. All modules for which the `aw_atop[axi_pkg::ATOP_R_RESP]` bit could be set at their subordinate port must respond with the appropriate number of B and R beats for each such ATOP request. - ATOPs must not use the same AXI ID as any other transaction that is outstanding at the same time. diff --git a/axi.core b/axi.core index e75ed636f..9b1086eac 100644 --- a/axi.core +++ b/axi.core @@ -44,12 +44,12 @@ filesets: - src/axi_rw_join.sv - src/axi_rw_split.sv - src/axi_serializer.sv - - src/axi_slave_compare.sv + - src/axi_subordinate_compare.sv - src/axi_throttle.sv - src/axi_to_mem.sv # Level 3 - src/axi_cdc.sv - - src/axi_err_slv.sv + - src/axi_err_sbr.sv - src/axi_dw_converter.sv - src/axi_from_mem.sv - src/axi_id_serialize.sv @@ -95,7 +95,7 @@ filesets: - test/tb_axi_modify_address.sv - test/tb_axi_serializer.sv - test/tb_axi_sim_mem.sv - - test/tb_axi_slave_compare.sv + - test/tb_axi_subordinate_compare.sv - test/tb_axi_to_axi_lite.sv - test/tb_axi_to_mem_banked.sv - test/tb_axi_xbar.sv @@ -116,34 +116,34 @@ generators: module where the interconnect wrapper is intended to be used. Parameters: - masters: A dictionary where each key names a master interface connecting + managers: A dictionary where each key names a manager interface connecting to the interconnect and the associated value contains configuration for that interface. - id_width (int): Width of the id signals for the master + id_width (int): Width of the id signals for the manager - slaves: A dictionary where each key names a slave interface connecting + subordinates: A dictionary where each key names a subordinate interface connecting to the interconnect and the associated value contains configuration for that interface. The following configuration keys are defined - offset (int): Base address for the slave - size (int): Size of the allocated memory map for the slave + offset (int): Base address for the subordinate + size (int): Size of the allocated memory map for the subordinate Example usage: The following config will generate an interconnect wrapper to which two - AXI4 master interfaces (dma and ibus) with different id widths are - connected, and connects downstream to three AXI4 slaves (rom, gpio, ram) + AXI4 manager interfaces (dma and ibus) with different id widths are + connected, and connects downstream to three AXI4 subordinates (rom, gpio, ram) soc_intercon: generator: axi_intercon_gen parameters: - masters: + managers: dma: id_width : 1 ibus: id_width : 2 - slaves: + subordinates: ram: offset : 0 size: 0x10000000 diff --git a/doc/axi_demux.md b/doc/axi_demux.md index 43008ba64..980bebf07 100644 --- a/doc/axi_demux.md +++ b/doc/axi_demux.md @@ -5,15 +5,15 @@ ## Design Overview -The demultiplexer has one *slave port* and a configurable number of *master ports*. A block diagram is shown below: +The demultiplexer has one *subordinate port* and a configurable number of *manager ports*. A block diagram is shown below: ![Block diagram of the AXI demultiplexer](axi_demux.png "Block diagram of the AXI demultiplexer") -The AW and AR channels each have a *select* input, to determine the master port to which they are sent. The select can, for example, be driven by an (external) address decoder to map address ranges to different AXI slaves. +The AW and AR channels each have a *select* input, to determine the manager port to which they are sent. The select can, for example, be driven by an (external) address decoder to map address ranges to different AXI subordinates. Beats on the W channel are routed by demultiplexer according to the selection for the corresponding AW beat. This relies on the AXI property that W bursts must be sent in the same order as AW beats and beats from different W bursts may not be interleaved. -Beats on the B and R channel are multiplexed from the master ports to the slave port with a round-robin arbitration tree. +Beats on the B and R channel are multiplexed from the manager ports to the subordinate port with a round-robin arbitration tree. ## Configuration @@ -23,11 +23,11 @@ This demultiplexer is configured through the parameters listed in the following | Name | Type | Definition | |:---------------------|:-------------------|:-----------| | `IdWidth` | `int unsigned` | The AXI ID width (of all ports). | -| `NumMstPorts` | `int unsigned` | The number of AXI master ports of the demultiplexer (in other words, how many AXI slave modules can be attached). | -| `MaxTrans` | `int unsigned` | The slave port can have at most this many transactions [in flight](../doc#in-flight). | +| `NumMgrPorts` | `int unsigned` | The number of AXI manager ports of the demultiplexer (in other words, how many AXI subordinate modules can be attached). | +| `MaxTrans` | `int unsigned` | The subordinate port can have at most this many transactions [in flight](../doc#in-flight). | | `LookBits` | `int unsigned` | The number of ID bits (starting at the least significant) the demultiplexer uses to determine the uniqueness of an AXI ID (see section *Ordering and Stalls* below). This value has to be less or equal than `IdWidth`. | | `UniqueIds` | `bit` | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the demultiplexer (see section *Ordering and Stalls* below). Defaults to `1'b0`. | -| `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel. Enabling this allows the demultiplexer to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from `slv_aw_select_i`. | +| `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel. Enabling this allows the demultiplexer to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from `sbr_aw_select_i`. | | `SpillXX` | `bit` | Inserts one spill register on the respective channel (AW, W, B, AR, and R) before the demultiplexer. | The other parameters are types to define the ports of the demultiplexer. The `_*chan_t` types must be bound in accordance to the configuration using the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. @@ -46,21 +46,21 @@ If all `SpillXX` and `FallThrough` are disabled, all paths through this multiple | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | | `test_i` | Test mode enable (active-high). | -| `slv_*` (except `slv_*_select_i`) | Single slave port of the demultiplexer. | -| `slv_{aw,ar}_select_i` | Index of the master port to which a write or read, respectively, is demultiplexed. This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). | -| `mst_*` | Array of master ports of the demultiplexer. The array index of each port is the index of the master port. | +| `sbr_*` (except `sbr_*_select_i`) | Single subordinate port of the demultiplexer. | +| `sbr_{aw,ar}_select_i` | Index of the manager port to which a write or read, respectively, is demultiplexed. This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). | +| `mgr_*` | Array of manager ports of the demultiplexer. The array index of each port is the index of the manager port. | ## Ordering and Stalls -When the demultiplexer receives two transactions with the same ID and direction (i.e., both read or both write) but targeting two different master ports, it will not accept the second transaction until the first has completed. During this time, the demultiplexer stalls the AR or AW channel, respectively. To determine whether two transactions have the same ID, the `LookBits` least-significant bits are compared. That parameter can be set to the full `IdWidth` to avoid false ID conflicts, or it can be set to a lower value to reduce area and delay at the cost of more false conflicts. +When the demultiplexer receives two transactions with the same ID and direction (i.e., both read or both write) but targeting two different manager ports, it will not accept the second transaction until the first has completed. During this time, the demultiplexer stalls the AR or AW channel, respectively. To determine whether two transactions have the same ID, the `LookBits` least-significant bits are compared. That parameter can be set to the full `IdWidth` to avoid false ID conflicts, or it can be set to a lower value to reduce area and delay at the cost of more false conflicts. The reason for this behavior are AXI ordering constraints, see the [documentation of the crossbar](axi_xbar.md#ordering-and-stalls) for details. There are use cases that do not require the demultiplexer to keep track of and enforce this ordering, and the `UniqueIds` parameter can be set to specialize the demultiplexer for these cases: `UniqueIds` may be set to `1'b1` if and only if - each transaction has an ID that is unique among all in-flight transactions in the same direction; -- or for any ID, all transactions with that ID target the same master port as all other in-flight transactions with the same ID and direction; +- or for any ID, all transactions with that ID target the same manager port as all other in-flight transactions with the same ID and direction; - or both. Setting the `UniqueIds` parameter to `1'b1` when those conditions are not always met leads to undefined behavior. @@ -69,11 +69,11 @@ Setting the `UniqueIds` parameter to `1'b1` reduces the area complexity of the d ### Implementation -`2 * 2^LookBits` counters track the number of [in-flight](../doc#in-flight) transactions. That is, for each ID in the (potentially) reduced set of IDs of `LookBits` bits, there is one counter for write transactions and one for read transactions. Each counter can count up to (and including) `MaxTrans`, and there is a register that holds the index of the master port to which a counter is assigned. +`2 * 2^LookBits` counters track the number of [in-flight](../doc#in-flight) transactions. That is, for each ID in the (potentially) reduced set of IDs of `LookBits` bits, there is one counter for write transactions and one for read transactions. Each counter can count up to (and including) `MaxTrans`, and there is a register that holds the index of the manager port to which a counter is assigned. -When the demultiplexer gets an AW or an AR, it indexes the counters with the AXI ID. If the indexed counter has a value greater than zero and its master port index register is not equal to the index to which the AW or AR is to be sent, a transaction with the same direction and ID is already in flight to another master port. The demultiplexer then stalls the AW or AR. In all other cases, the demultiplexer forwards the AW or AR, increments the value of the indexed counter, and sets the master port index of the counter. A counter is decremented upon a handshake a B respectively last R beat at a slave port. +When the demultiplexer gets an AW or an AR, it indexes the counters with the AXI ID. If the indexed counter has a value greater than zero and its manager port index register is not equal to the index to which the AW or AR is to be sent, a transaction with the same direction and ID is already in flight to another manager port. The demultiplexer then stalls the AW or AR. In all other cases, the demultiplexer forwards the AW or AR, increments the value of the indexed counter, and sets the manager port index of the counter. A counter is decremented upon a handshake a B respectively last R beat at a subordinate port. -W beats are routed to the master port defined by the value of `slv_aw_select_i` for the corresponding AW. As the order of the W bursts is given by the order of the AWs, the select signals are stored in a FIFO queue. This FIFO is pushed upon a handshake on the AW slave channel and popped upon a handshake of the last W beat of a burst on a W master channel. +W beats are routed to the manager port defined by the value of `sbr_aw_select_i` for the corresponding AW. As the order of the W bursts is given by the order of the AWs, the select signals are stored in a FIFO queue. This FIFO is pushed upon a handshake on the AW subordinate channel and popped upon a handshake of the last W beat of a burst on a W manager channel. ## Atomic Transactions diff --git a/doc/axi_lite_demux.md b/doc/axi_lite_demux.md index f3cfbd322..e94c88ef7 100644 --- a/doc/axi_lite_demux.md +++ b/doc/axi_lite_demux.md @@ -4,13 +4,13 @@ ## Design Overview -The demultiplexer has one *slave port* and a configurable number of *master ports*. +The demultiplexer has one *subordinate port* and a configurable number of *manager ports*. -The AW and AR channels each have a *select* input, to determine the master port to which they are sent. The select can, for example, be driven by an (external) address decoder to map address ranges to different AXI4-Lite slaves. +The AW and AR channels each have a *select* input, to determine the manager port to which they are sent. The select can, for example, be driven by an (external) address decoder to map address ranges to different AXI4-Lite subordinates. Beats on the W channel are routed by the demultiplexer with the same selection as the corresponding AW beat. -Beats on the B and R channel are multiplexed from the master ports by the switching decision saved in their respective FIFO's. +Beats on the B and R channel are multiplexed from the manager ports by the switching decision saved in their respective FIFO's. ## Configuration @@ -19,9 +19,9 @@ This demultiplexer is configured through the parameters listed in the following | Name | Type | Definition | |:---------------------|:-------------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| `NumMstPorts` | `int unsigned` | The number of AXI4-Lite master ports of the demultiplexer (in other words, how many AXI4-Lite slave modules can be attached). | -| `MaxTrans` | `int unsigned` | The slave port can have at most this many transactions [in flight](../doc#in-flight). | -| `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel (i.e. don't consume a cycle). Enabling this allows the demultiplexer to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from `slv_aw_select_i`. | +| `NumMgrPorts` | `int unsigned` | The number of AXI4-Lite manager ports of the demultiplexer (in other words, how many AXI4-Lite subordinate modules can be attached). | +| `MaxTrans` | `int unsigned` | The subordinate port can have at most this many transactions [in flight](../doc#in-flight). | +| `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel (i.e. don't consume a cycle). Enabling this allows the demultiplexer to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from `sbr_aw_select_i`. | | `SpillXX` | `bit` | Inserts one spill register on the respective channel (AW, W, B, AR, and R) before the demultiplexer. | The other parameters are types to define the ports of the demultiplexer. The `_*chan_t` types must be bound in accordance to the configuration using the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. @@ -39,13 +39,13 @@ If all `SpillXX` and `FallThrough` are disabled, all paths through this multiple | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | | `test_i` | Test mode enable (active-high). | -| `slv_*` (except `slv_*_select_i`) | Single slave port of the demultiplexer. | -| `slv_{aw,ar}_select_i` | Index of the master port to which a write or read, respectively, is demultiplexed. This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). | -| `mst_*` | Array of master ports of the demultiplexer. The array index of each port is the index of the master port. | +| `sbr_*` (except `sbr_*_select_i`) | Single subordinate port of the demultiplexer. | +| `sbr_{aw,ar}_select_i` | Index of the manager port to which a write or read, respectively, is demultiplexed. This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). | +| `mgr_*` | Array of manager ports of the demultiplexer. The array index of each port is the index of the manager port. | ### Implementation -W beats are routed to the master port defined by the value of `slv_aw_select_i` for the corresponding AW. As the order of the W transactions is given by the order of the AWs, the select signals are stored in a FIFO. This FIFO is pushed upon a handshake on the AW slave channel and popped upon a handshake of the corresponding W transaction. +W beats are routed to the manager port defined by the value of `sbr_aw_select_i` for the corresponding AW. As the order of the W transactions is given by the order of the AWs, the select signals are stored in a FIFO. This FIFO is pushed upon a handshake on the AW subordinate channel and popped upon a handshake of the corresponding W transaction. The demultiplexer saves the routing decision in their respective FIFO for the response routing. diff --git a/doc/axi_lite_mailbox.md b/doc/axi_lite_mailbox.md index 10398622b..c6c3f587e 100644 --- a/doc/axi_lite_mailbox.md +++ b/doc/axi_lite_mailbox.md @@ -1,6 +1,6 @@ # AXI4-Lite Mailbox -`axi_lite_mailbox` implements a hardware mailbox, where two AXI4-Lite slave ports are connected to each other over two FIFOs. Data written on port 0 is made available on the read data at port 1 and vice versa. +`axi_lite_mailbox` implements a hardware mailbox, where two AXI4-Lite subordinate ports are connected to each other over two FIFOs. Data written on port 0 is made available on the read data at port 1 and vice versa. The module features an interrupt for each port which can be enabled with the [IRQEN](#irqen-register) register. Interrupts can be configured to trigger depending on the fill levels of the read ([RIRQT](#rirqt-register)) and write ([WIRQT](#wirqt-register)) FIFO. It is further possible to trigger an interrupt on an mailbox error condition as defined by the [ERROR](#error-register) register. @@ -10,7 +10,7 @@ This table describes the parameters of the module. | Name | Type | Description | |:---------------|:---------------|:---------------------------------------------------------------------------------------------| -| `MailboxDepth` | `int unsigned `| The depth of the FIFOs between the two slave ports, min `32'd2` | +| `MailboxDepth` | `int unsigned `| The depth of the FIFOs between the two subordinate ports, min `32'd2` | | `IrqEdgeTrig` | `bit` | Interrupts trigger mode.
[0]: level trigger
[1]: edge trigger | | `IrqActHigh` | `bit` | Interrupts polarity.
[0]: active low / falling edge
[1]: active high / rising edge | | `AddrWidth` | `int unsigned` | The AXI4-Lite address width on the AW and AR channels | @@ -28,8 +28,8 @@ This table describes the ports of the module. | `clk_i` | `input logic` | clock | | `rst_ni` | `input logic` | asynchronous reset active low | | `test_i` | `input logic` | testmode enable | -| `slv_reqs_i` | `input req_lite_t [1:0]` | requests of the two AXI4-Lite ports | -| `slv_rsps_o` | `output rsp_lite_t [1:0]` | responses of the two AXI4-Lite ports | +| `sbr_reqs_i` | `input req_lite_t [1:0]` | requests of the two AXI4-Lite ports | +| `sbr_rsps_o` | `output rsp_lite_t [1:0]` | responses of the two AXI4-Lite ports | | `irq_o` | `output logic [1:0]` | interrupt output for each port | | `base_addr_i` | `input addr_t [1:0]` | base address for each port | @@ -57,13 +57,13 @@ Each register has one of the access types `R/W = read and write`, `R = read-only ### MBOXW Register -Mailbox write register. Write here to send data to the other slave port. A interrupt request will be raised when the fill pointer of the FIFO surpasses the [WIRQT Register](#wirqt-register) (if enabled). +Mailbox write register. Write here to send data to the other subordinate port. A interrupt request will be raised when the fill pointer of the FIFO surpasses the [WIRQT Register](#wirqt-register) (if enabled). Writes are ignored when the FIFO is full and a `axi_pkg::RESP_SLVERR` is returned. Additionally the corresponding bit in the [ERROR Register](#error-register) is set. ### MBOXR Register -Mailbox read register. Read here to receive data from the other slave port. A interrupt request will be raised when the fill pointer of the FIFO surpasses the [RIRQT Register](#rirqt-register) (if enabled). +Mailbox read register. Read here to receive data from the other subordinate port. A interrupt request will be raised when the fill pointer of the FIFO surpasses the [RIRQT Register](#rirqt-register) (if enabled). When the FIFO is empty, the read response `axi_pkg::RESP_SLVERR` is returned. Additionally the corresponding bit in the [ERROR Register](#error-register) is set. @@ -115,7 +115,7 @@ When a value larger than or equal to the `MailboxDepth` parameter is written to ### IRQS Register -Interrupt request status register. This register holds the current interrupt status of this slave port. There are three types of interrupts which can be enabled in the [IRQEN register](#irqen-register). The bits inside this register are sticky and get set when the trigger condition is fulfilled. This register has to be cleared explicitly by acknowledging the interrupt request status described below. This register will also get updated when the respective interrupt is not enabled. +Interrupt request status register. This register holds the current interrupt status of this subordinate port. There are three types of interrupts which can be enabled in the [IRQEN register](#irqen-register). The bits inside this register are sticky and get set when the trigger condition is fulfilled. This register has to be cleared explicitly by acknowledging the interrupt request status described below. This register will also get updated when the respective interrupt is not enabled. * `EIRQ`: Error interrupt request, is set to high when there was a read from an empty mailbox or a write to a full mailbox. * `RTIRQ`: Read threshold interrupt request, is set to high when the fill pointer of the FIFO connected to the R channel is higher than the threshold set in `RIRQT`. * `WTIRQ`: Write threshold interrupt request, is set to high when the fill pointer of the FIFO connected to the W channel is higher than the threshold set in `WIRQT`. @@ -143,7 +143,7 @@ Interrupt request enable register. Here the interrupts from [IRQS](#irqs-registe ### IRQP Register -Interrupt request pending register. This read-only register holds the pending interrupts for this slave port. It is generated by the bitwise AND of the [IRQS](#irqs-register) and [IRQEN](#irqen-register) registers. +Interrupt request pending register. This read-only register holds the pending interrupts for this subordinate port. It is generated by the bitwise AND of the [IRQS](#irqs-register) and [IRQEN](#irqen-register) registers. An interrupt gets triggered by the OR of the bits of this register. | Bit(s) | Name | Access Type | Reset Value | Description | @@ -156,7 +156,7 @@ An interrupt gets triggered by the OR of the bits of this register. ### CTRL Register -Mailbox control register. Here the FIFOs can be cleared from each interface. The flush signal of each FIFO is the OR combination of the respective bit of this register at each slave port. On register write, the FIFO is cleared and the register is reset. +Mailbox control register. Here the FIFOs can be cleared from each interface. The flush signal of each FIFO is the OR combination of the respective bit of this register at each subordinate port. On register write, the FIFO is cleared and the register is reset. | Bit(s) | Name | Access Type | Reset Value | Description | |:---------------:|:--------:|:-----------:|:-----------:|:---------------------------------------------| diff --git a/doc/axi_lite_mux.md b/doc/axi_lite_mux.md index 67d596975..453fdb572 100644 --- a/doc/axi_lite_mux.md +++ b/doc/axi_lite_mux.md @@ -1,6 +1,6 @@ # AXI4-Lite Multiplexer -The opposite function to the AXI4-Lite demultiplexer is performed by the AXI4-Lite Multiplexer. It merges multiple AXI4-Lite connections into one. The requests from multiple slave ports get interleaved and transmitted over a single master port. +The opposite function to the AXI4-Lite demultiplexer is performed by the AXI4-Lite Multiplexer. It merges multiple AXI4-Lite connections into one. The requests from multiple subordinate ports get interleaved and transmitted over a single manager port. ![Block-diagram of the AXI4-Lite Multiplexer Module.](axi_lite_mux.png "Block-diagram of the AXI4-Lite Multiplexer Module.") @@ -10,7 +10,7 @@ The following table shows the parameters of the module. The module further requi | Name | Type | Function | |:--------------|:---------------|:---------------------------------------------------------------------------------------------------------------| -| `NumSlvPorts` | `int unsigned` | How many slave ports the multiplexer features. This many master modules can be connected to the multiplexer. | +| `NumSbrPorts` | `int unsigned` | How many subordinate ports the multiplexer features. This many manager modules can be connected to the multiplexer. | | `MaxWTrans` | `int unsigned` | The depth of the FIFO holding the highest bits of the ID between the AW and W channel. | | `FallThrough` | `bit` | Is the FIFO between the AW and W channel in fall-through mode. Enabling will lead to an additional delay cycle | | `SpillXX` | `bit` | Enables the optional spill-register on the respective channel. | diff --git a/doc/axi_lite_xbar.md b/doc/axi_lite_xbar.md index a1fd87c91..b3d86a7ed 100644 --- a/doc/axi_lite_xbar.md +++ b/doc/axi_lite_xbar.md @@ -4,22 +4,22 @@ ## Design Overview -`axi_lite_xbar` is a fully-connected crossbar, which means that each master module that is connected to a *slave port* for of the crossbar has direct wires to all slave modules that are connected to the *master ports* of the crossbar. +`axi_lite_xbar` is a fully-connected crossbar, which means that each manager module that is connected to a *subordinate port* for of the crossbar has direct wires to all subordinate modules that are connected to the *manager ports* of the crossbar. A block-diagram of the crossbar is shown below: ![Block-diagram showing the design of the full AXI4-Lite Crossbar.](axi_lite_xbar.png "Block-diagram showing the design of the full AXI4-Lite Crossbar.") -The crossbar has a configurable number of slave and master ports. +The crossbar has a configurable number of subordinate and manager ports. ## Address Map `axi_lite_xbar` uses the [same address decoding scheme](axi_xbar.md#address-map) as `axi_xbar`. -## Decode Errors and Default Slave Port +## Decode Errors and Default Subordinate Port -Each slave port has its own internal *decode error slave* module. If the address of a transaction does not match any rule, the transaction is routed to that decode error slave module. That module absorbs each transaction and responds with a decode error (with the proper number of beats). The data of each read response beat is `32'hBADCAB1E` (zero-extended or truncated to match the data width). +Each subordinate port has its own internal *decode error subordinate* module. If the address of a transaction does not match any rule, the transaction is routed to that decode error subordinate module. That module absorbs each transaction and responds with a decode error (with the proper number of beats). The data of each read response beat is `32'hBADCAB1E` (zero-extended or truncated to match the data width). -Each slave port can have a default master port. If the default master port is enabled for a slave port, any address on that slave port that does not match any rule is routed to the default master port instead of the decode error slave. The default master port can be enabled and changed at run time (it is an input signal to the crossbar), and the same restrictions as for the address map apply. +Each subordinate port can have a default manager port. If the default manager port is enabled for a subordinate port, any address on that subordinate port that does not match any rule is routed to the default manager port instead of the decode error subordinate. The default manager port can be enabled and changed at run time (it is an input signal to the crossbar), and the same restrictions as for the address map apply. ## Configuration @@ -28,14 +28,14 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg | Name | Type | Definition | |:------------------|:-------------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| `NumSlvPorts` | `int unsigned` | The number of AXI4-Lite slave ports of the crossbar (in other words, how many AXI4-Lite master modules can be attached). | -| `NumMstPorts` | `int unsigned` | The number of AXI4-Lite master ports of the crossbar (in other words, how many AXI4-Lite slave modules can be attached). | -| `MaxMstTrans` | `int unsigned` | Each slave port can have at most this many transactions [in flight](../doc#in-flight). | -| `MaxSlvTrans` | `int unsigned` | Each master port can have at most this many transactions [in flight](../doc#in-flight). | +| `NumSbrPorts` | `int unsigned` | The number of AXI4-Lite subordinate ports of the crossbar (in other words, how many AXI4-Lite manager modules can be attached). | +| `NumMgrPorts` | `int unsigned` | The number of AXI4-Lite manager ports of the crossbar (in other words, how many AXI4-Lite subordinate modules can be attached). | +| `MaxMgrTrans` | `int unsigned` | Each subordinate port can have at most this many transactions [in flight](../doc#in-flight). | +| `MaxSbrTrans` | `int unsigned` | Each manager port can have at most this many transactions [in flight](../doc#in-flight). | | `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel. Enabling this allows the crossbar to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from the AW channel. | | `LatencyMode` | `enum logic [9:0]` | Latency on the individual channels, defined in detail in section *Pipelining and Latency* below. | -| `IdWidthSlvPorts` | `int unsigned` | Not used by the AXI4-Lite crossbar. Set `default: '0`. | -| `IdUsedSlvPorts` | `int unsigned` | Not used by the AXI4-Lite crossbar. Set `default: '0`. | +| `IdWidthSbrPorts` | `int unsigned` | Not used by the AXI4-Lite crossbar. Set `default: '0`. | +| `IdUsedSbrPorts` | `int unsigned` | Not used by the AXI4-Lite crossbar. Set `default: '0`. | | `AddrWidth` | `int unsigned` | The AXI4-Lite address width. | | `DataWidth` | `int unsigned` | The AXI4-Lite data width. | | `NumAddrRules` | `int unsigned` | The number of address map rules. | @@ -44,10 +44,10 @@ The other parameters are types to define the ports of the crossbar. The `*_chan ### Pipelining and Latency -The `LatencyMode` parameter allows to insert spill registers after each channel (AW, W, B, AR, and R) of each master port (i.e., each multiplexer) and before each channel of each slave port (i.e., each demultiplexer). Spill registers cut combinatorial paths, so this parameter reduces the length of combinatorial paths through the crossbar. +The `LatencyMode` parameter allows to insert spill registers after each channel (AW, W, B, AR, and R) of each manager port (i.e., each multiplexer) and before each channel of each subordinate port (i.e., each demultiplexer). Spill registers cut combinatorial paths, so this parameter reduces the length of combinatorial paths through the crossbar. Some common configurations are given in the `xbar_latency_e` `enum`. The recommended configuration (`CUT_ALL_AX`) is to have a latency of 2 on the AW and AR channels because these channels have the most combinatorial logic on them. Additionally, `FallThrough` should be set to `0` to prevent logic on the AW channel from extending combinatorial paths on the W channel. However, it is possible to run the crossbar in a fully combinatorial configuration by setting `LatencyMode` to `NO_LATENCY` and `FallThrough` to `1`. -If two crossbars are connected in both directions, meaning both have one of their master_ports connected to a slave_port of the other, it is required to have either `CUT_SLV_PORTS`, `CUT_MST_PORTS` or `CUT_ALL_PORTS` as the configuration of the two crossbars. This is to prevent timing loops. The other configurations will lead to timing loops in simulation and synthesis on the not cut channels between the two crossbars. +If two crossbars are connected in both directions, meaning both have one of their manager_ports connected to a subordinate_port of the other, it is required to have either `CUT_SBR_PORTS`, `CUT_MGR_PORTS` or `CUT_ALL_PORTS` as the configuration of the two crossbars. This is to prevent timing loops. The other configurations will lead to timing loops in simulation and synthesis on the not cut channels between the two crossbars. ## Ports @@ -56,16 +56,16 @@ If two crossbars are connected in both directions, meaning both have one of thei | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | | `test_i` | Test mode enable (active-high). | -| `slv_ports_*` | Array of slave ports of the crossbar. The array index of each port is the index of the slave port. This index will be prepended to all requests at one of the master ports. | -| `mst_ports_*` | Array of master ports of the crossbar. The array index of each port is the index of the master port. | +| `sbr_ports_*` | Array of subordinate ports of the crossbar. The array index of each port is the index of the subordinate port. This index will be prepended to all requests at one of the manager ports. | +| `mgr_ports_*` | Array of manager ports of the crossbar. The array index of each port is the index of the manager port. | | `addr_map_i` | Address map of the crossbar (see section *Address Map* above). | -| `en_default_mst_port_i` | One bit per slave port that defines whether the default master port is active for that slave port (see section *Decode Errors and Default Slave Port* above). | -| `default_mst_port_i` | One master port index per slave port that defines the default master port for that slave port (if active). | +| `en_default_mgr_port_i` | One bit per subordinate port that defines whether the default manager port is active for that subordinate port (see section *Decode Errors and Default Subordinate Port* above). | +| `default_mgr_port_i` | One manager port index per subordinate port that defines the default manager port for that subordinate port (if active). | ## Ordering and Stalls -The ordering inside the crossbar is organized by a network of FIFO's ensuring the in order transaction transmission. It is possible to have multiple transactions to different master ports in flight, however when one of the slave modules connected to these master ports stalls, other consecutive in fight transaction will also be stalled. +The ordering inside the crossbar is organized by a network of FIFO's ensuring the in order transaction transmission. It is possible to have multiple transactions to different manager ports in flight, however when one of the subordinate modules connected to these manager ports stalls, other consecutive in fight transaction will also be stalled. ## Verification Methodology diff --git a/doc/axi_mux.md b/doc/axi_mux.md index e774bd677..8eb66e7fe 100644 --- a/doc/axi_mux.md +++ b/doc/axi_mux.md @@ -1,35 +1,35 @@ # AXI Multiplexer -The opposite function to the AXI demultiplexer is performed by the AXI Multiplexer. It merges multiple AXI-4 connections and merges them into one. The requests from multiple slave ports of the module get interleaved and transmitted over its one master port. +The opposite function to the AXI demultiplexer is performed by the AXI Multiplexer. It merges multiple AXI-4 connections and merges them into one. The requests from multiple subordinate ports of the module get interleaved and transmitted over its one manager port. ![Block-diagram of the AXI 4 Multiplexer Module.](axi_mux.png "Block-diagram of the AXI 4 Multiplexer Module.") -The Multiplexer module is has a simpler structure than the demultiplexer introduced in the previous section. The requests on the AW and AR channels get merged with the same round robin arbitration used for merging the responses in the demultiplexer. One key difference however is the mechanism how the multiplexer determines from which slave port a request came. It uses for this the higher bits of the `axi_id` field of a request. The number of bits can be calculated with: +The Multiplexer module is has a simpler structure than the demultiplexer introduced in the previous section. The requests on the AW and AR channels get merged with the same round robin arbitration used for merging the responses in the demultiplexer. One key difference however is the mechanism how the multiplexer determines from which subordinate port a request came. It uses for this the higher bits of the `axi_id` field of a request. The number of bits can be calculated with: ```systemverilog -$clog2(NumSlavePorts) +$clog2(NumSubordinatePorts) ``` -This restricts the type of ID which can be sent through each slave port of the module. When the higher ID bits do not correspond to the index of the port the following response will be sent back through to the wrong master, leading to a breakdown of the functionality. So for using this module it is recommended to extend each AXI ID by the required amount of bits indicating the index of the respective slave port, before being sent over this module. +This restricts the type of ID which can be sent through each subordinate port of the module. When the higher ID bits do not correspond to the index of the port the following response will be sent back through to the wrong manager, leading to a breakdown of the functionality. So for using this module it is recommended to extend each AXI ID by the required amount of bits indicating the index of the respective subordinate port, before being sent over this module. -For a write transaction the W beats belonging to an AW request have to be sent in order. For this the highest bits of the `aw_id` get pushed into a FIFO. When the FIFO is not empty the data determines which W slave port gets connected to the master port. When the last beat of a write transaction is sent, the data gets poped. -All responses get routed with the same scheme for tracking to which slave port a response should be sent. If the module has a response ready at its master port it connects the respective slave port indicated by the AXI ID. +For a write transaction the W beats belonging to an AW request have to be sent in order. For this the highest bits of the `aw_id` get pushed into a FIFO. When the FIFO is not empty the data determines which W subordinate port gets connected to the manager port. When the last beat of a write transaction is sent, the data gets poped. +All responses get routed with the same scheme for tracking to which subordinate port a response should be sent. If the module has a response ready at its manager port it connects the respective subordinate port indicated by the AXI ID. -The reason the switching is done this way is that again, the ordering model of the AXI protocol has to be respected. By using the extended ID it further helps to decouple requests from different master modules connected to the Multiplexer. It ensures that each master module has its unique set of AXI ID's, leading to potential performance increases when different masters are using vastly different burst lengths. As this could enable a slave module to interleave the responses. -Another reason, why the switching of the responses is done over the ID is the required atomic transaction support. The protocol specifies that a master module has to ensure that a atomic transaction uses a different ID than normal transactions already in flight. This is to prevent ordering requirements between atomic transaction and normal ones. Another problem is further again that an atomic transaction can lead to a response in the B and R channel, further defining a dependence between the read and write channels. +The reason the switching is done this way is that again, the ordering model of the AXI protocol has to be respected. By using the extended ID it further helps to decouple requests from different manager modules connected to the Multiplexer. It ensures that each manager module has its unique set of AXI ID's, leading to potential performance increases when different managers are using vastly different burst lengths. As this could enable a subordinate module to interleave the responses. +Another reason, why the switching of the responses is done over the ID is the required atomic transaction support. The protocol specifies that a manager module has to ensure that a atomic transaction uses a different ID than normal transactions already in flight. This is to prevent ordering requirements between atomic transaction and normal ones. Another problem is further again that an atomic transaction can lead to a response in the B and R channel, further defining a dependence between the read and write channels. -Using an ID prefix for the switching in the multiplexer prevents that this module has to deal with the ordering requirements between these different types of instructions. The responsibility gets put to the master module connected to the slave port of the multiplexer. +Using an ID prefix for the switching in the multiplexer prevents that this module has to deal with the ordering requirements between these different types of instructions. The responsibility gets put to the manager module connected to the subordinate port of the multiplexer. The following table shows the parameters of the module. The module further requires the structs describing the five AXI channels. | Name | Type | Function | |:------------ |:-------------- |:----------------------------------------------------------------------------------------------------------- | | `IdWidth` | `int unsigned` | The width of the AXI transaction ID in bits. | -| `NumSlvPorts`| `int unsigned` | How many slave ports the multiplexer features. This many master modules can be connected to the multiplexer.| +| `NumSbrPorts`| `int unsigned` | How many subordinate ports the multiplexer features. This many manager modules can be connected to the multiplexer.| | `MaxWTrans` | `int unsigned` | The depth of the FIFO holding the highest bits of the ID between the AW and W channel. | | `FallThrough`| `bit` | Is the FIFO between the AW and W channel in fall-through mode. Enabling will lead to longer cycle delays. | | `SpillXX` | `bit` | Enables the optional spill-register on the respective channel. | -The ports of the multiplexer module are defined by the AXI4 channel structs. The module features only the respective slaves and master port, as the switching happens over the highest bits of the AXI ID. +The ports of the multiplexer module are defined by the AXI4 channel structs. The module features only the respective subordinates and manager port, as the switching happens over the highest bits of the AXI ID. diff --git a/doc/axi_xbar.md b/doc/axi_xbar.md index e45514e4f..46056bebf 100644 --- a/doc/axi_xbar.md +++ b/doc/axi_xbar.md @@ -5,19 +5,19 @@ ## Design Overview -`axi_xbar` is a fully-connected crossbar, which means that each master module that is connected to a *slave port* for of the crossbar has direct wires to all slave modules that are connected to the *master ports* of the crossbar. +`axi_xbar` is a fully-connected crossbar, which means that each manager module that is connected to a *subordinate port* for of the crossbar has direct wires to all subordinate modules that are connected to the *manager ports* of the crossbar. A block-diagram of the crossbar is shown below: ![Block-diagram showing the design of the full AXI4 Crossbar.](axi_xbar.png "Block-diagram showing the design of the full AXI4 Crossbar.") -The crossbar has a configurable number of slave and master ports. +The crossbar has a configurable number of subordinate and manager ports. -The ID width of the master ports is wider than that of the slave ports. The additional ID bits are used by the internal multiplexers to route responses. The ID width of the master ports must be `IdWidthSlvPorts + $clog_2(NumSlvPorts)`. +The ID width of the manager ports is wider than that of the subordinate ports. The additional ID bits are used by the internal multiplexers to route responses. The ID width of the manager ports must be `IdWidthSbrPorts + $clog_2(NumSbrPorts)`. ## Address Map -One address map is shared by all master ports. The *address map* contains an arbitrary number of rules (but at least one). Each *rule* maps one address range to one master port. Multiple rules can map to the same master port. The address ranges of two rules may overlap: in case two address ranges overlap, the rule at the higher (more significant) position in the address map prevails. +One address map is shared by all manager ports. The *address map* contains an arbitrary number of rules (but at least one). Each *rule* maps one address range to one manager port. Multiple rules can map to the same manager port. The address ranges of two rules may overlap: in case two address ranges overlap, the rule at the higher (more significant) position in the address map prevails. Each address range includes the start address but does **not** include the end address. That is, an address *matches* an address range if and only if ``` @@ -25,14 +25,14 @@ Each address range includes the start address but does **not** include the end a ``` The start address must be less than or equal to the end address. -The address map can be defined and changed at run time (it is an input signal to the crossbar). However, the address map must not be changed while any AW or AR channel of any slave port is valid. +The address map can be defined and changed at run time (it is an input signal to the crossbar). However, the address map must not be changed while any AW or AR channel of any subordinate port is valid. -## Decode Errors and Default Slave Port +## Decode Errors and Default Subordinate Port -Each slave port has its own internal *decode error slave* module. If the address of a transaction does not match any rule, the transaction is routed to that decode error slave module. That module absorbs each transaction and responds with a decode error (with the proper number of beats). The data of each read response beat is `32'hBADCAB1E` (zero-extended or truncated to match the data width). +Each subordinate port has its own internal *decode error subordinate* module. If the address of a transaction does not match any rule, the transaction is routed to that decode error subordinate module. That module absorbs each transaction and responds with a decode error (with the proper number of beats). The data of each read response beat is `32'hBADCAB1E` (zero-extended or truncated to match the data width). -Each slave port can have a default master port. If the default master port is enabled for a slave port, any address on that slave port that does not match any rule is routed to the default master port instead of the decode error slave. The default master port can be enabled and changed at run time (it is an input signal to the crossbar), and the same restrictions as for the address map apply. +Each subordinate port can have a default manager port. If the default manager port is enabled for a subordinate port, any address on that subordinate port that does not match any rule is routed to the default manager port instead of the decode error subordinate. The default manager port can be enabled and changed at run time (it is an input signal to the crossbar), and the same restrictions as for the address map apply. ## Configuration @@ -41,14 +41,14 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg | Name | Type | Definition | |:------------------|:-------------------|:-----------| -| `NumSlvPorts` | `int unsigned` | The number of AXI slave ports of the crossbar (in other words, how many AXI master modules can be attached). | -| `NumMstPorts` | `int unsigned` | The number of AXI master ports of the crossbar (in other words, how many AXI slave modules can be attached). | -| `MaxMstTrans` | `int unsigned` | Each slave port can have at most this many transactions [in flight](../doc#in-flight). | -| `MaxSlvTrans` | `int unsigned` | Each master port can have at most this many transactions per ID [in flight](../doc#in-flight). | +| `NumSbrPorts` | `int unsigned` | The number of AXI subordinate ports of the crossbar (in other words, how many AXI manager modules can be attached). | +| `NumMgrPorts` | `int unsigned` | The number of AXI manager ports of the crossbar (in other words, how many AXI subordinate modules can be attached). | +| `MaxMgrTrans` | `int unsigned` | Each subordinate port can have at most this many transactions [in flight](../doc#in-flight). | +| `MaxSbrTrans` | `int unsigned` | Each manager port can have at most this many transactions per ID [in flight](../doc#in-flight). | | `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel. Enabling this allows the crossbar to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from the AW channel. | | `LatencyMode` | `enum logic [9:0]` | Latency on the individual channels, defined in detail in section *Pipelining and Latency* below. | -| `IdWidthSlvPorts` | `int unsigned` | The AXI ID width of the slave ports. | -| `IdUsedSlvPorts` | `int unsigned` | The number of slave port ID bits (starting at the least significant) the crossbar uses to determine the uniqueness of an AXI ID (see section *Ordering and Stalls* below). This value has to be less or equal than `IdWidthSlvPorts`. | +| `IdWidthSbrPorts` | `int unsigned` | The AXI ID width of the subordinate ports. | +| `IdUsedSbrPorts` | `int unsigned` | The number of subordinate port ID bits (starting at the least significant) the crossbar uses to determine the uniqueness of an AXI ID (see section *Ordering and Stalls* below). This value has to be less or equal than `IdWidthSbrPorts`. | | `UniqueIds` | `bit` | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the crossbar. See the [`axi_demux` documentation](axi_demux#ordering-and-stalls) for details. | | `AddrWidth` | `int unsigned` | The AXI address width. | | `DataWidth` | `int unsigned` | The AXI data width. | @@ -58,11 +58,11 @@ The other parameters are types to define the ports of the crossbar. The `*_chan ### Pipelining and Latency -The `LatencyMode` parameter allows to insert spill registers after each channel (AW, W, B, AR, and R) of each master port (i.e., each multiplexer) and before each channel of each slave port (i.e., each demultiplexer). Spill registers cut combinatorial paths, so this parameter reduces the length of combinatorial paths through the crossbar. +The `LatencyMode` parameter allows to insert spill registers after each channel (AW, W, B, AR, and R) of each manager port (i.e., each multiplexer) and before each channel of each subordinate port (i.e., each demultiplexer). Spill registers cut combinatorial paths, so this parameter reduces the length of combinatorial paths through the crossbar. Some common configurations are given in the `xbar_latency_e` `enum`. The recommended configuration (`CUT_ALL_AX`) is to have a latency of 2 on the AW and AR channels because these channels have the most combinatorial logic on them. Additionally, `FallThrough` should be set to `0` to prevent logic on the AW channel from extending combinatorial paths on the W channel. However, it is possible to run the crossbar in a fully combinatorial configuration by setting `LatencyMode` to `NO_LATENCY` and `FallThrough` to `1`. -If two crossbars are connected in both directions, meaning both have one of their master ports connected to a slave port of the other, the `LatencyMode` of both crossbars must be set to either `CUT_SLV_PORTS`, `CUT_MST_PORTS`, or `CUT_ALL_PORTS`. Any other latency mode will lead to timing loops on the uncut channels between the two crossbars. The latency mode of the two crossbars does not have to be identical. +If two crossbars are connected in both directions, meaning both have one of their manager ports connected to a subordinate port of the other, the `LatencyMode` of both crossbars must be set to either `CUT_SBR_PORTS`, `CUT_MGR_PORTS`, or `CUT_ALL_PORTS`. Any other latency mode will lead to timing loops on the uncut channels between the two crossbars. The latency mode of the two crossbars does not have to be identical. ## Ports @@ -72,18 +72,18 @@ If two crossbars are connected in both directions, meaning both have one of thei | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | | `test_i` | Test mode enable (active-high). | -| `slv_ports_*` | Array of slave ports of the crossbar. The array index of each port is the index of the slave port. This index will be prepended to all requests at one of the master ports. | -| `mst_ports_*` | Array of master ports of the crossbar. The array index of each port is the index of the master port. | +| `sbr_ports_*` | Array of subordinate ports of the crossbar. The array index of each port is the index of the subordinate port. This index will be prepended to all requests at one of the manager ports. | +| `mgr_ports_*` | Array of manager ports of the crossbar. The array index of each port is the index of the manager port. | | `addr_map_i` | Address map of the crossbar (see section *Address Map* above). | -| `en_default_mst_port_i` | One bit per slave port that defines whether the default master port is active for that slave port (see section *Decode Errors and Default Slave Port* above). | -| `default_mst_port_i` | One master port index per slave port that defines the default master port for that slave port (if active). | +| `en_default_mgr_port_i` | One bit per subordinate port that defines whether the default manager port is active for that subordinate port (see section *Decode Errors and Default Subordinate Port* above). | +| `default_mgr_port_i` | One manager port index per subordinate port that defines the default manager port for that subordinate port (if active). | ## Ordering and Stalls -When one slave port receives two transactions with the same ID and direction (i.e., both read or both write) but targeting two different master ports, it will not accept the second transaction until the first has completed. During this time, the crossbar stalls the AR or AW channel of that slave port. To determine whether two transactions have the same ID, the `IdUsedSlvPorts` least-significant bits are compared. That parameter can be set to the full `IdWidthSlvPorts` to avoid false ID conflicts, or it can be set to a lower value to reduce area and delay at the cost of more false conflicts. +When one subordinate port receives two transactions with the same ID and direction (i.e., both read or both write) but targeting two different manager ports, it will not accept the second transaction until the first has completed. During this time, the crossbar stalls the AR or AW channel of that subordinate port. To determine whether two transactions have the same ID, the `IdUsedSbrPorts` least-significant bits are compared. That parameter can be set to the full `IdWidthSbrPorts` to avoid false ID conflicts, or it can be set to a lower value to reduce area and delay at the cost of more false conflicts. -The reason for this ordering constraint is that AXI transactions with the same ID and direction must remain ordered. If this crossbar would forward both transactions described above, the second master port could get a response before the first one, and the crossbar would have to reorder the responses before returning them on the master port. However, for efficiency reasons, this crossbar does not have reorder buffers. +The reason for this ordering constraint is that AXI transactions with the same ID and direction must remain ordered. If this crossbar would forward both transactions described above, the second manager port could get a response before the first one, and the crossbar would have to reorder the responses before returning them on the manager port. However, for efficiency reasons, this crossbar does not have reorder buffers. ## Verification Methodology @@ -93,17 +93,17 @@ This module has been verified with a directed random verification testbench, des ## Design Rationale for No Pipelining Inside Crossbar -Inserting spill registers between demuxers and muxers seems attractive to further reduce the length of combinatorial paths in the crossbar. However, this can lead to deadlocks in the W channel where two different muxes at the master ports would circular wait on two different demuxes (TODO). In fact, spill registers between the switching modules causes all four deadlock criteria to be met. Recall that the criteria are: +Inserting spill registers between demuxers and muxers seems attractive to further reduce the length of combinatorial paths in the crossbar. However, this can lead to deadlocks in the W channel where two different muxes at the manager ports would circular wait on two different demuxes (TODO). In fact, spill registers between the switching modules causes all four deadlock criteria to be met. Recall that the criteria are: 1. Mutual Exclusion 2. Hold and Wait 3. No Preemption 4. Circular Wait -The first criterion is given by the nature of a multiplexer on the W channel: all W beats have to arrive in the same order as the AW beats regardless of the ID at the slave module. Thus, the different master ports of the multiplexer exclude each other because the order is given by the arbitration tree of the AW channel. +The first criterion is given by the nature of a multiplexer on the W channel: all W beats have to arrive in the same order as the AW beats regardless of the ID at the subordinate module. Thus, the different manager ports of the multiplexer exclude each other because the order is given by the arbitration tree of the AW channel. The second and third criterion are inherent to the AXI protocol: For (2), the valid signal has to be held high until the ready signal goes high. For (3), AXI does not allow interleaving of W beats and requires W bursts to be in the same order as AW beats. -The fourth criterion is thus the only one that can be broken to prevent deadlocks. However, inserting a spill register between a master port of the demultiplexer and a slave port of the multiplexer can lead to a circular dependency inside the W FIFOs. This comes from the particular way the round robin arbiter from the AW channel in the multiplexer defines its priorities. It is constructed in a way by giving each of its slave ports an increasing priority and then comparing pairwise down till a winner is chosen. When the winner gets transferred, the priority state is advanced by one position, preventing starvation. +The fourth criterion is thus the only one that can be broken to prevent deadlocks. However, inserting a spill register between a manager port of the demultiplexer and a subordinate port of the multiplexer can lead to a circular dependency inside the W FIFOs. This comes from the particular way the round robin arbiter from the AW channel in the multiplexer defines its priorities. It is constructed in a way by giving each of its subordinate ports an increasing priority and then comparing pairwise down till a winner is chosen. When the winner gets transferred, the priority state is advanced by one position, preventing starvation. The problem can be shown with an example. Assume an arbitration tree with 10 inputs. Two requests want to be served in the same clock cycle. The one with the higher priority wins and the priority state advances. In the next cycle again the same two inputs have a request waiting. Again it is possible that the same port as last time wins as the priority shifted only one position further. This can lead in conjunction with the other arbitration trees in the other muxes of the crossbar to the circular dependencies inside the FIFOs. Removing the spill register between the demultiplexer and multiplexer forces the switching decision into the W FIFOs in the same clock cycle. This leads to a strict ordering of the switching decision, thus preventing the circular wait. diff --git a/doc/svg/axi_demux.svg b/doc/svg/axi_demux.svg index a2432f905..5a84a3662 100644 --- a/doc/svg/axi_demux.svg +++ b/doc/svg/axi_demux.svg @@ -1877,7 +1877,7 @@ id="tspan4180" x="15.999999" y="21" - style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';fill:#0000ff;fill-opacity:1;stroke-width:0.26458332">slv_aw_sbr_aw_slv_aw_sbr_aw_slv_aw_sbr_aw_slv_w_sbr_w_slv_aw_sbr_aw_slv_w_sbr_w_slv_w_sbr_w_slv_b_sbr_b_slv_b_sbr_b_slv_b_sbr_b_slv_ar_sbr_ar_slv_ar_sbr_ar_slv_ar_sbr_ar_slv_ar_sbr_ar_slv_r_sbr_r_slv_r_sbr_r_slv_r_sbr_r_lookup_mst_select_o + style="stroke-width:0.26458332">lookup_mgr_select_o lookup_mst_select_occupied_o + style="stroke-width:0.26458332">lookup_mgr_select_occupied_o push_mst_select_i + style="stroke-width:0.26458332">push_mgr_select_i mst_aw_mgr_aw_mst_aw_mgr_aw_mst_aw_mgr_aw_mst_w_mgr_w_mst_w_mgr_w_mst_w_mgr_w_mst_b_mgr_b_mst_b_mgr_b_mst_b_mgr_b_mst_ar_mgr_ar_mst_ar_mgr_ar_mst_ar_mgr_ar_mst_r_mgr_r_mst_r_mgr_r_mst_r_mgr_r_lookup_mst_select_o + style="stroke-width:0.26458332">lookup_mgr_select_o lookup_mst_select_occupied_o + style="stroke-width:0.26458332">lookup_mgr_select_occupied_o push_mst_select_i + style="stroke-width:0.26458332">push_mgr_select_i slv_reqs_i[2] + id="tspan1345">sbr_reqs_i[2] slv_rsps_o[2] + id="tspan1381">sbr_rsps_o[2] slv_reqs_i[1] + id="tspan1345-6">sbr_reqs_i[1] slv_rsps_o[1] + id="tspan1381-8">sbr_rsps_o[1] slv_reqs_i[0] + id="tspan1345-9">sbr_reqs_i[0] slv_rsps_o[0] + id="tspan1381-5">sbr_rsps_o[0] mst_req_o + id="tspan1345-5">mgr_req_o mst_req_i + id="tspan1381-7">mgr_req_i slv_port [3sbr_port [3] mst_port [3mgr_port [3] slv_port [2] + id="tspan10618-0">sbr_port [2] mst_port [2] + id="tspan10618-9-9">mgr_port [2] slv_port [1] + id="tspan10618-93">sbr_port [1] mst_port [1] + id="tspan10618-9-7">mgr_port [1] slv_port [0] + id="tspan10618-1">sbr_port [0] mst_port [0] + id="tspan10618-9-1">mgr_port [0] default_mst_port[3] + id="tspan11845">default_mgr_port[3] default_mst_port[2] + id="tspan11845-7">default_mgr_port[2] default_mst_port[1] + id="tspan11845-1">default_mgr_port[1] default_mst_port[0] + id="tspan11845-2">default_mgr_port[0] slv_aw_sbr_aw_slv_aw_sbr_aw_slv_aw_sbr_aw_slv_w_sbr_w_slv_w_sbr_w_slv_w_sbr_w_slv_b_sbr_b_slv_b_sbr_b_slv_b_sbr_b_slv_ar_sbr_ar_slv_ar_sbr_ar_slv_ar_sbr_ar_slv_r_sbr_r_slv_r_sbr_r_slv_r_sbr_r_mst_aw_mgr_aw_mst_aw_mgr_aw_mst_aw_mgr_aw_mst_w_mgr_w_mst_w_mgr_w_mst_w_mgr_w_mst_b_mgr_b_mst_b_mgr_b_mst_b_mgr_b_mst_ar_mgr_ar_mst_ar_mgr_ar_mst_ar_mgr_ar_mst_r_mgr_r_mst_r_mgr_r_mst_t_mgr_t_slv_port [3sbr_port [3] mst_port [3mgr_port [3] slv_port [2] + id="tspan10618-0">sbr_port [2] mst_port [2] + id="tspan10618-9-9">mgr_port [2] slv_port [1] + id="tspan10618-93">sbr_port [1] mst_port [1] + id="tspan10618-9-7">mgr_port [1] slv_port [0] + id="tspan10618-1">sbr_port [0] mst_port [0] + id="tspan10618-9-1">mgr_port [0] default_mst_port[3] + id="tspan11845">default_mgr_port[3] default_mst_port[2] + id="tspan11845-7">default_mgr_port[2] default_mst_port[1] + id="tspan11845-1">default_mgr_port[1] default_mst_port[0] + id="tspan11845-2">default_mgr_port[0] - txn_supported(slv_req_i.aw.atop, slv_req_i.aw.burst, slv_req_i.aw.cache, slv_req_i.aw.len) - ) else $warning("Unsupported AW transaction received, returning slave error!"); - assume property (@(posedge clk_i) slv_req_i.ar_valid |-> - txn_supported('0, slv_req_i.ar.burst, slv_req_i.ar.cache, slv_req_i.ar.len) - ) else $warning("Unsupported AR transaction received, returning slave error!"); - assume property (@(posedge clk_i) slv_req_i.aw_valid |-> - slv_req_i.aw.atop == '0 || slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_ATOMICSTORE + assume property (@(posedge clk_i) sbr_req_i.aw_valid |-> + txn_supported(sbr_req_i.aw.atop, sbr_req_i.aw.burst, sbr_req_i.aw.cache, sbr_req_i.aw.len) + ) else $warning("Unsupported AW transaction received, returning subordinate error!"); + assume property (@(posedge clk_i) sbr_req_i.ar_valid |-> + txn_supported('0, sbr_req_i.ar.burst, sbr_req_i.ar.cache, sbr_req_i.ar.len) + ) else $warning("Unsupported AR transaction received, returning subordinate error!"); + assume property (@(posedge clk_i) sbr_req_i.aw_valid |-> + sbr_req_i.aw.atop == '0 || sbr_req_i.aw.atop[5:4] == axi_pkg::ATOP_ATOMICSTORE ) else $fatal(1, "Unsupported ATOP that gives rise to a R response received,\ cannot respond in protocol-compliant manner!"); // Outputs - assert property (@(posedge clk_i) mst_req_o.aw_valid |-> mst_req_o.aw.len == '0) + assert property (@(posedge clk_i) mgr_req_o.aw_valid |-> mgr_req_o.aw.len == '0) else $fatal(1, "AW burst longer than a single beat emitted!"); - assert property (@(posedge clk_i) mst_req_o.ar_valid |-> mst_req_o.ar.len == '0) + assert property (@(posedge clk_i) mgr_req_o.ar_valid |-> mgr_req_o.ar.len == '0) else $fatal(1, "AR burst longer than a single beat emitted!"); // pragma translate_on `endif diff --git a/src/axi_bus_compare.sv b/src/axi_bus_compare.sv index 95cf002f7..3ea960aed 100644 --- a/src/axi_bus_compare.sv +++ b/src/axi_bus_compare.sv @@ -30,9 +30,9 @@ module axi_bus_compare #( parameter type axi_ar_chan_t = logic, /// R channel type of the AXI4+ATOP interface parameter type axi_r_chan_t = logic, - /// Request struct type of the AXI4+ATOP slave port + /// Request struct type of the AXI4+ATOP subordinate port parameter type axi_req_t = logic, - /// Response struct type of the AXI4+ATOP slave port + /// Response struct type of the AXI4+ATOP subordinate port parameter type axi_rsp_t = logic, /// ID type (*do not overwrite*) parameter type id_t = logic [2**IdWidth-1:0] diff --git a/src/axi_cdc.sv b/src/axi_cdc.sv index 871dbdfe6..1c485c1bb 100644 --- a/src/axi_cdc.sv +++ b/src/axi_cdc.sv @@ -32,12 +32,12 @@ module axi_cdc #( /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. parameter int unsigned LogDepth = 1 ) ( - // slave side - clocked by `src_clk_i` + // subordinate side - clocked by `src_clk_i` input logic src_clk_i, input logic src_rst_ni, input axi_req_t src_req_i, output axi_rsp_t src_rsp_o, - // master side - clocked by `dst_clk_i` + // manager side - clocked by `dst_clk_i` input logic dst_clk_i, input logic dst_rst_ni, output axi_req_t dst_req_o, @@ -69,21 +69,21 @@ module axi_cdc #( .src_rst_ni, .src_req_i, .src_rsp_o, - (* async *) .async_data_master_aw_data_o ( async_data_aw_data ), - (* async *) .async_data_master_aw_wptr_o ( async_data_aw_wptr ), - (* async *) .async_data_master_aw_rptr_i ( async_data_aw_rptr ), - (* async *) .async_data_master_w_data_o ( async_data_w_data ), - (* async *) .async_data_master_w_wptr_o ( async_data_w_wptr ), - (* async *) .async_data_master_w_rptr_i ( async_data_w_rptr ), - (* async *) .async_data_master_b_data_i ( async_data_b_data ), - (* async *) .async_data_master_b_wptr_i ( async_data_b_wptr ), - (* async *) .async_data_master_b_rptr_o ( async_data_b_rptr ), - (* async *) .async_data_master_ar_data_o ( async_data_ar_data ), - (* async *) .async_data_master_ar_wptr_o ( async_data_ar_wptr ), - (* async *) .async_data_master_ar_rptr_i ( async_data_ar_rptr ), - (* async *) .async_data_master_r_data_i ( async_data_r_data ), - (* async *) .async_data_master_r_wptr_i ( async_data_r_wptr ), - (* async *) .async_data_master_r_rptr_o ( async_data_r_rptr ) + (* async *) .async_data_manager_aw_data_o ( async_data_aw_data ), + (* async *) .async_data_manager_aw_wptr_o ( async_data_aw_wptr ), + (* async *) .async_data_manager_aw_rptr_i ( async_data_aw_rptr ), + (* async *) .async_data_manager_w_data_o ( async_data_w_data ), + (* async *) .async_data_manager_w_wptr_o ( async_data_w_wptr ), + (* async *) .async_data_manager_w_rptr_i ( async_data_w_rptr ), + (* async *) .async_data_manager_b_data_i ( async_data_b_data ), + (* async *) .async_data_manager_b_wptr_i ( async_data_b_wptr ), + (* async *) .async_data_manager_b_rptr_o ( async_data_b_rptr ), + (* async *) .async_data_manager_ar_data_o ( async_data_ar_data ), + (* async *) .async_data_manager_ar_wptr_o ( async_data_ar_wptr ), + (* async *) .async_data_manager_ar_rptr_i ( async_data_ar_rptr ), + (* async *) .async_data_manager_r_data_i ( async_data_r_data ), + (* async *) .async_data_manager_r_wptr_i ( async_data_r_wptr ), + (* async *) .async_data_manager_r_rptr_o ( async_data_r_rptr ) ); axi_cdc_dst #( @@ -100,21 +100,21 @@ module axi_cdc #( .dst_rst_ni, .dst_req_o, .dst_rsp_i, - (* async *) .async_data_slave_aw_wptr_i ( async_data_aw_wptr ), - (* async *) .async_data_slave_aw_rptr_o ( async_data_aw_rptr ), - (* async *) .async_data_slave_aw_data_i ( async_data_aw_data ), - (* async *) .async_data_slave_w_wptr_i ( async_data_w_wptr ), - (* async *) .async_data_slave_w_rptr_o ( async_data_w_rptr ), - (* async *) .async_data_slave_w_data_i ( async_data_w_data ), - (* async *) .async_data_slave_b_wptr_o ( async_data_b_wptr ), - (* async *) .async_data_slave_b_rptr_i ( async_data_b_rptr ), - (* async *) .async_data_slave_b_data_o ( async_data_b_data ), - (* async *) .async_data_slave_ar_wptr_i ( async_data_ar_wptr ), - (* async *) .async_data_slave_ar_rptr_o ( async_data_ar_rptr ), - (* async *) .async_data_slave_ar_data_i ( async_data_ar_data ), - (* async *) .async_data_slave_r_wptr_o ( async_data_r_wptr ), - (* async *) .async_data_slave_r_rptr_i ( async_data_r_rptr ), - (* async *) .async_data_slave_r_data_o ( async_data_r_data ) + (* async *) .async_data_subordinate_aw_wptr_i ( async_data_aw_wptr ), + (* async *) .async_data_subordinate_aw_rptr_o ( async_data_aw_rptr ), + (* async *) .async_data_subordinate_aw_data_i ( async_data_aw_data ), + (* async *) .async_data_subordinate_w_wptr_i ( async_data_w_wptr ), + (* async *) .async_data_subordinate_w_rptr_o ( async_data_w_rptr ), + (* async *) .async_data_subordinate_w_data_i ( async_data_w_data ), + (* async *) .async_data_subordinate_b_wptr_o ( async_data_b_wptr ), + (* async *) .async_data_subordinate_b_rptr_i ( async_data_b_rptr ), + (* async *) .async_data_subordinate_b_data_o ( async_data_b_data ), + (* async *) .async_data_subordinate_ar_wptr_i ( async_data_ar_wptr ), + (* async *) .async_data_subordinate_ar_rptr_o ( async_data_ar_rptr ), + (* async *) .async_data_subordinate_ar_data_i ( async_data_ar_data ), + (* async *) .async_data_subordinate_r_wptr_o ( async_data_r_wptr ), + (* async *) .async_data_subordinate_r_rptr_i ( async_data_r_rptr ), + (* async *) .async_data_subordinate_r_data_o ( async_data_r_data ) ); endmodule @@ -131,14 +131,14 @@ module axi_cdc_intf #( /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. parameter int unsigned LOG_DEPTH = 1 ) ( - // slave side - clocked by `src_clk_i` + // subordinate side - clocked by `src_clk_i` input logic src_clk_i, input logic src_rst_ni, - AXI_BUS.Slave src, - // master side - clocked by `dst_clk_i` + AXI_BUS.Subordinate src, + // manager side - clocked by `dst_clk_i` input logic dst_clk_i, input logic dst_rst_ni, - AXI_BUS.Master dst + AXI_BUS.Manager dst ); typedef logic [AXI_ID_WIDTH-1:0] id_t; @@ -191,14 +191,14 @@ module axi_lite_cdc_intf #( /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. parameter int unsigned LOG_DEPTH = 1 ) ( - // slave side - clocked by `src_clk_i` + // subordinate side - clocked by `src_clk_i` input logic src_clk_i, input logic src_rst_ni, - AXI_LITE.Slave src, - // master side - clocked by `dst_clk_i` + AXI_LITE.Subordinate src, + // manager side - clocked by `dst_clk_i` input logic dst_clk_i, input logic dst_rst_ni, - AXI_LITE.Master dst + AXI_LITE.Manager dst ); typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; diff --git a/src/axi_cdc_dst.sv b/src/axi_cdc_dst.sv index 3f5eaef86..41aa73673 100644 --- a/src/axi_cdc_dst.sv +++ b/src/axi_cdc_dst.sv @@ -32,23 +32,23 @@ module axi_cdc_dst #( parameter type axi_req_t = logic, parameter type axi_rsp_t = logic ) ( - // asynchronous slave port - input aw_chan_t [2**LogDepth-1:0] async_data_slave_aw_data_i, - input logic [LogDepth:0] async_data_slave_aw_wptr_i, - output logic [LogDepth:0] async_data_slave_aw_rptr_o, - input w_chan_t [2**LogDepth-1:0] async_data_slave_w_data_i, - input logic [LogDepth:0] async_data_slave_w_wptr_i, - output logic [LogDepth:0] async_data_slave_w_rptr_o, - output b_chan_t [2**LogDepth-1:0] async_data_slave_b_data_o, - output logic [LogDepth:0] async_data_slave_b_wptr_o, - input logic [LogDepth:0] async_data_slave_b_rptr_i, - input ar_chan_t [2**LogDepth-1:0] async_data_slave_ar_data_i, - input logic [LogDepth:0] async_data_slave_ar_wptr_i, - output logic [LogDepth:0] async_data_slave_ar_rptr_o, - output r_chan_t [2**LogDepth-1:0] async_data_slave_r_data_o, - output logic [LogDepth:0] async_data_slave_r_wptr_o, - input logic [LogDepth:0] async_data_slave_r_rptr_i, - // synchronous master port - clocked by `dst_clk_i` + // asynchronous subordinate port + input aw_chan_t [2**LogDepth-1:0] async_data_subordinate_aw_data_i, + input logic [LogDepth:0] async_data_subordinate_aw_wptr_i, + output logic [LogDepth:0] async_data_subordinate_aw_rptr_o, + input w_chan_t [2**LogDepth-1:0] async_data_subordinate_w_data_i, + input logic [LogDepth:0] async_data_subordinate_w_wptr_i, + output logic [LogDepth:0] async_data_subordinate_w_rptr_o, + output b_chan_t [2**LogDepth-1:0] async_data_subordinate_b_data_o, + output logic [LogDepth:0] async_data_subordinate_b_wptr_o, + input logic [LogDepth:0] async_data_subordinate_b_rptr_i, + input ar_chan_t [2**LogDepth-1:0] async_data_subordinate_ar_data_i, + input logic [LogDepth:0] async_data_subordinate_ar_wptr_i, + output logic [LogDepth:0] async_data_subordinate_ar_rptr_o, + output r_chan_t [2**LogDepth-1:0] async_data_subordinate_r_data_o, + output logic [LogDepth:0] async_data_subordinate_r_wptr_o, + input logic [LogDepth:0] async_data_subordinate_r_rptr_i, + // synchronous manager port - clocked by `dst_clk_i` input logic dst_clk_i, input logic dst_rst_ni, output axi_req_t dst_req_o, @@ -65,9 +65,9 @@ module axi_cdc_dst #( `endif .LOG_DEPTH ( LogDepth ) ) i_cdc_fifo_gray_dst_aw ( - .async_data_i ( async_data_slave_aw_data_i ), - .async_wptr_i ( async_data_slave_aw_wptr_i ), - .async_rptr_o ( async_data_slave_aw_rptr_o ), + .async_data_i ( async_data_subordinate_aw_data_i ), + .async_wptr_i ( async_data_subordinate_aw_wptr_i ), + .async_rptr_o ( async_data_subordinate_aw_rptr_o ), .dst_clk_i, .dst_rst_ni, .dst_data_o ( dst_req_o.aw ), @@ -83,9 +83,9 @@ module axi_cdc_dst #( `endif .LOG_DEPTH ( LogDepth ) ) i_cdc_fifo_gray_dst_w ( - .async_data_i ( async_data_slave_w_data_i ), - .async_wptr_i ( async_data_slave_w_wptr_i ), - .async_rptr_o ( async_data_slave_w_rptr_o ), + .async_data_i ( async_data_subordinate_w_data_i ), + .async_wptr_i ( async_data_subordinate_w_wptr_i ), + .async_rptr_o ( async_data_subordinate_w_rptr_o ), .dst_clk_i, .dst_rst_ni, .dst_data_o ( dst_req_o.w ), @@ -106,9 +106,9 @@ module axi_cdc_dst #( .src_data_i ( dst_rsp_i.b ), .src_valid_i ( dst_rsp_i.b_valid ), .src_ready_o ( dst_req_o.b_ready ), - .async_data_o ( async_data_slave_b_data_o ), - .async_wptr_o ( async_data_slave_b_wptr_o ), - .async_rptr_i ( async_data_slave_b_rptr_i ) + .async_data_o ( async_data_subordinate_b_data_o ), + .async_wptr_o ( async_data_subordinate_b_wptr_o ), + .async_rptr_i ( async_data_subordinate_b_rptr_i ) ); cdc_fifo_gray_dst #( @@ -124,9 +124,9 @@ module axi_cdc_dst #( .dst_data_o ( dst_req_o.ar ), .dst_valid_o ( dst_req_o.ar_valid ), .dst_ready_i ( dst_rsp_i.ar_ready ), - .async_data_i ( async_data_slave_ar_data_i ), - .async_wptr_i ( async_data_slave_ar_wptr_i ), - .async_rptr_o ( async_data_slave_ar_rptr_o ) + .async_data_i ( async_data_subordinate_ar_data_i ), + .async_wptr_i ( async_data_subordinate_ar_wptr_i ), + .async_rptr_o ( async_data_subordinate_ar_rptr_o ) ); cdc_fifo_gray_src #( @@ -142,9 +142,9 @@ module axi_cdc_dst #( .src_data_i ( dst_rsp_i.r ), .src_valid_i ( dst_rsp_i.r_valid ), .src_ready_o ( dst_req_o.r_ready ), - .async_data_o ( async_data_slave_r_data_o ), - .async_wptr_o ( async_data_slave_r_wptr_o ), - .async_rptr_i ( async_data_slave_r_rptr_i ) + .async_data_o ( async_data_subordinate_r_data_o ), + .async_wptr_o ( async_data_subordinate_r_wptr_o ), + .async_rptr_i ( async_data_subordinate_r_rptr_i ) ); endmodule @@ -158,12 +158,12 @@ module axi_cdc_dst_intf #( /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. parameter int unsigned LOG_DEPTH = 1 ) ( - // asynchronous slave port - AXI_BUS_ASYNC_GRAY.Slave src, - // synchronous master port - clocked by `dst_clk_i` + // asynchronous subordinate port + AXI_BUS_ASYNC_GRAY.Subordinate src, + // synchronous manager port - clocked by `dst_clk_i` input logic dst_clk_i, input logic dst_rst_ni, - AXI_BUS.Master dst + AXI_BUS.Manager dst ); typedef logic [AXI_ID_WIDTH-1:0] id_t; @@ -192,21 +192,21 @@ module axi_cdc_dst_intf #( .axi_rsp_t ( axi_rsp_t ), .LogDepth ( LOG_DEPTH ) ) i_axi_cdc_dst ( - .async_data_slave_aw_data_i ( src.aw_data ), - .async_data_slave_aw_wptr_i ( src.aw_wptr ), - .async_data_slave_aw_rptr_o ( src.aw_rptr ), - .async_data_slave_w_data_i ( src.w_data ), - .async_data_slave_w_wptr_i ( src.w_wptr ), - .async_data_slave_w_rptr_o ( src.w_rptr ), - .async_data_slave_b_data_o ( src.b_data ), - .async_data_slave_b_wptr_o ( src.b_wptr ), - .async_data_slave_b_rptr_i ( src.b_rptr ), - .async_data_slave_ar_data_i ( src.ar_data ), - .async_data_slave_ar_wptr_i ( src.ar_wptr ), - .async_data_slave_ar_rptr_o ( src.ar_rptr ), - .async_data_slave_r_data_o ( src.r_data ), - .async_data_slave_r_wptr_o ( src.r_wptr ), - .async_data_slave_r_rptr_i ( src.r_rptr ), + .async_data_subordinate_aw_data_i ( src.aw_data ), + .async_data_subordinate_aw_wptr_i ( src.aw_wptr ), + .async_data_subordinate_aw_rptr_o ( src.aw_rptr ), + .async_data_subordinate_w_data_i ( src.w_data ), + .async_data_subordinate_w_wptr_i ( src.w_wptr ), + .async_data_subordinate_w_rptr_o ( src.w_rptr ), + .async_data_subordinate_b_data_o ( src.b_data ), + .async_data_subordinate_b_wptr_o ( src.b_wptr ), + .async_data_subordinate_b_rptr_i ( src.b_rptr ), + .async_data_subordinate_ar_data_i ( src.ar_data ), + .async_data_subordinate_ar_wptr_i ( src.ar_wptr ), + .async_data_subordinate_ar_rptr_o ( src.ar_rptr ), + .async_data_subordinate_r_data_o ( src.r_data ), + .async_data_subordinate_r_wptr_o ( src.r_wptr ), + .async_data_subordinate_r_rptr_i ( src.r_rptr ), .dst_clk_i, .dst_rst_ni, .dst_req_o ( dst_req ), @@ -225,12 +225,12 @@ module axi_lite_cdc_dst_intf #( /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. parameter int unsigned LOG_DEPTH = 1 ) ( - // asynchronous slave port - AXI_LITE_ASYNC_GRAY.Slave src, - // synchronous master port - clocked by `dst_clk_i` + // asynchronous subordinate port + AXI_LITE_ASYNC_GRAY.Subordinate src, + // synchronous manager port - clocked by `dst_clk_i` input logic dst_clk_i, input logic dst_rst_ni, - AXI_LITE.Master dst + AXI_LITE.Manager dst ); typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; @@ -257,21 +257,21 @@ module axi_lite_cdc_dst_intf #( .axi_rsp_t ( axi_lite_rsp_t ), .LogDepth ( LOG_DEPTH ) ) i_axi_cdc_dst ( - .async_data_slave_aw_data_i ( src.aw_data ), - .async_data_slave_aw_wptr_i ( src.aw_wptr ), - .async_data_slave_aw_rptr_o ( src.aw_rptr ), - .async_data_slave_w_data_i ( src.w_data ), - .async_data_slave_w_wptr_i ( src.w_wptr ), - .async_data_slave_w_rptr_o ( src.w_rptr ), - .async_data_slave_b_data_o ( src.b_data ), - .async_data_slave_b_wptr_o ( src.b_wptr ), - .async_data_slave_b_rptr_i ( src.b_rptr ), - .async_data_slave_ar_data_i ( src.ar_data ), - .async_data_slave_ar_wptr_i ( src.ar_wptr ), - .async_data_slave_ar_rptr_o ( src.ar_rptr ), - .async_data_slave_r_data_o ( src.r_data ), - .async_data_slave_r_wptr_o ( src.r_wptr ), - .async_data_slave_r_rptr_i ( src.r_rptr ), + .async_data_subordinate_aw_data_i ( src.aw_data ), + .async_data_subordinate_aw_wptr_i ( src.aw_wptr ), + .async_data_subordinate_aw_rptr_o ( src.aw_rptr ), + .async_data_subordinate_w_data_i ( src.w_data ), + .async_data_subordinate_w_wptr_i ( src.w_wptr ), + .async_data_subordinate_w_rptr_o ( src.w_rptr ), + .async_data_subordinate_b_data_o ( src.b_data ), + .async_data_subordinate_b_wptr_o ( src.b_wptr ), + .async_data_subordinate_b_rptr_i ( src.b_rptr ), + .async_data_subordinate_ar_data_i ( src.ar_data ), + .async_data_subordinate_ar_wptr_i ( src.ar_wptr ), + .async_data_subordinate_ar_rptr_o ( src.ar_rptr ), + .async_data_subordinate_r_data_o ( src.r_data ), + .async_data_subordinate_r_wptr_o ( src.r_wptr ), + .async_data_subordinate_r_rptr_i ( src.r_rptr ), .dst_clk_i, .dst_rst_ni, .dst_req_o ( dst_req ), diff --git a/src/axi_cdc_src.sv b/src/axi_cdc_src.sv index 0aeba6c5c..773e9ee8d 100644 --- a/src/axi_cdc_src.sv +++ b/src/axi_cdc_src.sv @@ -32,27 +32,27 @@ module axi_cdc_src #( parameter type axi_req_t = logic, parameter type axi_rsp_t = logic ) ( - // synchronous slave port - clocked by `src_clk_i` + // synchronous subordinate port - clocked by `src_clk_i` input logic src_clk_i, input logic src_rst_ni, input axi_req_t src_req_i, output axi_rsp_t src_rsp_o, - // asynchronous master port - output aw_chan_t [2**LogDepth-1:0] async_data_master_aw_data_o, - output logic [LogDepth:0] async_data_master_aw_wptr_o, - input logic [LogDepth:0] async_data_master_aw_rptr_i, - output w_chan_t [2**LogDepth-1:0] async_data_master_w_data_o, - output logic [LogDepth:0] async_data_master_w_wptr_o, - input logic [LogDepth:0] async_data_master_w_rptr_i, - input b_chan_t [2**LogDepth-1:0] async_data_master_b_data_i, - input logic [LogDepth:0] async_data_master_b_wptr_i, - output logic [LogDepth:0] async_data_master_b_rptr_o, - output ar_chan_t [2**LogDepth-1:0] async_data_master_ar_data_o, - output logic [LogDepth:0] async_data_master_ar_wptr_o, - input logic [LogDepth:0] async_data_master_ar_rptr_i, - input r_chan_t [2**LogDepth-1:0] async_data_master_r_data_i, - input logic [LogDepth:0] async_data_master_r_wptr_i, - output logic [LogDepth:0] async_data_master_r_rptr_o + // asynchronous manager port + output aw_chan_t [2**LogDepth-1:0] async_data_manager_aw_data_o, + output logic [LogDepth:0] async_data_manager_aw_wptr_o, + input logic [LogDepth:0] async_data_manager_aw_rptr_i, + output w_chan_t [2**LogDepth-1:0] async_data_manager_w_data_o, + output logic [LogDepth:0] async_data_manager_w_wptr_o, + input logic [LogDepth:0] async_data_manager_w_rptr_i, + input b_chan_t [2**LogDepth-1:0] async_data_manager_b_data_i, + input logic [LogDepth:0] async_data_manager_b_wptr_i, + output logic [LogDepth:0] async_data_manager_b_rptr_o, + output ar_chan_t [2**LogDepth-1:0] async_data_manager_ar_data_o, + output logic [LogDepth:0] async_data_manager_ar_wptr_o, + input logic [LogDepth:0] async_data_manager_ar_rptr_i, + input r_chan_t [2**LogDepth-1:0] async_data_manager_r_data_i, + input logic [LogDepth:0] async_data_manager_r_wptr_i, + output logic [LogDepth:0] async_data_manager_r_rptr_o ); cdc_fifo_gray_src #( @@ -69,9 +69,9 @@ module axi_cdc_src #( .src_data_i ( src_req_i.aw ), .src_valid_i ( src_req_i.aw_valid ), .src_ready_o ( src_rsp_o.aw_ready ), - .async_data_o ( async_data_master_aw_data_o ), - .async_wptr_o ( async_data_master_aw_wptr_o ), - .async_rptr_i ( async_data_master_aw_rptr_i ) + .async_data_o ( async_data_manager_aw_data_o ), + .async_wptr_o ( async_data_manager_aw_wptr_o ), + .async_rptr_i ( async_data_manager_aw_rptr_i ) ); cdc_fifo_gray_src #( @@ -87,9 +87,9 @@ module axi_cdc_src #( .src_data_i ( src_req_i.w ), .src_valid_i ( src_req_i.w_valid ), .src_ready_o ( src_rsp_o.w_ready ), - .async_data_o ( async_data_master_w_data_o ), - .async_wptr_o ( async_data_master_w_wptr_o ), - .async_rptr_i ( async_data_master_w_rptr_i ) + .async_data_o ( async_data_manager_w_data_o ), + .async_wptr_o ( async_data_manager_w_wptr_o ), + .async_rptr_i ( async_data_manager_w_rptr_i ) ); cdc_fifo_gray_dst #( @@ -105,9 +105,9 @@ module axi_cdc_src #( .dst_data_o ( src_rsp_o.b ), .dst_valid_o ( src_rsp_o.b_valid ), .dst_ready_i ( src_req_i.b_ready ), - .async_data_i ( async_data_master_b_data_i ), - .async_wptr_i ( async_data_master_b_wptr_i ), - .async_rptr_o ( async_data_master_b_rptr_o ) + .async_data_i ( async_data_manager_b_data_i ), + .async_wptr_i ( async_data_manager_b_wptr_i ), + .async_rptr_o ( async_data_manager_b_rptr_o ) ); cdc_fifo_gray_src #( @@ -123,9 +123,9 @@ module axi_cdc_src #( .src_data_i ( src_req_i.ar ), .src_valid_i ( src_req_i.ar_valid ), .src_ready_o ( src_rsp_o.ar_ready ), - .async_data_o ( async_data_master_ar_data_o ), - .async_wptr_o ( async_data_master_ar_wptr_o ), - .async_rptr_i ( async_data_master_ar_rptr_i ) + .async_data_o ( async_data_manager_ar_data_o ), + .async_wptr_o ( async_data_manager_ar_wptr_o ), + .async_rptr_i ( async_data_manager_ar_rptr_i ) ); cdc_fifo_gray_dst #( @@ -141,9 +141,9 @@ module axi_cdc_src #( .dst_data_o ( src_rsp_o.r ), .dst_valid_o ( src_rsp_o.r_valid ), .dst_ready_i ( src_req_i.r_ready ), - .async_data_i ( async_data_master_r_data_i ), - .async_wptr_i ( async_data_master_r_wptr_i ), - .async_rptr_o ( async_data_master_r_rptr_o ) + .async_data_i ( async_data_manager_r_data_i ), + .async_wptr_i ( async_data_manager_r_wptr_i ), + .async_rptr_o ( async_data_manager_r_rptr_o ) ); endmodule @@ -157,12 +157,12 @@ module axi_cdc_src_intf #( /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. parameter int unsigned LOG_DEPTH = 1 ) ( - // synchronous slave port - clocked by `src_clk_i` + // synchronous subordinate port - clocked by `src_clk_i` input logic src_clk_i, input logic src_rst_ni, - AXI_BUS.Slave src, - // asynchronous master port - AXI_BUS_ASYNC_GRAY.Master dst + AXI_BUS.Subordinate src, + // asynchronous manager port + AXI_BUS_ASYNC_GRAY.Manager dst ); typedef logic [AXI_ID_WIDTH-1:0] id_t; @@ -198,21 +198,21 @@ module axi_cdc_src_intf #( .src_rst_ni, .src_req_i ( src_req ), .src_rsp_o ( src_rsp ), - .async_data_master_aw_data_o ( dst.aw_data ), - .async_data_master_aw_wptr_o ( dst.aw_wptr ), - .async_data_master_aw_rptr_i ( dst.aw_rptr ), - .async_data_master_w_data_o ( dst.w_data ), - .async_data_master_w_wptr_o ( dst.w_wptr ), - .async_data_master_w_rptr_i ( dst.w_rptr ), - .async_data_master_b_data_i ( dst.b_data ), - .async_data_master_b_wptr_i ( dst.b_wptr ), - .async_data_master_b_rptr_o ( dst.b_rptr ), - .async_data_master_ar_data_o ( dst.ar_data ), - .async_data_master_ar_wptr_o ( dst.ar_wptr ), - .async_data_master_ar_rptr_i ( dst.ar_rptr ), - .async_data_master_r_data_i ( dst.r_data ), - .async_data_master_r_wptr_i ( dst.r_wptr ), - .async_data_master_r_rptr_o ( dst.r_rptr ) + .async_data_manager_aw_data_o ( dst.aw_data ), + .async_data_manager_aw_wptr_o ( dst.aw_wptr ), + .async_data_manager_aw_rptr_i ( dst.aw_rptr ), + .async_data_manager_w_data_o ( dst.w_data ), + .async_data_manager_w_wptr_o ( dst.w_wptr ), + .async_data_manager_w_rptr_i ( dst.w_rptr ), + .async_data_manager_b_data_i ( dst.b_data ), + .async_data_manager_b_wptr_i ( dst.b_wptr ), + .async_data_manager_b_rptr_o ( dst.b_rptr ), + .async_data_manager_ar_data_o ( dst.ar_data ), + .async_data_manager_ar_wptr_o ( dst.ar_wptr ), + .async_data_manager_ar_rptr_i ( dst.ar_rptr ), + .async_data_manager_r_data_i ( dst.r_data ), + .async_data_manager_r_wptr_i ( dst.r_wptr ), + .async_data_manager_r_rptr_o ( dst.r_rptr ) ); endmodule @@ -224,12 +224,12 @@ module axi_lite_cdc_src_intf #( /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. parameter int unsigned LOG_DEPTH = 1 ) ( - // synchronous slave port - clocked by `src_clk_i` + // synchronous subordinate port - clocked by `src_clk_i` input logic src_clk_i, input logic src_rst_ni, - AXI_BUS.Slave src, - // asynchronous master port - AXI_LITE_ASYNC_GRAY.Master dst + AXI_BUS.Subordinate src, + // asynchronous manager port + AXI_LITE_ASYNC_GRAY.Manager dst ); typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; @@ -263,21 +263,21 @@ module axi_lite_cdc_src_intf #( .src_rst_ni, .src_req_i ( src_req ), .src_rsp_o ( src_rsp ), - .async_data_master_aw_data_o ( dst.aw_data ), - .async_data_master_aw_wptr_o ( dst.aw_wptr ), - .async_data_master_aw_rptr_i ( dst.aw_rptr ), - .async_data_master_w_data_o ( dst.w_data ), - .async_data_master_w_wptr_o ( dst.w_wptr ), - .async_data_master_w_rptr_i ( dst.w_rptr ), - .async_data_master_b_data_i ( dst.b_data ), - .async_data_master_b_wptr_i ( dst.b_wptr ), - .async_data_master_b_rptr_o ( dst.b_rptr ), - .async_data_master_ar_data_o ( dst.ar_data ), - .async_data_master_ar_wptr_o ( dst.ar_wptr ), - .async_data_master_ar_rptr_i ( dst.ar_rptr ), - .async_data_master_r_data_i ( dst.r_data ), - .async_data_master_r_wptr_i ( dst.r_wptr ), - .async_data_master_r_rptr_o ( dst.r_rptr ) + .async_data_manager_aw_data_o ( dst.aw_data ), + .async_data_manager_aw_wptr_o ( dst.aw_wptr ), + .async_data_manager_aw_rptr_i ( dst.aw_rptr ), + .async_data_manager_w_data_o ( dst.w_data ), + .async_data_manager_w_wptr_o ( dst.w_wptr ), + .async_data_manager_w_rptr_i ( dst.w_rptr ), + .async_data_manager_b_data_i ( dst.b_data ), + .async_data_manager_b_wptr_i ( dst.b_wptr ), + .async_data_manager_b_rptr_o ( dst.b_rptr ), + .async_data_manager_ar_data_o ( dst.ar_data ), + .async_data_manager_ar_wptr_o ( dst.ar_wptr ), + .async_data_manager_ar_rptr_i ( dst.ar_rptr ), + .async_data_manager_r_data_i ( dst.r_data ), + .async_data_manager_r_wptr_i ( dst.r_wptr ), + .async_data_manager_r_rptr_o ( dst.r_rptr ) ); endmodule diff --git a/src/axi_cut.sv b/src/axi_cut.sv index a2b505230..48c420e11 100644 --- a/src/axi_cut.sv +++ b/src/axi_cut.sv @@ -33,11 +33,11 @@ module axi_cut #( input logic clk_i, input logic rst_ni, // salve port - input axi_req_t slv_req_i, - output axi_rsp_t slv_rsp_o, - // master port - output axi_req_t mst_req_o, - input axi_rsp_t mst_rsp_i + input axi_req_t sbr_req_i, + output axi_rsp_t sbr_rsp_o, + // manager port + output axi_req_t mgr_req_o, + input axi_rsp_t mgr_rsp_i ); // a spill register for each channel @@ -47,12 +47,12 @@ module axi_cut #( ) i_reg_aw ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.aw_valid ), - .ready_o ( slv_rsp_o.aw_ready ), - .data_i ( slv_req_i.aw ), - .valid_o ( mst_req_o.aw_valid ), - .ready_i ( mst_rsp_i.aw_ready ), - .data_o ( mst_req_o.aw ) + .valid_i ( sbr_req_i.aw_valid ), + .ready_o ( sbr_rsp_o.aw_ready ), + .data_i ( sbr_req_i.aw ), + .valid_o ( mgr_req_o.aw_valid ), + .ready_i ( mgr_rsp_i.aw_ready ), + .data_o ( mgr_req_o.aw ) ); spill_register #( @@ -61,12 +61,12 @@ module axi_cut #( ) i_reg_w ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.w_valid ), - .ready_o ( slv_rsp_o.w_ready ), - .data_i ( slv_req_i.w ), - .valid_o ( mst_req_o.w_valid ), - .ready_i ( mst_rsp_i.w_ready ), - .data_o ( mst_req_o.w ) + .valid_i ( sbr_req_i.w_valid ), + .ready_o ( sbr_rsp_o.w_ready ), + .data_i ( sbr_req_i.w ), + .valid_o ( mgr_req_o.w_valid ), + .ready_i ( mgr_rsp_i.w_ready ), + .data_o ( mgr_req_o.w ) ); spill_register #( @@ -75,12 +75,12 @@ module axi_cut #( ) i_reg_b ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsp_i.b_valid ), - .ready_o ( mst_req_o.b_ready ), - .data_i ( mst_rsp_i.b ), - .valid_o ( slv_rsp_o.b_valid ), - .ready_i ( slv_req_i.b_ready ), - .data_o ( slv_rsp_o.b ) + .valid_i ( mgr_rsp_i.b_valid ), + .ready_o ( mgr_req_o.b_ready ), + .data_i ( mgr_rsp_i.b ), + .valid_o ( sbr_rsp_o.b_valid ), + .ready_i ( sbr_req_i.b_ready ), + .data_o ( sbr_rsp_o.b ) ); spill_register #( @@ -89,12 +89,12 @@ module axi_cut #( ) i_reg_ar ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.ar_valid ), - .ready_o ( slv_rsp_o.ar_ready ), - .data_i ( slv_req_i.ar ), - .valid_o ( mst_req_o.ar_valid ), - .ready_i ( mst_rsp_i.ar_ready ), - .data_o ( mst_req_o.ar ) + .valid_i ( sbr_req_i.ar_valid ), + .ready_o ( sbr_rsp_o.ar_ready ), + .data_i ( sbr_req_i.ar ), + .valid_o ( mgr_req_o.ar_valid ), + .ready_i ( mgr_rsp_i.ar_ready ), + .data_o ( mgr_req_o.ar ) ); spill_register #( @@ -103,12 +103,12 @@ module axi_cut #( ) i_reg_r ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsp_i.r_valid ), - .ready_o ( mst_req_o.r_ready ), - .data_i ( mst_rsp_i.r ), - .valid_o ( slv_rsp_o.r_valid ), - .ready_i ( slv_req_i.r_ready ), - .data_o ( slv_rsp_o.r ) + .valid_i ( mgr_rsp_i.r_valid ), + .ready_o ( mgr_req_o.r_ready ), + .data_i ( mgr_rsp_i.r ), + .valid_o ( sbr_rsp_o.r_valid ), + .ready_i ( sbr_req_i.r_ready ), + .data_o ( sbr_rsp_o.r ) ); endmodule @@ -130,8 +130,8 @@ module axi_cut_intf #( ) ( input logic clk_i , input logic rst_ni , - AXI_BUS.Slave in , - AXI_BUS.Master out + AXI_BUS.Subordinate in , + AXI_BUS.Manager out ); typedef logic [ID_WIDTH-1:0] id_t; @@ -148,14 +148,14 @@ module axi_cut_intf #( `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_rsp_t slv_rsp, mst_rsp; + axi_req_t sbr_req, mgr_req; + axi_rsp_t sbr_rsp, mgr_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, in) - `AXI_ASSIGN_FROM_RSP(in, slv_rsp) + `AXI_ASSIGN_TO_REQ(sbr_req, in) + `AXI_ASSIGN_FROM_RSP(in, sbr_rsp) - `AXI_ASSIGN_FROM_REQ(out, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, out) + `AXI_ASSIGN_FROM_REQ(out, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, out) axi_cut #( .Bypass ( BYPASS ), @@ -169,10 +169,10 @@ module axi_cut_intf #( ) i_axi_cut ( .clk_i, .rst_ni, - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rep ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rep ) + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); // Check the invariants. @@ -206,8 +206,8 @@ module axi_lite_cut_intf #( ) ( input logic clk_i , input logic rst_ni , - AXI_LITE.Slave in , - AXI_LITE.Master out + AXI_LITE.Subordinate in , + AXI_LITE.Manager out ); typedef logic [ADDR_WIDTH-1:0] addr_t; @@ -222,14 +222,14 @@ module axi_lite_cut_intf #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - axi_lite_req_t slv_req, mst_req; - axi_lite_rsp_t slv_rsp, mst_rsp; + axi_lite_req_t sbr_req, mgr_req; + axi_lite_rsp_t sbr_rsp, mgr_rsp; - `AXI_LITE_ASSIGN_TO_REQ(slv_req, in) - `AXI_LITE_ASSIGN_FROM_RSP(in, slv_rsp) + `AXI_LITE_ASSIGN_TO_REQ(sbr_req, in) + `AXI_LITE_ASSIGN_FROM_RSP(in, sbr_rsp) - `AXI_LITE_ASSIGN_FROM_REQ(out, mst_req) - `AXI_LITE_ASSIGN_TO_RSP(mst_rsp, out) + `AXI_LITE_ASSIGN_FROM_REQ(out, mgr_req) + `AXI_LITE_ASSIGN_TO_RSP(mgr_rsp, out) axi_cut #( .Bypass ( BYPASS ), @@ -243,10 +243,10 @@ module axi_lite_cut_intf #( ) i_axi_cut ( .clk_i, .rst_ni, - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); // Check the invariants. diff --git a/src/axi_delayer.sv b/src/axi_delayer.sv index abcfc0626..3709dc833 100644 --- a/src/axi_delayer.sv +++ b/src/axi_delayer.sv @@ -32,12 +32,12 @@ module axi_delayer #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - // slave port - input axi_req_t slv_req_i, - output axi_rsp_t slv_rsp_o, - // master port - output axi_req_t mst_req_o, - input axi_rsp_t mst_rsp_i + // subordinate port + input axi_req_t sbr_req_i, + output axi_rsp_t sbr_rsp_o, + // manager port + output axi_req_t mgr_req_o, + input axi_rsp_t mgr_rsp_i ); // AW stream_delay #( @@ -47,12 +47,12 @@ module axi_delayer #( ) i_stream_delay_aw ( .clk_i, .rst_ni, - .payload_i ( slv_req_i.aw ), - .ready_o ( slv_rsp_o.aw_ready ), - .valid_i ( slv_req_i.aw_valid ), - .payload_o ( mst_req_o.aw ), - .ready_i ( mst_rsp_i.aw_ready ), - .valid_o ( mst_req_o.aw_valid ) + .payload_i ( sbr_req_i.aw ), + .ready_o ( sbr_rsp_o.aw_ready ), + .valid_i ( sbr_req_i.aw_valid ), + .payload_o ( mgr_req_o.aw ), + .ready_i ( mgr_rsp_i.aw_ready ), + .valid_o ( mgr_req_o.aw_valid ) ); // AR @@ -63,12 +63,12 @@ module axi_delayer #( ) i_stream_delay_ar ( .clk_i, .rst_ni, - .payload_i ( slv_req_i.ar ), - .ready_o ( slv_rsp_o.ar_ready ), - .valid_i ( slv_req_i.ar_valid ), - .payload_o ( mst_req_o.ar ), - .ready_i ( mst_rsp_i.ar_ready ), - .valid_o ( mst_req_o.ar_valid ) + .payload_i ( sbr_req_i.ar ), + .ready_o ( sbr_rsp_o.ar_ready ), + .valid_i ( sbr_req_i.ar_valid ), + .payload_o ( mgr_req_o.ar ), + .ready_i ( mgr_rsp_i.ar_ready ), + .valid_o ( mgr_req_o.ar_valid ) ); // W @@ -79,12 +79,12 @@ module axi_delayer #( ) i_stream_delay_w ( .clk_i, .rst_ni, - .payload_i ( slv_req_i.w ), - .ready_o ( slv_rsp_o.w_ready ), - .valid_i ( slv_req_i.w_valid ), - .payload_o ( mst_req_o.w ), - .ready_i ( mst_rsp_i.w_ready ), - .valid_o ( mst_req_o.w_valid ) + .payload_i ( sbr_req_i.w ), + .ready_o ( sbr_rsp_o.w_ready ), + .valid_i ( sbr_req_i.w_valid ), + .payload_o ( mgr_req_o.w ), + .ready_i ( mgr_rsp_i.w_ready ), + .valid_o ( mgr_req_o.w_valid ) ); // B @@ -95,12 +95,12 @@ module axi_delayer #( ) i_stream_delay_b ( .clk_i, .rst_ni, - .payload_i ( mst_rsp_i.b ), - .ready_o ( mst_req_o.b_ready ), - .valid_i ( mst_rsp_i.b_valid ), - .payload_o ( slv_rsp_o.b ), - .ready_i ( slv_req_i.b_ready ), - .valid_o ( slv_rsp_o.b_valid ) + .payload_i ( mgr_rsp_i.b ), + .ready_o ( mgr_req_o.b_ready ), + .valid_i ( mgr_rsp_i.b_valid ), + .payload_o ( sbr_rsp_o.b ), + .ready_i ( sbr_req_i.b_ready ), + .valid_o ( sbr_rsp_o.b_valid ) ); // R @@ -111,12 +111,12 @@ module axi_delayer #( ) i_stream_delay_r ( .clk_i, .rst_ni, - .payload_i ( mst_rsp_i.r ), - .ready_o ( mst_req_o.r_ready ), - .valid_i ( mst_rsp_i.r_valid ), - .payload_o ( slv_rsp_o.r ), - .ready_i ( slv_req_i.r_ready ), - .valid_o ( slv_rsp_o.r_valid ) + .payload_i ( mgr_rsp_i.r ), + .ready_o ( mgr_req_o.r_ready ), + .valid_i ( mgr_rsp_i.r_valid ), + .payload_o ( sbr_rsp_o.r ), + .ready_i ( sbr_req_i.r_ready ), + .valid_o ( sbr_rsp_o.r_valid ) ); endmodule @@ -137,8 +137,8 @@ module axi_delayer_intf #( ) ( input logic clk_i, input logic rst_ni, - AXI_BUS.Slave slv, - AXI_BUS.Master mst + AXI_BUS.Subordinate sbr, + AXI_BUS.Manager mgr ); typedef logic [AXI_ID_WIDTH-1:0] id_t; @@ -155,14 +155,14 @@ module axi_delayer_intf #( `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_rsp_t slv_rsp, mst_rsp; + axi_req_t sbr_req, mgr_req; + axi_rsp_t sbr_rsp, mgr_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, slv_rsp) + `AXI_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, sbr_rsp) - `AXI_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, mst) + `AXI_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_delayer #( .aw_chan_t ( aw_chan_t ), @@ -179,10 +179,10 @@ module axi_delayer_intf #( ) i_axi_delayer ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); // pragma translate_off diff --git a/src/axi_demux.sv b/src/axi_demux.sv index c4b566e14..a4d7f4f95 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -21,11 +21,11 @@ `define TARGET_VSIM `endif -/// Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports. +/// Demultiplex one AXI4+ATOP subordinate port to multiple AXI4+ATOP manager ports. /// -/// The AW and AR slave channels each have a `select` input to determine to which master port the +/// The AW and AR subordinate channels each have a `select` input to determine to which manager port the /// current request is sent. The `select` can, for example, be driven by an address decoding module -/// to map address ranges to different AXI slaves. +/// to map address ranges to different AXI subordinates. /// /// ## Design overview /// @@ -35,7 +35,7 @@ /// corresponding AW beat. This relies on the AXI property that W bursts must be sent in the same /// order as AW beats and beats from different W bursts may not be interleaved. /// -/// Beats on the B and R channel are multiplexed from the master ports to the slave port with +/// Beats on the B and R channel are multiplexed from the manager ports to the subordinate port with /// a round-robin arbitration tree. module axi_demux #( parameter int unsigned IdWidth = 32'd0, @@ -47,7 +47,7 @@ module axi_demux #( parameter type r_chan_t = logic, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic, - parameter int unsigned NumMstPorts = 32'd0, + parameter int unsigned NumMgrPorts = 32'd0, parameter int unsigned MaxTrans = 32'd8, parameter int unsigned LookBits = 32'd3, parameter bit UniqueIds = 1'b0, @@ -57,40 +57,40 @@ module axi_demux #( parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0, // Dependent parameters, DO NOT OVERRIDE! - parameter int unsigned SelectWidth = (NumMstPorts > 32'd1) ? $clog2(NumMstPorts) : 32'd1, + parameter int unsigned SelectWidth = (NumMgrPorts > 32'd1) ? $clog2(NumMgrPorts) : 32'd1, parameter type select_t = logic [SelectWidth-1:0] ) ( input logic clk_i, input logic rst_ni, input logic test_i, - // Slave Port - input axi_req_t slv_req_i, - input select_t slv_aw_select_i, - input select_t slv_ar_select_i, - output axi_rsp_t slv_rsp_o, - // Master Ports - output axi_req_t [NumMstPorts-1:0] mst_reqs_o, - input axi_rsp_t [NumMstPorts-1:0] mst_rsps_i + // Subordinate Port + input axi_req_t sbr_req_i, + input select_t sbr_aw_select_i, + input select_t sbr_ar_select_i, + output axi_rsp_t sbr_rsp_o, + // Manager Ports + output axi_req_t [NumMgrPorts-1:0] mgr_reqs_o, + input axi_rsp_t [NumMgrPorts-1:0] mgr_rsps_i ); localparam int unsigned IdCounterWidth = cf_math_pkg::idx_width(MaxTrans); typedef logic [IdCounterWidth-1:0] id_cnt_t; - // pass through if only one master port - if (NumMstPorts == 32'h1) begin : gen_no_demux + // pass through if only one manager port + if (NumMgrPorts == 32'h1) begin : gen_no_demux spill_register #( .T ( aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.aw_valid ), - .ready_o ( slv_rsp_o.aw_ready ), - .data_i ( slv_req_i.aw ), - .valid_o ( mst_reqs_o[0].aw_valid ), - .ready_i ( mst_rsps_i[0].aw_ready ), - .data_o ( mst_reqs_o[0].aw ) + .valid_i ( sbr_req_i.aw_valid ), + .ready_o ( sbr_rsp_o.aw_ready ), + .data_i ( sbr_req_i.aw ), + .valid_o ( mgr_reqs_o[0].aw_valid ), + .ready_i ( mgr_rsps_i[0].aw_ready ), + .data_o ( mgr_reqs_o[0].aw ) ); spill_register #( .T ( w_chan_t ), @@ -98,12 +98,12 @@ module axi_demux #( ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.w_valid ), - .ready_o ( slv_rsp_o.w_ready ), - .data_i ( slv_req_i.w ), - .valid_o ( mst_reqs_o[0].w_valid ), - .ready_i ( mst_rsps_i[0].w_ready ), - .data_o ( mst_reqs_o[0].w ) + .valid_i ( sbr_req_i.w_valid ), + .ready_o ( sbr_rsp_o.w_ready ), + .data_i ( sbr_req_i.w ), + .valid_o ( mgr_reqs_o[0].w_valid ), + .ready_i ( mgr_rsps_i[0].w_ready ), + .data_o ( mgr_reqs_o[0].w ) ); spill_register #( .T ( b_chan_t ), @@ -111,12 +111,12 @@ module axi_demux #( ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsps_i[0].b_valid ), - .ready_o ( mst_reqs_o[0].b_ready ), - .data_i ( mst_rsps_i[0].b ), - .valid_o ( slv_rsp_o.b_valid ), - .ready_i ( slv_req_i.b_ready ), - .data_o ( slv_rsp_o.b ) + .valid_i ( mgr_rsps_i[0].b_valid ), + .ready_o ( mgr_reqs_o[0].b_ready ), + .data_i ( mgr_rsps_i[0].b ), + .valid_o ( sbr_rsp_o.b_valid ), + .ready_i ( sbr_req_i.b_ready ), + .data_o ( sbr_rsp_o.b ) ); spill_register #( .T ( ar_chan_t ), @@ -124,12 +124,12 @@ module axi_demux #( ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.ar_valid ), - .ready_o ( slv_rsp_o.ar_ready ), - .data_i ( slv_req_i.ar ), - .valid_o ( mst_reqs_o[0].ar_valid ), - .ready_i ( mst_rsps_i[0].ar_ready ), - .data_o ( mst_reqs_o[0].ar ) + .valid_i ( sbr_req_i.ar_valid ), + .ready_o ( sbr_rsp_o.ar_ready ), + .data_i ( sbr_req_i.ar ), + .valid_o ( mgr_reqs_o[0].ar_valid ), + .ready_i ( mgr_rsps_i[0].ar_ready ), + .data_o ( mgr_reqs_o[0].ar ) ); spill_register #( .T ( r_chan_t ), @@ -137,12 +137,12 @@ module axi_demux #( ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsps_i[0].r_valid ), - .ready_o ( mst_reqs_o[0].r_ready ), - .data_i ( mst_rsps_i[0].r ), - .valid_o ( slv_rsp_o.r_valid ), - .ready_i ( slv_req_i.r_ready ), - .data_o ( slv_rsp_o.r ) + .valid_i ( mgr_rsps_i[0].r_valid ), + .ready_o ( mgr_reqs_o[0].r_ready ), + .data_i ( mgr_rsps_i[0].r ), + .valid_o ( sbr_rsp_o.r_valid ), + .ready_i ( sbr_req_i.r_ready ), + .data_o ( sbr_rsp_o.r ) ); // other non degenerate cases @@ -158,11 +158,11 @@ module axi_demux #( // Write Transaction //-------------------------------------- // comes from spill register at input - aw_chan_t slv_aw_chan; - select_t slv_aw_select; + aw_chan_t sbr_aw_chan; + select_t sbr_aw_select; - logic slv_aw_valid, slv_aw_valid_chan, slv_aw_valid_sel; - logic slv_aw_ready, slv_aw_ready_chan, slv_aw_ready_sel; + logic sbr_aw_valid, sbr_aw_valid_chan, sbr_aw_valid_sel; + logic sbr_aw_ready, sbr_aw_ready_chan, sbr_aw_ready_sel; // AW ID counter select_t lookup_aw_select; @@ -170,7 +170,7 @@ module axi_demux #( // Upon an ATOP load, inject IDs from the AW into the AR channel logic atop_inject; - // W select counter: stores the decision to which master W beats should go + // W select counter: stores the decision to which manager W beats should go select_t w_select, w_select_q; logic w_select_valid; id_cnt_t w_open; @@ -181,23 +181,23 @@ module axi_demux #( logic aw_valid, aw_ready; // W channel from spill reg - w_chan_t slv_w_chan; - logic slv_w_valid, slv_w_ready; + w_chan_t sbr_w_chan; + logic sbr_w_valid, sbr_w_ready; // B channles input into the arbitration - b_chan_t [NumMstPorts-1:0] mst_b_chans; - logic [NumMstPorts-1:0] mst_b_valids, mst_b_readies; + b_chan_t [NumMgrPorts-1:0] mgr_b_chans; + logic [NumMgrPorts-1:0] mgr_b_valids, mgr_b_readies; // B channel to spill register - b_chan_t slv_b_chan; - logic slv_b_valid, slv_b_ready; + b_chan_t sbr_b_chan; + logic sbr_b_valid, sbr_b_ready; //-------------------------------------- // Read Transaction //-------------------------------------- // comes from spill register at input - logic slv_ar_valid, ar_valid_chan, ar_valid_sel; - logic slv_ar_ready, slv_ar_ready_chan, slv_ar_ready_sel; + logic sbr_ar_valid, ar_valid_chan, ar_valid_sel; + logic sbr_ar_ready, sbr_ar_ready_chan, sbr_ar_ready_sel; // AR ID counter select_t lookup_ar_select; @@ -209,12 +209,12 @@ module axi_demux #( logic ar_valid, ar_ready; // R channles input into the arbitration - r_chan_t [NumMstPorts-1:0] mst_r_chans; - logic [NumMstPorts-1:0] mst_r_valids, mst_r_readies; + r_chan_t [NumMgrPorts-1:0] mgr_r_chans; + logic [NumMgrPorts-1:0] mgr_r_valids, mgr_r_readies; // R channel to spill register - r_chan_t slv_r_chan; - logic slv_r_valid, slv_r_ready; + r_chan_t sbr_r_chan; + logic sbr_r_valid, sbr_r_ready; //-------------------------------------- //-------------------------------------- @@ -232,12 +232,12 @@ module axi_demux #( ) i_aw_channel_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.aw_valid ), - .ready_o ( slv_aw_ready_chan ), - .data_i ( slv_req_i.aw ), - .valid_o ( slv_aw_valid_chan ), - .ready_i ( slv_aw_ready ), - .data_o ( slv_aw_chan ) + .valid_i ( sbr_req_i.aw_valid ), + .ready_o ( sbr_aw_ready_chan ), + .data_i ( sbr_req_i.aw ), + .valid_o ( sbr_aw_valid_chan ), + .ready_i ( sbr_aw_ready ), + .data_o ( sbr_aw_chan ) ); spill_register #( .T ( select_t ), @@ -245,20 +245,20 @@ module axi_demux #( ) i_aw_select_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.aw_valid ), - .ready_o ( slv_aw_ready_sel ), - .data_i ( slv_aw_select_i ), - .valid_o ( slv_aw_valid_sel ), - .ready_i ( slv_aw_ready ), - .data_o ( slv_aw_select ) + .valid_i ( sbr_req_i.aw_valid ), + .ready_o ( sbr_aw_ready_sel ), + .data_i ( sbr_aw_select_i ), + .valid_o ( sbr_aw_valid_sel ), + .ready_i ( sbr_aw_ready ), + .data_o ( sbr_aw_select ) ); - assign slv_rsp_o.aw_ready = slv_aw_ready_chan & slv_aw_ready_sel; - assign slv_aw_valid = slv_aw_valid_chan & slv_aw_valid_sel; + assign sbr_rsp_o.aw_ready = sbr_aw_ready_chan & sbr_aw_ready_sel; + assign sbr_aw_valid = sbr_aw_valid_chan & sbr_aw_valid_sel; // Control of the AW handshake always_comb begin // AXI Handshakes - slv_aw_ready = 1'b0; + sbr_aw_ready = 1'b0; aw_valid = 1'b0; // `lock_aw_valid`, used to be protocol conform as it is not allowed to deassert // a valid if there was no corresponding ready. As this process has to be able to inject @@ -276,34 +276,34 @@ module axi_demux #( aw_valid = 1'b1; // transaction if (aw_ready) begin - slv_aw_ready = 1'b1; + sbr_aw_ready = 1'b1; lock_aw_valid_d = 1'b0; load_aw_lock = 1'b1; // inject the ATOP if necessary - atop_inject = slv_aw_chan.atop[axi_pkg::ATOP_R_RESP] & AtopSupport; + atop_inject = sbr_aw_chan.atop[axi_pkg::ATOP_R_RESP] & AtopSupport; end end else begin // An AW can be handled if `i_aw_id_counter` and `i_counter_open_w` are not full. An ATOP that // requires an R response can be handled if additionally `i_ar_id_counter` is not full (this // only applies if ATOPs are supported at all). if (!aw_id_cnt_full && (w_open != {IdCounterWidth{1'b1}}) && - (!(ar_id_cnt_full && slv_aw_chan.atop[axi_pkg::ATOP_R_RESP]) || + (!(ar_id_cnt_full && sbr_aw_chan.atop[axi_pkg::ATOP_R_RESP]) || !AtopSupport)) begin // There is a valid AW vector make the id lookup and go further, if it passes. // Also stall if previous transmitted AWs still have active W's in flight. // This prevents deadlocking of the W channel. The counters are there for the // Handling of the B responses. - if (slv_aw_valid && - ((w_open == '0) || (w_select == slv_aw_select)) && - (!aw_select_occupied || (slv_aw_select == lookup_aw_select))) begin + if (sbr_aw_valid && + ((w_open == '0) || (w_select == sbr_aw_select)) && + (!aw_select_occupied || (sbr_aw_select == lookup_aw_select))) begin // connect the handshake aw_valid = 1'b1; // push arbitration to the W FIFO regardless, do not wait for the AW transaction w_cnt_up = 1'b1; // on AW transaction if (aw_ready) begin - slv_aw_ready = 1'b1; - atop_inject = slv_aw_chan.atop[axi_pkg::ATOP_R_RESP] & AtopSupport; + sbr_aw_ready = 1'b1; + atop_inject = sbr_aw_chan.atop[axi_pkg::ATOP_R_RESP] & AtopSupport; // no AW transaction this cycle, lock the decision end else begin lock_aw_valid_d = 1'b1; @@ -321,31 +321,31 @@ module axi_demux #( if (UniqueIds) begin : gen_unique_ids_aw // If the `UniqueIds` parameter is set, each write transaction has an ID that is unique among // all in-flight write transactions, or all write transactions with a given ID target the same - // master port as all write transactions with the same ID, or both. This means that the + // manager port as all write transactions with the same ID, or both. This means that the // signals that are driven by the ID counters if this parameter is not set can instead be // derived from existing signals. The ID counters can therefore be omitted. - assign lookup_aw_select = slv_aw_select; + assign lookup_aw_select = sbr_aw_select; assign aw_select_occupied = 1'b0; assign aw_id_cnt_full = 1'b0; end else begin : gen_aw_id_counter axi_demux_id_counters #( .IdBits ( LookBits ), .CounterWidth ( IdCounterWidth ), - .mst_port_select_t ( select_t ) + .mgr_port_select_t ( select_t ) ) i_aw_id_counter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .lookup_axi_id_i ( slv_aw_chan.id[0+:LookBits] ), - .lookup_mst_select_o ( lookup_aw_select ), - .lookup_mst_select_occupied_o ( aw_select_occupied ), + .lookup_axi_id_i ( sbr_aw_chan.id[0+:LookBits] ), + .lookup_mgr_select_o ( lookup_aw_select ), + .lookup_mgr_select_occupied_o ( aw_select_occupied ), .full_o ( aw_id_cnt_full ), .inject_axi_id_i ( '0 ), .inject_i ( 1'b0 ), - .push_axi_id_i ( slv_aw_chan.id[0+:LookBits] ), - .push_mst_select_i ( slv_aw_select ), + .push_axi_id_i ( sbr_aw_chan.id[0+:LookBits] ), + .push_mgr_select_i ( sbr_aw_select ), .push_i ( w_cnt_up ), - .pop_axi_id_i ( slv_b_chan.id[0+:LookBits] ), - .pop_i ( slv_b_valid & slv_b_ready ) + .pop_axi_id_i ( sbr_b_chan.id[0+:LookBits] ), + .pop_i ( sbr_b_valid & sbr_b_ready ) ); // pop from ID counter on outward transaction end @@ -353,7 +353,7 @@ module axi_demux #( // This counter steers the demultiplexer of the W channel. // `w_select` determines, which handshaking is connected. // AWs are only forwarded, if the counter is empty, or `w_select_q` is the same as - // `slv_aw_select`. + // `sbr_aw_select`. counter #( .WIDTH ( IdCounterWidth ), .STICKY_OVERFLOW ( 1'b0 ) @@ -369,8 +369,8 @@ module axi_demux #( .overflow_o ( /*not used*/ ) ); - `FFLARN(w_select_q, slv_aw_select, w_cnt_up, select_t'(0), clk_i, rst_ni) - assign w_select = (|w_open) ? w_select_q : slv_aw_select; + `FFLARN(w_select_q, sbr_aw_select, w_cnt_up, select_t'(0), clk_i, rst_ni) + assign w_select = (|w_open) ? w_select_q : sbr_aw_select; assign w_select_valid = w_cnt_up | (|w_open); //-------------------------------------- @@ -382,12 +382,12 @@ module axi_demux #( ) i_w_spill_reg( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.w_valid ), - .ready_o ( slv_rsp_o.w_ready ), - .data_i ( slv_req_i.w ), - .valid_o ( slv_w_valid ), - .ready_i ( slv_w_ready ), - .data_o ( slv_w_chan ) + .valid_i ( sbr_req_i.w_valid ), + .ready_o ( sbr_rsp_o.w_ready ), + .data_i ( sbr_req_i.w ), + .valid_o ( sbr_w_valid ), + .ready_i ( sbr_w_ready ), + .data_o ( sbr_w_chan ) ); //-------------------------------------- @@ -400,17 +400,17 @@ module axi_demux #( ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_b_valid ), - .ready_o ( slv_b_ready ), - .data_i ( slv_b_chan ), - .valid_o ( slv_rsp_o.b_valid ), - .ready_i ( slv_req_i.b_ready ), - .data_o ( slv_rsp_o.b ) + .valid_i ( sbr_b_valid ), + .ready_o ( sbr_b_ready ), + .data_i ( sbr_b_chan ), + .valid_o ( sbr_rsp_o.b_valid ), + .ready_i ( sbr_req_i.b_ready ), + .data_o ( sbr_rsp_o.b ) ); // Arbitration of the different B responses rr_arb_tree #( - .NumIn ( NumMstPorts ), + .NumIn ( NumMgrPorts ), .DataType ( b_chan_t ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) @@ -419,32 +419,32 @@ module axi_demux #( .rst_ni ( rst_ni ), .flush_i( 1'b0 ), .rr_i ( '0 ), - .req_i ( mst_b_valids ), - .gnt_o ( mst_b_readies ), - .data_i ( mst_b_chans ), - .gnt_i ( slv_b_ready ), - .req_o ( slv_b_valid ), - .data_o ( slv_b_chan ), + .req_i ( mgr_b_valids ), + .gnt_o ( mgr_b_readies ), + .data_i ( mgr_b_chans ), + .gnt_i ( sbr_b_ready ), + .req_o ( sbr_b_valid ), + .data_o ( sbr_b_chan ), .idx_o ( ) ); //-------------------------------------- // AR Channel //-------------------------------------- - ar_chan_t slv_ar_chan; - select_t slv_ar_select; + ar_chan_t sbr_ar_chan; + select_t sbr_ar_select; spill_register #( .T ( ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_chan_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.ar_valid ), - .ready_o ( slv_ar_ready_chan ), - .data_i ( slv_req_i.ar ), + .valid_i ( sbr_req_i.ar_valid ), + .ready_o ( sbr_ar_ready_chan ), + .data_i ( sbr_req_i.ar ), .valid_o ( ar_valid_chan ), - .ready_i ( slv_ar_ready ), - .data_o ( slv_ar_chan ) + .ready_i ( sbr_ar_ready ), + .data_o ( sbr_ar_chan ) ); spill_register #( .T ( select_t ), @@ -452,20 +452,20 @@ module axi_demux #( ) i_ar_sel_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.ar_valid ), - .ready_o ( slv_ar_ready_sel ), - .data_i ( slv_ar_select_i ), + .valid_i ( sbr_req_i.ar_valid ), + .ready_o ( sbr_ar_ready_sel ), + .data_i ( sbr_ar_select_i ), .valid_o ( ar_valid_sel ), - .ready_i ( slv_ar_ready ), - .data_o ( slv_ar_select ) + .ready_i ( sbr_ar_ready ), + .data_o ( sbr_ar_select ) ); - assign slv_rsp_o.ar_ready = slv_ar_ready_chan & slv_ar_ready_sel; - assign slv_ar_valid = ar_valid_chan & ar_valid_sel; + assign sbr_rsp_o.ar_ready = sbr_ar_ready_chan & sbr_ar_ready_sel; + assign sbr_ar_valid = ar_valid_chan & ar_valid_sel; // control of the AR handshake always_comb begin // AXI Handshakes - slv_ar_ready = 1'b0; + sbr_ar_ready = 1'b0; ar_valid = 1'b0; // `lock_ar_valid`: Used to be protocol conform as it is not allowed to deassert `ar_valid` // if there was no corresponding `ar_ready`. There is the possibility that an injection @@ -481,7 +481,7 @@ module axi_demux #( ar_valid = 1'b1; // transaction if (ar_ready) begin - slv_ar_ready = 1'b1; + sbr_ar_ready = 1'b1; ar_push = 1'b1; lock_ar_valid_d = 1'b0; load_ar_lock = 1'b1; @@ -490,13 +490,13 @@ module axi_demux #( // The process can start handling AR transaction if `i_ar_id_counter` has space. if (!ar_id_cnt_full) begin // There is a valid AR, so look the ID up. - if (slv_ar_valid && (!ar_select_occupied || - (slv_ar_select == lookup_ar_select))) begin + if (sbr_ar_valid && (!ar_select_occupied || + (sbr_ar_select == lookup_ar_select))) begin // connect the AR handshake ar_valid = 1'b1; // on transaction if (ar_ready) begin - slv_ar_ready = 1'b1; + sbr_ar_ready = 1'b1; ar_push = 1'b1; // no transaction this cycle, lock the valid decision! end else begin @@ -514,31 +514,31 @@ module axi_demux #( if (UniqueIds) begin : gen_unique_ids_ar // If the `UniqueIds` parameter is set, each read transaction has an ID that is unique among // all in-flight read transactions, or all read transactions with a given ID target the same - // master port as all read transactions with the same ID, or both. This means that the + // manager port as all read transactions with the same ID, or both. This means that the // signals that are driven by the ID counters if this parameter is not set can instead be // derived from existing signals. The ID counters can therefore be omitted. - assign lookup_ar_select = slv_ar_select; + assign lookup_ar_select = sbr_ar_select; assign ar_select_occupied = 1'b0; assign ar_id_cnt_full = 1'b0; end else begin : gen_ar_id_counter axi_demux_id_counters #( .IdBits ( LookBits ), .CounterWidth ( IdCounterWidth ), - .mst_port_select_t ( select_t ) + .mgr_port_select_t ( select_t ) ) i_ar_id_counter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .lookup_axi_id_i ( slv_ar_chan.id[0+:LookBits] ), - .lookup_mst_select_o ( lookup_ar_select ), - .lookup_mst_select_occupied_o ( ar_select_occupied ), + .lookup_axi_id_i ( sbr_ar_chan.id[0+:LookBits] ), + .lookup_mgr_select_o ( lookup_ar_select ), + .lookup_mgr_select_occupied_o ( ar_select_occupied ), .full_o ( ar_id_cnt_full ), - .inject_axi_id_i ( slv_aw_chan.id[0+:LookBits] ), + .inject_axi_id_i ( sbr_aw_chan.id[0+:LookBits] ), .inject_i ( atop_inject ), - .push_axi_id_i ( slv_ar_chan.id[0+:LookBits] ), - .push_mst_select_i ( slv_ar_select ), + .push_axi_id_i ( sbr_ar_chan.id[0+:LookBits] ), + .push_mgr_select_i ( sbr_ar_select ), .push_i ( ar_push ), - .pop_axi_id_i ( slv_r_chan.id[0+:LookBits] ), - .pop_i ( slv_r_valid & slv_r_ready & slv_r_chan.last ) + .pop_axi_id_i ( sbr_r_chan.id[0+:LookBits] ), + .pop_i ( sbr_r_valid & sbr_r_ready & sbr_r_chan.last ) ); end @@ -552,17 +552,17 @@ module axi_demux #( ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_r_valid ), - .ready_o ( slv_r_ready ), - .data_i ( slv_r_chan ), - .valid_o ( slv_rsp_o.r_valid ), - .ready_i ( slv_req_i.r_ready ), - .data_o ( slv_rsp_o.r ) + .valid_i ( sbr_r_valid ), + .ready_o ( sbr_r_ready ), + .data_i ( sbr_r_chan ), + .valid_o ( sbr_rsp_o.r_valid ), + .ready_i ( sbr_req_i.r_ready ), + .data_o ( sbr_rsp_o.r ) ); // Arbitration of the different r responses rr_arb_tree #( - .NumIn ( NumMstPorts ), + .NumIn ( NumMgrPorts ), .DataType ( r_chan_t ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) @@ -571,63 +571,63 @@ module axi_demux #( .rst_ni ( rst_ni ), .flush_i( 1'b0 ), .rr_i ( '0 ), - .req_i ( mst_r_valids ), - .gnt_o ( mst_r_readies ), - .data_i ( mst_r_chans ), - .gnt_i ( slv_r_ready ), - .req_o ( slv_r_valid ), - .data_o ( slv_r_chan ), + .req_i ( mgr_r_valids ), + .gnt_o ( mgr_r_readies ), + .data_i ( mgr_r_chans ), + .gnt_i ( sbr_r_ready ), + .req_o ( sbr_r_valid ), + .data_o ( sbr_r_chan ), .idx_o ( ) ); - assign ar_ready = ar_valid & mst_rsps_i[slv_ar_select].ar_ready; - assign aw_ready = aw_valid & mst_rsps_i[slv_aw_select].aw_ready; + assign ar_ready = ar_valid & mgr_rsps_i[sbr_ar_select].ar_ready; + assign aw_ready = aw_valid & mgr_rsps_i[sbr_aw_select].aw_ready; // process that defines the individual demuxes and assignments for the arbitration - // as mst_reqs_o has to be drivem from the same always comb block! + // as mgr_reqs_o has to be drivem from the same always comb block! always_comb begin // default assignments - mst_reqs_o = '0; - slv_w_ready = 1'b0; + mgr_reqs_o = '0; + sbr_w_ready = 1'b0; w_cnt_down = 1'b0; - for (int unsigned i = 0; i < NumMstPorts; i++) begin + for (int unsigned i = 0; i < NumMgrPorts; i++) begin // AW channel - mst_reqs_o[i].aw = slv_aw_chan; - mst_reqs_o[i].aw_valid = 1'b0; - if (aw_valid && (slv_aw_select == i)) begin - mst_reqs_o[i].aw_valid = 1'b1; + mgr_reqs_o[i].aw = sbr_aw_chan; + mgr_reqs_o[i].aw_valid = 1'b0; + if (aw_valid && (sbr_aw_select == i)) begin + mgr_reqs_o[i].aw_valid = 1'b1; end // W channel - mst_reqs_o[i].w = slv_w_chan; - mst_reqs_o[i].w_valid = 1'b0; + mgr_reqs_o[i].w = sbr_w_chan; + mgr_reqs_o[i].w_valid = 1'b0; if (w_select_valid && (w_select == i)) begin - mst_reqs_o[i].w_valid = slv_w_valid; - slv_w_ready = mst_rsps_i[i].w_ready; - w_cnt_down = slv_w_valid & mst_rsps_i[i].w_ready & slv_w_chan.last; + mgr_reqs_o[i].w_valid = sbr_w_valid; + sbr_w_ready = mgr_rsps_i[i].w_ready; + w_cnt_down = sbr_w_valid & mgr_rsps_i[i].w_ready & sbr_w_chan.last; end // B channel - mst_reqs_o[i].b_ready = mst_b_readies[i]; + mgr_reqs_o[i].b_ready = mgr_b_readies[i]; // AR channel - mst_reqs_o[i].ar = slv_ar_chan; - mst_reqs_o[i].ar_valid = 1'b0; - if (ar_valid && (slv_ar_select == i)) begin - mst_reqs_o[i].ar_valid = 1'b1; + mgr_reqs_o[i].ar = sbr_ar_chan; + mgr_reqs_o[i].ar_valid = 1'b0; + if (ar_valid && (sbr_ar_select == i)) begin + mgr_reqs_o[i].ar_valid = 1'b1; end // R channel - mst_reqs_o[i].r_ready = mst_r_readies[i]; + mgr_reqs_o[i].r_ready = mgr_r_readies[i]; end end // unpack the response B and R channels for the arbitration - for (genvar i = 0; i < NumMstPorts; i++) begin : gen_b_channels - assign mst_b_chans[i] = mst_rsps_i[i].b; - assign mst_b_valids[i] = mst_rsps_i[i].b_valid; - assign mst_r_chans[i] = mst_rsps_i[i].r; - assign mst_r_valids[i] = mst_rsps_i[i].r_valid; + for (genvar i = 0; i < NumMgrPorts; i++) begin : gen_b_channels + assign mgr_b_chans[i] = mgr_rsps_i[i].b; + assign mgr_b_valids[i] = mgr_rsps_i[i].b_valid; + assign mgr_r_chans[i] = mgr_rsps_i[i].r; + assign mgr_r_valids[i] = mgr_rsps_i[i].r_valid; end @@ -636,47 +636,47 @@ module axi_demux #( `ifndef VERILATOR `ifndef XSIM initial begin: validate_params - no_mst_ports: assume (NumMstPorts > 0) else - $fatal(1, "The Number of slaves (NumMstPorts) has to be at least 1"); + no_mgr_ports: assume (NumMgrPorts > 0) else + $fatal(1, "The Number of subordinates (NumMgrPorts) has to be at least 1"); AXI_ID_BITS: assume (IdWidth >= LookBits) else $fatal(1, "IdBits has to be equal or smaller than IdWidth."); end default disable iff (!rst_ni); - aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> - (slv_aw_select_i < NumMstPorts))) else - $fatal(1, "slv_aw_select_i is %d: AW has selected a slave that is not defined.\ - NumMstPorts: %d", slv_aw_select_i, NumMstPorts); - ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |-> - (slv_ar_select_i < NumMstPorts))) else - $fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\ - NumMstPorts: %d", slv_ar_select_i, NumMstPorts); + aw_select: assume property( @(posedge clk_i) (sbr_req_i.aw_valid |-> + (sbr_aw_select_i < NumMgrPorts))) else + $fatal(1, "sbr_aw_select_i is %d: AW has selected a subordinate that is not defined.\ + NumMgrPorts: %d", sbr_aw_select_i, NumMgrPorts); + ar_select: assume property( @(posedge clk_i) (sbr_req_i.ar_valid |-> + (sbr_ar_select_i < NumMgrPorts))) else + $fatal(1, "sbr_ar_select_i is %d: AR has selected a subordinate that is not defined.\ + NumMgrPorts: %d", sbr_ar_select_i, NumMgrPorts); aw_valid_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) |=> aw_valid) else $fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle."); ar_valid_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready) |=> ar_valid) else $fatal(1, "ar_valid was deasserted, when ar_ready = 0 in last cycle."); - slv_aw_chan_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) - |=> $stable(slv_aw_chan)) else - $fatal(1, "slv_aw_chan unstable with valid set."); - slv_aw_select_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) - |=> $stable(slv_aw_select)) else - $fatal(1, "slv_aw_select unstable with valid set."); - slv_ar_chan_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready) - |=> $stable(slv_ar_chan)) else - $fatal(1, "slv_ar_chan unstable with valid set."); - slv_ar_select_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready) - |=> $stable(slv_ar_select)) else - $fatal(1, "slv_ar_select unstable with valid set."); + sbr_aw_chan_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) + |=> $stable(sbr_aw_chan)) else + $fatal(1, "sbr_aw_chan unstable with valid set."); + sbr_aw_select_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) + |=> $stable(sbr_aw_select)) else + $fatal(1, "sbr_aw_select unstable with valid set."); + sbr_ar_chan_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready) + |=> $stable(sbr_ar_chan)) else + $fatal(1, "sbr_ar_chan unstable with valid set."); + sbr_ar_select_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready) + |=> $stable(sbr_ar_select)) else + $fatal(1, "sbr_ar_select unstable with valid set."); internal_ar_select: assert property( @(posedge clk_i) - (ar_valid |-> slv_ar_select < NumMstPorts)) - else $fatal(1, "slv_ar_select illegal while ar_valid."); + (ar_valid |-> sbr_ar_select < NumMgrPorts)) + else $fatal(1, "sbr_ar_select illegal while ar_valid."); internal_aw_select: assert property( @(posedge clk_i) - (aw_valid |-> slv_aw_select < NumMstPorts)) - else $fatal(1, "slv_aw_select illegal while aw_valid."); + (aw_valid |-> sbr_aw_select < NumMgrPorts)) + else $fatal(1, "sbr_aw_select illegal while aw_valid."); w_underflow: assert property( @(posedge clk_i) ((w_open == '0) && (w_cnt_up ^ w_cnt_down) |-> !w_cnt_down)) else $fatal(1, "W counter underflowed!"); - `ASSUME(NoAtopAllowed, !AtopSupport && slv_req_i.aw_valid |-> slv_req_i.aw.atop == '0) + `ASSUME(NoAtopAllowed, !AtopSupport && sbr_req_i.aw_valid |-> sbr_req_i.aw.atop == '0) `endif `endif // pragma translate_on @@ -687,18 +687,18 @@ module axi_demux_id_counters #( // the lower bits of the AXI ID that should be considered, results in 2**AXI_ID_BITS counters parameter int unsigned IdBits = 2, parameter int unsigned CounterWidth = 4, - parameter type mst_port_select_t = logic + parameter type mgr_port_select_t = logic ) ( input clk_i, // Clock input rst_ni, // Asynchronous reset active low // lookup input logic [IdBits-1:0] lookup_axi_id_i, - output mst_port_select_t lookup_mst_select_o, - output logic lookup_mst_select_occupied_o, + output mgr_port_select_t lookup_mgr_select_o, + output logic lookup_mgr_select_occupied_o, // push output logic full_o, input logic [IdBits-1:0] push_axi_id_i, - input mst_port_select_t push_mst_select_i, + input mgr_port_select_t push_mgr_select_i, input logic push_i, // inject ATOPs in AR channel input logic [IdBits-1:0] inject_axi_id_i, @@ -711,7 +711,7 @@ module axi_demux_id_counters #( typedef logic [CounterWidth-1:0] cnt_t; // registers, each gets loaded when push_en[i] - mst_port_select_t [NumCounters-1:0] mst_select_q; + mgr_port_select_t [NumCounters-1:0] mgr_select_q; // counter signals logic [NumCounters-1:0] push_en, inject_en, pop_en, occupied, cnt_full; @@ -719,8 +719,8 @@ module axi_demux_id_counters #( //----------------------------------- // Lookup //----------------------------------- - assign lookup_mst_select_o = mst_select_q[lookup_axi_id_i]; - assign lookup_mst_select_occupied_o = occupied[lookup_axi_id_i]; + assign lookup_mgr_select_o = mgr_select_q[lookup_axi_id_i]; + assign lookup_mgr_select_occupied_o = occupied[lookup_axi_id_i]; //----------------------------------- // Push and Pop //----------------------------------- @@ -788,7 +788,7 @@ module axi_demux_id_counters #( assign cnt_full[i] = overflow | (&in_flight); // holds the selection signal for this id - `FFLARN(mst_select_q[i], push_mst_select_i, push_en[i], '0, clk_i, rst_ni) + `FFLARN(mgr_select_q[i], push_mgr_select_i, push_en[i], '0, clk_i, rst_ni) // pragma translate_off `ifndef VERILATOR @@ -813,7 +813,7 @@ module axi_demux_intf #( parameter int unsigned AXI_ADDR_WIDTH = 32'd0, parameter int unsigned AXI_DATA_WIDTH = 32'd0, parameter int unsigned AXI_USER_WIDTH = 32'd0, - parameter int unsigned NO_MST_PORTS = 32'd3, + parameter int unsigned NO_MGR_PORTS = 32'd3, parameter int unsigned MAX_TRANS = 32'd8, parameter int unsigned AXI_LOOK_BITS = 32'd3, parameter bit UNIQUE_IDS = 1'b0, @@ -823,16 +823,16 @@ module axi_demux_intf #( parameter bit SPILL_AR = 1'b1, parameter bit SPILL_R = 1'b0, // Dependent parameters, DO NOT OVERRIDE! - parameter int unsigned SELECT_WIDTH = (NO_MST_PORTS > 32'd1) ? $clog2(NO_MST_PORTS) : 32'd1, - parameter type select_t = logic [SELECT_WIDTH-1:0] // MST port select type + parameter int unsigned SELECT_WIDTH = (NO_MGR_PORTS > 32'd1) ? $clog2(NO_MGR_PORTS) : 32'd1, + parameter type select_t = logic [SELECT_WIDTH-1:0] // MGR port select type ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Testmode enable - input select_t slv_aw_select_i, // has to be stable, when aw_valid - input select_t slv_ar_select_i, // has to be stable, when ar_valid - AXI_BUS.Slave slv, // slave port - AXI_BUS.Master mst [NO_MST_PORTS-1:0] // master ports + input select_t sbr_aw_select_i, // has to be stable, when aw_valid + input select_t sbr_ar_select_i, // has to be stable, when ar_valid + AXI_BUS.Subordinate sbr, // subordinate port + AXI_BUS.Manager mgr [NO_MGR_PORTS-1:0] // manager ports ); typedef logic [AXI_ID_WIDTH-1:0] id_t; @@ -848,17 +848,17 @@ module axi_demux_intf #( `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req; - axi_rsp_t slv_rsp; - axi_req_t [NO_MST_PORTS-1:0] mst_req; - axi_rsp_t [NO_MST_PORTS-1:0] mst_rsp; + axi_req_t sbr_req; + axi_rsp_t sbr_rsp; + axi_req_t [NO_MGR_PORTS-1:0] mgr_req; + axi_rsp_t [NO_MGR_PORTS-1:0] mgr_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, slv_rsp) + `AXI_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, sbr_rsp) - for (genvar i = 0; i < NO_MST_PORTS; i++) begin : gen_assign_mst_ports - `AXI_ASSIGN_FROM_REQ(mst[i], mst_req[i]) - `AXI_ASSIGN_TO_RSP(mst_rsp[i], mst[i]) + for (genvar i = 0; i < NO_MGR_PORTS; i++) begin : gen_assign_mgr_ports + `AXI_ASSIGN_FROM_REQ(mgr[i], mgr_req[i]) + `AXI_ASSIGN_TO_RSP(mgr_rsp[i], mgr[i]) end axi_demux #( @@ -871,7 +871,7 @@ module axi_demux_intf #( .r_chan_t ( r_chan_t ), // R Channel Type .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ), - .NumMstPorts ( NO_MST_PORTS ), + .NumMgrPorts ( NO_MGR_PORTS ), .MaxTrans ( MAX_TRANS ), .LookBits ( AXI_LOOK_BITS ), .UniqueIds ( UNIQUE_IDS ), @@ -884,13 +884,13 @@ module axi_demux_intf #( .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Testmode enable - // slave port - .slv_req_i ( slv_req ), - .slv_aw_select_i ( slv_aw_select_i ), - .slv_ar_select_i ( slv_ar_select_i ), - .slv_rsp_o ( slv_rsp ), - // master port - .mst_reqs_o ( mst_req ), - .mst_rsps_i ( mst_rsp ) + // subordinate port + .sbr_req_i ( sbr_req ), + .sbr_aw_select_i ( sbr_aw_select_i ), + .sbr_ar_select_i ( sbr_ar_select_i ), + .sbr_rsp_o ( sbr_rsp ), + // manager port + .mgr_reqs_o ( mgr_req ), + .mgr_rsps_i ( mgr_rsp ) ); endmodule diff --git a/src/axi_dw_converter.sv b/src/axi_dw_converter.sv index 0a12ef38c..bf70ae9a4 100644 --- a/src/axi_dw_converter.sv +++ b/src/axi_dw_converter.sv @@ -17,94 +17,94 @@ module axi_dw_converter #( parameter int unsigned MaxReads = 1 , // Number of outstanding reads - parameter int unsigned SlvPortDataWidth = 8 , // Data width of the slv port - parameter int unsigned MstPortDataWidth = 8 , // Data width of the mst port + parameter int unsigned SbrPortDataWidth = 8 , // Data width of the sbr port + parameter int unsigned MgrPortDataWidth = 8 , // Data width of the mgr port parameter int unsigned AddrWidth = 1 , // Address width parameter int unsigned IdWidth = 1 , // ID width parameter type aw_chan_t = logic, // AW Channel Type - parameter type mst_w_chan_t = logic, // W Channel Type for the mst port - parameter type slv_w_chan_t = logic, // W Channel Type for the slv port + parameter type mgr_w_chan_t = logic, // W Channel Type for the mgr port + parameter type sbr_w_chan_t = logic, // W Channel Type for the sbr port parameter type b_chan_t = logic, // B Channel Type parameter type ar_chan_t = logic, // AR Channel Type - parameter type mst_r_chan_t = logic, // R Channel Type for the mst port - parameter type slv_r_chan_t = logic, // R Channel Type for the slv port - parameter type mst_port_axi_req_t = logic, // AXI Request Type for mst ports - parameter type mst_port_axi_rsp_t = logic, // AXI Response Type for mst ports - parameter type slv_port_axi_req_t = logic, // AXI Request Type for slv ports - parameter type slv_port_axi_rsp_t = logic // AXI Response Type for slv ports + parameter type mgr_r_chan_t = logic, // R Channel Type for the mgr port + parameter type sbr_r_chan_t = logic, // R Channel Type for the sbr port + parameter type mgr_port_axi_req_t = logic, // AXI Request Type for mgr ports + parameter type mgr_port_axi_rsp_t = logic, // AXI Response Type for mgr ports + parameter type sbr_port_axi_req_t = logic, // AXI Request Type for sbr ports + parameter type sbr_port_axi_rsp_t = logic // AXI Response Type for sbr ports ) ( input logic clk_i, input logic rst_ni, - // Slave interface - input slv_port_axi_req_t slv_req_i, - output slv_port_axi_rsp_t slv_rsp_o, - // Master interface - output mst_port_axi_req_t mst_req_o, - input mst_port_axi_rsp_t mst_rsp_i + // Subordinate interface + input sbr_port_axi_req_t sbr_req_i, + output sbr_port_axi_rsp_t sbr_rsp_o, + // Manager interface + output mgr_port_axi_req_t mgr_req_o, + input mgr_port_axi_rsp_t mgr_rsp_i ); - if (MstPortDataWidth == SlvPortDataWidth) begin: gen_no_dw_conversion - assign mst_req_o = slv_req_i ; - assign slv_rsp_o = mst_rsp_i; + if (MgrPortDataWidth == SbrPortDataWidth) begin: gen_no_dw_conversion + assign mgr_req_o = sbr_req_i ; + assign sbr_rsp_o = mgr_rsp_i; end : gen_no_dw_conversion - if (MstPortDataWidth > SlvPortDataWidth) begin: gen_dw_upsize + if (MgrPortDataWidth > SbrPortDataWidth) begin: gen_dw_upsize axi_dw_upsizer #( .MaxReads (MaxReads ), - .SlvPortDataWidth (SlvPortDataWidth), - .MstPortDataWidth (MstPortDataWidth), + .SbrPortDataWidth (SbrPortDataWidth), + .MgrPortDataWidth (MgrPortDataWidth), .AddrWidth (AddrWidth ), .IdWidth (IdWidth ), .aw_chan_t (aw_chan_t ), - .mst_w_chan_t (mst_w_chan_t ), - .slv_w_chan_t (slv_w_chan_t ), + .mgr_w_chan_t (mgr_w_chan_t ), + .sbr_w_chan_t (sbr_w_chan_t ), .b_chan_t (b_chan_t ), .ar_chan_t (ar_chan_t ), - .mst_r_chan_t (mst_r_chan_t ), - .slv_r_chan_t (slv_r_chan_t ), - .mst_port_axi_req_t (mst_port_axi_req_t ), - .mst_port_axi_rsp_t (mst_port_axi_rsp_t ), - .slv_port_axi_req_t (slv_port_axi_req_t ), - .slv_port_axi_rsp_t (slv_port_axi_rsp_t ) + .mgr_r_chan_t (mgr_r_chan_t ), + .sbr_r_chan_t (sbr_r_chan_t ), + .mgr_port_axi_req_t (mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t (mgr_port_axi_rsp_t ), + .sbr_port_axi_req_t (sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t (sbr_port_axi_rsp_t ) ) i_axi_dw_upsizer ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // Slave interface - .slv_req_i (slv_req_i), - .slv_rsp_o (slv_rsp_o), - // Master interface - .mst_req_o (mst_req_o), - .mst_rsp_i (mst_rsp_i) + // Subordinate interface + .sbr_req_i (sbr_req_i), + .sbr_rsp_o (sbr_rsp_o), + // Manager interface + .mgr_req_o (mgr_req_o), + .mgr_rsp_i (mgr_rsp_i) ); end : gen_dw_upsize - if (MstPortDataWidth < SlvPortDataWidth) begin: gen_dw_downsize + if (MgrPortDataWidth < SbrPortDataWidth) begin: gen_dw_downsize axi_dw_downsizer #( .MaxReads (MaxReads ), - .SlvPortDataWidth (SlvPortDataWidth), - .MstPortDataWidth (MstPortDataWidth), + .SbrPortDataWidth (SbrPortDataWidth), + .MgrPortDataWidth (MgrPortDataWidth), .AddrWidth (AddrWidth ), .IdWidth (IdWidth ), .aw_chan_t (aw_chan_t ), - .mst_w_chan_t (mst_w_chan_t ), - .slv_w_chan_t (slv_w_chan_t ), + .mgr_w_chan_t (mgr_w_chan_t ), + .sbr_w_chan_t (sbr_w_chan_t ), .b_chan_t (b_chan_t ), .ar_chan_t (ar_chan_t ), - .mst_r_chan_t (mst_r_chan_t ), - .slv_r_chan_t (slv_r_chan_t ), - .mst_port_axi_req_t (mst_port_axi_req_t ), - .mst_port_axi_rsp_t (mst_port_axi_rsp_t ), - .slv_port_axi_req_t (slv_port_axi_req_t ), - .slv_port_axi_rsp_t (slv_port_axi_rsp_t ) + .mgr_r_chan_t (mgr_r_chan_t ), + .sbr_r_chan_t (sbr_r_chan_t ), + .mgr_port_axi_req_t (mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t (mgr_port_axi_rsp_t ), + .sbr_port_axi_req_t (sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t (sbr_port_axi_rsp_t ) ) i_axi_dw_downsizer ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // Slave interface - .slv_req_i (slv_req_i), - .slv_rsp_o (slv_rsp_o), - // Master interface - .mst_req_o (mst_req_o), - .mst_rsp_i (mst_rsp_i) + // Subordinate interface + .sbr_req_i (sbr_req_i), + .sbr_rsp_o (sbr_rsp_o), + // Manager interface + .mgr_req_o (mgr_req_o), + .mgr_rsp_i (mgr_rsp_i) ); end : gen_dw_downsize @@ -118,73 +118,73 @@ endmodule : axi_dw_converter module axi_dw_converter_intf #( parameter int unsigned AXI_ID_WIDTH = 1, parameter int unsigned AXI_ADDR_WIDTH = 1, - parameter int unsigned AXI_SLV_PORT_DATA_WIDTH = 8, - parameter int unsigned AXI_MST_PORT_DATA_WIDTH = 8, + parameter int unsigned AXI_SBR_PORT_DATA_WIDTH = 8, + parameter int unsigned AXI_MGR_PORT_DATA_WIDTH = 8, parameter int unsigned AXI_USER_WIDTH = 0, parameter int unsigned AXI_MAX_READS = 8 ) ( input logic clk_i, input logic rst_ni, - AXI_BUS.Slave slv, - AXI_BUS.Master mst + AXI_BUS.Subordinate sbr, + AXI_BUS.Manager mgr ); typedef logic [AXI_ID_WIDTH-1:0] id_t ; typedef logic [AXI_ADDR_WIDTH-1:0] addr_t ; - typedef logic [AXI_MST_PORT_DATA_WIDTH-1:0] mst_data_t ; - typedef logic [AXI_MST_PORT_DATA_WIDTH/8-1:0] mst_strb_t; - typedef logic [AXI_SLV_PORT_DATA_WIDTH-1:0] slv_data_t ; - typedef logic [AXI_SLV_PORT_DATA_WIDTH/8-1:0] slv_strb_t; + typedef logic [AXI_MGR_PORT_DATA_WIDTH-1:0] mgr_data_t ; + typedef logic [AXI_MGR_PORT_DATA_WIDTH/8-1:0] mgr_strb_t; + typedef logic [AXI_SBR_PORT_DATA_WIDTH-1:0] sbr_data_t ; + typedef logic [AXI_SBR_PORT_DATA_WIDTH/8-1:0] sbr_strb_t; typedef logic [AXI_USER_WIDTH-1:0] user_t ; `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, mst_data_t, mst_strb_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, slv_data_t, slv_strb_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(mgr_w_chan_t, mgr_data_t, mgr_strb_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(sbr_w_chan_t, sbr_data_t, sbr_strb_t, user_t) `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, mst_data_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, slv_data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, aw_chan_t, mst_w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, b_chan_t, mst_r_chan_t) - `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, aw_chan_t, slv_w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_R_CHAN_T(mgr_r_chan_t, mgr_data_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(sbr_r_chan_t, sbr_data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(mgr_port_axi_req_t, aw_chan_t, mgr_w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RSP_T(mgr_port_axi_rsp_t, b_chan_t, mgr_r_chan_t) + `AXI_TYPEDEF_REQ_T(sbr_port_axi_req_t, aw_chan_t, sbr_w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RSP_T(sbr_port_axi_rsp_t, b_chan_t, sbr_r_chan_t) - slv_port_axi_req_t slv_req; - slv_port_axi_rsp_t slv_rsp; - mst_port_axi_req_t mst_req; - mst_port_axi_rsp_t mst_rsp; + sbr_port_axi_req_t sbr_req; + sbr_port_axi_rsp_t sbr_rsp; + mgr_port_axi_req_t mgr_req; + mgr_port_axi_rsp_t mgr_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, slv_rsp) + `AXI_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, sbr_rsp) - `AXI_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, mst) + `AXI_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_dw_converter #( .MaxReads ( AXI_MAX_READS ), - .SlvPortDataWidth ( AXI_SLV_PORT_DATA_WIDTH ), - .MstPortDataWidth ( AXI_MST_PORT_DATA_WIDTH ), + .SbrPortDataWidth ( AXI_SBR_PORT_DATA_WIDTH ), + .MgrPortDataWidth ( AXI_MGR_PORT_DATA_WIDTH ), .AddrWidth ( AXI_ADDR_WIDTH ), .IdWidth ( AXI_ID_WIDTH ), .aw_chan_t ( aw_chan_t ), - .mst_w_chan_t ( mst_w_chan_t ), - .slv_w_chan_t ( slv_w_chan_t ), + .mgr_w_chan_t ( mgr_w_chan_t ), + .sbr_w_chan_t ( sbr_w_chan_t ), .b_chan_t ( b_chan_t ), .ar_chan_t ( ar_chan_t ), - .mst_r_chan_t ( mst_r_chan_t ), - .slv_r_chan_t ( slv_r_chan_t ), - .mst_port_axi_req_t ( mst_port_axi_req_t ), - .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), - .slv_port_axi_req_t ( slv_port_axi_req_t ), - .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ) + .mgr_r_chan_t ( mgr_r_chan_t ), + .sbr_r_chan_t ( sbr_r_chan_t ), + .mgr_port_axi_req_t ( mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t ( mgr_port_axi_rsp_t ), + .sbr_port_axi_req_t ( sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t ( sbr_port_axi_rsp_t ) ) i_axi_dw_converter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - // slave port - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - // master port - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + // subordinate port + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + // manager port + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); endmodule : axi_dw_converter_intf diff --git a/src/axi_dw_downsizer.sv b/src/axi_dw_downsizer.sv index 07815fab2..d2df56014 100644 --- a/src/axi_dw_downsizer.sv +++ b/src/axi_dw_downsizer.sv @@ -13,7 +13,7 @@ // Description: // Data width downsize conversion. -// Connects a wide master to a narrower slave. +// Connects a wide manager to a narrower subordinate. // NOTE: The downsizer does not support WRAP bursts, and will answer with SLVERR // upon receiving a burst of such type. The downsizer does support FIXED @@ -21,30 +21,30 @@ // on multi-beat FIXED bursts. module axi_dw_downsizer #( parameter int unsigned MaxReads = 1 , // Number of outstanding reads - parameter int unsigned SlvPortDataWidth = 8 , // Data width of the slv port - parameter int unsigned MstPortDataWidth = 8 , // Data width of the mst port + parameter int unsigned SbrPortDataWidth = 8 , // Data width of the sbr port + parameter int unsigned MgrPortDataWidth = 8 , // Data width of the mgr port parameter int unsigned AddrWidth = 1 , // Address width parameter int unsigned IdWidth = 1 , // ID width parameter type aw_chan_t = logic, // AW Channel Type - parameter type mst_w_chan_t = logic, // W Channel Type for mst port - parameter type slv_w_chan_t = logic, // W Channel Type for slv port + parameter type mgr_w_chan_t = logic, // W Channel Type for mgr port + parameter type sbr_w_chan_t = logic, // W Channel Type for sbr port parameter type b_chan_t = logic, // B Channel Type parameter type ar_chan_t = logic, // AR Channel Type - parameter type mst_r_chan_t = logic, // R Channel Type for mst port - parameter type slv_r_chan_t = logic, // R Channel Type for slv port - parameter type mst_port_axi_req_t = logic, // AXI Request Type for mst ports - parameter type mst_port_axi_rsp_t = logic, // AXI Response Type for mst ports - parameter type slv_port_axi_req_t = logic, // AXI Request Type for slv ports - parameter type slv_port_axi_rsp_t = logic // AXI Response Type for slv ports + parameter type mgr_r_chan_t = logic, // R Channel Type for mgr port + parameter type sbr_r_chan_t = logic, // R Channel Type for sbr port + parameter type mgr_port_axi_req_t = logic, // AXI Request Type for mgr ports + parameter type mgr_port_axi_rsp_t = logic, // AXI Response Type for mgr ports + parameter type sbr_port_axi_req_t = logic, // AXI Request Type for sbr ports + parameter type sbr_port_axi_rsp_t = logic // AXI Response Type for sbr ports ) ( input logic clk_i, input logic rst_ni, - // Slave interface - input slv_port_axi_req_t slv_req_i, - output slv_port_axi_rsp_t slv_rsp_o, - // Master interface - output mst_port_axi_req_t mst_req_o, - input mst_port_axi_rsp_t mst_rsp_i + // Subordinate interface + input sbr_port_axi_req_t sbr_req_i, + output sbr_port_axi_rsp_t sbr_rsp_o, + // Manager interface + output mgr_port_axi_req_t mgr_req_o, + input mgr_port_axi_rsp_t mgr_rsp_i ); /***************** @@ -60,18 +60,18 @@ module axi_dw_downsizer #( typedef logic [TranIdWidth-1:0] tran_id_t; // Data width - localparam SlvPortStrbWidth = SlvPortDataWidth / 8; - localparam MstPortStrbWidth = MstPortDataWidth / 8; + localparam SbrPortStrbWidth = SbrPortDataWidth / 8; + localparam MgrPortStrbWidth = MgrPortDataWidth / 8; - localparam SlvPortMaxSize = $clog2(SlvPortStrbWidth); - localparam MstPortMaxSize = $clog2(MstPortStrbWidth); + localparam SbrPortMaxSize = $clog2(SbrPortStrbWidth); + localparam MgrPortMaxSize = $clog2(MgrPortStrbWidth); - localparam SlvPortByteMask = SlvPortStrbWidth - 1; - localparam MstPortByteMask = MstPortStrbWidth - 1; + localparam SbrPortByteMask = SbrPortStrbWidth - 1; + localparam MgrPortByteMask = MgrPortStrbWidth - 1; // Byte-grouped data words - typedef logic [MstPortStrbWidth-1:0][7:0] mst_data_t; - typedef logic [SlvPortStrbWidth-1:0][7:0] slv_data_t; + typedef logic [MgrPortStrbWidth-1:0][7:0] mgr_data_t; + typedef logic [SbrPortStrbWidth-1:0][7:0] sbr_data_t; // Address width typedef logic [AddrWidth-1:0] addr_t; @@ -80,11 +80,11 @@ module axi_dw_downsizer #( typedef logic [IdWidth-1:0] id_t; // Length of burst after upsizing - typedef logic [$clog2(SlvPortStrbWidth/MstPortStrbWidth) + 7:0] burst_len_t; + typedef logic [$clog2(SbrPortStrbWidth/MgrPortStrbWidth) + 7:0] burst_len_t; // Internal AXI bus - mst_port_axi_req_t mst_req; - mst_port_axi_rsp_t mst_rsp; + mgr_port_axi_req_t mgr_req; + mgr_port_axi_rsp_t mgr_rsp; /************** * ARBITERS * @@ -92,45 +92,45 @@ module axi_dw_downsizer #( // R - slv_r_chan_t [MaxReads-1:0] slv_r_tran; - logic [MaxReads-1:0] slv_r_valid_tran; - logic [MaxReads-1:0] slv_r_ready_tran; + sbr_r_chan_t [MaxReads-1:0] sbr_r_tran; + logic [MaxReads-1:0] sbr_r_valid_tran; + logic [MaxReads-1:0] sbr_r_ready_tran; rr_arb_tree #( .NumIn (MaxReads ), - .DataType (slv_r_chan_t), + .DataType (sbr_r_chan_t), .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) - ) i_slv_r_arb ( + ) i_sbr_r_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), .flush_i(1'b0 ), .rr_i ('0 ), - .req_i (slv_r_valid_tran ), - .gnt_o (slv_r_ready_tran ), - .data_i (slv_r_tran ), - .gnt_i (slv_req_i.r_ready), - .req_o (slv_rsp_o.r_valid), - .data_o (slv_rsp_o.r ), + .req_i (sbr_r_valid_tran ), + .gnt_o (sbr_r_ready_tran ), + .data_i (sbr_r_tran ), + .gnt_i (sbr_req_i.r_ready), + .req_o (sbr_rsp_o.r_valid), + .data_o (sbr_rsp_o.r ), .idx_o (/* Unused */ ) ); - logic [MaxReads-1:0] mst_r_ready_tran; - assign mst_req.r_ready = |mst_r_ready_tran; + logic [MaxReads-1:0] mgr_r_ready_tran; + assign mgr_req.r_ready = |mgr_r_ready_tran; // AR - id_t arb_slv_ar_id; - logic arb_slv_ar_req; - logic arb_slv_ar_gnt; - logic [MaxReads-1:0] arb_slv_ar_gnt_tran; - // Multiplex AR slave between AR and AW for the injection of atomic operations with an R response. + id_t arb_sbr_ar_id; + logic arb_sbr_ar_req; + logic arb_sbr_ar_gnt; + logic [MaxReads-1:0] arb_sbr_ar_gnt_tran; + // Multiplex AR subordinate between AR and AW for the injection of atomic operations with an R response. logic inject_aw_into_ar; logic inject_aw_into_ar_req; logic inject_aw_into_ar_gnt; - assign arb_slv_ar_gnt = |arb_slv_ar_gnt_tran; + assign arb_sbr_ar_gnt = |arb_sbr_ar_gnt_tran; rr_arb_tree #( .NumIn (2 ), @@ -138,25 +138,25 @@ module axi_dw_downsizer #( .ExtPrio (1'b0 ), .AxiVldRdy (1'b1 ), .LockIn (1'b0 ) - ) i_slv_ar_arb ( + ) i_sbr_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), .flush_i (1'b0 ), .rr_i ('0 ), - .req_i ({inject_aw_into_ar_req, slv_req_i.ar_valid}), - .gnt_o ({inject_aw_into_ar_gnt, slv_rsp_o.ar_ready}), - .data_i ({slv_req_i.aw.id, slv_req_i.ar.id} ), - .req_o (arb_slv_ar_req ), - .gnt_i (arb_slv_ar_gnt ), - .data_o (arb_slv_ar_id ), + .req_i ({inject_aw_into_ar_req, sbr_req_i.ar_valid}), + .gnt_o ({inject_aw_into_ar_gnt, sbr_rsp_o.ar_ready}), + .data_i ({sbr_req_i.aw.id, sbr_req_i.ar.id} ), + .req_o (arb_sbr_ar_req ), + .gnt_i (arb_sbr_ar_gnt ), + .data_o (arb_sbr_ar_id ), .idx_o (inject_aw_into_ar ) ); - ar_chan_t [MaxReads-1:0] mst_ar_tran; - id_t [MaxReads-1:0] mst_ar_id; - logic [MaxReads-1:0] mst_ar_valid_tran; - logic [MaxReads-1:0] mst_ar_ready_tran; - tran_id_t mst_req_idx; + ar_chan_t [MaxReads-1:0] mgr_ar_tran; + id_t [MaxReads-1:0] mgr_ar_id; + logic [MaxReads-1:0] mgr_ar_valid_tran; + logic [MaxReads-1:0] mgr_ar_ready_tran; + tran_id_t mgr_req_idx; rr_arb_tree #( .NumIn (MaxReads ), @@ -164,73 +164,73 @@ module axi_dw_downsizer #( .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) - ) i_mst_ar_arb ( + ) i_mgr_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), .flush_i(1'b0 ), .rr_i ('0 ), - .req_i (mst_ar_valid_tran), - .gnt_o (mst_ar_ready_tran), - .data_i (mst_ar_tran ), - .gnt_i (mst_rsp.ar_ready ), - .req_o (mst_req.ar_valid ), - .data_o (mst_req.ar ), - .idx_o (mst_req_idx ) + .req_i (mgr_ar_valid_tran), + .gnt_o (mgr_ar_ready_tran), + .data_i (mgr_ar_tran ), + .gnt_i (mgr_rsp.ar_ready ), + .req_o (mgr_req.ar_valid ), + .data_o (mgr_req.ar ), + .idx_o (mgr_req_idx ) ); /***************** - * ERROR SLAVE * + * ERROR SUBORDINATE * *****************/ - mst_port_axi_req_t axi_err_req; - mst_port_axi_rsp_t axi_err_rsp; + mgr_port_axi_req_t axi_err_req; + mgr_port_axi_rsp_t axi_err_rsp; - axi_err_slv #( + axi_err_sbr #( .IdWidth (IdWidth ), .Resp (axi_pkg::RESP_SLVERR), - .axi_req_t (mst_port_axi_req_t ), - .axi_rsp_t (mst_port_axi_rsp_t ) - ) i_axi_err_slv ( + .axi_req_t (mgr_port_axi_req_t ), + .axi_rsp_t (mgr_port_axi_rsp_t ) + ) i_axi_err_sbr ( .clk_i (clk_i ), .rst_ni (rst_ni ), .test_i (1'b0 ), - .slv_req_i(axi_err_req), - .slv_rsp_o(axi_err_rsp) + .sbr_req_i(axi_err_req), + .sbr_rsp_o(axi_err_rsp) ); /*********** * DEMUX * ***********/ - // Requests can be sent either to the error slave, - // or to the DWC's master port. + // Requests can be sent either to the error subordinate, + // or to the DWC's manager port. - logic [MaxReads-1:0] mst_req_ar_err; - logic mst_req_aw_err; + logic [MaxReads-1:0] mgr_req_ar_err; + logic mgr_req_aw_err; axi_demux #( .IdWidth (IdWidth ), .LookBits (IdWidth ), .aw_chan_t (aw_chan_t ), - .w_chan_t (mst_w_chan_t ), + .w_chan_t (mgr_w_chan_t ), .b_chan_t (b_chan_t ), .ar_chan_t (ar_chan_t ), - .r_chan_t (mst_r_chan_t ), - .axi_req_t (mst_port_axi_req_t), - .axi_rsp_t (mst_port_axi_rsp_t), - .NumMstPorts (2 ), + .r_chan_t (mgr_r_chan_t ), + .axi_req_t (mgr_port_axi_req_t), + .axi_rsp_t (mgr_port_axi_rsp_t), + .NumMgrPorts (2 ), .MaxTrans (MaxReads ), .SpillAw (1'b1 ) // Required to break dependency between AW and W channels ) i_axi_demux ( .clk_i (clk_i ), .rst_ni (rst_ni ), .test_i (1'b0 ), - .mst_reqs_o ({axi_err_req, mst_req_o} ), - .mst_rsps_i ({axi_err_rsp, mst_rsp_i} ), - .slv_ar_select_i(mst_req_ar_err[mst_req_idx]), - .slv_aw_select_i(mst_req_aw_err ), - .slv_req_i (mst_req ), - .slv_rsp_o (mst_rsp ) + .mgr_reqs_o ({axi_err_req, mgr_req_o} ), + .mgr_rsps_i ({axi_err_rsp, mgr_rsp_i} ), + .sbr_ar_select_i(mgr_req_ar_err[mgr_req_idx]), + .sbr_aw_select_i(mgr_req_aw_err ), + .sbr_req_i (mgr_req ), + .sbr_rsp_o (mgr_rsp ) ); /********** @@ -249,7 +249,7 @@ module axi_dw_downsizer #( ar_chan_t ar ; logic ar_valid ; logic ar_throw_error ; - slv_r_chan_t r ; + sbr_r_chan_t r ; logic r_valid ; burst_len_t burst_len ; axi_pkg::size_t orig_ar_size; @@ -288,7 +288,7 @@ module axi_dw_downsizer #( logic [MaxReads-1:0] id_clash_downsizer; tran_id_t idx_id_clash_downsizer; for (genvar t = 0; t < MaxReads; t++) begin: gen_id_clash - assign id_clash_downsizer[t] = arb_slv_ar_id == mst_ar_id[t] && !idle_read_downsizer[t]; + assign id_clash_downsizer[t] = arb_sbr_ar_id == mgr_ar_id[t] && !idle_read_downsizer[t]; end onehot_to_bin #( @@ -316,11 +316,11 @@ module axi_dw_downsizer #( ) i_read_id_queue ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .inp_id_i (arb_slv_ar_id ), + .inp_id_i (arb_sbr_ar_id ), .inp_data_i (idx_ar_downsizer), .inp_req_i (|idqueue_push ), .inp_gnt_o (/* Unused */ ), - .oup_id_i (mst_rsp.r.id ), + .oup_id_i (mgr_rsp.r.id ), .oup_pop_i (|idqueue_pop ), .oup_req_i (1'b1 ), .oup_data_o (idqueue_id ), @@ -341,7 +341,7 @@ module axi_dw_downsizer #( assign idle_read_downsizer[t] = (r_state_q == R_IDLE) || (r_state_q == R_INJECT_AW); // Byte-grouped data signal for the serialization step - slv_data_t r_data; + sbr_data_t r_data; always_comb begin // Maintain state @@ -349,26 +349,26 @@ module axi_dw_downsizer #( r_req_d = r_req_q ; // AR Channel - mst_ar_tran[t] = r_req_q.ar ; - mst_ar_id[t] = r_req_q.ar.id ; - mst_ar_valid_tran[t] = r_req_q.ar_valid; + mgr_ar_tran[t] = r_req_q.ar ; + mgr_ar_id[t] = r_req_q.ar.id ; + mgr_ar_valid_tran[t] = r_req_q.ar_valid; // Throw an error - mst_req_ar_err[t] = r_req_q.ar_throw_error; + mgr_req_ar_err[t] = r_req_q.ar_throw_error; // R Channel - slv_r_tran[t] = r_req_q.r ; - slv_r_valid_tran[t] = r_req_q.r_valid; + sbr_r_tran[t] = r_req_q.r ; + sbr_r_valid_tran[t] = r_req_q.r_valid; idqueue_push[t] = '0; idqueue_pop[t] = '0; - arb_slv_ar_gnt_tran[t] = 1'b0; + arb_sbr_ar_gnt_tran[t] = 1'b0; - mst_r_ready_tran[t] = 1'b0; + mgr_r_ready_tran[t] = 1'b0; // Got a grant on the AR channel - if (mst_ar_valid_tran[t] && mst_ar_ready_tran[t]) begin + if (mgr_ar_valid_tran[t] && mgr_ar_ready_tran[t]) begin r_req_d.ar_valid = 1'b0; r_req_d.ar_throw_error = 1'b0; end @@ -383,8 +383,8 @@ module axi_dw_downsizer #( r_req_d.r = '0; // New read request - if (arb_slv_ar_req && (idx_ar_downsizer == t)) begin - arb_slv_ar_gnt_tran[t] = 1'b1; + if (arb_sbr_ar_req && (idx_ar_downsizer == t)) begin + arb_sbr_ar_gnt_tran[t] = 1'b1; // Push to ID queue idqueue_push[t] = 1'b1; @@ -397,24 +397,24 @@ module axi_dw_downsizer #( r_state_d = R_PASSTHROUGH; // Save beat - r_req_d.ar = slv_req_i.ar ; + r_req_d.ar = sbr_req_i.ar ; r_req_d.ar_valid = 1'b1 ; - r_req_d.burst_len = slv_req_i.ar.len ; - r_req_d.orig_ar_size = slv_req_i.ar.size; + r_req_d.burst_len = sbr_req_i.ar.len ; + r_req_d.orig_ar_size = sbr_req_i.ar.size; r_req_d.injected_aw = 1'b0 ; case (r_req_d.ar.burst) axi_pkg::BURST_INCR : begin // Evaluate downsize ratio automatic addr_t size_mask = (1 << r_req_d.ar.size) - 1 ; - automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + MstPortStrbWidth - 1) / MstPortStrbWidth; + automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + MgrPortStrbWidth - 1) / MgrPortStrbWidth; // Evaluate output burst length - automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / MstPortStrbWidth; + automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MgrPortByteMask) / MgrPortStrbWidth; r_req_d.burst_len = (r_req_d.ar.len + 1) * conv_ratio - align_adj - 1 ; if (conv_ratio != 1) begin - r_req_d.ar.size = MstPortMaxSize; + r_req_d.ar.size = MgrPortMaxSize; if (r_req_d.burst_len <= 255) begin r_state_d = R_INCR_DOWNSIZE ; @@ -431,16 +431,16 @@ module axi_dw_downsizer #( if (r_req_d.ar.len == '0) begin // Evaluate downsize ratio automatic addr_t size_mask = (1 << r_req_d.ar.size) - 1 ; - automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + MstPortStrbWidth - 1) / MstPortStrbWidth; + automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + MgrPortStrbWidth - 1) / MgrPortStrbWidth; // Evaluate output burst length - automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / MstPortStrbWidth; + automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MgrPortByteMask) / MgrPortStrbWidth; r_req_d.burst_len = (conv_ratio >= align_adj + 1) ? (conv_ratio - align_adj - 1) : 0; if (conv_ratio != 1) begin r_state_d = R_INCR_DOWNSIZE ; r_req_d.ar.len = r_req_d.burst_len ; - r_req_d.ar.size = MstPortMaxSize ; + r_req_d.ar.size = MgrPortMaxSize ; r_req_d.ar.burst = axi_pkg::BURST_INCR; end end else begin @@ -484,14 +484,14 @@ module axi_dw_downsizer #( axi_pkg::BURST_INCR : begin // Evaluate downsize ratio automatic addr_t size_mask = (1 << r_req_d.ar.size) - 1 ; - automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + MstPortStrbWidth - 1) / MstPortStrbWidth; + automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + MgrPortStrbWidth - 1) / MgrPortStrbWidth; // Evaluate output burst length - automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / MstPortStrbWidth; + automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MgrPortByteMask) / MgrPortStrbWidth; r_req_d.burst_len = (r_req_d.ar.len + 1) * conv_ratio - align_adj - 1 ; if (conv_ratio != 1) begin - r_req_d.ar.size = MstPortMaxSize; + r_req_d.ar.size = MgrPortMaxSize; if (r_req_d.burst_len <= 255) begin r_state_d = R_INCR_DOWNSIZE ; @@ -508,16 +508,16 @@ module axi_dw_downsizer #( if (r_req_d.ar.len == '0) begin // Evaluate downsize ratio automatic addr_t size_mask = (1 << r_req_d.ar.size) - 1 ; - automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + MstPortStrbWidth - 1) / MstPortStrbWidth; + automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + MgrPortStrbWidth - 1) / MgrPortStrbWidth; // Evaluate output burst length - automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / MstPortStrbWidth; + automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MgrPortByteMask) / MgrPortStrbWidth; r_req_d.burst_len = (conv_ratio >= align_adj + 1) ? (conv_ratio - align_adj - 1) : 0; if (conv_ratio != 1) begin r_state_d = R_INCR_DOWNSIZE ; r_req_d.ar.len = r_req_d.burst_len ; - r_req_d.ar.size = MstPortMaxSize ; + r_req_d.ar.size = MgrPortMaxSize ; r_req_d.ar.burst = axi_pkg::BURST_INCR; end end else begin @@ -536,7 +536,7 @@ module axi_dw_downsizer #( R_PASSTHROUGH, R_INCR_DOWNSIZE, R_SPLIT_INCR_DOWNSIZE: begin // Got a grant on the R channel - if (slv_r_valid_tran[t] && slv_r_ready_tran[t]) begin + if (sbr_r_valid_tran[t] && sbr_r_ready_tran[t]) begin r_req_d.r = '0 ; r_req_d.r_valid = 1'b0; r_data = '0 ; @@ -547,30 +547,30 @@ module axi_dw_downsizer #( // Our turn if ((idqueue_id == t) && idqueue_valid) // Ready to accept more data - if (!slv_r_valid_tran[t] || (slv_r_valid_tran[t] && slv_r_ready_tran[t])) begin - mst_r_ready_tran[t] = 1'b1; + if (!sbr_r_valid_tran[t] || (sbr_r_valid_tran[t] && sbr_r_ready_tran[t])) begin + mgr_r_ready_tran[t] = 1'b1; - if (mst_rsp.r_valid) begin - automatic addr_t mst_port_offset = MstPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(MstPortStrbWidth)-1:0]; - automatic addr_t slv_port_offset = SlvPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(SlvPortStrbWidth)-1:0]; + if (mgr_rsp.r_valid) begin + automatic addr_t mgr_port_offset = MgrPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(MgrPortStrbWidth)-1:0]; + automatic addr_t sbr_port_offset = SbrPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(SbrPortStrbWidth)-1:0]; // Serialization - for (int b = 0; b < SlvPortStrbWidth; b++) - if ((b >= slv_port_offset) && - (b - slv_port_offset < (1 << r_req_q.orig_ar_size)) && - (b + mst_port_offset - slv_port_offset < MstPortStrbWidth)) begin - r_data[b] = mst_rsp.r.data[8*(b + mst_port_offset - slv_port_offset) +: 8]; + for (int b = 0; b < SbrPortStrbWidth; b++) + if ((b >= sbr_port_offset) && + (b - sbr_port_offset < (1 << r_req_q.orig_ar_size)) && + (b + mgr_port_offset - sbr_port_offset < MgrPortStrbWidth)) begin + r_data[b] = mgr_rsp.r.data[8*(b + mgr_port_offset - sbr_port_offset) +: 8]; end r_req_d.burst_len = r_req_q.burst_len - 1 ; r_req_d.ar.len = r_req_q.ar.len - 1 ; r_req_d.r.data = r_data ; r_req_d.r.last = (r_req_q.burst_len == 0); - r_req_d.r.id = mst_rsp.r.id ; - r_req_d.r.user = mst_rsp.r.user ; + r_req_d.r.id = mgr_rsp.r.id ; + r_req_d.r.user = mgr_rsp.r.user ; // Merge response of this beat with prior one according to precedence rules. - r_req_d.r.resp = axi_pkg::resp_precedence(r_req_q.r.resp, mst_rsp.r.resp); + r_req_d.r.resp = axi_pkg::resp_precedence(r_req_q.r.resp, mgr_rsp.r.resp); case (r_req_d.ar.burst) axi_pkg::BURST_INCR: begin @@ -605,7 +605,7 @@ module axi_dw_downsizer #( end end - if (slv_r_valid_tran[t] && slv_r_ready_tran[t]) + if (sbr_r_valid_tran[t] && sbr_r_ready_tran[t]) if (r_req_q.burst_len == '1) r_state_d = R_IDLE; end @@ -636,7 +636,7 @@ module axi_dw_downsizer #( w_state_e w_state_d, w_state_q; // This FIFO holds the number of bursts generated by each write transactions handled by this downsizer. - // This is used to forward only the correct B beats to the slave. + // This is used to forward only the correct B beats to the subordinate. logic forward_b_beat_i; logic forward_b_beat_o; logic forward_b_beat_push; @@ -662,7 +662,7 @@ module axi_dw_downsizer #( ); // Byte-grouped data signal for the lane steering step - mst_data_t w_data; + mgr_data_t w_data; always_comb begin inject_aw_into_ar_req = 1'b0; @@ -677,47 +677,47 @@ module axi_dw_downsizer #( w_req_d = w_req_q ; // AW Channel - mst_req.aw = w_req_q.aw ; - mst_req.aw_valid = w_req_q.aw_valid; - slv_rsp_o.aw_ready = '0 ; + mgr_req.aw = w_req_q.aw ; + mgr_req.aw_valid = w_req_q.aw_valid; + sbr_rsp_o.aw_ready = '0 ; // Throw an error. - mst_req_aw_err = w_req_q.aw_throw_error; + mgr_req_aw_err = w_req_q.aw_throw_error; // W Channel - mst_req.w = '0; - mst_req.w_valid = '0; - slv_rsp_o.w_ready = '0; + mgr_req.w = '0; + mgr_req.w_valid = '0; + sbr_rsp_o.w_ready = '0; // Initialize w_data w_data = '0; // B Channel (No latency) - if (mst_rsp.b_valid) begin + if (mgr_rsp.b_valid) begin // Merge response of this burst with prior one according to precedence rules. - w_req_d.burst_resp = axi_pkg::resp_precedence(w_req_q.burst_resp, mst_rsp.b.resp); + w_req_d.burst_resp = axi_pkg::resp_precedence(w_req_q.burst_resp, mgr_resp.b.resp); end - slv_rsp_o.b = mst_rsp.b ; - slv_rsp_o.b.resp = w_req_d.burst_resp; + sbr_rsp_o.b = mgr_rsp.b ; + sbr_rsp_o.b.resp = w_req_d.burst_resp; - // Each write transaction might trigger several B beats on the master (narrow) side. + // Each write transaction might trigger several B beats on the manager (narrow) side. // Only forward the last B beat of each transaction. if (forward_b_beat_o) begin - slv_rsp_o.b_valid = mst_rsp.b_valid ; - mst_req.b_ready = slv_req_i.b_ready; + sbr_rsp_o.b_valid = mgr_rsp.b_valid ; + mgr_req.b_ready = sbr_req_i.b_ready; // Got an ack on the B channel. Pop transaction. - if (mst_req.b_ready && mst_rsp.b_valid) + if (mgr_req.b_ready && mgr_rsp.b_valid) forward_b_beat_pop = 1'b1; end else begin // Otherwise, just acknowlegde the B beats - slv_rsp_o.b_valid = 1'b0 ; - mst_req.b_ready = 1'b1 ; - forward_b_beat_pop = mst_rsp.b_valid; + sbr_rsp_o.b_valid = 1'b0 ; + mgr_req.b_ready = 1'b1 ; + forward_b_beat_pop = mgr_rsp.b_valid; end // Got a grant on the AW channel - if (mst_req.aw_valid & mst_rsp.aw_ready) begin + if (mgr_req.aw_valid & mgr_rsp.aw_ready) begin w_req_d.aw_valid = 1'b0; w_req_d.aw_throw_error = 1'b0; end @@ -726,28 +726,28 @@ module axi_dw_downsizer #( W_PASSTHROUGH, W_INCR_DOWNSIZE, W_SPLIT_INCR_DOWNSIZE: begin // Request was accepted if (!w_req_q.aw_valid) - if (slv_req_i.w_valid) begin - automatic addr_t mst_port_offset = MstPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(MstPortStrbWidth)-1:0]; - automatic addr_t slv_port_offset = SlvPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(SlvPortStrbWidth)-1:0]; + if (sbr_req_i.w_valid) begin + automatic addr_t mgr_port_offset = MgrPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(MgrPortStrbWidth)-1:0]; + automatic addr_t sbr_port_offset = SbrPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(SbrPortStrbWidth)-1:0]; // Valid output - mst_req.w_valid = 1'b1 ; - mst_req.w.last = w_req_q.aw.len == 0; - mst_req.w.user = slv_req_i.w.user ; + mgr_req.w_valid = 1'b1 ; + mgr_req.w.last = w_req_q.aw.len == 0; + mgr_req.w.user = sbr_req_i.w.user ; // Lane steering - for (int b = 0; b < SlvPortStrbWidth; b++) - if ((b >= slv_port_offset) && - (b - slv_port_offset < (1 << w_req_q.orig_aw_size)) && - (b + mst_port_offset - slv_port_offset < MstPortStrbWidth)) begin - w_data[b + mst_port_offset - slv_port_offset] = slv_req_i.w.data[8*b +: 8]; - mst_req.w.strb[b + mst_port_offset - slv_port_offset] = slv_req_i.w.strb[b] ; + for (int b = 0; b < SbrPortStrbWidth; b++) + if ((b >= sbr_port_offset) && + (b - sbr_port_offset < (1 << w_req_q.orig_aw_size)) && + (b + mgr_port_offset - sbr_port_offset < MgrPortStrbWidth)) begin + w_data[b + mgr_port_offset - sbr_port_offset] = sbr_req_i.w.data[8*b +: 8]; + mgr_req.w.strb[b + mgr_port_offset - sbr_port_offset] = sbr_req_i.w.strb[b] ; end - mst_req.w.data = w_data; + mgr_req.w.data = w_data; end // Acknowledgment - if (mst_rsp.w_ready && mst_req.w_valid) begin + if (mgr_rsp.w_ready && mgr_req.w_valid) begin w_req_d.burst_len = w_req_q.burst_len - 1; w_req_d.aw.len = w_req_q.aw.len - 1 ; @@ -762,11 +762,11 @@ module axi_dw_downsizer #( case (w_state_q) W_PASSTHROUGH: - slv_rsp_o.w_ready = 1'b1; + sbr_rsp_o.w_ready = 1'b1; W_INCR_DOWNSIZE, W_SPLIT_INCR_DOWNSIZE: if (w_req_q.burst_len == 0 || (aligned_addr(w_req_d.aw.addr, w_req_q.orig_aw_size) != aligned_addr(w_req_q.aw.addr, w_req_q.orig_aw_size))) - slv_rsp_o.w_ready = 1'b1; + sbr_rsp_o.w_ready = 1'b1; endcase // Trigger another burst request, if needed @@ -800,38 +800,38 @@ module axi_dw_downsizer #( w_req_d.burst_resp = axi_pkg::RESP_OKAY; if (!forward_b_beat_full) begin - if (slv_req_i.aw_valid && slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // ATOP with an R response + if (sbr_req_i.aw_valid && sbr_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // ATOP with an R response inject_aw_into_ar_req = 1'b1 ; - slv_rsp_o.aw_ready = inject_aw_into_ar_gnt; + sbr_rsp_o.aw_ready = inject_aw_into_ar_gnt; end else begin // Regular AW - slv_rsp_o.aw_ready = 1'b1; + sbr_rsp_o.aw_ready = 1'b1; end // New write request - if (slv_req_i.aw_valid && slv_rsp_o.aw_ready) begin + if (sbr_req_i.aw_valid && sbr_rsp_o.aw_ready) begin // Default state w_state_d = W_PASSTHROUGH; // Save beat - w_req_d.aw = slv_req_i.aw ; + w_req_d.aw = sbr_req_i.aw ; w_req_d.aw_valid = 1'b1 ; - w_req_d.burst_len = slv_req_i.aw.len ; - w_req_d.orig_aw_len = slv_req_i.aw.len ; - w_req_d.orig_aw_size = slv_req_i.aw.size ; - w_req_d.orig_aw_burst = slv_req_i.aw.burst; + w_req_d.burst_len = sbr_req_i.aw.len ; + w_req_d.orig_aw_len = sbr_req_i.aw.len ; + w_req_d.orig_aw_size = sbr_req_i.aw.size ; + w_req_d.orig_aw_burst = sbr_req_i.aw.burst; - case (slv_req_i.aw.burst) + case (sbr_req_i.aw.burst) axi_pkg::BURST_INCR: begin // Evaluate downsize ratio - automatic addr_t size_mask = (1 << slv_req_i.aw.size) - 1 ; - automatic addr_t conv_ratio = ((1 << slv_req_i.aw.size) + MstPortStrbWidth - 1) / MstPortStrbWidth; + automatic addr_t size_mask = (1 << sbr_req_i.aw.size) - 1 ; + automatic addr_t conv_ratio = ((1 << sbr_req_i.aw.size) + MgrPortStrbWidth - 1) / MgrPortStrbWidth; // Evaluate output burst length - automatic addr_t align_adj = (slv_req_i.aw.addr & size_mask & ~MstPortByteMask) / MstPortStrbWidth; - w_req_d.burst_len = (slv_req_i.aw.len + 1) * conv_ratio - align_adj - 1 ; + automatic addr_t align_adj = (sbr_req_i.aw.addr & size_mask & ~MgrPortByteMask) / MgrPortStrbWidth; + w_req_d.burst_len = (sbr_req_i.aw.len + 1) * conv_ratio - align_adj - 1 ; if (conv_ratio != 1) begin - w_req_d.aw.size = MstPortMaxSize; + w_req_d.aw.size = MgrPortMaxSize; if (w_req_d.burst_len <= 255) begin w_state_d = W_INCR_DOWNSIZE ; @@ -845,19 +845,19 @@ module axi_dw_downsizer #( axi_pkg::BURST_FIXED: begin // Single transaction - if (slv_req_i.aw.len == '0) begin + if (sbr_req_i.aw.len == '0) begin // Evaluate downsize ratio - automatic addr_t size_mask = (1 << slv_req_i.aw.size) - 1 ; - automatic addr_t conv_ratio = ((1 << slv_req_i.aw.size) + MstPortStrbWidth - 1) / MstPortStrbWidth; + automatic addr_t size_mask = (1 << sbr_req_i.aw.size) - 1 ; + automatic addr_t conv_ratio = ((1 << sbr_req_i.aw.size) + MgrPortStrbWidth - 1) / MgrPortStrbWidth; // Evaluate output burst length - automatic addr_t align_adj = (slv_req_i.aw.addr & size_mask & ~MstPortByteMask) / MstPortStrbWidth; + automatic addr_t align_adj = (sbr_req_i.aw.addr & size_mask & ~MgrPortByteMask) / MgrPortStrbWidth; w_req_d.burst_len = (conv_ratio >= align_adj + 1) ? (conv_ratio - align_adj - 1) : 0; if (conv_ratio != 1) begin w_state_d = W_INCR_DOWNSIZE ; w_req_d.aw.len = w_req_d.burst_len ; - w_req_d.aw.size = MstPortMaxSize ; + w_req_d.aw.size = MgrPortMaxSize ; w_req_d.aw.burst = axi_pkg::BURST_INCR; end end else begin diff --git a/src/axi_dw_upsizer.sv b/src/axi_dw_upsizer.sv index 3d2743825..8ebf7fa49 100644 --- a/src/axi_dw_upsizer.sv +++ b/src/axi_dw_upsizer.sv @@ -13,37 +13,37 @@ // Description: // Data width upsize conversion. -// Connects a narrow master to a wider slave. +// Connects a narrow manager to a wider subordinate. // NOTE: The upsizer does not support WRAP bursts, and will answer with SLVERR // upon receiving a burst of such type. module axi_dw_upsizer #( parameter int unsigned MaxReads = 1 , // Number of outstanding reads - parameter int unsigned SlvPortDataWidth = 8 , // Data width of the slv port - parameter int unsigned MstPortDataWidth = 8 , // Data width of the mst port + parameter int unsigned SbrPortDataWidth = 8 , // Data width of the sbr port + parameter int unsigned MgrPortDataWidth = 8 , // Data width of the mgr port parameter int unsigned AddrWidth = 1 , // Address width parameter int unsigned IdWidth = 1 , // ID width parameter type aw_chan_t = logic, // AW Channel Type - parameter type mst_w_chan_t = logic, // W Channel Type for mst port - parameter type slv_w_chan_t = logic, // W Channel Type for slv port + parameter type mgr_w_chan_t = logic, // W Channel Type for mgr port + parameter type sbr_w_chan_t = logic, // W Channel Type for sbr port parameter type b_chan_t = logic, // B Channel Type parameter type ar_chan_t = logic, // AR Channel Type - parameter type mst_r_chan_t = logic, // R Channel Type for mst port - parameter type slv_r_chan_t = logic, // R Channel Type for slv port - parameter type mst_port_axi_req_t = logic, // AXI Request Type for mst ports - parameter type mst_port_axi_rsp_t = logic, // AXI Response Type for mst ports - parameter type slv_port_axi_req_t = logic, // AXI Request Type for slv ports - parameter type slv_port_axi_rsp_t = logic // AXI Response Type for slv ports + parameter type mgr_r_chan_t = logic, // R Channel Type for mgr port + parameter type sbr_r_chan_t = logic, // R Channel Type for sbr port + parameter type mgr_port_axi_req_t = logic, // AXI Request Type for mgr ports + parameter type mgr_port_axi_rsp_t = logic, // AXI Response Type for mgr ports + parameter type sbr_port_axi_req_t = logic, // AXI Request Type for sbr ports + parameter type sbr_port_axi_rsp_t = logic // AXI Response Type for sbr ports ) ( input logic clk_i, input logic rst_ni, - // Slave interface - input slv_port_axi_req_t slv_req_i, - output slv_port_axi_rsp_t slv_rsp_o, - // Master interface - output mst_port_axi_req_t mst_req_o, - input mst_port_axi_rsp_t mst_rsp_i + // Subordinate interface + input sbr_port_axi_req_t sbr_req_i, + output sbr_port_axi_rsp_t sbr_rsp_o, + // Manager interface + output mgr_port_axi_req_t mgr_req_o, + input mgr_port_axi_rsp_t mgr_rsp_i ); /***************** @@ -60,15 +60,15 @@ module axi_dw_upsizer #( typedef logic [TranIdWidth-1:0] tran_id_t; // Data width - localparam SlvPortStrbWidth = SlvPortDataWidth / 8; - localparam MstPortStrbWidth = MstPortDataWidth / 8; + localparam SbrPortStrbWidth = SbrPortDataWidth / 8; + localparam MgrPortStrbWidth = MgrPortDataWidth / 8; - localparam SlvPortMaxSize = $clog2(SlvPortStrbWidth); - localparam MstPortMaxSize = $clog2(MstPortStrbWidth); + localparam SbrPortMaxSize = $clog2(SbrPortStrbWidth); + localparam MgrPortMaxSize = $clog2(MgrPortStrbWidth); // Byte-grouped data words - typedef logic [MstPortStrbWidth-1:0][7:0] mst_data_t; - typedef logic [SlvPortStrbWidth-1:0][7:0] slv_data_t; + typedef logic [MgrPortStrbWidth-1:0][7:0] mgr_data_t; + typedef logic [SbrPortStrbWidth-1:0][7:0] sbr_data_t; // Address width typedef logic [AddrWidth-1:0] addr_t; @@ -77,11 +77,11 @@ module axi_dw_upsizer #( typedef logic [IdWidth-1:0] id_t; // Length of burst after upsizing - typedef logic [$clog2(MstPortStrbWidth/SlvPortStrbWidth) + 7:0] burst_len_t; + typedef logic [$clog2(MgrPortStrbWidth/SbrPortStrbWidth) + 7:0] burst_len_t; // Internal AXI bus - mst_port_axi_req_t mst_req; - mst_port_axi_rsp_t mst_rsp; + mgr_port_axi_req_t mgr_req; + mgr_port_axi_rsp_t mgr_rsp; /************** * ARBITERS * @@ -89,45 +89,45 @@ module axi_dw_upsizer #( // R - slv_r_chan_t [MaxReads-1:0] slv_r_tran; - logic [MaxReads-1:0] slv_r_valid_tran; - logic [MaxReads-1:0] slv_r_ready_tran; + sbr_r_chan_t [MaxReads-1:0] sbr_r_tran; + logic [MaxReads-1:0] sbr_r_valid_tran; + logic [MaxReads-1:0] sbr_r_ready_tran; rr_arb_tree #( .NumIn (MaxReads ), - .DataType (slv_r_chan_t), + .DataType (sbr_r_chan_t), .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) - ) i_slv_r_arb ( + ) i_sbr_r_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), .flush_i(1'b0 ), .rr_i ('0 ), - .req_i (slv_r_valid_tran ), - .gnt_o (slv_r_ready_tran ), - .data_i (slv_r_tran ), - .gnt_i (slv_req_i.r_ready), - .req_o (slv_rsp_o.r_valid), - .data_o (slv_rsp_o.r ), + .req_i (sbr_r_valid_tran ), + .gnt_o (sbr_r_ready_tran ), + .data_i (sbr_r_tran ), + .gnt_i (sbr_req_i.r_ready), + .req_o (sbr_rsp_o.r_valid), + .data_o (sbr_rsp_o.r ), .idx_o (/* Unused */ ) ); - logic [MaxReads-1:0] mst_r_ready_tran; - assign mst_req.r_ready = |mst_r_ready_tran; + logic [MaxReads-1:0] mgr_r_ready_tran; + assign mgr_req.r_ready = |mgr_r_ready_tran; // AR - id_t arb_slv_ar_id; - logic arb_slv_ar_req; - logic arb_slv_ar_gnt; - logic [MaxReads-1:0] arb_slv_ar_gnt_tran; - // Multiplex AR slave between AR and AW for the injection of atomic operations with an R response. + id_t arb_sbr_ar_id; + logic arb_sbr_ar_req; + logic arb_sbr_ar_gnt; + logic [MaxReads-1:0] arb_sbr_ar_gnt_tran; + // Multiplex AR subordinate between AR and AW for the injection of atomic operations with an R response. logic inject_aw_into_ar; logic inject_aw_into_ar_req; logic inject_aw_into_ar_gnt; - assign arb_slv_ar_gnt = |arb_slv_ar_gnt_tran; + assign arb_sbr_ar_gnt = |arb_sbr_ar_gnt_tran; rr_arb_tree #( .NumIn (2 ), @@ -135,25 +135,25 @@ module axi_dw_upsizer #( .ExtPrio (1'b0 ), .AxiVldRdy (1'b1 ), .LockIn (1'b0 ) - ) i_slv_ar_arb ( + ) i_sbr_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), .flush_i(1'b0 ), .rr_i ('0 ), - .req_i ({inject_aw_into_ar_req, slv_req_i.ar_valid}), - .gnt_o ({inject_aw_into_ar_gnt, slv_rsp_o.ar_ready}), - .data_i ({slv_req_i.aw.id, slv_req_i.ar.id} ), - .req_o (arb_slv_ar_req ), - .gnt_i (arb_slv_ar_gnt ), - .data_o (arb_slv_ar_id ), + .req_i ({inject_aw_into_ar_req, sbr_req_i.ar_valid}), + .gnt_o ({inject_aw_into_ar_gnt, sbr_rsp_o.ar_ready}), + .data_i ({sbr_req_i.aw.id, sbr_req_i.ar.id} ), + .req_o (arb_sbr_ar_req ), + .gnt_i (arb_sbr_ar_gnt ), + .data_o (arb_sbr_ar_id ), .idx_o (inject_aw_into_ar ) ); - ar_chan_t [MaxReads-1:0] mst_ar_tran; - id_t [MaxReads-1:0] mst_ar_id; - logic [MaxReads-1:0] mst_ar_valid_tran; - logic [MaxReads-1:0] mst_ar_ready_tran; - tran_id_t mst_req_idx; + ar_chan_t [MaxReads-1:0] mgr_ar_tran; + id_t [MaxReads-1:0] mgr_ar_id; + logic [MaxReads-1:0] mgr_ar_valid_tran; + logic [MaxReads-1:0] mgr_ar_ready_tran; + tran_id_t mgr_req_idx; rr_arb_tree #( .NumIn (MaxReads) , @@ -161,73 +161,73 @@ module axi_dw_upsizer #( .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) - ) i_mst_ar_arb ( + ) i_mgr_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), .flush_i(1'b0 ), .rr_i ('0 ), - .req_i (mst_ar_valid_tran), - .gnt_o (mst_ar_ready_tran), - .data_i (mst_ar_tran ), - .gnt_i (mst_rsp.ar_ready ), - .req_o (mst_req.ar_valid ), - .data_o (mst_req.ar ), - .idx_o (mst_req_idx ) + .req_i (mgr_ar_valid_tran), + .gnt_o (mgr_ar_ready_tran), + .data_i (mgr_ar_tran ), + .gnt_i (mgr_rsp.ar_ready ), + .req_o (mgr_req.ar_valid ), + .data_o (mgr_req.ar ), + .idx_o (mgr_req_idx ) ); /***************** - * ERROR SLAVE * + * ERROR SUBORDINATE * *****************/ - mst_port_axi_req_t axi_err_req; - mst_port_axi_rsp_t axi_err_rsp; + mgr_port_axi_req_t axi_err_req; + mgr_port_axi_rsp_t axi_err_rsp; - axi_err_slv #( + axi_err_sbr #( .IdWidth (IdWidth ), .Resp (axi_pkg::RESP_SLVERR), - .axi_req_t (mst_port_axi_req_t ), - .axi_rsp_t (mst_port_axi_rsp_t ) - ) i_axi_err_slv ( + .axi_req_t (mgr_port_axi_req_t ), + .axi_rsp_t (mgr_port_axi_rsp_t ) + ) i_axi_err_sbr ( .clk_i (clk_i ), .rst_ni (rst_ni ), .test_i (1'b0 ), - .slv_req_i(axi_err_req), - .slv_rsp_o(axi_err_rsp) + .sbr_req_i(axi_err_req), + .sbr_rsp_o(axi_err_rsp) ); /*********** * DEMUX * ***********/ - // Requests can be sent either to the error slave, - // or to the DWC's master port. + // Requests can be sent either to the error subordinate, + // or to the DWC's manager port. - logic [MaxReads-1:0] mst_req_ar_err; - logic mst_req_aw_err; + logic [MaxReads-1:0] mgr_req_ar_err; + logic mgr_req_aw_err; axi_demux #( .IdWidth (IdWidth ), .LookBits (IdWidth ), .aw_chan_t (aw_chan_t ), - .w_chan_t (mst_w_chan_t ), + .w_chan_t (mgr_w_chan_t ), .b_chan_t (b_chan_t ), .ar_chan_t (ar_chan_t ), - .r_chan_t (mst_r_chan_t ), - .axi_req_t (mst_port_axi_req_t), - .axi_rsp_t (mst_port_axi_rsp_t), - .NumMstPorts (2 ), + .r_chan_t (mgr_r_chan_t ), + .axi_req_t (mgr_port_axi_req_t), + .axi_rsp_t (mgr_port_axi_rsp_t), + .NumMgrPorts (2 ), .MaxTrans (MaxReads ), .SpillAw (1'b1 ) // Required to break dependency between AW and W channels ) i_axi_demux ( .clk_i (clk_i ), .rst_ni (rst_ni ), .test_i (1'b0 ), - .mst_reqs_o ({axi_err_req, mst_req_o} ), - .mst_rsps_i ({axi_err_rsp, mst_rsp_i} ), - .slv_ar_select_i(mst_req_ar_err[mst_req_idx]), - .slv_aw_select_i(mst_req_aw_err ), - .slv_req_i (mst_req ), - .slv_rsp_o (mst_rsp ) + .mgr_reqs_o ({axi_err_req, mgr_req_o} ), + .mgr_rsps_i ({axi_err_rsp, mgr_rsp_i} ), + .sbr_ar_select_i(mgr_req_ar_err[mgr_req_idx]), + .sbr_aw_select_i(mgr_req_aw_err ), + .sbr_req_i (mgr_req ), + .sbr_rsp_o (mgr_rsp ) ); /********** @@ -246,7 +246,7 @@ module axi_dw_upsizer #( aw_chan_t aw ; logic aw_valid ; logic aw_throw_error ; - mst_w_chan_t w ; + mgr_w_chan_t w ; logic w_valid ; axi_pkg::len_t burst_len ; axi_pkg::size_t orig_aw_size; @@ -272,7 +272,7 @@ module axi_dw_upsizer #( logic [MaxReads-1:0] id_clash_upsizer; tran_id_t idx_id_clash_upsizer ; for (genvar t = 0; t < MaxReads; t++) begin: gen_id_clash - assign id_clash_upsizer[t] = arb_slv_ar_id == mst_ar_id[t] && !idle_read_upsizer[t]; + assign id_clash_upsizer[t] = arb_sbr_ar_id == mgr_ar_id[t] && !idle_read_upsizer[t]; end onehot_to_bin #( @@ -297,7 +297,7 @@ module axi_dw_upsizer #( assign r_upsizer_valid = |rid_upsizer_match; for (genvar t = 0; t < MaxReads; t++) begin: gen_rid_match - assign rid_upsizer_match[t] = (mst_rsp.r.id == mst_ar_id[t]) && !idle_read_upsizer[t]; + assign rid_upsizer_match[t] = (mgr_rsp.r.id == mgr_ar_id[t]) && !idle_read_upsizer[t]; end onehot_to_bin #( @@ -323,7 +323,7 @@ module axi_dw_upsizer #( assign idle_read_upsizer[t] = (r_state_q == R_IDLE) || (r_state_q == R_INJECT_AW); // Byte-grouped data signal for the lane steering step - slv_data_t r_data; + sbr_data_t r_data; always_comb begin // Maintain state @@ -331,27 +331,27 @@ module axi_dw_upsizer #( r_req_d = r_req_q ; // AR Channel - mst_ar_tran[t] = r_req_q.ar ; - mst_ar_id[t] = r_req_q.ar.id ; - mst_ar_valid_tran[t] = r_req_q.ar_valid; + mgr_ar_tran[t] = r_req_q.ar ; + mgr_ar_id[t] = r_req_q.ar.id ; + mgr_ar_valid_tran[t] = r_req_q.ar_valid; // Throw an error - mst_req_ar_err[t] = r_req_q.ar_throw_error; + mgr_req_ar_err[t] = r_req_q.ar_throw_error; // R Channel // No latency - slv_r_tran[t] = '0 ; - slv_r_tran[t].id = mst_rsp.r.id ; - slv_r_tran[t].resp = mst_rsp.r.resp; - slv_r_tran[t].user = mst_rsp.r.user; + sbr_r_tran[t] = '0 ; + sbr_r_tran[t].id = mgr_rsp.r.id ; + sbr_r_tran[t].resp = mgr_rsp.r.resp; + sbr_r_tran[t].user = mgr_rsp.r.user; - arb_slv_ar_gnt_tran[t] = 1'b0; + arb_sbr_ar_gnt_tran[t] = 1'b0; - mst_r_ready_tran[t] = 1'b0; - slv_r_valid_tran[t] = 1'b0; + mgr_r_ready_tran[t] = 1'b0; + sbr_r_valid_tran[t] = 1'b0; // Got a grant on the AR channel - if (mst_ar_valid_tran[t] && mst_ar_ready_tran[t]) begin + if (mgr_ar_valid_tran[t] && mgr_ar_ready_tran[t]) begin r_req_d.ar_valid = 1'b0; r_req_d.ar_throw_error = 1'b0; end @@ -365,8 +365,8 @@ module axi_dw_upsizer #( r_req_d.ar = '0; // New read request - if (arb_slv_ar_req && (idx_ar_upsizer == t)) begin - arb_slv_ar_gnt_tran[t] = 1'b1; + if (arb_sbr_ar_req && (idx_ar_upsizer == t)) begin + arb_sbr_ar_gnt_tran[t] = 1'b1; // Must inject an AW request into this upsizer if (inject_aw_into_ar) begin @@ -376,10 +376,10 @@ module axi_dw_upsizer #( r_state_d = R_PASSTHROUGH; // Save beat - r_req_d.ar = slv_req_i.ar ; + r_req_d.ar = sbr_req_i.ar ; r_req_d.ar_valid = 1'b1 ; - r_req_d.burst_len = slv_req_i.ar.len ; - r_req_d.orig_ar_size = slv_req_i.ar.size; + r_req_d.burst_len = sbr_req_i.ar.len ; + r_req_d.orig_ar_size = sbr_req_i.ar.size; case (r_req_d.ar.burst) axi_pkg::BURST_INCR: begin @@ -388,12 +388,12 @@ module axi_dw_upsizer #( // No need to upsize single-beat transactions. if (r_req_d.ar.len != '0) begin // Evaluate output burst length - automatic addr_t start_addr = aligned_addr(r_req_d.ar.addr, MstPortMaxSize); + automatic addr_t start_addr = aligned_addr(r_req_d.ar.addr, MgrPortMaxSize); automatic addr_t end_addr = aligned_addr(beat_addr(r_req_d.ar.addr, r_req_d.orig_ar_size, r_req_d.burst_len, r_req_d.ar.burst, - r_req_d.burst_len), MstPortMaxSize); - r_req_d.ar.len = (end_addr - start_addr) >> MstPortMaxSize; - r_req_d.ar.size = MstPortMaxSize ; + r_req_d.burst_len), MgrPortMaxSize); + r_req_d.ar.len = (end_addr - start_addr) >> MgrPortMaxSize; + r_req_d.ar.size = MgrPortMaxSize ; r_state_d = R_INCR_UPSIZE ; end end @@ -446,12 +446,12 @@ module axi_dw_upsizer #( // No need to upsize single-beat transactions. if (r_req_d.ar.len != '0) begin // Evaluate output burst length - automatic addr_t start_addr = aligned_addr(r_req_d.ar.addr, MstPortMaxSize); + automatic addr_t start_addr = aligned_addr(r_req_d.ar.addr, MgrPortMaxSize); automatic addr_t end_addr = aligned_addr(beat_addr(r_req_d.ar.addr, r_req_d.orig_ar_size, r_req_d.burst_len, r_req_d.ar.burst, - r_req_d.burst_len), MstPortMaxSize); - r_req_d.ar.len = (end_addr - start_addr) >> MstPortMaxSize; - r_req_d.ar.size = MstPortMaxSize ; + r_req_d.burst_len), MgrPortMaxSize); + r_req_d.ar.len = (end_addr - start_addr) >> MgrPortMaxSize; + r_req_d.ar.size = MgrPortMaxSize ; r_state_d = R_INCR_UPSIZE ; end end @@ -477,26 +477,26 @@ module axi_dw_upsizer #( R_PASSTHROUGH, R_INCR_UPSIZE: begin // Request was accepted if (!r_req_q.ar_valid) - if (mst_rsp.r_valid && (idx_r_upsizer == t) && r_upsizer_valid) begin - automatic addr_t mst_port_offset = MstPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(MstPortStrbWidth)-1:0]; - automatic addr_t slv_port_offset = SlvPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(SlvPortStrbWidth)-1:0]; + if (mgr_rsp.r_valid && (idx_r_upsizer == t) && r_upsizer_valid) begin + automatic addr_t mgr_port_offset = MgrPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(MgrPortStrbWidth)-1:0]; + automatic addr_t sbr_port_offset = SbrPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(SbrPortStrbWidth)-1:0]; // Valid output - slv_r_valid_tran[t] = 1'b1 ; - slv_r_tran[t].last = mst_rsp.r.last && (r_req_q.burst_len == 0); + sbr_r_valid_tran[t] = 1'b1 ; + sbr_r_tran[t].last = mgr_rsp.r.last && (r_req_q.burst_len == 0); // Lane steering - for (int b = 0; b < MstPortStrbWidth; b++) begin - if ((b >= mst_port_offset) && - (b - mst_port_offset < (1 << r_req_q.orig_ar_size)) && - (b + slv_port_offset - mst_port_offset < SlvPortStrbWidth)) begin - r_data[b + slv_port_offset - mst_port_offset] = mst_rsp.r.data[8*b +: 8]; + for (int b = 0; b < MgrPortStrbWidth; b++) begin + if ((b >= mgr_port_offset) && + (b - mgr_port_offset < (1 << r_req_q.orig_ar_size)) && + (b + sbr_port_offset - mgr_port_offset < SbrPortStrbWidth)) begin + r_data[b + sbr_port_offset - mgr_port_offset] = mgr_rsp.r.data[8*b +: 8]; end end - slv_r_tran[t].data = r_data; + sbr_r_tran[t].data = r_data; // Acknowledgment - if (slv_r_ready_tran[t]) begin + if (sbr_r_ready_tran[t]) begin r_req_d.burst_len = r_req_q.burst_len - 1; case (r_req_q.ar.burst) @@ -510,11 +510,11 @@ module axi_dw_upsizer #( case (r_state_q) R_PASSTHROUGH: - mst_r_ready_tran[t] = 1'b1; + mgr_r_ready_tran[t] = 1'b1; R_INCR_UPSIZE: - if (r_req_q.burst_len == 0 || (aligned_addr(r_req_d.ar.addr, MstPortMaxSize) != aligned_addr(r_req_q.ar.addr, MstPortMaxSize))) - mst_r_ready_tran[t] = 1'b1; + if (r_req_q.burst_len == 0 || (aligned_addr(r_req_d.ar.addr, MgrPortMaxSize) != aligned_addr(r_req_q.ar.addr, MgrPortMaxSize))) + mgr_r_ready_tran[t] = 1'b1; endcase if (r_req_q.burst_len == '0) @@ -549,7 +549,7 @@ module axi_dw_upsizer #( w_state_e w_state_d, w_state_q; // Byte-grouped data signal for the serialization step - mst_data_t w_data; + mgr_data_t w_data; always_comb begin inject_aw_into_ar_req = 1'b0; @@ -559,28 +559,28 @@ module axi_dw_upsizer #( w_req_d = w_req_q ; // AW Channel - mst_req.aw = w_req_q.aw ; - mst_req.aw_valid = w_req_q.aw_valid; - slv_rsp_o.aw_ready = '0 ; + mgr_req.aw = w_req_q.aw ; + mgr_req.aw_valid = w_req_q.aw_valid; + sbr_rsp_o.aw_ready = '0 ; // Throw an error. - mst_req_aw_err = w_req_q.aw_throw_error; + mgr_req_aw_err = w_req_q.aw_throw_error; // W Channel - mst_req.w = w_req_q.w ; - mst_req.w_valid = w_req_q.w_valid; - slv_rsp_o.w_ready = '0 ; + mgr_req.w = w_req_q.w ; + mgr_req.w_valid = w_req_q.w_valid; + sbr_rsp_o.w_ready = '0 ; // Initialize w_data w_data = w_req_q.w.data; // B Channel (No latency) - slv_rsp_o.b = mst_rsp.b ; - slv_rsp_o.b_valid = mst_rsp.b_valid ; - mst_req.b_ready = slv_req_i.b_ready; + sbr_rsp_o.b = mgr_rsp.b ; + sbr_rsp_o.b_valid = mgr_rsp.b_valid ; + mgr_req.b_ready = sbr_req_i.b_ready; // Got a grant on the AW channel - if (mst_req.aw_valid && mst_rsp.aw_ready) begin + if (mgr_req.aw_valid && mgr_rsp.aw_ready) begin w_req_d.aw_valid = 1'b0; w_req_d.aw_throw_error = 1'b0; end @@ -588,7 +588,7 @@ module axi_dw_upsizer #( case (w_state_q) W_PASSTHROUGH, W_INCR_UPSIZE: begin // Got a grant on the W channel - if (mst_req.w_valid && mst_rsp.w_ready) begin + if (mgr_req.w_valid && mgr_rsp.w_ready) begin w_data = '0 ; w_req_d.w = '0 ; w_req_d.w_valid = 1'b0; @@ -597,25 +597,25 @@ module axi_dw_upsizer #( // Request was accepted if (!w_req_q.aw_valid) begin // Ready if downstream interface is idle, or if it is ready - slv_rsp_o.w_ready = ~mst_req.w_valid || mst_rsp.w_ready; + sbr_rsp_o.w_ready = ~mgr_req.w_valid || mgr_rsp.w_ready; - if (slv_req_i.w_valid && slv_rsp_o.w_ready) begin - automatic addr_t mst_port_offset = MstPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(MstPortStrbWidth)-1:0]; - automatic addr_t slv_port_offset = SlvPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(SlvPortStrbWidth)-1:0]; + if (sbr_req_i.w_valid && sbr_rsp_o.w_ready) begin + automatic addr_t mgr_port_offset = MgrPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(MgrPortStrbWidth)-1:0]; + automatic addr_t sbr_port_offset = SbrPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(SbrPortStrbWidth)-1:0]; // Serialization - for (int b = 0; b < MstPortStrbWidth; b++) - if ((b >= mst_port_offset) && - (b - mst_port_offset < (1 << w_req_q.orig_aw_size)) && - (b + slv_port_offset - mst_port_offset < SlvPortStrbWidth)) begin - w_data[b] = slv_req_i.w.data[8*(b + slv_port_offset - mst_port_offset) +: 8]; - w_req_d.w.strb[b] = slv_req_i.w.strb[b + slv_port_offset - mst_port_offset] ; + for (int b = 0; b < MgrPortStrbWidth; b++) + if ((b >= mgr_port_offset) && + (b - mgr_port_offset < (1 << w_req_q.orig_aw_size)) && + (b + sbr_port_offset - mgr_port_offset < SbrPortStrbWidth)) begin + w_data[b] = sbr_req_i.w.data[8*(b + sbr_port_offset - mgr_port_offset) +: 8]; + w_req_d.w.strb[b] = sbr_req_i.w.strb[b + sbr_port_offset - mgr_port_offset] ; end w_req_d.burst_len = w_req_q.burst_len - 1 ; w_req_d.w.data = w_data ; w_req_d.w.last = (w_req_q.burst_len == 0); - w_req_d.w.user = slv_req_i.w.user ; + w_req_d.w.user = sbr_req_i.w.user ; case (w_req_q.aw.burst) axi_pkg::BURST_INCR: begin @@ -633,15 +633,15 @@ module axi_dw_upsizer #( W_INCR_UPSIZE: // Forward when the burst is finished, or after filling up a word - if (w_req_q.burst_len == 0 || (aligned_addr(w_req_d.aw.addr, MstPortMaxSize) != aligned_addr(w_req_q.aw.addr, MstPortMaxSize))) + if (w_req_q.burst_len == 0 || (aligned_addr(w_req_d.aw.addr, MgrPortMaxSize) != aligned_addr(w_req_q.aw.addr, MgrPortMaxSize))) w_req_d.w_valid = 1'b1; endcase end end - if (mst_req.w_valid && mst_rsp.w_ready) + if (mgr_req.w_valid && mgr_rsp.w_ready) if (w_req_q.burst_len == '1) begin - slv_rsp_o.w_ready = 1'b0 ; + sbr_rsp_o.w_ready = 1'b0 ; w_state_d = W_IDLE; end end @@ -656,39 +656,39 @@ module axi_dw_upsizer #( w_req_d.w = '0 ; w_req_d.w_valid = 1'b0; - if (slv_req_i.aw_valid && slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // ATOP with an R response + if (sbr_req_i.aw_valid && sbr_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // ATOP with an R response inject_aw_into_ar_req = 1'b1 ; - slv_rsp_o.aw_ready = inject_aw_into_ar_gnt; + sbr_rsp_o.aw_ready = inject_aw_into_ar_gnt; end else begin // Regular AW - slv_rsp_o.aw_ready = 1'b1; + sbr_rsp_o.aw_ready = 1'b1; end // New write request - if (slv_req_i.aw_valid & slv_rsp_o.aw_ready) begin + if (sbr_req_i.aw_valid & sbr_rsp_o.aw_ready) begin // Default state w_state_d = W_PASSTHROUGH; // Save beat - w_req_d.aw = slv_req_i.aw; + w_req_d.aw = sbr_req_i.aw; w_req_d.aw_valid = 1'b1 ; - w_req_d.burst_len = slv_req_i.aw.len ; - w_req_d.orig_aw_size = slv_req_i.aw.size; + w_req_d.burst_len = sbr_req_i.aw.len ; + w_req_d.orig_aw_size = sbr_req_i.aw.size; - case (slv_req_i.aw.burst) + case (sbr_req_i.aw.burst) axi_pkg::BURST_INCR: begin // Modifiable transaction - if (modifiable(slv_req_i.aw.cache)) + if (modifiable(sbr_req_i.aw.cache)) // No need to upsize single-beat transactions. - if (slv_req_i.aw.len != '0) begin + if (sbr_req_i.aw.len != '0) begin // Evaluate output burst length - automatic addr_t start_addr = aligned_addr(slv_req_i.aw.addr, MstPortMaxSize); - automatic addr_t end_addr = aligned_addr(beat_addr(slv_req_i.aw.addr, - slv_req_i.aw.size, slv_req_i.aw.len, slv_req_i.aw.burst, slv_req_i.aw.len), - MstPortMaxSize); + automatic addr_t start_addr = aligned_addr(sbr_req_i.aw.addr, MgrPortMaxSize); + automatic addr_t end_addr = aligned_addr(beat_addr(sbr_req_i.aw.addr, + sbr_req_i.aw.size, sbr_req_i.aw.len, sbr_req_i.aw.burst, sbr_req_i.aw.len), + MgrPortMaxSize); - w_req_d.aw.len = (end_addr - start_addr) >> MstPortMaxSize; - w_req_d.aw.size = MstPortMaxSize ; + w_req_d.aw.len = (end_addr - start_addr) >> MgrPortMaxSize; + w_req_d.aw.size = MgrPortMaxSize ; w_state_d = W_INCR_UPSIZE ; end end @@ -704,7 +704,7 @@ module axi_dw_upsizer #( w_req_d.aw_throw_error = 1'b1 ; // ... but might if this is a single-beat transaction - if (slv_req_i.aw.len == '0) + if (sbr_req_i.aw.len == '0) w_req_d.aw_throw_error = 1'b0; end endcase diff --git a/src/axi_err_slv.sv b/src/axi_err_sbr.sv similarity index 92% rename from src/axi_err_slv.sv rename to src/axi_err_sbr.sv index 4c8cfe3a0..0fca3acc4 100644 --- a/src/axi_err_slv.sv +++ b/src/axi_err_sbr.sv @@ -13,25 +13,25 @@ // - Andreas Kurth // - Matheus Cavalcante -// AXI Error Slave: This module always responds with an AXI error for transactions that are sent to +// AXI Error Subordinate: This module always responds with an AXI error for transactions that are sent to // it. This module optionally supports ATOPs if the `ATOPs` parameter is set. -module axi_err_slv #( +module axi_err_sbr #( parameter int unsigned IdWidth = 0, // AXI ID Width parameter type axi_req_t = logic, // AXI 4 request struct, with atop field parameter type axi_rsp_t = logic, // AXI 4 response struct - parameter axi_pkg::resp_t Resp = axi_pkg::RESP_DECERR, // Error generated by this slave. + parameter axi_pkg::resp_t Resp = axi_pkg::RESP_DECERR, // Error generated by this subordinate. parameter int unsigned RespWidth = 32'd64, // Data response width, gets zero extended or truncated to r.data. parameter logic [RespWidth-1:0] RespData = 64'hCA11AB1EBADCAB1E, // Hexvalue for data return value - parameter bit ATOPs = 1'b1, // Activate support for ATOPs. Set to 1 if this slave could ever get an atomic AXI transaction. + parameter bit ATOPs = 1'b1, // Activate support for ATOPs. Set to 1 if this subordinate could ever get an atomic AXI transaction. parameter int unsigned MaxTrans = 1 // Maximum # of accepted transactions before stalling ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Testmode enable - // slave port - input axi_req_t slv_req_i, - output axi_rsp_t slv_rsp_o + // subordinate port + input axi_req_t sbr_req_i, + output axi_rsp_t sbr_rsp_o ); typedef logic [IdWidth-1:0] id_t; typedef struct packed { @@ -51,14 +51,14 @@ module axi_err_slv #( ) i_atop_filter ( .clk_i, .rst_ni, - .slv_req_i ( slv_req_i ), - .slv_rsp_o ( slv_rsp_o ), - .mst_req_o ( err_req ), - .mst_rsp_i ( err_rsp ) + .sbr_req_i ( sbr_req_i ), + .sbr_rsp_o ( sbr_rsp_o ), + .mgr_req_o ( err_req ), + .mgr_rsp_i ( err_rsp ) ); end else begin - assign err_req = slv_req_i; - assign slv_rsp_o = err_rsp; + assign err_req = sbr_req_i; + assign sbr_rsp_o = err_rsp; end // w fifo @@ -251,7 +251,7 @@ module axi_err_slv #( end default disable iff (!rst_ni); if (!ATOPs) begin : gen_assert_atops_unsupported - assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> slv_req_i.aw.atop == '0)) else + assume property( @(posedge clk_i) (sbr_req_i.aw_valid |-> sbr_req_i.aw.atop == '0)) else $fatal(1, "Got ATOP but not configured to support ATOPs!"); end `endif diff --git a/src/axi_fifo.sv b/src/axi_fifo.sv index fb9185259..cb1481fc4 100644 --- a/src/axi_fifo.sv +++ b/src/axi_fifo.sv @@ -34,33 +34,33 @@ module axi_fifo #( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, - // slave port - input axi_req_t slv_req_i, - output axi_rsp_t slv_rsp_o, - // master port - output axi_req_t mst_req_o, - input axi_rsp_t mst_rsp_i + // subordinate port + input axi_req_t sbr_req_i, + output axi_rsp_t sbr_rsp_o, + // manager port + output axi_req_t mgr_req_o, + input axi_rsp_t mgr_rsp_i ); if (Depth == '0) begin : gen_no_fifo // degenerate case, connect input to output - assign mst_req_o = slv_req_i; - assign slv_rsp_o = mst_rsp_i; + assign mgr_req_o = sbr_req_i; + assign sbr_rsp_o = mgr_rsp_i; end else begin : gen_axi_fifo logic aw_fifo_empty, ar_fifo_empty, w_fifo_empty, r_fifo_empty, b_fifo_empty; logic aw_fifo_full, ar_fifo_full, w_fifo_full, r_fifo_full, b_fifo_full; - assign mst_req_o.aw_valid = ~aw_fifo_empty; - assign mst_req_o.ar_valid = ~ar_fifo_empty; - assign mst_req_o.w_valid = ~w_fifo_empty; - assign slv_rsp_o.r_valid = ~r_fifo_empty; - assign slv_rsp_o.b_valid = ~b_fifo_empty; + assign mgr_req_o.aw_valid = ~aw_fifo_empty; + assign mgr_req_o.ar_valid = ~ar_fifo_empty; + assign mgr_req_o.w_valid = ~w_fifo_empty; + assign sbr_rsp_o.r_valid = ~r_fifo_empty; + assign sbr_rsp_o.b_valid = ~b_fifo_empty; - assign slv_rsp_o.aw_ready = ~aw_fifo_full; - assign slv_rsp_o.ar_ready = ~ar_fifo_full; - assign slv_rsp_o.w_ready = ~w_fifo_full; - assign mst_req_o.r_ready = ~r_fifo_full; - assign mst_req_o.b_ready = ~b_fifo_full; + assign sbr_rsp_o.aw_ready = ~aw_fifo_full; + assign sbr_rsp_o.ar_ready = ~ar_fifo_full; + assign sbr_rsp_o.w_ready = ~w_fifo_full; + assign mgr_req_o.r_ready = ~r_fifo_full; + assign mgr_req_o.b_ready = ~b_fifo_full; // A FiFo for each channel fifo_v3 #( @@ -75,10 +75,10 @@ module axi_fifo #( .full_o (aw_fifo_full), .empty_o (aw_fifo_empty), .usage_o (), - .data_i (slv_req_i.aw), - .push_i (slv_req_i.aw_valid && slv_rsp_o.aw_ready), - .data_o (mst_req_o.aw), - .pop_i (mst_req_o.aw_valid && mst_rsp_i.aw_ready) + .data_i (sbr_req_i.aw), + .push_i (sbr_req_i.aw_valid && sbr_rsp_o.aw_ready), + .data_o (mgr_req_o.aw), + .pop_i (mgr_req_o.aw_valid && mgr_rsp_i.aw_ready) ); fifo_v3 #( .dtype(ar_chan_t), @@ -92,10 +92,10 @@ module axi_fifo #( .full_o (ar_fifo_full), .empty_o (ar_fifo_empty), .usage_o (), - .data_i (slv_req_i.ar), - .push_i (slv_req_i.ar_valid && slv_rsp_o.ar_ready), - .data_o (mst_req_o.ar), - .pop_i (mst_req_o.ar_valid && mst_rsp_i.ar_ready) + .data_i (sbr_req_i.ar), + .push_i (sbr_req_i.ar_valid && sbr_rsp_o.ar_ready), + .data_o (mgr_req_o.ar), + .pop_i (mgr_req_o.ar_valid && mgr_rsp_i.ar_ready) ); fifo_v3 #( .dtype(w_chan_t), @@ -109,10 +109,10 @@ module axi_fifo #( .full_o (w_fifo_full), .empty_o (w_fifo_empty), .usage_o (), - .data_i (slv_req_i.w), - .push_i (slv_req_i.w_valid && slv_rsp_o.w_ready), - .data_o (mst_req_o.w), - .pop_i (mst_req_o.w_valid && mst_rsp_i.w_ready) + .data_i (sbr_req_i.w), + .push_i (sbr_req_i.w_valid && sbr_rsp_o.w_ready), + .data_o (mgr_req_o.w), + .pop_i (mgr_req_o.w_valid && mgr_rsp_i.w_ready) ); fifo_v3 #( .dtype(r_chan_t), @@ -126,10 +126,10 @@ module axi_fifo #( .full_o (r_fifo_full), .empty_o (r_fifo_empty), .usage_o (), - .data_i (mst_rsp_i.r), - .push_i (mst_rsp_i.r_valid && mst_req_o.r_ready), - .data_o (slv_rsp_o.r), - .pop_i (slv_rsp_o.r_valid && slv_req_i.r_ready) + .data_i (mgr_rsp_i.r), + .push_i (mgr_rsp_i.r_valid && mgr_req_o.r_ready), + .data_o (sbr_rsp_o.r), + .pop_i (sbr_rsp_o.r_valid && sbr_req_i.r_ready) ); fifo_v3 #( .dtype(b_chan_t), @@ -143,10 +143,10 @@ module axi_fifo #( .full_o (b_fifo_full), .empty_o (b_fifo_empty), .usage_o (), - .data_i (mst_rsp_i.b), - .push_i (mst_rsp_i.b_valid && mst_req_o.b_ready), - .data_o (slv_rsp_o.b), - .pop_i (slv_rsp_o.b_valid && slv_req_i.b_ready) + .data_i (mgr_rsp_i.b), + .push_i (mgr_rsp_i.b_valid && mgr_req_o.b_ready), + .data_o (sbr_rsp_o.b), + .pop_i (sbr_rsp_o.b_valid && sbr_req_i.b_ready) ); end @@ -175,8 +175,8 @@ module axi_fifo_intf #( input logic clk_i, input logic rst_ni, input logic test_i, - AXI_BUS.Slave slv, - AXI_BUS.Master mst + AXI_BUS.Subordinate sbr, + AXI_BUS.Manager mgr ); typedef logic [ID_WIDTH-1:0] id_t; @@ -193,14 +193,14 @@ module axi_fifo_intf #( `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_rsp_t slv_rsp, mst_rsp; + axi_req_t sbr_req, mgr_req; + axi_rsp_t sbr_rsp, mgr_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, slv_rsp) + `AXI_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, sbr_rsp) - `AXI_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, mst) + `AXI_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_fifo #( .Depth (DEPTH), @@ -216,10 +216,10 @@ module axi_fifo_intf #( .clk_i, .rst_ni, .test_i, - .slv_req_i(slv_req), - .slv_rsp_o(slv_rsp), - .mst_req_o(mst_req), - .mst_rsp_i(mst_rsp) + .sbr_req_i (sbr_req), + .sbr_rsp_o(sbr_rsp), + .mgr_req_o (mgr_req), + .mgr_rsp_i(mgr_rsp) ); // Check the invariants. @@ -234,21 +234,21 @@ module axi_fifo_intf #( else $fatal(1, "Wrong id width parameter"); assert (USER_WIDTH > 0) else $fatal(1, "Wrong user width parameter"); - assert (slv.AXI_ADDR_WIDTH == ADDR_WIDTH) + assert (sbr.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); - assert (slv.AXI_DATA_WIDTH == DATA_WIDTH) + assert (sbr.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); - assert (slv.AXI_ID_WIDTH == ID_WIDTH) + assert (sbr.AXI_ID_WIDTH == ID_WIDTH) else $fatal(1, "Wrong interface definition"); - assert (slv.AXI_USER_WIDTH == USER_WIDTH) + assert (sbr.AXI_USER_WIDTH == USER_WIDTH) else $fatal(1, "Wrong interface definition"); - assert (mst.AXI_ADDR_WIDTH == ADDR_WIDTH) + assert (mgr.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); - assert (mst.AXI_DATA_WIDTH == DATA_WIDTH) + assert (mgr.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); - assert (mst.AXI_ID_WIDTH == ID_WIDTH) + assert (mgr.AXI_ID_WIDTH == ID_WIDTH) else $fatal(1, "Wrong interface definition"); - assert (mst.AXI_USER_WIDTH == USER_WIDTH) + assert (mgr.AXI_USER_WIDTH == USER_WIDTH) else $fatal(1, "Wrong interface definition"); end `endif diff --git a/src/axi_from_mem.sv b/src/axi_from_mem.sv index 7ca3aa2ff..7c620bb32 100644 --- a/src/axi_from_mem.sv +++ b/src/axi_from_mem.sv @@ -41,40 +41,40 @@ module axi_from_mem #( input logic clk_i, /// Asynchronous reset, active low. input logic rst_ni, - /// Memory slave port, request is active. + /// Memory subordinate port, request is active. input logic mem_req_i, - /// Memory slave port, request address. + /// Memory subordinate port, request address. /// /// Byte address, will be extended or truncated to match `AddrWidth`. input logic [MemAddrWidth-1:0] mem_addr_i, - /// Memory slave port, request is a write. + /// Memory subordinate port, request is a write. /// /// `0`: Read request. /// `1`: Write request. input logic mem_we_i, /// Memory salve port, write data for request. input logic [DataWidth-1:0] mem_wdata_i, - /// Memory slave port, write byte enable for request. + /// Memory subordinate port, write byte enable for request. /// /// Active high. input logic [DataWidth/8-1:0] mem_be_i, /// Memory request is granted. output logic mem_gnt_o, - /// Memory slave port, response is valid. For each request, regardless if read or write, + /// Memory subordinate port, response is valid. For each request, regardless if read or write, /// this will be active once for one cycle. output logic mem_rsp_valid_o, - /// Memory slave port, response read data. This is forwarded directly from the AXI4-Lite + /// Memory subordinate port, response read data. This is forwarded directly from the AXI4-Lite /// `R` channel. Only valid for responses generated by a read request. output logic [DataWidth-1:0] mem_rsp_rdata_o, /// Memory request encountered an error. This is forwarded from the AXI4-Lite error response. output logic mem_rsp_error_o, - /// AXI4 master port, slave aw cache signal - input axi_pkg::cache_t slv_aw_cache_i, - /// AXI4 master port, slave ar cache signal - input axi_pkg::cache_t slv_ar_cache_i, - /// AXI4 master port, request output. + /// AXI4 manager port, subordinate aw cache signal + input axi_pkg::cache_t sbr_aw_cache_i, + /// AXI4 manager port, subordinate ar cache signal + input axi_pkg::cache_t sbr_ar_cache_i, + /// AXI4 manager port, request output. output axi_req_t axi_req_o, - /// AXI4 master port, response input. + /// AXI4 manager port, response input. input axi_rsp_t axi_rsp_i ); @@ -113,12 +113,12 @@ module axi_from_mem #( .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_axi_lite_to_axi ( - .slv_req_lite_i ( axi_lite_req ), - .slv_rsp_lite_o ( axi_lite_rsp ), - .slv_aw_cache_i, - .slv_ar_cache_i, - .mst_req_o ( axi_req_o ), - .mst_rsp_i ( axi_rsp_i ) + .sbr_req_lite_i ( axi_lite_req ), + .sbr_rsp_lite_o ( axi_lite_rsp ), + .sbr_aw_cache_i, + .sbr_ar_cache_i, + .mgr_req_o ( axi_req_o ), + .mgr_rsp_i ( axi_rsp_i ) ); endmodule diff --git a/src/axi_id_prepend.sv b/src/axi_id_prepend.sv index 305039cb2..74aa28066 100644 --- a/src/axi_id_prepend.sv +++ b/src/axi_id_prepend.sv @@ -13,148 +13,148 @@ // - Andreas Kurth // AXI ID Prepend: This module prepends/strips the MSB from the AXI IDs. -// Constraints enforced through assertions: ID width of slave and master port +// Constraints enforced through assertions: ID width of subordinate and manager port module axi_id_prepend #( parameter int unsigned NumBus = 1, // Can take multiple axi busses - parameter int unsigned IdWidthSlvPort = 4, // AXI ID Width of the Slave Ports - parameter int unsigned IdWidthMstPort = 6, // AXI ID Width of the Master Ports - parameter type slv_aw_chan_t = logic, // AW Channel Type for slv port - parameter type slv_w_chan_t = logic, // W Channel Type for slv port - parameter type slv_b_chan_t = logic, // B Channel Type for slv port - parameter type slv_ar_chan_t = logic, // AR Channel Type for slv port - parameter type slv_r_chan_t = logic, // R Channel Type for slv port - parameter type mst_aw_chan_t = logic, // AW Channel Type for mst port - parameter type mst_w_chan_t = logic, // W Channel Type for mst port - parameter type mst_b_chan_t = logic, // B Channel Type for mst port - parameter type mst_ar_chan_t = logic, // AR Channel Type for mst port - parameter type mst_r_chan_t = logic, // R Channel Type for mst port + parameter int unsigned IdWidthSbrPort = 4, // AXI ID Width of the Subordinate Ports + parameter int unsigned IdWidthMgrPort = 6, // AXI ID Width of the Manager Ports + parameter type sbr_aw_chan_t = logic, // AW Channel Type for sbr port + parameter type sbr_w_chan_t = logic, // W Channel Type for sbr port + parameter type sbr_b_chan_t = logic, // B Channel Type for sbr port + parameter type sbr_ar_chan_t = logic, // AR Channel Type for sbr port + parameter type sbr_r_chan_t = logic, // R Channel Type for sbr port + parameter type mgr_aw_chan_t = logic, // AW Channel Type for mgr port + parameter type mgr_w_chan_t = logic, // W Channel Type for mgr port + parameter type mgr_b_chan_t = logic, // B Channel Type for mgr port + parameter type mgr_ar_chan_t = logic, // AR Channel Type for mgr port + parameter type mgr_r_chan_t = logic, // R Channel Type for mgr port // DEPENDENT PARAMETER DO NOT OVERWRITE! - parameter int unsigned PreIdWidth = IdWidthMstPort - IdWidthSlvPort + parameter int unsigned PreIdWidth = IdWidthMgrPort - IdWidthSbrPort ) ( input logic [PreIdWidth-1:0] pre_id_i, // ID to be prepended - // slave port (input), connect master modules here + // subordinate port (input), connect manager modules here // AW channel - input slv_aw_chan_t [NumBus-1:0] slv_aw_chans_i, - input logic [NumBus-1:0] slv_aw_valids_i, - output logic [NumBus-1:0] slv_aw_readies_o, + input sbr_aw_chan_t [NumBus-1:0] sbr_aw_chans_i, + input logic [NumBus-1:0] sbr_aw_valids_i, + output logic [NumBus-1:0] sbr_aw_readies_o, // W channel - input slv_w_chan_t [NumBus-1:0] slv_w_chans_i, - input logic [NumBus-1:0] slv_w_valids_i, - output logic [NumBus-1:0] slv_w_readies_o, + input sbr_w_chan_t [NumBus-1:0] sbr_w_chans_i, + input logic [NumBus-1:0] sbr_w_valids_i, + output logic [NumBus-1:0] sbr_w_readies_o, // B channel - output slv_b_chan_t [NumBus-1:0] slv_b_chans_o, - output logic [NumBus-1:0] slv_b_valids_o, - input logic [NumBus-1:0] slv_b_readies_i, + output sbr_b_chan_t [NumBus-1:0] sbr_b_chans_o, + output logic [NumBus-1:0] sbr_b_valids_o, + input logic [NumBus-1:0] sbr_b_readies_i, // AR channel - input slv_ar_chan_t [NumBus-1:0] slv_ar_chans_i, - input logic [NumBus-1:0] slv_ar_valids_i, - output logic [NumBus-1:0] slv_ar_readies_o, + input sbr_ar_chan_t [NumBus-1:0] sbr_ar_chans_i, + input logic [NumBus-1:0] sbr_ar_valids_i, + output logic [NumBus-1:0] sbr_ar_readies_o, // R channel - output slv_r_chan_t [NumBus-1:0] slv_r_chans_o, - output logic [NumBus-1:0] slv_r_valids_o, - input logic [NumBus-1:0] slv_r_readies_i, - // master ports (output), connect slave modules here + output sbr_r_chan_t [NumBus-1:0] sbr_r_chans_o, + output logic [NumBus-1:0] sbr_r_valids_o, + input logic [NumBus-1:0] sbr_r_readies_i, + // manager ports (output), connect subordinate modules here // AW channel - output mst_aw_chan_t [NumBus-1:0] mst_aw_chans_o, - output logic [NumBus-1:0] mst_aw_valids_o, - input logic [NumBus-1:0] mst_aw_readies_i, + output mgr_aw_chan_t [NumBus-1:0] mgr_aw_chans_o, + output logic [NumBus-1:0] mgr_aw_valids_o, + input logic [NumBus-1:0] mgr_aw_readies_i, // W channel - output mst_w_chan_t [NumBus-1:0] mst_w_chans_o, - output logic [NumBus-1:0] mst_w_valids_o, - input logic [NumBus-1:0] mst_w_readies_i, + output mgr_w_chan_t [NumBus-1:0] mgr_w_chans_o, + output logic [NumBus-1:0] mgr_w_valids_o, + input logic [NumBus-1:0] mgr_w_readies_i, // B channel - input mst_b_chan_t [NumBus-1:0] mst_b_chans_i, - input logic [NumBus-1:0] mst_b_valids_i, - output logic [NumBus-1:0] mst_b_readies_o, + input mgr_b_chan_t [NumBus-1:0] mgr_b_chans_i, + input logic [NumBus-1:0] mgr_b_valids_i, + output logic [NumBus-1:0] mgr_b_readies_o, // AR channel - output mst_ar_chan_t [NumBus-1:0] mst_ar_chans_o, - output logic [NumBus-1:0] mst_ar_valids_o, - input logic [NumBus-1:0] mst_ar_readies_i, + output mgr_ar_chan_t [NumBus-1:0] mgr_ar_chans_o, + output logic [NumBus-1:0] mgr_ar_valids_o, + input logic [NumBus-1:0] mgr_ar_readies_i, // R channel - input mst_r_chan_t [NumBus-1:0] mst_r_chans_i, - input logic [NumBus-1:0] mst_r_valids_i, - output logic [NumBus-1:0] mst_r_readies_o + input mgr_r_chan_t [NumBus-1:0] mgr_r_chans_i, + input logic [NumBus-1:0] mgr_r_valids_i, + output logic [NumBus-1:0] mgr_r_readies_o ); // prepend the ID for (genvar i = 0; i < NumBus; i++) begin : gen_id_prepend if (PreIdWidth == 0) begin : gen_no_prepend - assign mst_aw_chans_o[i] = slv_aw_chans_i[i]; - assign mst_ar_chans_o[i] = slv_ar_chans_i[i]; + assign mgr_aw_chans_o[i] = sbr_aw_chans_i[i]; + assign mgr_ar_chans_o[i] = sbr_ar_chans_i[i]; end else begin : gen_prepend always_comb begin - mst_aw_chans_o[i] = slv_aw_chans_i[i]; - mst_ar_chans_o[i] = slv_ar_chans_i[i]; - mst_aw_chans_o[i].id = {pre_id_i, slv_aw_chans_i[i].id[IdWidthSlvPort-1:0]}; - mst_ar_chans_o[i].id = {pre_id_i, slv_ar_chans_i[i].id[IdWidthSlvPort-1:0]}; + mgr_aw_chans_o[i] = sbr_aw_chans_i[i]; + mgr_ar_chans_o[i] = sbr_ar_chans_i[i]; + mgr_aw_chans_o[i].id = {pre_id_i, sbr_aw_chans_i[i].id[IdWidthSbrPort-1:0]}; + mgr_ar_chans_o[i].id = {pre_id_i, sbr_ar_chans_i[i].id[IdWidthSbrPort-1:0]}; end end // The ID is in the highest bits of the struct, so an assignment from a channel with a wide ID // to a channel with a shorter ID correctly cuts the prepended ID. - assign slv_b_chans_o[i] = mst_b_chans_i[i]; - assign slv_r_chans_o[i] = mst_r_chans_i[i]; + assign sbr_b_chans_o[i] = mgr_b_chans_i[i]; + assign sbr_r_chans_o[i] = mgr_r_chans_i[i]; end // assign the handshaking's and w channel - assign mst_w_chans_o = slv_w_chans_i; - assign mst_aw_valids_o = slv_aw_valids_i; - assign slv_aw_readies_o = mst_aw_readies_i; - assign mst_w_valids_o = slv_w_valids_i; - assign slv_w_readies_o = mst_w_readies_i; - assign slv_b_valids_o = mst_b_valids_i; - assign mst_b_readies_o = slv_b_readies_i; - assign mst_ar_valids_o = slv_ar_valids_i; - assign slv_ar_readies_o = mst_ar_readies_i; - assign slv_r_valids_o = mst_r_valids_i; - assign mst_r_readies_o = slv_r_readies_i; + assign mgr_w_chans_o = sbr_w_chans_i; + assign mgr_aw_valids_o = sbr_aw_valids_i; + assign sbr_aw_readies_o = mgr_aw_readies_i; + assign mgr_w_valids_o = sbr_w_valids_i; + assign sbr_w_readies_o = mgr_w_readies_i; + assign sbr_b_valids_o = mgr_b_valids_i; + assign mgr_b_readies_o = sbr_b_readies_i; + assign mgr_ar_valids_o = sbr_ar_valids_i; + assign sbr_ar_readies_o = mgr_ar_readies_i; + assign sbr_r_valids_o = mgr_r_valids_i; + assign mgr_r_readies_o = sbr_r_readies_i; // pragma translate_off `ifndef VERILATOR initial begin : p_assert assert(NumBus > 0) else $fatal(1, "Input must be at least one element wide."); - assert(PreIdWidth == ($bits(mst_aw_chans_o[0].id) - $bits(slv_aw_chans_i[0].id))) - else $fatal(1, "Prepend ID Width must be: $bits(mst_aw_chans_o.id)-$bits(slv_aw_chans_i.id)"); - assert ($bits(mst_aw_chans_o[0].id) > $bits(slv_aw_chans_i[0].id)) - else $fatal(1, "The master AXI port has to have a wider ID than the slave port."); + assert(PreIdWidth == ($bits(mgr_aw_chans_o[0].id) - $bits(sbr_aw_chans_i[0].id))) + else $fatal(1, "Prepend ID Width must be: $bits(mgr_aw_chans_o.id)-$bits(sbr_aw_chans_i.id)"); + assert ($bits(mgr_aw_chans_o[0].id) > $bits(sbr_aw_chans_i[0].id)) + else $fatal(1, "The manager AXI port has to have a wider ID than the subordinate port."); end aw_id : assert final( - mst_aw_chans_o[0].id[$bits(slv_aw_chans_i[0].id)-1:0] === slv_aw_chans_i[0].id) + mgr_aw_chans_o[0].id[$bits(sbr_aw_chans_i[0].id)-1:0] === sbr_aw_chans_i[0].id) else $fatal (1, "Something with the AW channel ID prepending went wrong."); - aw_addr : assert final(mst_aw_chans_o[0].addr === slv_aw_chans_i[0].addr) + aw_addr : assert final(mgr_aw_chans_o[0].addr === sbr_aw_chans_i[0].addr) else $fatal (1, "Something with the AW channel ID prepending went wrong."); - aw_len : assert final(mst_aw_chans_o[0].len === slv_aw_chans_i[0].len) + aw_len : assert final(mgr_aw_chans_o[0].len === sbr_aw_chans_i[0].len) else $fatal (1, "Something with the AW channel ID prepending went wrong."); - aw_size : assert final(mst_aw_chans_o[0].size === slv_aw_chans_i[0].size) + aw_size : assert final(mgr_aw_chans_o[0].size === sbr_aw_chans_i[0].size) else $fatal (1, "Something with the AW channel ID prepending went wrong."); - aw_qos : assert final(mst_aw_chans_o[0].qos === slv_aw_chans_i[0].qos) + aw_qos : assert final(mgr_aw_chans_o[0].qos === sbr_aw_chans_i[0].qos) else $fatal (1, "Something with the AW channel ID prepending went wrong."); b_id : assert final( - mst_b_chans_i[0].id[$bits(slv_b_chans_o[0].id)-1:0] === slv_b_chans_o[0].id) + mgr_b_chans_i[0].id[$bits(sbr_b_chans_o[0].id)-1:0] === sbr_b_chans_o[0].id) else $fatal (1, "Something with the B channel ID stripping went wrong."); - b_resp : assert final(mst_b_chans_i[0].resp === slv_b_chans_o[0].resp) + b_resp : assert final(mgr_b_chans_i[0].resp === sbr_b_chans_o[0].resp) else $fatal (1, "Something with the B channel ID stripping went wrong."); ar_id : assert final( - mst_ar_chans_o[0].id[$bits(slv_ar_chans_i[0].id)-1:0] === slv_ar_chans_i[0].id) + mgr_ar_chans_o[0].id[$bits(sbr_ar_chans_i[0].id)-1:0] === sbr_ar_chans_i[0].id) else $fatal (1, "Something with the AR channel ID prepending went wrong."); - ar_addr : assert final(mst_ar_chans_o[0].addr === slv_ar_chans_i[0].addr) + ar_addr : assert final(mgr_ar_chans_o[0].addr === sbr_ar_chans_i[0].addr) else $fatal (1, "Something with the AR channel ID prepending went wrong."); - ar_len : assert final(mst_ar_chans_o[0].len === slv_ar_chans_i[0].len) + ar_len : assert final(mgr_ar_chans_o[0].len === sbr_ar_chans_i[0].len) else $fatal (1, "Something with the AR channel ID prepending went wrong."); - ar_size : assert final(mst_ar_chans_o[0].size === slv_ar_chans_i[0].size) + ar_size : assert final(mgr_ar_chans_o[0].size === sbr_ar_chans_i[0].size) else $fatal (1, "Something with the AR channel ID prepending went wrong."); - ar_qos : assert final(mst_ar_chans_o[0].qos === slv_ar_chans_i[0].qos) + ar_qos : assert final(mgr_ar_chans_o[0].qos === sbr_ar_chans_i[0].qos) else $fatal (1, "Something with the AR channel ID prepending went wrong."); - r_id : assert final(mst_r_chans_i[0].id[$bits(slv_r_chans_o[0].id)-1:0] === slv_r_chans_o[0].id) + r_id : assert final(mgr_r_chans_i[0].id[$bits(sbr_r_chans_o[0].id)-1:0] === sbr_r_chans_o[0].id) else $fatal (1, "Something with the R channel ID stripping went wrong."); - r_data : assert final(mst_r_chans_i[0].data === slv_r_chans_o[0].data) + r_data : assert final(mgr_r_chans_i[0].data === sbr_r_chans_o[0].data) else $fatal (1, "Something with the R channel ID stripping went wrong."); - r_resp : assert final(mst_r_chans_i[0].resp === slv_r_chans_o[0].resp) + r_resp : assert final(mgr_r_chans_i[0].resp === sbr_r_chans_o[0].resp) else $fatal (1, "Something with the R channel ID stripping went wrong."); `endif // pragma translate_on diff --git a/src/axi_id_remap.sv b/src/axi_id_remap.sv index 9db5ea042..9f3ae6190 100644 --- a/src/axi_id_remap.sv +++ b/src/axi_id_remap.sv @@ -16,121 +16,121 @@ `include "common_cells/registers.svh" -/// Remap AXI IDs from wide IDs at the slave port to narrower IDs at the master port. +/// Remap AXI IDs from wide IDs at the subordinate port to narrower IDs at the manager port. /// /// This module is designed to remap an overly wide, sparsely used ID space to a narrower, densely -/// used ID space. This scenario occurs, for example, when an AXI master has wide ID ports but +/// used ID space. This scenario occurs, for example, when an AXI manager has wide ID ports but /// effectively only uses a (not necessarily contiguous) subset of IDs. /// /// This module retains the independence of IDs. That is, if two transactions have different IDs at -/// the slave port of this module, they are guaranteed to have different IDs at the master port of -/// this module. This implies a lower bound on the [width of IDs on the master -/// port](#parameter.MstPortIdWidth). If you require narrower master port IDs and can forgo ID +/// the subordinate port of this module, they are guaranteed to have different IDs at the manager port of +/// this module. This implies a lower bound on the [width of IDs on the manager +/// port](#parameter.MgrPortIdWidth). If you require narrower manager port IDs and can forgo ID /// independence, use [`axi_id_serialize`](module.axi_id_serialize) instead. /// /// Internally, a [table is used for remapping IDs](module.axi_id_remap_table). module axi_id_remap #( - /// ID width of the AXI4+ATOP slave port. - parameter int unsigned SlvPortIdWidth = 32'd0, - /// Maximum number of different IDs that can be in flight at the slave port. Reads and writes are + /// ID width of the AXI4+ATOP subordinate port. + parameter int unsigned SbrPortIdWidth = 32'd0, + /// Maximum number of different IDs that can be in flight at the subordinate port. Reads and writes are /// counted separately (except for ATOPs, which count as both read and write). /// /// It is legal for upstream to have transactions with more unique IDs than the maximum given by /// this parameter in flight, but a transaction exceeding the maximum will be stalled until all /// transactions of another ID complete. /// - /// The maximum value of this parameter is `2**SlvPortIdWidth`. - parameter int unsigned SlvPortMaxUniqIds = 32'd0, + /// The maximum value of this parameter is `2**SbrPortIdWidth`. + parameter int unsigned SbrPortMaxUniqIds = 32'd0, /// Maximum number of in-flight transactions with the same ID. /// /// It is legal for upstream to have more transactions than the maximum given by this parameter in /// flight for any ID, but a transaction exceeding the maximum will be stalled until another /// transaction with the same ID completes. parameter int unsigned MaxTxnsPerId = 32'd0, - /// ID width of the AXI4+ATOP master port. + /// ID width of the AXI4+ATOP manager port. /// - /// The minimum value of this parameter is the ceiled binary logarithm of `SlvPortMaxUniqIds`, - /// because IDs at the master port must be wide enough to represent IDs up to - /// `SlvPortMaxUniqIds-1`. + /// The minimum value of this parameter is the ceiled binary logarithm of `SbrPortMaxUniqIds`, + /// because IDs at the manager port must be wide enough to represent IDs up to + /// `SbrPortMaxUniqIds-1`. /// - /// If master IDs are wider than the minimum, they are extended by prepending zeros. - parameter int unsigned MstPortIdWidth = 32'd0, - /// Request struct type of the AXI4+ATOP slave port. + /// If manager IDs are wider than the minimum, they are extended by prepending zeros. + parameter int unsigned MgrPortIdWidth = 32'd0, + /// Request struct type of the AXI4+ATOP subordinate port. /// - /// The width of all IDs in this struct must match `SlvPortIdWidth`. - parameter type slv_port_axi_req_t = logic, - /// Response struct type of the AXI4+ATOP slave port. + /// The width of all IDs in this struct must match `SbrPortIdWidth`. + parameter type sbr_port_axi_req_t = logic, + /// Response struct type of the AXI4+ATOP subordinate port. /// - /// The width of all IDs in this struct must match `SlvPortIdWidth`. - parameter type slv_port_axi_rsp_t = logic, - /// Request struct type of the AXI4+ATOP master port + /// The width of all IDs in this struct must match `SbrPortIdWidth`. + parameter type sbr_port_axi_rsp_t = logic, + /// Request struct type of the AXI4+ATOP manager port /// - /// The width of all IDs in this struct must match `MstPortIdWidth`. - parameter type mst_port_axi_req_t = logic, - /// Response struct type of the AXI4+ATOP master port + /// The width of all IDs in this struct must match `MgrPortIdWidth`. + parameter type mgr_port_axi_req_t = logic, + /// Response struct type of the AXI4+ATOP manager port /// - /// The width of all IDs in this struct must match `MstPortIdWidth`. - parameter type mst_port_axi_rsp_t = logic + /// The width of all IDs in this struct must match `MgrPortIdWidth`. + parameter type mgr_port_axi_rsp_t = logic ) ( /// Rising-edge clock of all ports input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Slave port request - input slv_port_axi_req_t slv_req_i, - /// Slave port response - output slv_port_axi_rsp_t slv_rsp_o, - /// Master port request - output mst_port_axi_req_t mst_req_o, - /// Master port response - input mst_port_axi_rsp_t mst_rsp_i + /// Subordinate port request + input sbr_port_axi_req_t sbr_req_i, + /// Subordinate port response + output sbr_port_axi_rsp_t sbr_rsp_o, + /// Manager port request + output mgr_port_axi_req_t mgr_req_o, + /// Manager port response + input mgr_port_axi_rsp_t mgr_rsp_i ); // Feed all signals that are not ID or flow control of AW and AR through. - assign mst_req_o.aw.addr = slv_req_i.aw.addr; - assign mst_req_o.aw.len = slv_req_i.aw.len; - assign mst_req_o.aw.size = slv_req_i.aw.size; - assign mst_req_o.aw.burst = slv_req_i.aw.burst; - assign mst_req_o.aw.lock = slv_req_i.aw.lock; - assign mst_req_o.aw.cache = slv_req_i.aw.cache; - assign mst_req_o.aw.prot = slv_req_i.aw.prot; - assign mst_req_o.aw.qos = slv_req_i.aw.qos; - assign mst_req_o.aw.region = slv_req_i.aw.region; - assign mst_req_o.aw.atop = slv_req_i.aw.atop; - assign mst_req_o.aw.user = slv_req_i.aw.user; - - assign mst_req_o.w = slv_req_i.w; - assign mst_req_o.w_valid = slv_req_i.w_valid; - assign slv_rsp_o.w_ready = mst_rsp_i.w_ready; - - assign slv_rsp_o.b.resp = mst_rsp_i.b.resp; - assign slv_rsp_o.b.user = mst_rsp_i.b.user; - assign slv_rsp_o.b_valid = mst_rsp_i.b_valid; - assign mst_req_o.b_ready = slv_req_i.b_ready; - - assign mst_req_o.ar.addr = slv_req_i.ar.addr; - assign mst_req_o.ar.len = slv_req_i.ar.len; - assign mst_req_o.ar.size = slv_req_i.ar.size; - assign mst_req_o.ar.burst = slv_req_i.ar.burst; - assign mst_req_o.ar.lock = slv_req_i.ar.lock; - assign mst_req_o.ar.cache = slv_req_i.ar.cache; - assign mst_req_o.ar.prot = slv_req_i.ar.prot; - assign mst_req_o.ar.qos = slv_req_i.ar.qos; - assign mst_req_o.ar.region = slv_req_i.ar.region; - assign mst_req_o.ar.user = slv_req_i.ar.user; - - assign slv_rsp_o.r.data = mst_rsp_i.r.data; - assign slv_rsp_o.r.resp = mst_rsp_i.r.resp; - assign slv_rsp_o.r.last = mst_rsp_i.r.last; - assign slv_rsp_o.r.user = mst_rsp_i.r.user; - assign slv_rsp_o.r_valid = mst_rsp_i.r_valid; - assign mst_req_o.r_ready = slv_req_i.r_ready; + assign mgr_req_o.aw.addr = sbr_req_i.aw.addr; + assign mgr_req_o.aw.len = sbr_req_i.aw.len; + assign mgr_req_o.aw.size = sbr_req_i.aw.size; + assign mgr_req_o.aw.burst = sbr_req_i.aw.burst; + assign mgr_req_o.aw.lock = sbr_req_i.aw.lock; + assign mgr_req_o.aw.cache = sbr_req_i.aw.cache; + assign mgr_req_o.aw.prot = sbr_req_i.aw.prot; + assign mgr_req_o.aw.qos = sbr_req_i.aw.qos; + assign mgr_req_o.aw.region = sbr_req_i.aw.region; + assign mgr_req_o.aw.atop = sbr_req_i.aw.atop; + assign mgr_req_o.aw.user = sbr_req_i.aw.user; + + assign mgr_req_o.w = sbr_req_i.w; + assign mgr_req_o.w_valid = sbr_req_i.w_valid; + assign sbr_rsp_o.w_ready = mgr_resp_i.w_ready; + + assign sbr_rsp_o.b.resp = mgr_rsp_i.b.resp; + assign sbr_rsp_o.b.user = mgr_rsp_i.b.user; + assign sbr_rsp_o.b_valid = mgr_rsp_i.b_valid; + assign mgr_req_o.b_ready = sbr_req_i.b_ready; + + assign mgr_req_o.ar.addr = sbr_req_i.ar.addr; + assign mgr_req_o.ar.len = sbr_req_i.ar.len; + assign mgr_req_o.ar.size = sbr_req_i.ar.size; + assign mgr_req_o.ar.burst = sbr_req_i.ar.burst; + assign mgr_req_o.ar.lock = sbr_req_i.ar.lock; + assign mgr_req_o.ar.cache = sbr_req_i.ar.cache; + assign mgr_req_o.ar.prot = sbr_req_i.ar.prot; + assign mgr_req_o.ar.qos = sbr_req_i.ar.qos; + assign mgr_req_o.ar.region = sbr_req_i.ar.region; + assign mgr_req_o.ar.user = sbr_req_i.ar.user; + + assign sbr_rsp_o.r.data = mgr_rsp_i.r.data; + assign sbr_rsp_o.r.resp = mgr_rsp_i.r.resp; + assign sbr_rsp_o.r.last = mgr_rsp_i.r.last; + assign sbr_rsp_o.r.user = mgr_rsp_i.r.user; + assign sbr_rsp_o.r_valid = mgr_rsp_i.r_valid; + assign mgr_req_o.r_ready = sbr_req_i.r_ready; // Remap tables keep track of in-flight bursts and their input and output IDs. - localparam int unsigned IdxWidth = cf_math_pkg::idx_width(SlvPortMaxUniqIds); - typedef logic [SlvPortMaxUniqIds-1:0] field_t; - typedef logic [SlvPortIdWidth-1:0] id_inp_t; + localparam int unsigned IdxWidth = cf_math_pkg::idx_width(SbrPortMaxUniqIds); + typedef logic [SbrPortMaxUniqIds-1:0] field_t; + typedef logic [SbrPortIdWidth-1:0] id_inp_t; typedef logic [IdxWidth-1:0] idx_t; field_t wr_free, rd_free, both_free; id_inp_t rd_push_inp_id; @@ -143,8 +143,8 @@ module axi_id_remap #( wr_push, rd_push; axi_id_remap_table #( - .InpIdWidth ( SlvPortIdWidth ), - .MaxUniqInpIds ( SlvPortMaxUniqIds ), + .InpIdWidth ( SbrPortIdWidth ), + .MaxUniqInpIds ( SbrPortMaxUniqIds ), .MaxTxnsPerId ( MaxTxnsPerId ) ) i_wr_table ( .clk_i, @@ -153,19 +153,19 @@ module axi_id_remap #( .free_oup_id_o ( wr_free_oup_id ), .full_o ( wr_full ), .push_i ( wr_push ), - .push_inp_id_i ( slv_req_i.aw.id ), + .push_inp_id_i ( sbr_req_i.aw.id ), .push_oup_id_i ( wr_push_oup_id ), - .exists_inp_id_i ( slv_req_i.aw.id ), + .exists_inp_id_i ( sbr_req_i.aw.id ), .exists_o ( wr_exists ), .exists_oup_id_o ( wr_exists_id ), .exists_full_o ( wr_exists_full ), - .pop_i ( slv_rsp_o.b_valid && slv_req_i.b_ready ), - .pop_oup_id_i ( mst_rsp_i.b.id[IdxWidth-1:0] ), - .pop_inp_id_o ( slv_rsp_o.b.id ) + .pop_i ( sbr_rsp_o.b_valid && sbr_req_i.b_ready ), + .pop_oup_id_i ( mgr_rsp_i.b.id[IdxWidth-1:0] ), + .pop_inp_id_o ( sbr_rsp_o.b.id ) ); axi_id_remap_table #( - .InpIdWidth ( SlvPortIdWidth ), - .MaxUniqInpIds ( SlvPortMaxUniqIds ), + .InpIdWidth ( SbrPortIdWidth ), + .MaxUniqInpIds ( SbrPortMaxUniqIds ), .MaxTxnsPerId ( MaxTxnsPerId ) ) i_rd_table ( .clk_i, @@ -176,17 +176,17 @@ module axi_id_remap #( .push_i ( rd_push ), .push_inp_id_i ( rd_push_inp_id ), .push_oup_id_i ( rd_push_oup_id ), - .exists_inp_id_i ( slv_req_i.ar.id ), + .exists_inp_id_i ( sbr_req_i.ar.id ), .exists_o ( rd_exists ), .exists_oup_id_o ( rd_exists_id ), .exists_full_o ( rd_exists_full ), - .pop_i ( slv_rsp_o.r_valid && slv_req_i.r_ready && slv_rsp_o.r.last ), - .pop_oup_id_i ( mst_rsp_i.r.id[IdxWidth-1:0] ), - .pop_inp_id_o ( slv_rsp_o.r.id ) + .pop_i ( sbr_rsp_o.r_valid && sbr_req_i.r_ready && sbr_rsp_o.r.last ), + .pop_oup_id_i ( mgr_rsp_i.r.id[IdxWidth-1:0] ), + .pop_inp_id_o ( sbr_rsp_o.r.id ) ); assign both_free = wr_free & rd_free; lzc #( - .WIDTH ( SlvPortMaxUniqIds ), + .WIDTH ( SbrPortMaxUniqIds ), .MODE ( 1'b0 ) ) i_lzc ( .in_i ( both_free ), @@ -195,9 +195,9 @@ module axi_id_remap #( ); // Zero-extend output IDs if the output IDs is are wider than the IDs from the tables. - localparam ZeroWidth = MstPortIdWidth - IdxWidth; - assign mst_req_o.ar.id = {{ZeroWidth{1'b0}}, rd_push_oup_id}; - assign mst_req_o.aw.id = {{ZeroWidth{1'b0}}, wr_push_oup_id}; + localparam ZeroWidth = MgrPortIdWidth - IdxWidth; + assign mgr_req_o.ar.id = {{ZeroWidth{1'b0}}, rd_push_oup_id}; + assign mgr_req_o.aw.id = {{ZeroWidth{1'b0}}, wr_push_oup_id}; // Handle requests. enum logic [1:0] {Ready, HoldAR, HoldAW, HoldAx} state_d, state_q; @@ -205,12 +205,12 @@ module axi_id_remap #( aw_id_d, aw_id_q; logic ar_prio_d, ar_prio_q; always_comb begin - mst_req_o.aw_valid = 1'b0; - slv_rsp_o.aw_ready = 1'b0; + mgr_req_o.aw_valid = 1'b0; + sbr_rsp_o.aw_ready = 1'b0; wr_push = 1'b0; wr_push_oup_id = '0; - mst_req_o.ar_valid = 1'b0; - slv_rsp_o.ar_ready = 1'b0; + mgr_req_o.ar_valid = 1'b0; + sbr_rsp_o.ar_ready = 1'b0; rd_push = 1'b0; rd_push_inp_id = '0; rd_push_oup_id = '0; @@ -222,48 +222,48 @@ module axi_id_remap #( unique case (state_q) Ready: begin // Reads - if (slv_req_i.ar_valid) begin + if (sbr_req_i.ar_valid) begin // If a burst with the same input ID is already in flight or there are free output IDs: if ((rd_exists && !rd_exists_full) || (!rd_exists && !rd_full)) begin // Determine the output ID: if another in-flight burst had the same input ID, we must // reuse its output ID to maintain ordering; else, we assign the next free ID. - rd_push_inp_id = slv_req_i.ar.id; + rd_push_inp_id = sbr_req_i.ar.id; rd_push_oup_id = rd_exists ? rd_exists_id : rd_free_oup_id; // Forward the AR and push a new entry to the read table. - mst_req_o.ar_valid = 1'b1; + mgr_req_o.ar_valid = 1'b1; rd_push = 1'b1; end end // Writes - if (slv_req_i.aw_valid) begin + if (sbr_req_i.aw_valid) begin // If this is not an ATOP that gives rise to an R response, we can handle it in isolation // on the write direction. - if (!slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin + if (!sbr_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // If a burst with the same input ID is already in flight or there are free output IDs: if ((wr_exists && !wr_exists_full) || (!wr_exists && !wr_full)) begin // Determine the output ID: if another in-flight burst had the same input ID, we must // reuse its output ID to maintain ordering; else, we assign the next free ID. wr_push_oup_id = wr_exists ? wr_exists_id : wr_free_oup_id; // Forward the AW and push a new entry to the write table. - mst_req_o.aw_valid = 1'b1; + mgr_req_o.aw_valid = 1'b1; wr_push = 1'b1; end // If this is an ATOP that gives rise to an R response, we must remap to an ID that is // free on both read and write direction and push also to the read table. // Only allowed if AR does not have arbitration priority - end else if (!(ar_prio_q && mst_req_o.ar_valid)) begin + end else if (!(ar_prio_q && mgr_req_o.ar_valid)) begin // Nullify a potential AR at our output. This is legal in this state. - mst_req_o.ar_valid = 1'b0; - slv_rsp_o.ar_ready = 1'b0; + mgr_req_o.ar_valid = 1'b0; + sbr_rsp_o.ar_ready = 1'b0; rd_push = 1'b0; if ((|both_free)) begin // Use an output ID that is free in both directions. wr_push_oup_id = both_free_oup_id; - rd_push_inp_id = slv_req_i.aw.id; + rd_push_inp_id = sbr_req_i.aw.id; rd_push_oup_id = both_free_oup_id; // Forward the AW and push a new entry to both tables. - mst_req_o.aw_valid = 1'b1; + mgr_req_o.aw_valid = 1'b1; rd_push = 1'b1; wr_push = 1'b1; // Give AR priority in the next cycle (so ATOPs cannot infinitely preempt ARs). @@ -273,69 +273,69 @@ module axi_id_remap #( end // Hold AR, AW, or both if they are valid but not yet ready. - if (mst_req_o.ar_valid) begin - slv_rsp_o.ar_ready = mst_rsp_i.ar_ready; - if (!mst_rsp_i.ar_ready) begin + if (mgr_req_o.ar_valid) begin + sbr_rsp_o.ar_ready = mgr_rsp_i.ar_ready; + if (!mgr_rsp_i.ar_ready) begin ar_id_d = rd_push_oup_id; end end - if (mst_req_o.aw_valid) begin - slv_rsp_o.aw_ready = mst_rsp_i.aw_ready; - if (!mst_rsp_i.aw_ready) begin + if (mgr_req_o.aw_valid) begin + sbr_resp_o.aw_ready = mgr_rsp_i.aw_ready; + if (!mgr_rsp_i.aw_ready) begin aw_id_d = wr_push_oup_id; end end - if ({mst_req_o.ar_valid, mst_rsp_i.ar_ready, - mst_req_o.aw_valid, mst_rsp_i.aw_ready} == 4'b1010) begin + if ({mgr_req_o.ar_valid, mgr_rsp_i.ar_ready, + mgr_req_o.aw_valid, mgr_rsp_i.aw_ready} == 4'b1010) begin state_d = HoldAx; - end else if ({mst_req_o.ar_valid, mst_rsp_i.ar_ready} == 2'b10) begin + end else if ({mgr_req_o.ar_valid, mgr_rsp_i.ar_ready} == 2'b10) begin state_d = HoldAR; - end else if ({mst_req_o.aw_valid, mst_rsp_i.aw_ready} == 2'b10) begin + end else if ({mgr_req_o.aw_valid, mgr_rsp_i.aw_ready} == 2'b10) begin state_d = HoldAW; end else begin state_d = Ready; end - if (mst_req_o.ar_valid && mst_rsp_i.ar_ready) begin + if (mgr_req_o.ar_valid && mgr_rsp_i.ar_ready) begin ar_prio_d = 1'b0; // Reset AR priority, because handshake was successful in this cycle. end end HoldAR: begin - // Drive `mst_req_o.ar.id` through `rd_push_oup_id`. + // Drive `mgr_req_o.ar.id` through `rd_push_oup_id`. rd_push_oup_id = ar_id_q; - mst_req_o.ar_valid = 1'b1; - slv_rsp_o.ar_ready = mst_rsp_i.ar_ready; - if (mst_rsp_i.ar_ready) begin + mgr_req_o.ar_valid = 1'b1; + sbr_rsp_o.ar_ready = mgr_rsp_i.ar_ready; + if (mgr_rsp_i.ar_ready) begin state_d = Ready; ar_prio_d = 1'b0; // Reset AR priority, because handshake was successful in this cycle. end end HoldAW: begin - // Drive mst_req_o.aw.id through `wr_push_oup_id`. + // Drive mgr_req_o.aw.id through `wr_push_oup_id`. wr_push_oup_id = aw_id_q; - mst_req_o.aw_valid = 1'b1; - slv_rsp_o.aw_ready = mst_rsp_i.aw_ready; - if (mst_rsp_i.aw_ready) begin + mgr_req_o.aw_valid = 1'b1; + sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready; + if (mgr_rsp_i.aw_ready) begin state_d = Ready; end end HoldAx: begin rd_push_oup_id = ar_id_q; - mst_req_o.ar_valid = 1'b1; - slv_rsp_o.ar_ready = mst_rsp_i.ar_ready; + mgr_req_o.ar_valid = 1'b1; + sbr_rsp_o.ar_ready = mgr_rsp_i.ar_ready; wr_push_oup_id = aw_id_q; - mst_req_o.aw_valid = 1'b1; - slv_rsp_o.aw_ready = mst_rsp_i.aw_ready; - unique case ({mst_rsp_i.ar_ready, mst_rsp_i.aw_ready}) + mgr_req_o.aw_valid = 1'b1; + sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready; + unique case ({mgr_rsp_i.ar_ready, mgr_rsp_i.aw_ready}) 2'b01: state_d = HoldAR; 2'b10: state_d = HoldAW; 2'b11: state_d = Ready; default: /*do nothing / stay in this state*/; endcase - if (mst_rsp_i.ar_ready) begin + if (mgr_rsp_i.ar_ready) begin ar_prio_d = 1'b0; // Reset AR priority, because handshake was successful in this cycle. end end @@ -353,50 +353,50 @@ module axi_id_remap #( // pragma translate_off `ifndef VERILATOR initial begin : p_assert - assert(SlvPortIdWidth > 32'd0) - else $fatal(1, "Parameter SlvPortIdWidth has to be larger than 0!"); - assert(MstPortIdWidth >= IdxWidth) - else $fatal(1, "Parameter MstPortIdWidth has to be at least IdxWidth!"); - assert (SlvPortMaxUniqIds > 0) - else $fatal(1, "Parameter SlvPortMaxUniqIds has to be larger than 0!"); - assert (SlvPortMaxUniqIds <= 2**SlvPortIdWidth) - else $fatal(1, "Parameter SlvPortMaxUniqIds may be at most 2**SlvPortIdWidth!"); + assert(SbrPortIdWidth > 32'd0) + else $fatal(1, "Parameter SbrPortIdWidth has to be larger than 0!"); + assert(MgrPortIdWidth >= IdxWidth) + else $fatal(1, "Parameter MgrPortIdWidth has to be at least IdxWidth!"); + assert (SbrPortMaxUniqIds > 0) + else $fatal(1, "Parameter SbrPortMaxUniqIds has to be larger than 0!"); + assert (SbrPortMaxUniqIds <= 2**SbrPortIdWidth) + else $fatal(1, "Parameter SbrPortMaxUniqIds may be at most 2**SbrPortIdWidth!"); assert (MaxTxnsPerId > 0) else $fatal(1, "Parameter MaxTxnsPerId has to be larger than 0!"); - assert($bits(slv_req_i.aw.addr) == $bits(mst_req_o.aw.addr)) + assert($bits(sbr_req_i.aw.addr) == $bits(mgr_req_o.aw.addr)) else $fatal(1, "AXI AW address widths are not equal!"); - assert($bits(slv_req_i.w.data) == $bits(mst_req_o.w.data)) + assert($bits(sbr_req_i.w.data) == $bits(mgr_req_o.w.data)) else $fatal(1, "AXI W data widths are not equal!"); - assert($bits(slv_req_i.w.user) == $bits(mst_req_o.w.user)) + assert($bits(sbr_req_i.w.user) == $bits(mgr_req_o.w.user)) else $fatal(1, "AXI W user widths are not equal!"); - assert($bits(slv_req_i.ar.addr) == $bits(mst_req_o.ar.addr)) + assert($bits(sbr_req_i.ar.addr) == $bits(mgr_req_o.ar.addr)) else $fatal(1, "AXI AR address widths are not equal!"); - assert($bits(slv_rsp_o.r.data) == $bits(mst_rsp_i.r.data)) + assert($bits(sbr_resp_o.r.data) == $bits(mgr_resp_i.r.data)) else $fatal(1, "AXI R data widths are not equal!"); - assert ($bits(slv_req_i.aw.id) == SlvPortIdWidth); - assert ($bits(slv_rsp_o.b.id) == SlvPortIdWidth); - assert ($bits(slv_req_i.ar.id) == SlvPortIdWidth); - assert ($bits(slv_rsp_o.r.id) == SlvPortIdWidth); - assert ($bits(mst_req_o.aw.id) == MstPortIdWidth); - assert ($bits(mst_rsp_i.b.id) == MstPortIdWidth); - assert ($bits(mst_req_o.ar.id) == MstPortIdWidth); - assert ($bits(mst_rsp_i.r.id) == MstPortIdWidth); + assert ($bits(sbr_req_i.aw.id) == SbrPortIdWidth); + assert ($bits(sbr_rsp_o.b.id) == SbrPortIdWidth); + assert ($bits(sbr_req_i.ar.id) == SbrPortIdWidth); + assert ($bits(sbr_rsp_o.r.id) == SbrPortIdWidth); + assert ($bits(mgr_req_o.aw.id) == MgrPortIdWidth); + assert ($bits(mgr_rsp_i.b.id) == MgrPortIdWidth); + assert ($bits(mgr_req_o.ar.id) == MgrPortIdWidth); + assert ($bits(mgr_rsp_i.r.id) == MgrPortIdWidth); end default disable iff (!rst_ni); - assert property (@(posedge clk_i) slv_req_i.aw_valid && slv_rsp_o.aw_ready - |-> mst_req_o.aw_valid && mst_rsp_i.aw_ready); - assert property (@(posedge clk_i) mst_rsp_i.b_valid && mst_req_o.b_ready - |-> slv_rsp_o.b_valid && slv_req_i.b_ready); - assert property (@(posedge clk_i) slv_req_i.ar_valid && slv_rsp_o.ar_ready - |-> mst_req_o.ar_valid && mst_rsp_i.ar_ready); - assert property (@(posedge clk_i) mst_rsp_i.r_valid && mst_req_o.r_ready - |-> slv_rsp_o.r_valid && slv_req_i.r_ready); - assert property (@(posedge clk_i) slv_rsp_o.r_valid - |-> slv_rsp_o.r.last == mst_rsp_i.r.last); - assert property (@(posedge clk_i) mst_req_o.ar_valid && !mst_rsp_i.ar_ready - |=> mst_req_o.ar_valid && $stable(mst_req_o.ar.id)); - assert property (@(posedge clk_i) mst_req_o.aw_valid && !mst_rsp_i.aw_ready - |=> mst_req_o.aw_valid && $stable(mst_req_o.aw.id)); + assert property (@(posedge clk_i) sbr_req_i.aw_valid && sbr_rsp_o.aw_ready + |-> mgr_req_o.aw_valid && mgr_rsp_i.aw_ready); + assert property (@(posedge clk_i) mgr_rsp_i.b_valid && mgr_req_o.b_ready + |-> sbr_rsp_o.b_valid && sbr_req_i.b_ready); + assert property (@(posedge clk_i) sbr_req_i.ar_valid && sbr_rsp_o.ar_ready + |-> mgr_req_o.ar_valid && mgr_rsp_i.ar_ready); + assert property (@(posedge clk_i) mgr_rsp_i.r_valid && mgr_req_o.r_ready + |-> sbr_rsp_o.r_valid && sbr_req_i.r_ready); + assert property (@(posedge clk_i) sbr_rsp_o.r_valid + |-> sbr_rsp_o.r.last == mgr_rsp_i.r.last); + assert property (@(posedge clk_i) mgr_req_o.ar_valid && !mgr_rsp_i.ar_ready + |=> mgr_req_o.ar_valid && $stable(mgr_req_o.ar.id)); + assert property (@(posedge clk_i) mgr_req_o.aw_valid && !mgr_rsp_i.aw_ready + |=> mgr_req_o.aw_valid && $stable(mgr_req_o.aw.id)); `endif // pragma translate_on endmodule @@ -581,80 +581,80 @@ endmodule /// /// See the documentation of the main module for the definition of ports and parameters. module axi_id_remap_intf #( - parameter int unsigned AXI_SLV_PORT_ID_WIDTH = 32'd0, - parameter int unsigned AXI_SLV_PORT_MAX_UNIQ_IDS = 32'd0, + parameter int unsigned AXI_SBR_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_SBR_PORT_MAX_UNIQ_IDS = 32'd0, parameter int unsigned AXI_MAX_TXNS_PER_ID = 32'd0, - parameter int unsigned AXI_MST_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_MGR_PORT_ID_WIDTH = 32'd0, parameter int unsigned AXI_ADDR_WIDTH = 32'd0, parameter int unsigned AXI_DATA_WIDTH = 32'd0, parameter int unsigned AXI_USER_WIDTH = 32'd0 ) ( input logic clk_i, input logic rst_ni, - AXI_BUS.Slave slv, - AXI_BUS.Master mst + AXI_BUS.Subordinate sbr, + AXI_BUS.Manager mgr ); - typedef logic [AXI_SLV_PORT_ID_WIDTH-1:0] slv_id_t; - typedef logic [AXI_MST_PORT_ID_WIDTH-1:0] mst_id_t; + typedef logic [AXI_SBR_PORT_ID_WIDTH-1:0] sbr_id_t; + typedef logic [AXI_MGR_PORT_ID_WIDTH-1:0] mgr_id_t; typedef logic [AXI_ADDR_WIDTH-1:0] axi_addr_t; typedef logic [AXI_DATA_WIDTH-1:0] axi_data_t; typedef logic [AXI_DATA_WIDTH/8-1:0] axi_strb_t; typedef logic [AXI_USER_WIDTH-1:0] axi_user_t; - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, axi_addr_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_chan_t, slv_r_chan_t) - - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, axi_addr_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, axi_addr_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, axi_data_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_chan_t, mst_w_chan_t, mst_ar_chan_t) - `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_chan_t, mst_r_chan_t) - - slv_port_axi_req_t slv_req; - slv_port_axi_rsp_t slv_rsp; - mst_port_axi_req_t mst_req; - mst_port_axi_rsp_t mst_rsp; - - `AXI_ASSIGN_TO_REQ(slv_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, slv_rsp) - `AXI_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, mst) + `AXI_TYPEDEF_AW_CHAN_T(sbr_aw_chan_t, axi_addr_t, sbr_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(sbr_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(sbr_b_chan_t, sbr_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(sbr_ar_chan_t, axi_addr_t, sbr_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(sbr_r_chan_t, axi_data_t, sbr_id_t, axi_user_t) + `AXI_TYPEDEF_REQ_T(sbr_port_axi_req_t, sbr_aw_chan_t, sbr_w_chan_t, sbr_ar_chan_t) + `AXI_TYPEDEF_RSP_T(sbr_port_axi_rsp_t, sbr_b_chan_t, sbr_r_chan_t) + + `AXI_TYPEDEF_AW_CHAN_T(mgr_aw_chan_t, axi_addr_t, mgr_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(mgr_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(mgr_b_chan_t, mgr_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mgr_ar_chan_t, axi_addr_t, mgr_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(mgr_r_chan_t, axi_data_t, mgr_id_t, axi_user_t) + `AXI_TYPEDEF_REQ_T(mgr_port_axi_req_t, mgr_aw_chan_t, mgr_w_chan_t, mgr_ar_chan_t) + `AXI_TYPEDEF_RSP_T(mgr_port_axi_rsp_t, mgr_b_chan_t, mgr_r_chan_t) + + sbr_port_axi_req_t sbr_req; + sbr_port_axi_rsp_t sbr_rsp; + mgr_port_axi_req_t mgr_req; + mgr_port_axi_rsp_t mgr_rsp; + + `AXI_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, sbr_rsp) + `AXI_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_id_remap #( - .SlvPortIdWidth ( AXI_SLV_PORT_ID_WIDTH ), - .SlvPortMaxUniqIds ( AXI_SLV_PORT_MAX_UNIQ_IDS ), + .SbrPortIdWidth ( AXI_SBR_PORT_ID_WIDTH ), + .SbrPortMaxUniqIds ( AXI_SBR_PORT_MAX_UNIQ_IDS ), .MaxTxnsPerId ( AXI_MAX_TXNS_PER_ID ), - .MstPortIdWidth ( AXI_MST_PORT_ID_WIDTH ), - .slv_port_axi_req_t ( slv_port_axi_req_t ), - .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), - .mst_port_axi_req_t ( mst_port_axi_req_t ), - .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ) + .MgrPortIdWidth ( AXI_MGR_PORT_ID_WIDTH ), + .sbr_port_axi_req_t ( sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t ( sbr_port_axi_rsp_t ), + .mgr_port_axi_req_t ( mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t ( mgr_port_axi_rsp_t ) ) i_axi_id_remap ( .clk_i, .rst_ni, - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); // pragma translate_off `ifndef VERILATOR initial begin - assert (slv.AXI_ID_WIDTH == AXI_SLV_PORT_ID_WIDTH); - assert (slv.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); - assert (slv.AXI_DATA_WIDTH == AXI_DATA_WIDTH); - assert (slv.AXI_USER_WIDTH == AXI_USER_WIDTH); - assert (mst.AXI_ID_WIDTH == AXI_MST_PORT_ID_WIDTH); - assert (mst.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); - assert (mst.AXI_DATA_WIDTH == AXI_DATA_WIDTH); - assert (mst.AXI_USER_WIDTH == AXI_USER_WIDTH); + assert (sbr.AXI_ID_WIDTH == AXI_SBR_PORT_ID_WIDTH); + assert (sbr.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (sbr.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (sbr.AXI_USER_WIDTH == AXI_USER_WIDTH); + assert (mgr.AXI_ID_WIDTH == AXI_MGR_PORT_ID_WIDTH); + assert (mgr.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (mgr.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (mgr.AXI_USER_WIDTH == AXI_USER_WIDTH); end `endif // pragma translate_on diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv index f982b4f60..856580208 100644 --- a/src/axi_id_serialize.sv +++ b/src/axi_id_serialize.sv @@ -18,28 +18,28 @@ /// Reduce AXI IDs by serializing transactions when necessary. /// /// This module is designed to remap a wide ID space to an arbitrarily narrow ID space. If -/// necessary, this module maps two different IDs at its slave port to the same ID at its master +/// necessary, this module maps two different IDs at its subordinate port to the same ID at its manager /// port, thereby constraining the order of those transactions and in this sense *serializing* them. -/// If the independence of IDs needs to be retained at the cost of a wider ID space at the master +/// If the independence of IDs needs to be retained at the cost of a wider ID space at the manager /// port, use [`axi_id_remap`](module.axi_id_remap) instead. /// -/// This module contains one [`axi_serializer`](module.axi_serializer) per master port ID (given by -/// the `MstPortMaxUniqIds parameter`). +/// This module contains one [`axi_serializer`](module.axi_serializer) per manager port ID (given by +/// the `MgrPortMaxUniqIds parameter`). module axi_id_serialize #( - /// ID width of the AXI4+ATOP slave port - parameter int unsigned SlvPortIdWidth = 32'd0, - /// Maximum number of transactions that can be in flight at the slave port. Reads and writes are + /// ID width of the AXI4+ATOP subordinate port + parameter int unsigned SbrPortIdWidth = 32'd0, + /// Maximum number of transactions that can be in flight at the subordinate port. Reads and writes are /// counted separately (except for ATOPs, which count as both read and write). - parameter int unsigned SlvPortMaxTxns = 32'd0, - /// ID width of the AXI4+ATOP master port - parameter int unsigned MstPortIdWidth = 32'd0, - /// Maximum number of different IDs that can be in flight at the master port. Reads and writes + parameter int unsigned SbrPortMaxTxns = 32'd0, + /// ID width of the AXI4+ATOP manager port + parameter int unsigned MgrPortIdWidth = 32'd0, + /// Maximum number of different IDs that can be in flight at the manager port. Reads and writes /// are counted separately (except for ATOPs, which count as both read and write). /// - /// The maximum value of this parameter is `2**MstPortIdWidth`. - parameter int unsigned MstPortMaxUniqIds = 32'd0, - /// Maximum number of in-flight transactions with the same ID at the master port. - parameter int unsigned MstPortMaxTxnsPerId = 32'd0, + /// The maximum value of this parameter is `2**MgrPortIdWidth`. + parameter int unsigned MgrPortMaxUniqIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID at the manager port. + parameter int unsigned MgrPortMaxTxnsPerId = 32'd0, /// Address width of both AXI4+ATOP ports parameter int unsigned AddrWidth = 32'd0, /// Data width of both AXI4+ATOP ports @@ -48,45 +48,45 @@ module axi_id_serialize #( parameter int unsigned UserWidth = 32'd0, /// Enable support for AXI4+ATOP atomics parameter bit AtopSupport = 1'b1, - /// Request struct type of the AXI4+ATOP slave port - parameter type slv_port_axi_req_t = logic, - /// Response struct type of the AXI4+ATOP slave port - parameter type slv_port_axi_rsp_t = logic, - /// Request struct type of the AXI4+ATOP master port - parameter type mst_port_axi_req_t = logic, - /// Response struct type of the AXI4+ATOP master port - parameter type mst_port_axi_rsp_t = logic + /// Request struct type of the AXI4+ATOP subordinate port + parameter type sbr_port_axi_req_t = logic, + /// Response struct type of the AXI4+ATOP subordinate port + parameter type sbr_port_axi_rsp_t = logic, + /// Request struct type of the AXI4+ATOP manager port + parameter type mgr_port_axi_req_t = logic, + /// Response struct type of the AXI4+ATOP manager port + parameter type mgr_port_axi_rsp_t = logic ) ( /// Rising-edge clock of both ports input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Slave port request - input slv_port_axi_req_t slv_req_i, - /// Slave port response - output slv_port_axi_rsp_t slv_rsp_o, - /// Master port request - output mst_port_axi_req_t mst_req_o, - /// Master port response - input mst_port_axi_rsp_t mst_rsp_i + /// Subordinate port request + input sbr_port_axi_req_t sbr_req_i, + /// Subordinate port response + output sbr_port_axi_rsp_t sbr_rsp_o, + /// Manager port request + output mgr_port_axi_req_t mgr_req_o, + /// Manager port response + input mgr_port_axi_rsp_t mgr_rsp_i ); - /// Number of bits of the slave port ID that determine the mapping to the master port ID - localparam int unsigned SelectWidth = cf_math_pkg::idx_width(MstPortMaxUniqIds); - /// Slice of slave port IDs that determines the master port ID + /// Number of bits of the subordinate port ID that determine the mapping to the manager port ID + localparam int unsigned SelectWidth = cf_math_pkg::idx_width(MgrPortMaxUniqIds); + /// Slice of subordinate port IDs that determines the manager port ID typedef logic [SelectWidth-1:0] select_t; /// ID width after the multiplexer - localparam int unsigned MuxIdWidth = (MstPortMaxUniqIds > 32'd1) ? SelectWidth + 32'd1 : 32'd1; + localparam int unsigned MuxIdWidth = (MgrPortMaxUniqIds > 32'd1) ? SelectWidth + 32'd1 : 32'd1; /// ID after serializer (i.e., with a constant value of zero) typedef logic [0:0] ser_id_t; /// ID after the multiplexer typedef logic [MuxIdWidth-1:0] mux_id_t; - /// ID at the slave port - typedef logic [SlvPortIdWidth-1:0] slv_id_t; - /// ID at the master port - typedef logic [MstPortIdWidth-1:0] mst_id_t; + /// ID at the subordinate port + typedef logic [SbrPortIdWidth-1:0] sbr_id_t; + /// ID at the manager port + typedef logic [MgrPortIdWidth-1:0] mgr_id_t; /// Address in any AXI channel typedef logic [AddrWidth-1:0] addr_t; /// Data in any AXI channel @@ -99,14 +99,14 @@ module axi_id_serialize #( /// W channel at any interface `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) - /// AW channel at slave port - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_t, addr_t, slv_id_t, user_t) - /// B channel at slave port - `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, user_t) - /// AR channel at slave port - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, user_t) - /// R channel at slave port - `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, user_t) + /// AW channel at subordinate port + `AXI_TYPEDEF_AW_CHAN_T(sbr_aw_t, addr_t, sbr_id_t, user_t) + /// B channel at subordinate port + `AXI_TYPEDEF_B_CHAN_T(sbr_b_t, sbr_id_t, user_t) + /// AR channel at subordinate port + `AXI_TYPEDEF_AR_CHAN_T(sbr_ar_t, addr_t, sbr_id_t, user_t) + /// R channel at subordinate port + `AXI_TYPEDEF_R_CHAN_T(sbr_r_t, data_t, sbr_id_t, user_t) /// AW channel after serializer `AXI_TYPEDEF_AW_CHAN_T(ser_aw_t, addr_t, ser_id_t, user_t) @@ -134,34 +134,34 @@ module axi_id_serialize #( /// AXI responses to the multiplexer `AXI_TYPEDEF_RSP_T(mux_rsp_t, mux_b_t, mux_r_t) - /// AW channel at master port - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, user_t) - /// B channel at master port - `AXI_TYPEDEF_B_CHAN_T(mst_b_t, mst_id_t, user_t) - /// AR channel at master port - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_t, addr_t, mst_id_t, user_t) - /// R channel at master port - `AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, user_t) + /// AW channel at manager port + `AXI_TYPEDEF_AW_CHAN_T(mgr_aw_t, addr_t, mgr_id_t, user_t) + /// B channel at manager port + `AXI_TYPEDEF_B_CHAN_T(mgr_b_t, mgr_id_t, user_t) + /// AR channel at manager port + `AXI_TYPEDEF_AR_CHAN_T(mgr_ar_t, addr_t, mgr_id_t, user_t) + /// R channel at manager port + `AXI_TYPEDEF_R_CHAN_T(mgr_r_t, data_t, mgr_id_t, user_t) - select_t slv_aw_select, slv_ar_select; - assign slv_aw_select = select_t'(slv_req_i.aw.id % MstPortMaxUniqIds); // TODO: customizable base - assign slv_ar_select = select_t'(slv_req_i.ar.id % MstPortMaxUniqIds); + select_t sbr_aw_select, sbr_ar_select; + assign sbr_aw_select = select_t'(sbr_req_i.aw.id % MgrPortMaxUniqIds); // TODO: customizable base + assign sbr_ar_select = select_t'(sbr_req_i.ar.id % MgrPortMaxUniqIds); - slv_port_axi_req_t [MstPortMaxUniqIds-1:0] to_serializer_reqs; - slv_port_axi_rsp_t [MstPortMaxUniqIds-1:0] to_serializer_rsps; + sbr_port_axi_req_t [MgrPortMaxUniqIds-1:0] to_serializer_reqs; + sbr_port_axi_rsp_t [MgrPortMaxUniqIds-1:0] to_serializer_rsps; axi_demux #( - .IdWidth ( SlvPortIdWidth ), - .aw_chan_t ( slv_aw_t ), + .IdWidth ( SbrPortIdWidth ), + .aw_chan_t ( sbr_aw_t ), .w_chan_t ( w_t ), - .b_chan_t ( slv_b_t ), - .ar_chan_t ( slv_ar_t ), - .r_chan_t ( slv_r_t ), - .axi_req_t ( slv_port_axi_req_t ), - .axi_rsp_t ( slv_port_axi_rsp_t ), - .NumMstPorts ( MstPortMaxUniqIds ), - .MaxTrans ( SlvPortMaxTxns ), - .LookBits ( SlvPortIdWidth ), + .b_chan_t ( sbr_b_t ), + .ar_chan_t ( sbr_ar_t ), + .r_chan_t ( sbr_r_t ), + .axi_req_t ( sbr_port_axi_req_t ), + .axi_rsp_t ( sbr_port_axi_rsp_t ), + .NumMgrPorts ( MgrPortMaxUniqIds ), + .MaxTrans ( SbrPortMaxTxns ), + .LookBits ( SbrPortIdWidth ), .AtopSupport ( AtopSupport ), .FallThrough ( 1'b1 ), .SpillAw ( 1'b1 ), @@ -173,33 +173,33 @@ module axi_id_serialize #( .clk_i, .rst_ni, .test_i ( 1'b0 ), - .slv_req_i ( slv_req_i ), - .slv_aw_select_i ( slv_aw_select ), - .slv_ar_select_i ( slv_ar_select ), - .slv_rsp_o ( slv_rsp_o ), - .mst_reqs_o ( to_serializer_reqs ), - .mst_rsps_i ( to_serializer_rsps ) + .sbr_req_i ( sbr_req_i ), + .sbr_aw_select_i ( sbr_aw_select ), + .sbr_ar_select_i ( sbr_ar_select ), + .sbr_rsp_o ( sbr_rsp_o ), + .mgr_reqs_o ( to_serializer_reqs ), + .mgr_rsps_i ( to_serializer_rsps ) ); - slv_port_axi_req_t [MstPortMaxUniqIds-1:0] tmp_serializer_reqs; - slv_port_axi_rsp_t [MstPortMaxUniqIds-1:0] tmp_serializer_rsps; - ser_req_t [MstPortMaxUniqIds-1:0] from_serializer_reqs; - ser_rsp_t [MstPortMaxUniqIds-1:0] from_serializer_rsps; + sbr_port_axi_req_t [MgrPortMaxUniqIds-1:0] tmp_serializer_reqs; + sbr_port_axi_rsp_t [MgrPortMaxUniqIds-1:0] tmp_serializer_rsps; + ser_req_t [MgrPortMaxUniqIds-1:0] from_serializer_reqs; + ser_rsp_t [MgrPortMaxUniqIds-1:0] from_serializer_rsps; - for (genvar i = 0; i < MstPortMaxUniqIds; i++) begin : gen_serializers + for (genvar i = 0; i < MgrPortMaxUniqIds; i++) begin : gen_serializers axi_serializer #( - .MaxReadTxns ( MstPortMaxTxnsPerId ), - .MaxWriteTxns ( MstPortMaxTxnsPerId ), - .IdWidth ( SlvPortIdWidth ), - .axi_req_t ( slv_port_axi_req_t ), - .axi_rsp_t ( slv_port_axi_rsp_t ) + .MaxReadTxns ( MgrPortMaxTxnsPerId ), + .MaxWriteTxns ( MgrPortMaxTxnsPerId ), + .IdWidth ( SbrPortIdWidth ), + .axi_req_t ( sbr_port_axi_req_t ), + .axi_rsp_t ( sbr_port_axi_rsp_t ) ) i_axi_serializer ( .clk_i, .rst_ni, - .slv_req_i ( to_serializer_reqs[i] ), - .slv_rsp_o ( to_serializer_rsps[i] ), - .mst_req_o ( tmp_serializer_reqs[i] ), - .mst_rsp_i ( tmp_serializer_rsps[i] ) + .sbr_req_i ( to_serializer_reqs[i] ), + .sbr_rsp_o ( to_serializer_rsps[i] ), + .mgr_req_o ( tmp_serializer_reqs[i] ), + .mgr_rsp_i ( tmp_serializer_rsps[i] ) ); always_comb begin `AXI_SET_REQ_STRUCT(from_serializer_reqs[i], tmp_serializer_reqs[i]) @@ -208,8 +208,8 @@ module axi_id_serialize #( from_serializer_reqs[i].ar.id = tmp_serializer_reqs[i].ar.id[0]; `AXI_SET_RSP_STRUCT(tmp_serializer_rsps[i], from_serializer_rsps[i]) // Zero-extend response IDs. - tmp_serializer_rsps[i].b.id = {{SlvPortIdWidth-1{1'b0}}, from_serializer_rsps[i].b.id}; - tmp_serializer_rsps[i].r.id = {{SlvPortIdWidth-1{1'b0}}, from_serializer_rsps[i].r.id}; + tmp_serializer_rsps[i].b.id = {{SbrPortIdWidth-1{1'b0}}, from_serializer_rsps[i].b.id}; + tmp_serializer_rsps[i].r.id = {{SbrPortIdWidth-1{1'b0}}, from_serializer_rsps[i].r.id}; end end @@ -217,22 +217,22 @@ module axi_id_serialize #( mux_rsp_t axi_mux_rsp; axi_mux #( - .SlvIDWidth ( 32'd1 ), - .slv_aw_chan_t ( ser_aw_t ), - .mst_aw_chan_t ( mux_aw_t ), + .SbrIDWidth ( 32'd1 ), + .sbr_aw_chan_t ( ser_aw_t ), + .mgr_aw_chan_t ( mux_aw_t ), .w_chan_t ( w_t ), - .slv_b_chan_t ( ser_b_t ), - .mst_b_chan_t ( mux_b_t ), - .slv_ar_chan_t ( ser_ar_t ), - .mst_ar_chan_t ( mux_ar_t ), - .slv_r_chan_t ( ser_r_t ), - .mst_r_chan_t ( mux_r_t ), - .slv_port_axi_req_t ( ser_req_t ), - .slv_port_axi_rsp_t ( ser_rsp_t ), - .mst_port_axi_req_t ( mux_req_t ), - .mst_port_axi_rsp_t ( mux_rsp_t ), - .NumSlvPorts ( MstPortMaxUniqIds ), - .MaxWTrans ( MstPortMaxTxnsPerId ), + .sbr_b_chan_t ( ser_b_t ), + .mgr_b_chan_t ( mux_b_t ), + .sbr_ar_chan_t ( ser_ar_t ), + .mgr_ar_chan_t ( mux_ar_t ), + .sbr_r_chan_t ( ser_r_t ), + .mgr_r_chan_t ( mux_r_t ), + .sbr_port_axi_req_t ( ser_req_t ), + .sbr_port_axi_rsp_t ( ser_rsp_t ), + .mgr_port_axi_req_t ( mux_req_t ), + .mgr_port_axi_rsp_t ( mux_rsp_t ), + .NumSbrPorts ( MgrPortMaxUniqIds ), + .MaxWTrans ( MgrPortMaxTxnsPerId ), .FallThrough ( 1'b0 ), .SpillAw ( 1'b1 ), .SpillW ( 1'b0 ), @@ -243,92 +243,92 @@ module axi_id_serialize #( .clk_i, .rst_ni, .test_i ( 1'b0 ), - .slv_reqs_i ( from_serializer_reqs ), - .slv_rsps_o ( from_serializer_rsps ), - .mst_req_o ( axi_mux_req ), - .mst_rsp_i ( axi_mux_rsp ) + .sbr_reqs_i ( from_serializer_reqs ), + .sbr_rsps_o ( from_serializer_rsps ), + .mgr_req_o ( axi_mux_req ), + .mgr_rsp_i ( axi_mux_rsp ) ); // Shift the ID one down if needed, as mux prepends IDs if (MuxIdWidth > 32'd1) begin : gen_id_shift always_comb begin - `AXI_SET_REQ_STRUCT(mst_req_o, axi_mux_req) - mst_req_o.aw.id = mst_id_t'(axi_mux_req.aw.id >> 32'd1); - mst_req_o.ar.id = mst_id_t'(axi_mux_req.ar.id >> 32'd1); - `AXI_SET_RSP_STRUCT(axi_mux_rsp, mst_rsp_i) - axi_mux_rsp.b.id = mux_id_t'(mst_rsp_i.b.id << 32'd1); - axi_mux_rsp.r.id = mux_id_t'(mst_rsp_i.r.id << 32'd1); + `AXI_SET_REQ_STRUCT(mgr_req_o, axi_mux_req) + mgr_req_o.aw.id = mgr_id_t'(axi_mux_req.aw.id >> 32'd1); + mgr_req_o.ar.id = mgr_id_t'(axi_mux_req.ar.id >> 32'd1); + `AXI_SET_RSP_STRUCT(axi_mux_rsp, mgr_rsp_i) + axi_mux_rsp.b.id = mux_id_t'(mgr_rsp_i.b.id << 32'd1); + axi_mux_rsp.r.id = mux_id_t'(mgr_rsp_i.r.id << 32'd1); end end else begin : gen_no_id_shift axi_id_prepend #( .NumBus ( 32'd1 ), - .IdWidthSlvPort ( MuxIdWidth ), - .IdWidthMstPort ( MstPortIdWidth ), - .slv_aw_chan_t ( mux_aw_t ), - .slv_w_chan_t ( w_t ), - .slv_b_chan_t ( mux_b_t ), - .slv_ar_chan_t ( mux_ar_t ), - .slv_r_chan_t ( mux_r_t ), - .mst_aw_chan_t ( mst_aw_t ), - .mst_w_chan_t ( w_t ), - .mst_b_chan_t ( mst_b_t ), - .mst_ar_chan_t ( mst_ar_t ), - .mst_r_chan_t ( mst_r_t ) + .IdWidthSbrPort ( MuxIdWidth ), + .IdWidthMgrPort ( MgrPortIdWidth ), + .sbr_aw_chan_t ( mux_aw_t ), + .sbr_w_chan_t ( w_t ), + .sbr_b_chan_t ( mux_b_t ), + .sbr_ar_chan_t ( mux_ar_t ), + .sbr_r_chan_t ( mux_r_t ), + .mgr_aw_chan_t ( mgr_aw_t ), + .mgr_w_chan_t ( w_t ), + .mgr_b_chan_t ( mgr_b_t ), + .mgr_ar_chan_t ( mgr_ar_t ), + .mgr_r_chan_t ( mgr_r_t ) ) i_axi_id_prepend ( .pre_id_i ( '0 ), - .slv_aw_chans_i ( axi_mux_req.aw ), - .slv_aw_valids_i ( axi_mux_req.aw_valid ), - .slv_aw_readies_o ( axi_mux_rsp.aw_ready ), - .slv_w_chans_i ( axi_mux_req.w ), - .slv_w_valids_i ( axi_mux_req.w_valid ), - .slv_w_readies_o ( axi_mux_rsp.w_ready ), - .slv_b_chans_o ( axi_mux_rsp.b ), - .slv_b_valids_o ( axi_mux_rsp.b_valid ), - .slv_b_readies_i ( axi_mux_req.b_ready ), - .slv_ar_chans_i ( axi_mux_req.ar ), - .slv_ar_valids_i ( axi_mux_req.ar_valid ), - .slv_ar_readies_o ( axi_mux_rsp.ar_ready ), - .slv_r_chans_o ( axi_mux_rsp.r ), - .slv_r_valids_o ( axi_mux_rsp.r_valid ), - .slv_r_readies_i ( axi_mux_req.r_ready ), - .mst_aw_chans_o ( mst_req_o.aw ), - .mst_aw_valids_o ( mst_req_o.aw_valid ), - .mst_aw_readies_i ( mst_rsp_i.aw_ready ), - .mst_w_chans_o ( mst_req_o.w ), - .mst_w_valids_o ( mst_req_o.w_valid ), - .mst_w_readies_i ( mst_rsp_i.w_ready ), - .mst_b_chans_i ( mst_rsp_i.b ), - .mst_b_valids_i ( mst_rsp_i.b_valid ), - .mst_b_readies_o ( mst_req_o.b_ready ), - .mst_ar_chans_o ( mst_req_o.ar ), - .mst_ar_valids_o ( mst_req_o.ar_valid ), - .mst_ar_readies_i ( mst_rsp_i.ar_ready ), - .mst_r_chans_i ( mst_rsp_i.r ), - .mst_r_valids_i ( mst_rsp_i.r_valid ), - .mst_r_readies_o ( mst_req_o.r_ready ) + .sbr_aw_chans_i ( axi_mux_req.aw ), + .sbr_aw_valids_i ( axi_mux_req.aw_valid ), + .sbr_aw_readies_o ( axi_mux_rsp.aw_ready ), + .sbr_w_chans_i ( axi_mux_req.w ), + .sbr_w_valids_i ( axi_mux_req.w_valid ), + .sbr_w_readies_o ( axi_mux_rsp.w_ready ), + .sbr_b_chans_o ( axi_mux_rsp.b ), + .sbr_b_valids_o ( axi_mux_rsp.b_valid ), + .sbr_b_readies_i ( axi_mux_req.b_ready ), + .sbr_ar_chans_i ( axi_mux_req.ar ), + .sbr_ar_valids_i ( axi_mux_req.ar_valid ), + .sbr_ar_readies_o ( axi_mux_rsp.ar_ready ), + .sbr_r_chans_o ( axi_mux_rsp.r ), + .sbr_r_valids_o ( axi_mux_rsp.r_valid ), + .sbr_r_readies_i ( axi_mux_req.r_ready ), + .mgr_aw_chans_o ( mgr_req_o.aw ), + .mgr_aw_valids_o ( mgr_req_o.aw_valid ), + .mgr_aw_readies_i ( mgr_rsp_i.aw_ready ), + .mgr_w_chans_o ( mgr_req_o.w ), + .mgr_w_valids_o ( mgr_req_o.w_valid ), + .mgr_w_readies_i ( mgr_rsp_i.w_ready ), + .mgr_b_chans_i ( mgr_rsp_i.b ), + .mgr_b_valids_i ( mgr_rsp_i.b_valid ), + .mgr_b_readies_o ( mgr_req_o.b_ready ), + .mgr_ar_chans_o ( mgr_req_o.ar ), + .mgr_ar_valids_o ( mgr_req_o.ar_valid ), + .mgr_ar_readies_i ( mgr_rsp_i.ar_ready ), + .mgr_r_chans_i ( mgr_rsp_i.r ), + .mgr_r_valids_i ( mgr_rsp_i.r_valid ), + .mgr_r_readies_o ( mgr_req_o.r_ready ) ); end // pragma translate_off `ifndef VERILATOR initial begin : p_assert - assert(MstPortMaxUniqIds > 32'd0) - else $fatal(1, "MstPortMaxUniqIds has to be > 0."); - assert(2**(MstPortIdWidth) >= MstPortMaxUniqIds) - else $fatal(1, "Not enought Id width on MST port to map all ID's."); - assert(SlvPortIdWidth > 32'd0) - else $fatal(1, "Parameter SlvPortIdWidth has to be larger than 0!"); - assert(MstPortIdWidth) - else $fatal(1, "Parameter MstPortIdWidth has to be larger than 0!"); - assert(MstPortIdWidth <= SlvPortIdWidth) - else $fatal(1, "Downsize implies that MstPortIdWidth <= SlvPortIdWidth!"); - assert($bits(slv_req_i.aw.addr) == $bits(mst_req_o.aw.addr)) + assert(MgrPortMaxUniqIds > 32'd0) + else $fatal(1, "MgrPortMaxUniqIds has to be > 0."); + assert(2**(MgrPortIdWidth) >= MgrPortMaxUniqIds) + else $fatal(1, "Not enought Id width on MGR port to map all ID's."); + assert(SbrPortIdWidth > 32'd0) + else $fatal(1, "Parameter SbrPortIdWidth has to be larger than 0!"); + assert(MgrPortIdWidth) + else $fatal(1, "Parameter MgrPortIdWidth has to be larger than 0!"); + assert(MgrPortIdWidth <= SbrPortIdWidth) + else $fatal(1, "Downsize implies that MgrPortIdWidth <= SbrPortIdWidth!"); + assert($bits(sbr_req_i.aw.addr) == $bits(mgr_req_o.aw.addr)) else $fatal(1, "AXI AW address widths are not equal!"); - assert($bits(slv_req_i.w.data) == $bits(mst_req_o.w.data)) + assert($bits(sbr_req_i.w.data) == $bits(mgr_req_o.w.data)) else $fatal(1, "AXI W data widths are not equal!"); - assert($bits(slv_req_i.ar.addr) == $bits(mst_req_o.ar.addr)) + assert($bits(sbr_req_i.ar.addr) == $bits(mgr_req_o.ar.addr)) else $fatal(1, "AXI AR address widths are not equal!"); - assert($bits(slv_rsp_o.r.data) == $bits(mst_rsp_i.r.data)) + assert($bits(sbr_rsp_o.r.data) == $bits(mgr_rsp_i.r.data)) else $fatal(1, "AXI R data widths are not equal!"); end `endif @@ -340,86 +340,86 @@ endmodule /// /// See the documentation of the main module for the definition of ports and parameters. module axi_id_serialize_intf #( - parameter int unsigned AXI_SLV_PORT_ID_WIDTH = 32'd0, - parameter int unsigned AXI_SLV_PORT_MAX_TXNS = 32'd0, - parameter int unsigned AXI_MST_PORT_ID_WIDTH = 32'd0, - parameter int unsigned AXI_MST_PORT_MAX_UNIQ_IDS = 32'd0, - parameter int unsigned AXI_MST_PORT_MAX_TXNS_PER_ID = 32'd0, + parameter int unsigned AXI_SBR_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_SBR_PORT_MAX_TXNS = 32'd0, + parameter int unsigned AXI_MGR_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_MGR_PORT_MAX_UNIQ_IDS = 32'd0, + parameter int unsigned AXI_MGR_PORT_MAX_TXNS_PER_ID = 32'd0, parameter int unsigned AXI_ADDR_WIDTH = 32'd0, parameter int unsigned AXI_DATA_WIDTH = 32'd0, parameter int unsigned AXI_USER_WIDTH = 32'd0 ) ( input logic clk_i, input logic rst_ni, - AXI_BUS.Slave slv, - AXI_BUS.Master mst + AXI_BUS.Subordinate sbr, + AXI_BUS.Manager mgr ); - typedef logic [AXI_SLV_PORT_ID_WIDTH-1:0] slv_id_t; - typedef logic [AXI_MST_PORT_ID_WIDTH-1:0] mst_id_t; + typedef logic [AXI_SBR_PORT_ID_WIDTH-1:0] sbr_id_t; + typedef logic [AXI_MGR_PORT_ID_WIDTH-1:0] mgr_id_t; typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; typedef logic [AXI_DATA_WIDTH-1:0] data_t; typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; typedef logic [AXI_USER_WIDTH-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(sbr_aw_t, addr_t, sbr_id_t, user_t) `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, user_t) - `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_t, w_t, slv_ar_t) - `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_t, slv_r_t) + `AXI_TYPEDEF_B_CHAN_T(sbr_b_t, sbr_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(sbr_ar_t, addr_t, sbr_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(sbr_r_t, data_t, sbr_id_t, user_t) + `AXI_TYPEDEF_REQ_T(sbr_port_axi_req_t, sbr_aw_t, w_t, sbr_ar_t) + `AXI_TYPEDEF_RSP_T(sbr_port_axi_rsp_t, sbr_b_t, sbr_r_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_t, mst_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_t, addr_t, mst_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, user_t) - `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_t, w_t, mst_ar_t) - `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_t, mst_r_t) + `AXI_TYPEDEF_AW_CHAN_T(mgr_aw_t, addr_t, mgr_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mgr_b_t, mgr_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mgr_ar_t, addr_t, mgr_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mgr_r_t, data_t, mgr_id_t, user_t) + `AXI_TYPEDEF_REQ_T(mgr_port_axi_req_t, mgr_aw_t, w_t, mgr_ar_t) + `AXI_TYPEDEF_RSP_T(mgr_port_axi_rsp_t, mgr_b_t, mgr_r_t) - slv_port_axi_req_t slv_req; - slv_port_axi_rsp_t slv_rsp; - mst_port_axi_req_t mst_req; - mst_port_axi_rsp_t mst_rsp; + sbr_port_axi_req_t sbr_req; + sbr_port_axi_rsp_t sbr_rsp; + mgr_port_axi_req_t mgr_req; + mgr_port_axi_rsp_t mgr_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, slv_rsp) - `AXI_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, mst) + `AXI_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, sbr_rsp) + `AXI_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_id_serialize #( - .SlvPortIdWidth ( AXI_SLV_PORT_ID_WIDTH ), - .SlvPortMaxTxns ( AXI_SLV_PORT_MAX_TXNS ), - .MstPortIdWidth ( AXI_MST_PORT_ID_WIDTH ), - .MstPortMaxUniqIds ( AXI_MST_PORT_MAX_UNIQ_IDS ), - .MstPortMaxTxnsPerId ( AXI_MST_PORT_MAX_TXNS_PER_ID ), + .SbrPortIdWidth ( AXI_SBR_PORT_ID_WIDTH ), + .SbrPortMaxTxns ( AXI_SBR_PORT_MAX_TXNS ), + .MgrPortIdWidth ( AXI_MGR_PORT_ID_WIDTH ), + .MgrPortMaxUniqIds ( AXI_MGR_PORT_MAX_UNIQ_IDS ), + .MgrPortMaxTxnsPerId ( AXI_MGR_PORT_MAX_TXNS_PER_ID ), .AddrWidth ( AXI_ADDR_WIDTH ), .DataWidth ( AXI_DATA_WIDTH ), .UserWidth ( AXI_USER_WIDTH ), - .slv_port_axi_req_t ( slv_port_axi_req_t ), - .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), - .mst_port_axi_req_t ( mst_port_axi_req_t ), - .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ) + .sbr_port_axi_req_t ( sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t ( sbr_port_axi_rsp_t ), + .mgr_port_axi_req_t ( mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t ( mgr_port_axi_rsp_t ) ) i_axi_id_serialize ( .clk_i, .rst_ni, - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); // pragma translate_off `ifndef VERILATOR initial begin - assert (slv.AXI_ID_WIDTH == AXI_SLV_PORT_ID_WIDTH); - assert (slv.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); - assert (slv.AXI_DATA_WIDTH == AXI_DATA_WIDTH); - assert (slv.AXI_USER_WIDTH == AXI_USER_WIDTH); - assert (mst.AXI_ID_WIDTH == AXI_MST_PORT_ID_WIDTH); - assert (mst.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); - assert (mst.AXI_DATA_WIDTH == AXI_DATA_WIDTH); - assert (mst.AXI_USER_WIDTH == AXI_USER_WIDTH); + assert (sbr.AXI_ID_WIDTH == AXI_SBR_PORT_ID_WIDTH); + assert (sbr.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (sbr.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (sbr.AXI_USER_WIDTH == AXI_USER_WIDTH); + assert (mgr.AXI_ID_WIDTH == AXI_MGR_PORT_ID_WIDTH); + assert (mgr.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (mgr.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (mgr.AXI_USER_WIDTH == AXI_USER_WIDTH); end `endif // pragma translate_on diff --git a/src/axi_intf.sv b/src/axi_intf.sv index c0257f21c..43c17f7ee 100644 --- a/src/axi_intf.sv +++ b/src/axi_intf.sv @@ -82,7 +82,7 @@ interface AXI_BUS #( logic r_valid; logic r_ready; - modport Master ( + modport Manager ( output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, input aw_ready, output w_data, w_strb, w_last, w_user, w_valid, input w_ready, input b_id, b_resp, b_user, b_valid, output b_ready, @@ -90,7 +90,7 @@ interface AXI_BUS #( input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready ); - modport Slave ( + modport Subordinate ( input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, output aw_ready, input w_data, w_strb, w_last, w_user, w_valid, output w_ready, output b_id, b_resp, b_user, b_valid, input b_ready, @@ -177,7 +177,7 @@ interface AXI_BUS_DV #( logic r_valid; logic r_ready; - modport Master ( + modport Manager ( output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, input aw_ready, output w_data, w_strb, w_last, w_user, w_valid, input w_ready, input b_id, b_resp, b_user, b_valid, output b_ready, @@ -185,7 +185,7 @@ interface AXI_BUS_DV #( input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready ); - modport Slave ( + modport Subordinate ( input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, output aw_ready, input w_data, w_strb, w_last, w_user, w_valid, output w_ready, output b_id, b_resp, b_user, b_valid, input b_ready, @@ -324,7 +324,7 @@ interface AXI_BUS_ASYNC buffer_t r_writetoken; buffer_t r_readpointer; - modport Master ( + modport Manager ( output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_writetoken, input aw_readpointer, output w_data, w_strb, w_last, w_user, w_writetoken, input w_readpointer, input b_id, b_resp, b_user, b_writetoken, output b_readpointer, @@ -332,7 +332,7 @@ interface AXI_BUS_ASYNC input r_id, r_data, r_resp, r_last, r_user, r_writetoken, output r_readpointer ); - modport Slave ( + modport Subordinate ( input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_writetoken, output aw_readpointer, input w_data, w_strb, w_last, w_user, w_writetoken, output w_readpointer, output b_id, b_resp, b_user, b_writetoken, input b_readpointer, @@ -379,14 +379,14 @@ interface AXI_BUS_ASYNC_GRAY #( ar_wptr, ar_rptr, r_wptr, r_rptr; - modport Master ( + modport Manager ( output aw_data, aw_wptr, input aw_rptr, output w_data, w_wptr, input w_rptr, input b_data, b_wptr, output b_rptr, output ar_data, ar_wptr, input ar_rptr, input r_data, r_wptr, output r_rptr); - modport Slave ( + modport Subordinate ( input aw_data, aw_wptr, output aw_rptr, input w_data, w_wptr, output w_rptr, output b_data, b_wptr, input b_rptr, @@ -433,7 +433,7 @@ interface AXI_LITE #( logic r_valid; logic r_ready; - modport Master ( + modport Manager ( output aw_addr, aw_prot, aw_valid, input aw_ready, output w_data, w_strb, w_valid, input w_ready, input b_resp, b_valid, output b_ready, @@ -441,7 +441,7 @@ interface AXI_LITE #( input r_data, r_resp, r_valid, output r_ready ); - modport Slave ( + modport Subordinate ( input aw_addr, aw_prot, aw_valid, output aw_ready, input w_data, w_strb, w_valid, output w_ready, output b_resp, b_valid, input b_ready, @@ -499,7 +499,7 @@ interface AXI_LITE_DV #( logic r_valid; logic r_ready; - modport Master ( + modport Manager ( output aw_addr, aw_prot, aw_valid, input aw_ready, output w_data, w_strb, w_valid, input w_ready, input b_resp, b_valid, output b_ready, @@ -507,7 +507,7 @@ interface AXI_LITE_DV #( input r_data, r_resp, r_valid, output r_ready ); - modport Slave ( + modport Subordinate ( input aw_addr, aw_prot, aw_valid, output aw_ready, input w_data, w_strb, w_valid, output w_ready, output b_resp, b_valid, input b_ready, @@ -556,14 +556,14 @@ interface AXI_LITE_ASYNC_GRAY #( ar_wptr, ar_rptr, r_wptr, r_rptr; - modport Master ( + modport Manager ( output aw_data, aw_wptr, input aw_rptr, output w_data, w_wptr, input w_rptr, input b_data, b_wptr, output b_rptr, output ar_data, ar_wptr, input ar_rptr, input r_data, r_wptr, output r_rptr); - modport Slave ( + modport Subordinate ( input aw_data, aw_wptr, output aw_rptr, input w_data, w_wptr, output w_rptr, output b_data, b_wptr, input b_rptr, diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv index 68626c588..358d7acbc 100644 --- a/src/axi_isolate.sv +++ b/src/axi_isolate.sv @@ -16,7 +16,7 @@ `include "axi/typedef.svh" `include "common_cells/registers.svh" -/// This module can isolate the AXI4+ATOPs bus on the master port from the slave port. When the +/// This module can isolate the AXI4+ATOPs bus on the manager port from the subordinate port. When the /// isolation is not active, the two ports are directly connected. /// /// This module counts how many open transactions are currently in flight on the read and write @@ -26,8 +26,8 @@ /// The isolation interface has two signals: `isolate_i` and `isolated_o`. When `isolate_i` is /// asserted, all open transactions are gracefully terminated. When no transactions are in flight /// anymore, the `isolated_o` output is asserted. As long as `isolated_o` is asserted, all output -/// signals in `mst_req_o` are silenced to `'0`. When isolated, new transactions initiated on the -/// slave port are stalled until the isolation is terminated by deasserting `isolate_i`. +/// signals in `mgr_req_o` are silenced to `'0`. When isolated, new transactions initiated on the +/// subordinate port are stalled until the isolation is terminated by deasserting `isolate_i`. /// /// ## Response /// @@ -61,19 +61,19 @@ module axi_isolate #( /// Rising-edge clock of all ports input logic clk_i, /// Asynchronous reset, active low - input logic rst_ni, - /// Slave port request - input axi_req_t slv_req_i, - /// Slave port response - output axi_rsp_t slv_rsp_o, - /// Master port request - output axi_req_t mst_req_o, - /// Master port response - input axi_rsp_t mst_rsp_i, - /// Isolate master port from slave port - input logic isolate_i, - /// Master port is isolated from slave port - output logic isolated_o + input logic rst_ni, + /// Subordinate port request + input axi_req_t sbr_req_i, + /// Subordinate port response + output axi_rsp_t sbr_rsp_o, + /// Manager port request + output axi_req_t mgr_req_o, + /// Manager port response + input axi_rsp_t mgr_rsp_i, + /// Isolate manager port from subordinate port + input logic isolate_i, + /// Manager port is isolated from subordinate port + output logic isolated_o ); typedef logic [IdWidth-1:0] id_t; @@ -102,7 +102,7 @@ module axi_isolate #( .r_chan_t ( r_chan_t ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ), - .NumMstPorts ( 2 ), + .NumMgrPorts ( 2 ), .MaxTrans ( NumPending ), // We don't need many bits here as the common case will be to go for the pass-through. .LookBits ( 1 ), @@ -116,15 +116,15 @@ module axi_isolate #( .clk_i, .rst_ni, .test_i ( 1'b0 ), - .slv_req_i, - .slv_aw_select_i ( isolated_o ), - .slv_ar_select_i ( isolated_o ), - .slv_rsp_o, - .mst_reqs_o ( demux_req ), - .mst_rsps_i ( demux_rsp ) + .sbr_req_i, + .sbr_aw_select_i ( isolated_o ), + .sbr_ar_select_i ( isolated_o ), + .sbr_rsp_o, + .mgr_reqs_o ( demux_req ), + .mgr_rsps_i ( demux_rsp ) ); - axi_err_slv #( + axi_err_sbr #( .IdWidth ( IdWidth ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ), @@ -132,16 +132,16 @@ module axi_isolate #( .RespData ( 'h1501A7ED ), .ATOPs ( AtopSupport ), .MaxTrans ( 1 ) - ) i_axi_err_slv ( + ) i_axi_err_sbr ( .clk_i, .rst_ni, .test_i ( 1'b0 ), - .slv_req_i ( demux_req[1] ), - .slv_rsp_o ( demux_rsp[1] ) + .sbr_req_i ( demux_req[1] ), + .sbr_rsp_o ( demux_rsp[1] ) ); end else begin - assign demux_req[0] = slv_req_i; - assign slv_rsp_o = demux_rsp[0]; + assign demux_req[0] = sbr_req_i; + assign sbr_rsp_o = demux_rsp[0]; end axi_isolate_inner #( @@ -151,10 +151,10 @@ module axi_isolate #( ) i_axi_isolate ( .clk_i, .rst_ni, - .slv_req_i ( demux_req[0] ), - .slv_rsp_o ( demux_rsp[0] ), - .mst_req_o, - .mst_rsp_i, + .sbr_req_i ( demux_req[0] ), + .sbr_rsp_o ( demux_rsp[0] ), + .mgr_req_o, + .mgr_rsp_i, .isolate_i, .isolated_o ); @@ -167,10 +167,10 @@ module axi_isolate_inner #( ) ( input logic clk_i, input logic rst_ni, - input axi_req_t slv_req_i, - output axi_rsp_t slv_rsp_o, - output axi_req_t mst_req_o, - input axi_rsp_t mst_rsp_i, + input axi_req_t sbr_req_i, + output axi_rsp_t sbr_rsp_o, + output axi_req_t mgr_req_o, + input axi_rsp_t mgr_rsp_i, input logic isolate_i, output logic isolated_o ); @@ -213,31 +213,31 @@ module axi_isolate_inner #( pending_ar_d = pending_ar_q; update_ar_cnt = 1'b0; // write counters - if (mst_req_o.aw_valid && (state_aw_q == Normal)) begin + if (mgr_req_o.aw_valid && (state_aw_q == Normal)) begin pending_aw_d++; update_aw_cnt = 1'b1; pending_w_d++; update_w_cnt = 1'b1; connect_w = 1'b1; - if (mst_req_o.aw.atop[axi_pkg::ATOP_R_RESP]) begin + if (mgr_req_o.aw.atop[axi_pkg::ATOP_R_RESP]) begin pending_ar_d++; // handle atomic with read response by injecting a count in AR update_ar_cnt = 1'b1; end end - if (mst_req_o.w_valid && mst_rsp_i.w_ready && mst_req_o.w.last) begin + if (mgr_req_o.w_valid && mgr_rsp_i.w_ready && mgr_req_o.w.last) begin pending_w_d--; update_w_cnt = 1'b1; end - if (mst_rsp_i.b_valid && mst_req_o.b_ready) begin + if (mgr_rsp_i.b_valid && mgr_req_o.b_ready) begin pending_aw_d--; update_aw_cnt = 1'b1; end // read counters - if (mst_req_o.ar_valid && (state_ar_q == Normal)) begin + if (mgr_req_o.ar_valid && (state_ar_q == Normal)) begin pending_ar_d++; update_ar_cnt = 1'b1; end - if (mst_rsp_i.r_valid && mst_req_o.r_ready && mst_rsp_i.r.last) begin + if (mgr_rsp_i.r_valid && mgr_req_o.r_ready && mgr_rsp_i.r.last) begin pending_ar_d--; update_ar_cnt = 1'b1; end @@ -251,8 +251,8 @@ module axi_isolate_inner #( state_ar_d = state_ar_q; update_ar_state = 1'b0; // Connect channel per default - mst_req_o = slv_req_i; - slv_rsp_o = mst_rsp_i; + mgr_req_o = sbr_req_i; + sbr_rsp_o = mgr_rsp_i; ///////////////////////////////////////////////////////////// // Write transaction @@ -264,15 +264,15 @@ module axi_isolate_inner #( // counter. if (pending_aw_q >= cnt_t'(NumPending) || pending_ar_q >= cnt_t'(2*NumPending) || (pending_w_q >= cnt_t'(NumPending))) begin - mst_req_o.aw_valid = 1'b0; - slv_rsp_o.aw_ready = 1'b0; + mgr_req_o.aw_valid = 1'b0; + sbr_rsp_o.aw_ready = 1'b0; if (isolate_i) begin state_aw_d = Drain; update_aw_state = 1'b1; end end else begin // here the AW handshake is connected normally - if (slv_req_i.aw_valid && !mst_rsp_i.aw_ready) begin + if (sbr_req_i.aw_valid && !mgr_rsp_i.aw_ready) begin state_aw_d = Hold; update_aw_state = 1'b1; end else begin @@ -284,29 +284,29 @@ module axi_isolate_inner #( end end Hold: begin // Hold the valid signal on 1'b1 if there was no transfer - mst_req_o.aw_valid = 1'b1; + mgr_req_o.aw_valid = 1'b1; // aw_ready normal connected - if (mst_rsp_i.aw_ready) begin + if (mgr_rsp_i.aw_ready) begin update_aw_state = 1'b1; state_aw_d = isolate_i ? Drain : Normal; end end Drain: begin // cut the AW channel until counter is zero - mst_req_o.aw = '0; - mst_req_o.aw_valid = 1'b0; - slv_rsp_o.aw_ready = 1'b0; + mgr_req_o.aw = '0; + mgr_req_o.aw_valid = 1'b0; + sbr_rsp_o.aw_ready = 1'b0; if (pending_aw_q == '0) begin state_aw_d = Isolate; update_aw_state = 1'b1; end end Isolate: begin // Cut the signals to the outputs - mst_req_o.aw = '0; - mst_req_o.aw_valid = 1'b0; - slv_rsp_o.aw_ready = 1'b0; - slv_rsp_o.b = '0; - slv_rsp_o.b_valid = 1'b0; - mst_req_o.b_ready = 1'b0; + mgr_req_o.aw = '0; + mgr_req_o.aw_valid = 1'b0; + sbr_rsp_o.aw_ready = 1'b0; + sbr_rsp_o.b = '0; + sbr_rsp_o.b_valid = 1'b0; + mgr_req_o.b_ready = 1'b0; if (!isolate_i) begin state_aw_d = Normal; update_aw_state = 1'b1; @@ -317,9 +317,9 @@ module axi_isolate_inner #( // W channel is cut as long the counter is zero and not explicitly unlocked through an AW. if ((pending_w_q == '0) && !connect_w ) begin - mst_req_o.w = '0; - mst_req_o.w_valid = 1'b0; - slv_rsp_o.w_ready = 1'b0; + mgr_req_o.w = '0; + mgr_req_o.w_valid = 1'b0; + sbr_rsp_o.w_ready = 1'b0; end ///////////////////////////////////////////////////////////// @@ -329,15 +329,15 @@ module axi_isolate_inner #( Normal: begin // cut handshake if counter capacity is reached if (pending_ar_q >= NumPending) begin - mst_req_o.ar_valid = 1'b0; - slv_rsp_o.ar_ready = 1'b0; + mgr_req_o.ar_valid = 1'b0; + sbr_rsp_o.ar_ready = 1'b0; if (isolate_i) begin state_ar_d = Drain; update_ar_state = 1'b1; end end else begin // here the AR handshake is connected normally - if (slv_req_i.ar_valid && !mst_rsp_i.ar_ready) begin + if (sbr_req_i.ar_valid && !mgr_rsp_i.ar_ready) begin state_ar_d = Hold; update_ar_state = 1'b1; end else begin @@ -349,29 +349,29 @@ module axi_isolate_inner #( end end Hold: begin // Hold the valid signal on 1'b1 if there was no transfer - mst_req_o.ar_valid = 1'b1; + mgr_req_o.ar_valid = 1'b1; // ar_ready normal connected - if (mst_rsp_i.ar_ready) begin + if (mgr_rsp_i.ar_ready) begin update_ar_state = 1'b1; state_ar_d = isolate_i ? Drain : Normal; end end Drain: begin - mst_req_o.ar = '0; - mst_req_o.ar_valid = 1'b0; - slv_rsp_o.ar_ready = 1'b0; + mgr_req_o.ar = '0; + mgr_req_o.ar_valid = 1'b0; + sbr_rsp_o.ar_ready = 1'b0; if (pending_ar_q == '0) begin state_ar_d = Isolate; update_ar_state = 1'b1; end end Isolate: begin - mst_req_o.ar = '0; - mst_req_o.ar_valid = 1'b0; - slv_rsp_o.ar_ready = 1'b0; - slv_rsp_o.r = '0; - slv_rsp_o.r_valid = 1'b0; - mst_req_o.r_ready = 1'b0; + mgr_req_o.ar = '0; + mgr_req_o.ar_valid = 1'b0; + sbr_rsp_o.ar_ready = 1'b0; + sbr_rsp_o.r = '0; + sbr_rsp_o.r_valid = 1'b0; + mgr_req_o.r_ready = 1'b0; if (!isolate_i) begin state_ar_d = Normal; update_ar_state = 1'b1; @@ -422,8 +422,8 @@ module axi_isolate_intf #( ) ( input logic clk_i, input logic rst_ni, - AXI_BUS.Slave slv, - AXI_BUS.Master mst, + AXI_BUS.Subordinate sbr, + AXI_BUS.Manager mgr, input logic isolate_i, output logic isolated_o ); @@ -443,14 +443,14 @@ module axi_isolate_intf #( `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_rsp_t slv_rsp, mst_rsp; + axi_req_t sbr_req, mgr_req; + axi_rsp_t sbr_rsp, mgr_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, slv_rsp) + `AXI_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, sbr_rsp) - `AXI_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, mst) + `AXI_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_isolate #( .NumPending ( NUM_PENDING ), @@ -465,10 +465,10 @@ module axi_isolate_intf #( ) i_axi_isolate ( .clk_i, .rst_ni, - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ), + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ), .isolate_i, .isolated_o ); diff --git a/src/axi_iw_converter.sv b/src/axi_iw_converter.sv index 377a9af4a..d510aba06 100644 --- a/src/axi_iw_converter.sv +++ b/src/axi_iw_converter.sv @@ -17,206 +17,206 @@ /// Convert between any two AXI ID widths. /// -/// Any combination of slave and master port ID width is valid. When the master port ID width is -/// larger than or equal to the slave port ID width, slave port IDs are simply prepended with zeros -/// to the width of master port IDs. For *reducing* the ID width, i.e., when the master port ID -/// width is smaller than the slave port ID width, there are two options. +/// Any combination of subordinate and manager port ID width is valid. When the manager port ID width is +/// larger than or equal to the subordinate port ID width, subordinate port IDs are simply prepended with zeros +/// to the width of manager port IDs. For *reducing* the ID width, i.e., when the manager port ID +/// width is smaller than the subordinate port ID width, there are two options. /// /// ## Options for reducing the ID width /// /// The two options for reducing ID widths differ in the maximum number of different IDs that can be -/// in flight at the slave port of this module, given in the `SlvPortMaxUniqIds` parameter. +/// in flight at the subordinate port of this module, given in the `SbrPortMaxUniqIds` parameter. /// -/// ### Fewer unique slave port IDs than master port IDs +/// ### Fewer unique subordinate port IDs than manager port IDs /// -/// If `SlvPortMaxUniqIds <= 2**MstPortIdWidth`, there are fewer unique slave port IDs than -/// master port IDs. Therefore, IDs that are different at the slave port of this module can remain -/// different at the reduced-ID-width master port and thus remain *independently reorderable*. -/// Since the IDs are master port are nonetheless shorter than at the slave port, they need to be +/// If `SbrPortMaxUniqIds <= 2**MgrPortIdWidth`, there are fewer unique subordinate port IDs than +/// manager port IDs. Therefore, IDs that are different at the subordinate port of this module can remain +/// different at the reduced-ID-width manager port and thus remain *independently reorderable*. +/// Since the IDs are manager port are nonetheless shorter than at the subordinate port, they need to be /// *remapped*. An instance of [`axi_id_remap`](module.axi_id_remap) handles this case. /// -/// ### More unique slave port IDs than master port IDs +/// ### More unique subordinate port IDs than manager port IDs /// -/// If `SlvPortMaxUniqIds > 2**MstPortIdWidth`, there are more unique slave port IDs than -/// master port IDs. Therefore, some IDs that are different at the slave port need to be assigned -/// to the same master port ID and thus become ordered with respect to each other. An instance of +/// If `SbrPortMaxUniqIds > 2**MgrPortIdWidth`, there are more unique subordinate port IDs than +/// manager port IDs. Therefore, some IDs that are different at the subordinate port need to be assigned +/// to the same manager port ID and thus become ordered with respect to each other. An instance of /// [`axi_id_serialize`](module.axi_id_serialize) handles this case. module axi_iw_converter #( - /// ID width of the AXI4+ATOP slave port - parameter int unsigned SlvPortIdWidth = 32'd0, - /// ID width of the AXI4+ATOP master port - parameter int unsigned MstPortIdWidth = 32'd0, - /// Maximum number of different IDs that can be in flight at the slave port. Reads and writes are + /// ID width of the AXI4+ATOP subordinate port + parameter int unsigned SbrPortIdWidth = 32'd0, + /// ID width of the AXI4+ATOP manager port + parameter int unsigned MgrPortIdWidth = 32'd0, + /// Maximum number of different IDs that can be in flight at the subordinate port. Reads and writes are /// counted separately (except for ATOPs, which count as both read and write). /// /// It is legal for upstream to have transactions with more unique IDs than the maximum given by /// this parameter in flight, but a transaction exceeding the maximum will be stalled until all /// transactions of another ID complete. - parameter int unsigned SlvPortMaxUniqIds = 32'd0, - /// Maximum number of in-flight transactions with the same ID at the slave port. + parameter int unsigned SbrPortMaxUniqIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID at the subordinate port. /// - /// This parameter is only relevant if `SlvPortMaxUniqIds <= 2**MstPortIdWidth`. In that + /// This parameter is only relevant if `SbrPortMaxUniqIds <= 2**MgrPortIdWidth`. In that /// case, this parameter is passed to [`axi_id_remap` as `MaxTxnsPerId` /// parameter](module.axi_id_remap#parameter.MaxTxnsPerId). - parameter int unsigned SlvPortMaxTxnsPerId = 32'd0, - /// Maximum number of in-flight transactions at the slave port. Reads and writes are counted + parameter int unsigned SbrPortMaxTxnsPerId = 32'd0, + /// Maximum number of in-flight transactions at the subordinate port. Reads and writes are counted /// separately (except for ATOPs, which count as both read and write). /// - /// This parameter is only relevant if `SlvPortMaxUniqIds > 2**MstPortIdWidth`. In that + /// This parameter is only relevant if `SbrPortMaxUniqIds > 2**MgrPortIdWidth`. In that /// case, this parameter is passed to - /// [`axi_id_serialize`](module.axi_id_serialize#parameter.SlvPortMaxTxns). - parameter int unsigned SlvPortMaxTxns = 32'd0, - /// Maximum number of different IDs that can be in flight at the master port. Reads and writes + /// [`axi_id_serialize`](module.axi_id_serialize#parameter.SbrPortMaxTxns). + parameter int unsigned SbrPortMaxTxns = 32'd0, + /// Maximum number of different IDs that can be in flight at the manager port. Reads and writes /// are counted separately (except for ATOPs, which count as both read and write). /// - /// This parameter is only relevant if `SlvPortMaxUniqIds > 2**MstPortIdWidth`. In that + /// This parameter is only relevant if `SbrPortMaxUniqIds > 2**MgrPortIdWidth`. In that /// case, this parameter is passed to - /// [`axi_id_serialize`](module.axi_id_serialize#parameter.MstPortMaxUniqIds). - parameter int unsigned MstPortMaxUniqIds = 32'd0, - /// Maximum number of in-flight transactions with the same ID at the master port. + /// [`axi_id_serialize`](module.axi_id_serialize#parameter.MgrPortMaxUniqIds). + parameter int unsigned MgrPortMaxUniqIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID at the manager port. /// - /// This parameter is only relevant if `SlvPortMaxUniqIds > 2**MstPortIdWidth`. In that + /// This parameter is only relevant if `SbrPortMaxUniqIds > 2**MgrPortIdWidth`. In that /// case, this parameter is passed to - /// [`axi_id_serialize`](module.axi_id_serialize#parameter.MstPortMaxTxnsPerId). - parameter int unsigned MstPortMaxTxnsPerId = 32'd0, + /// [`axi_id_serialize`](module.axi_id_serialize#parameter.MgrPortMaxTxnsPerId). + parameter int unsigned MgrPortMaxTxnsPerId = 32'd0, /// Address width of both AXI4+ATOP ports parameter int unsigned AddrWidth = 32'd0, /// Data width of both AXI4+ATOP ports parameter int unsigned DataWidth = 32'd0, /// User signal width of both AXI4+ATOP ports parameter int unsigned UserWidth = 32'd0, - /// Request struct type of the AXI4+ATOP slave port - parameter type slv_port_axi_req_t = logic, - /// Response struct type of the AXI4+ATOP slave port - parameter type slv_port_axi_rsp_t = logic, - /// Request struct type of the AXI4+ATOP master port - parameter type mst_port_axi_req_t = logic, - /// Response struct type of the AXI4+ATOP master port - parameter type mst_port_axi_rsp_t = logic + /// Request struct type of the AXI4+ATOP subordinate port + parameter type sbr_port_axi_req_t = logic, + /// Response struct type of the AXI4+ATOP subordinate port + parameter type sbr_port_axi_rsp_t = logic, + /// Request struct type of the AXI4+ATOP manager port + parameter type mgr_port_axi_req_t = logic, + /// Response struct type of the AXI4+ATOP manager port + parameter type mgr_port_axi_rsp_t = logic ) ( /// Rising-edge clock of both ports input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Slave port request - input slv_port_axi_req_t slv_req_i, - /// Slave port response - output slv_port_axi_rsp_t slv_rsp_o, - /// Master port request - output mst_port_axi_req_t mst_req_o, - /// Master port response - input mst_port_axi_rsp_t mst_rsp_i + /// Subordinate port request + input sbr_port_axi_req_t sbr_req_i, + /// Subordinate port response + output sbr_port_axi_rsp_t sbr_rsp_o, + /// Manager port request + output mgr_port_axi_req_t mgr_req_o, + /// Manager port response + input mgr_port_axi_rsp_t mgr_rsp_i ); typedef logic [AddrWidth-1:0] addr_t; typedef logic [DataWidth-1:0] data_t; - typedef logic [SlvPortIdWidth-1:0] slv_id_t; - typedef logic [MstPortIdWidth-1:0] mst_id_t; + typedef logic [SbrPortIdWidth-1:0] sbr_id_t; + typedef logic [MgrPortIdWidth-1:0] mgr_id_t; typedef logic [DataWidth/8-1:0] strb_t; typedef logic [UserWidth-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(sbr_aw_t, addr_t, sbr_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mgr_aw_t, addr_t, mgr_id_t, user_t) `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_t, mst_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_t, addr_t, mst_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(sbr_b_t, sbr_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mgr_b_t, mgr_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(sbr_ar_t, addr_t, sbr_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mgr_ar_t, addr_t, mgr_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(sbr_r_t, data_t, sbr_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mgr_r_t, data_t, mgr_id_t, user_t) - if (MstPortIdWidth < SlvPortIdWidth) begin : gen_downsize - if (SlvPortMaxUniqIds <= 2**MstPortIdWidth) begin : gen_remap + if (MgrPortIdWidth < SbrPortIdWidth) begin : gen_downsize + if (SbrPortMaxUniqIds <= 2**MgrPortIdWidth) begin : gen_remap axi_id_remap #( - .SlvPortIdWidth ( SlvPortIdWidth ), - .MstPortIdWidth ( MstPortIdWidth ), - .SlvPortMaxUniqIds ( SlvPortMaxUniqIds ), - .MaxTxnsPerId ( SlvPortMaxTxnsPerId ), - .slv_port_axi_req_t ( slv_port_axi_req_t ), - .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), - .mst_port_axi_req_t ( mst_port_axi_req_t ), - .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ) + .SbrPortIdWidth ( SbrPortIdWidth ), + .MgrPortIdWidth ( MgrPortIdWidth ), + .SbrPortMaxUniqIds ( SbrPortMaxUniqIds ), + .MaxTxnsPerId ( SbrPortMaxTxnsPerId ), + .sbr_port_axi_req_t ( sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t ( sbr_port_axi_rsp_t ), + .mgr_port_axi_req_t ( mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t ( mgr_port_axi_rsp_t ) ) i_axi_id_remap ( .clk_i, .rst_ni, - .slv_req_i ( slv_req_i ), - .slv_rsp_o ( slv_rsp_o ), - .mst_req_o ( mst_req_o ), - .mst_rsp_i ( mst_rsp_i ) + .sbr_req_i ( sbr_req_i ), + .sbr_rsp_o ( sbr_rsp_o ), + .mgr_req_o ( mgr_req_o ), + .mgr_rsp_i ( mgr_rsp_i ) ); end else begin : gen_serialize axi_id_serialize #( - .SlvPortIdWidth ( SlvPortIdWidth ), - .SlvPortMaxTxns ( SlvPortMaxTxns ), - .MstPortIdWidth ( MstPortIdWidth ), - .MstPortMaxUniqIds ( MstPortMaxUniqIds ), - .MstPortMaxTxnsPerId ( MstPortMaxTxnsPerId ), + .SbrPortIdWidth ( SbrPortIdWidth ), + .SbrPortMaxTxns ( SbrPortMaxTxns ), + .MgrPortIdWidth ( MgrPortIdWidth ), + .MgrPortMaxUniqIds ( MgrPortMaxUniqIds ), + .MgrPortMaxTxnsPerId ( MgrPortMaxTxnsPerId ), .AddrWidth ( AddrWidth ), .DataWidth ( DataWidth ), .UserWidth ( UserWidth ), - .slv_port_axi_req_t ( slv_port_axi_req_t ), - .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), - .mst_port_axi_req_t ( mst_port_axi_req_t ), - .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ) + .sbr_port_axi_req_t ( sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t ( sbr_port_axi_rsp_t ), + .mgr_port_axi_req_t ( mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t ( mgr_port_axi_rsp_t ) ) i_axi_id_serialize ( .clk_i, .rst_ni, - .slv_req_i ( slv_req_i ), - .slv_rsp_o ( slv_rsp_o ), - .mst_req_o ( mst_req_o ), - .mst_rsp_i ( mst_rsp_i ) + .sbr_req_i ( sbr_req_i ), + .sbr_rsp_o ( sbr_rsp_o ), + .mgr_req_o ( mgr_req_o ), + .mgr_rsp_i ( mgr_rsp_i ) ); end - end else if (MstPortIdWidth > SlvPortIdWidth) begin : gen_upsize + end else if (MgrPortIdWidth > SbrPortIdWidth) begin : gen_upsize axi_id_prepend #( .NumBus ( 32'd1 ), - .IdWidthSlvPort ( SlvPortIdWidth ), - .IdWidthMstPort ( MstPortIdWidth ), - .slv_aw_chan_t ( slv_aw_t ), - .slv_w_chan_t ( w_t ), - .slv_b_chan_t ( slv_b_t ), - .slv_ar_chan_t ( slv_ar_t ), - .slv_r_chan_t ( slv_r_t ), - .mst_aw_chan_t ( mst_aw_t ), - .mst_w_chan_t ( w_t ), - .mst_b_chan_t ( mst_b_t ), - .mst_ar_chan_t ( mst_ar_t ), - .mst_r_chan_t ( mst_r_t ) + .IdWidthSbrPort ( SbrPortIdWidth ), + .IdWidthMgrPort ( MgrPortIdWidth ), + .sbr_aw_chan_t ( sbr_aw_t ), + .sbr_w_chan_t ( w_t ), + .sbr_b_chan_t ( sbr_b_t ), + .sbr_ar_chan_t ( sbr_ar_t ), + .sbr_r_chan_t ( sbr_r_t ), + .mgr_aw_chan_t ( mgr_aw_t ), + .mgr_w_chan_t ( w_t ), + .mgr_b_chan_t ( mgr_b_t ), + .mgr_ar_chan_t ( mgr_ar_t ), + .mgr_r_chan_t ( mgr_r_t ) ) i_axi_id_prepend ( .pre_id_i ( '0 ), - .slv_aw_chans_i ( slv_req_i.aw ), - .slv_aw_valids_i ( slv_req_i.aw_valid ), - .slv_aw_readies_o ( slv_rsp_o.aw_ready ), - .slv_w_chans_i ( slv_req_i.w ), - .slv_w_valids_i ( slv_req_i.w_valid ), - .slv_w_readies_o ( slv_rsp_o.w_ready ), - .slv_b_chans_o ( slv_rsp_o.b ), - .slv_b_valids_o ( slv_rsp_o.b_valid ), - .slv_b_readies_i ( slv_req_i.b_ready ), - .slv_ar_chans_i ( slv_req_i.ar ), - .slv_ar_valids_i ( slv_req_i.ar_valid ), - .slv_ar_readies_o ( slv_rsp_o.ar_ready ), - .slv_r_chans_o ( slv_rsp_o.r ), - .slv_r_valids_o ( slv_rsp_o.r_valid ), - .slv_r_readies_i ( slv_req_i.r_ready ), - .mst_aw_chans_o ( mst_req_o.aw ), - .mst_aw_valids_o ( mst_req_o.aw_valid ), - .mst_aw_readies_i ( mst_rsp_i.aw_ready ), - .mst_w_chans_o ( mst_req_o.w ), - .mst_w_valids_o ( mst_req_o.w_valid ), - .mst_w_readies_i ( mst_rsp_i.w_ready ), - .mst_b_chans_i ( mst_rsp_i.b ), - .mst_b_valids_i ( mst_rsp_i.b_valid ), - .mst_b_readies_o ( mst_req_o.b_ready ), - .mst_ar_chans_o ( mst_req_o.ar ), - .mst_ar_valids_o ( mst_req_o.ar_valid ), - .mst_ar_readies_i ( mst_rsp_i.ar_ready ), - .mst_r_chans_i ( mst_rsp_i.r ), - .mst_r_valids_i ( mst_rsp_i.r_valid ), - .mst_r_readies_o ( mst_req_o.r_ready ) + .sbr_aw_chans_i ( sbr_req_i.aw ), + .sbr_aw_valids_i ( sbr_req_i.aw_valid ), + .sbr_aw_readies_o ( sbr_rsp_o.aw_ready ), + .sbr_w_chans_i ( sbr_req_i.w ), + .sbr_w_valids_i ( sbr_req_i.w_valid ), + .sbr_w_readies_o ( sbr_rsp_o.w_ready ), + .sbr_b_chans_o ( sbr_rsp_o.b ), + .sbr_b_valids_o ( sbr_rsp_o.b_valid ), + .sbr_b_readies_i ( sbr_req_i.b_ready ), + .sbr_ar_chans_i ( sbr_req_i.ar ), + .sbr_ar_valids_i ( sbr_req_i.ar_valid ), + .sbr_ar_readies_o ( sbr_rsp_o.ar_ready ), + .sbr_r_chans_o ( sbr_rsp_o.r ), + .sbr_r_valids_o ( sbr_rsp_o.r_valid ), + .sbr_r_readies_i ( sbr_req_i.r_ready ), + .mgr_aw_chans_o ( mgr_req_o.aw ), + .mgr_aw_valids_o ( mgr_req_o.aw_valid ), + .mgr_aw_readies_i ( mgr_rsp_i.aw_ready ), + .mgr_w_chans_o ( mgr_req_o.w ), + .mgr_w_valids_o ( mgr_req_o.w_valid ), + .mgr_w_readies_i ( mgr_rsp_i.w_ready ), + .mgr_b_chans_i ( mgr_rsp_i.b ), + .mgr_b_valids_i ( mgr_rsp_i.b_valid ), + .mgr_b_readies_o ( mgr_req_o.b_ready ), + .mgr_ar_chans_o ( mgr_req_o.ar ), + .mgr_ar_valids_o ( mgr_req_o.ar_valid ), + .mgr_ar_readies_i ( mgr_rsp_i.ar_ready ), + .mgr_r_chans_i ( mgr_rsp_i.r ), + .mgr_r_valids_i ( mgr_rsp_i.r_valid ), + .mgr_r_readies_o ( mgr_req_o.r_ready ) ); end else begin : gen_passthrough - assign mst_req_o = slv_req_i; - assign slv_rsp_o = mst_rsp_i; + assign mgr_req_o = sbr_req_i; + assign sbr_rsp_o = mgr_rsp_i; end // pragma translate_off @@ -228,26 +228,26 @@ module axi_iw_converter #( else $fatal(1, "Parameter DataWidth has to be larger than 0!"); assert(UserWidth > 32'd0) else $fatal(1, "Parameter UserWidth has to be larger than 0!"); - assert(SlvPortIdWidth > 32'd0) - else $fatal(1, "Parameter SlvPortIdWidth has to be larger than 0!"); - assert(MstPortIdWidth > 32'd0) - else $fatal(1, "Parameter MstPortIdWidth has to be larger than 0!"); - if (SlvPortMaxUniqIds <= 2**MstPortIdWidth) begin - assert(SlvPortMaxTxnsPerId > 32'd0) - else $fatal(1, "Parameter SlvPortMaxTxnsPerId has to be larger than 0!"); + assert(SbrPortIdWidth > 32'd0) + else $fatal(1, "Parameter SbrPortIdWidth has to be larger than 0!"); + assert(MgrPortIdWidth > 32'd0) + else $fatal(1, "Parameter MgrPortIdWidth has to be larger than 0!"); + if (SbrPortMaxUniqIds <= 2**MgrPortIdWidth) begin + assert(SbrPortMaxTxnsPerId > 32'd0) + else $fatal(1, "Parameter SbrPortMaxTxnsPerId has to be larger than 0!"); end else begin - assert(MstPortMaxUniqIds > 32'd0) - else $fatal(1, "Parameter MstPortMaxUniqIds has to be larger than 0!"); - assert(MstPortMaxTxnsPerId > 32'd0) - else $fatal(1, "Parameter MstPortMaxTxnsPerId has to be larger than 0!"); + assert(MgrPortMaxUniqIds > 32'd0) + else $fatal(1, "Parameter MgrPortMaxUniqIds has to be larger than 0!"); + assert(MgrPortMaxTxnsPerId > 32'd0) + else $fatal(1, "Parameter MgrPortMaxTxnsPerId has to be larger than 0!"); end - assert($bits(slv_req_i.aw.addr) == $bits(mst_req_o.aw.addr)) + assert($bits(sbr_req_i.aw.addr) == $bits(mgr_req_o.aw.addr)) else $fatal(1, "AXI AW address widths are not equal!"); - assert($bits(slv_req_i.w.data) == $bits(mst_req_o.w.data)) + assert($bits(sbr_req_i.w.data) == $bits(mgr_req_o.w.data)) else $fatal(1, "AXI W data widths are not equal!"); - assert($bits(slv_req_i.ar.addr) == $bits(mst_req_o.ar.addr)) + assert($bits(sbr_req_i.ar.addr) == $bits(mgr_req_o.ar.addr)) else $fatal(1, "AXI AR address widths are not equal!"); - assert($bits(slv_rsp_o.r.data) == $bits(mst_rsp_i.r.data)) + assert($bits(sbr_rsp_o.r.data) == $bits(mgr_rsp_i.r.data)) else $fatal(1, "AXI R data widths are not equal!"); end `endif @@ -261,89 +261,89 @@ endmodule /// /// See the documentation of the main module for the definition of ports and parameters. module axi_iw_converter_intf #( - parameter int unsigned AXI_SLV_PORT_ID_WIDTH = 32'd0, - parameter int unsigned AXI_MST_PORT_ID_WIDTH = 32'd0, - parameter int unsigned AXI_SLV_PORT_MAX_UNIQ_IDS = 32'd0, - parameter int unsigned AXI_SLV_PORT_MAX_TXNS_PER_ID = 32'd0, - parameter int unsigned AXI_SLV_PORT_MAX_TXNS = 32'd0, - parameter int unsigned AXI_MST_PORT_MAX_UNIQ_IDS = 32'd0, - parameter int unsigned AXI_MST_PORT_MAX_TXNS_PER_ID = 32'd0, + parameter int unsigned AXI_SBR_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_MGR_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_SBR_PORT_MAX_UNIQ_IDS = 32'd0, + parameter int unsigned AXI_SBR_PORT_MAX_TXNS_PER_ID = 32'd0, + parameter int unsigned AXI_SBR_PORT_MAX_TXNS = 32'd0, + parameter int unsigned AXI_MGR_PORT_MAX_UNIQ_IDS = 32'd0, + parameter int unsigned AXI_MGR_PORT_MAX_TXNS_PER_ID = 32'd0, parameter int unsigned AXI_ADDR_WIDTH = 32'd0, parameter int unsigned AXI_DATA_WIDTH = 32'd0, parameter int unsigned AXI_USER_WIDTH = 32'd0 ) ( input logic clk_i, input logic rst_ni, - AXI_BUS.Slave slv, - AXI_BUS.Master mst + AXI_BUS.Subordinate sbr, + AXI_BUS.Manager mgr ); - typedef logic [AXI_SLV_PORT_ID_WIDTH-1:0] slv_id_t; - typedef logic [AXI_MST_PORT_ID_WIDTH-1:0] mst_id_t; + typedef logic [AXI_SBR_PORT_ID_WIDTH-1:0] sbr_id_t; + typedef logic [AXI_MGR_PORT_ID_WIDTH-1:0] mgr_id_t; typedef logic [AXI_ADDR_WIDTH-1:0] axi_addr_t; typedef logic [AXI_DATA_WIDTH-1:0] axi_data_t; typedef logic [AXI_DATA_WIDTH/8-1:0] axi_strb_t; typedef logic [AXI_USER_WIDTH-1:0] axi_user_t; - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, axi_addr_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_AW_CHAN_T(sbr_aw_chan_t, axi_addr_t, sbr_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(sbr_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(sbr_b_chan_t, sbr_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(sbr_ar_chan_t, axi_addr_t, sbr_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(sbr_r_chan_t, axi_data_t, sbr_id_t, axi_user_t) + `AXI_TYPEDEF_REQ_T(sbr_port_axi_req_t, sbr_aw_chan_t, sbr_w_chan_t, sbr_ar_chan_t) + `AXI_TYPEDEF_RSP_T(sbr_port_axi_rsp_t, sbr_b_chan_t, sbr_r_chan_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, axi_addr_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, axi_addr_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, axi_data_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_chan_t, mst_w_chan_t, mst_ar_chan_t) - `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_AW_CHAN_T(mgr_aw_chan_t, axi_addr_t, mgr_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(mgr_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(mgr_b_chan_t, mgr_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mgr_ar_chan_t, axi_addr_t, mgr_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(mgr_r_chan_t, axi_data_t, mgr_id_t, axi_user_t) + `AXI_TYPEDEF_REQ_T(mgr_port_axi_req_t, mgr_aw_chan_t, mgr_w_chan_t, mgr_ar_chan_t) + `AXI_TYPEDEF_RSP_T(mgr_port_axi_rsp_t, mgr_b_chan_t, mgr_r_chan_t) - slv_port_axi_req_t slv_req; - slv_port_axi_rsp_t slv_rsp; - mst_port_axi_req_t mst_req; - mst_port_axi_rsp_t mst_rsp; + sbr_port_axi_req_t sbr_req; + sbr_port_axi_rsp_t sbr_rsp; + mgr_port_axi_req_t mgr_req; + mgr_port_axi_rsp_t mgr_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, slv_rsp) - `AXI_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, mst) + `AXI_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, sbr_rsp) + `AXI_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_iw_converter #( - .SlvPortIdWidth ( AXI_SLV_PORT_ID_WIDTH ), - .MstPortIdWidth ( AXI_MST_PORT_ID_WIDTH ), - .SlvPortMaxUniqIds ( AXI_SLV_PORT_MAX_UNIQ_IDS ), - .SlvPortMaxTxnsPerId ( AXI_SLV_PORT_MAX_TXNS_PER_ID ), - .SlvPortMaxTxns ( AXI_SLV_PORT_MAX_TXNS ), - .MstPortMaxUniqIds ( AXI_MST_PORT_MAX_UNIQ_IDS ), - .MstPortMaxTxnsPerId ( AXI_MST_PORT_MAX_TXNS_PER_ID ), + .SbrPortIdWidth ( AXI_SBR_PORT_ID_WIDTH ), + .MgrPortIdWidth ( AXI_MGR_PORT_ID_WIDTH ), + .SbrPortMaxUniqIds ( AXI_SBR_PORT_MAX_UNIQ_IDS ), + .SbrPortMaxTxnsPerId ( AXI_SBR_PORT_MAX_TXNS_PER_ID ), + .SbrPortMaxTxns ( AXI_SBR_PORT_MAX_TXNS ), + .MgrPortMaxUniqIds ( AXI_MGR_PORT_MAX_UNIQ_IDS ), + .MgrPortMaxTxnsPerId ( AXI_MGR_PORT_MAX_TXNS_PER_ID ), .AddrWidth ( AXI_ADDR_WIDTH ), .DataWidth ( AXI_DATA_WIDTH ), .UserWidth ( AXI_USER_WIDTH ), - .slv_port_axi_req_t ( slv_port_axi_req_t ), - .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), - .mst_port_axi_req_t ( mst_port_axi_req_t ), - .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ) + .sbr_port_axi_req_t ( sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t ( sbr_port_axi_rsp_t ), + .mgr_port_axi_req_t ( mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t ( mgr_port_axi_rsp_t ) ) i_axi_iw_converter ( .clk_i, .rst_ni, - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); // pragma translate_off `ifndef VERILATOR initial begin - assert (slv.AXI_ID_WIDTH == AXI_SLV_PORT_ID_WIDTH); - assert (slv.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); - assert (slv.AXI_DATA_WIDTH == AXI_DATA_WIDTH); - assert (slv.AXI_USER_WIDTH == AXI_USER_WIDTH); - assert (mst.AXI_ID_WIDTH == AXI_MST_PORT_ID_WIDTH); - assert (mst.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); - assert (mst.AXI_DATA_WIDTH == AXI_DATA_WIDTH); - assert (mst.AXI_USER_WIDTH == AXI_USER_WIDTH); + assert (sbr.AXI_ID_WIDTH == AXI_SBR_PORT_ID_WIDTH); + assert (sbr.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (sbr.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (sbr.AXI_USER_WIDTH == AXI_USER_WIDTH); + assert (mgr.AXI_ID_WIDTH == AXI_MGR_PORT_ID_WIDTH); + assert (mgr.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (mgr.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (mgr.AXI_USER_WIDTH == AXI_USER_WIDTH); end `endif // pragma translate_on diff --git a/src/axi_join.sv b/src/axi_join.sv index f15648ebe..0e5f045cd 100644 --- a/src/axi_join.sv +++ b/src/axi_join.sv @@ -17,8 +17,8 @@ /// A connector that joins two AXI interfaces. module axi_join_intf ( - AXI_BUS.Slave in, - AXI_BUS.Master out + AXI_BUS.Subordinate in, + AXI_BUS.Manager out ); `AXI_ASSIGN(out, in) diff --git a/src/axi_lfsr.sv b/src/axi_lfsr.sv index 995ce131e..88164f857 100644 --- a/src/axi_lfsr.sv +++ b/src/axi_lfsr.sv @@ -94,10 +94,10 @@ module axi_lfsr #( .clk_i, .rst_ni, .test_i ( testmode_i ), - .slv_req_i ( req_i ), - .slv_rsp_o ( rsp_o ), - .mst_req_o ( axi_lite_req ), - .mst_rsp_i ( axi_lite_rsp ) + .sbr_req_i ( req_i ), + .sbr_rsp_o ( rsp_o ), + .mgr_req_o ( axi_lite_req ), + .mgr_rsp_i ( axi_lite_rsp ) ); axi_lite_lfsr #( diff --git a/src/axi_lite_demux.sv b/src/axi_lite_demux.sv index 9f0901e31..2a42b8976 100644 --- a/src/axi_lite_demux.sv +++ b/src/axi_lite_demux.sv @@ -20,7 +20,7 @@ `define TARGET_VSIM `endif -// axi_lite_demux: Demultiplex an AXI4-Lite bus from one slave port to multiple master ports. +// axi_lite_demux: Demultiplex an AXI4-Lite bus from one subordinate port to multiple manager ports. // The selection signal at the AW and AR channel has to follow the same // stability rules as the corresponding AXI4-Lite channel. @@ -32,28 +32,28 @@ module axi_lite_demux #( parameter type r_chan_t = logic, // AXI4-Lite R channel parameter type axi_lite_req_t = logic, // AXI4-Lite request struct parameter type axi_lite_rsp_t = logic, // AXI4-Lite response struct - parameter int unsigned NumMstPorts = 32'd0, // Number of instantiated ports + parameter int unsigned NumMgrPorts = 32'd0, // Number of instantiated ports parameter int unsigned MaxTrans = 32'd0, // Maximum number of open transactions per channel parameter bit FallThrough = 1'b0, // FIFOs are in fall through mode - parameter bit SpillAw = 1'b1, // insert one cycle latency on slave AW - parameter bit SpillW = 1'b0, // insert one cycle latency on slave W - parameter bit SpillB = 1'b0, // insert one cycle latency on slave B - parameter bit SpillAr = 1'b1, // insert one cycle latency on slave AR - parameter bit SpillR = 1'b0, // insert one cycle latency on slave R + parameter bit SpillAw = 1'b1, // insert one cycle latency on subordinate AW + parameter bit SpillW = 1'b0, // insert one cycle latency on subordinate W + parameter bit SpillB = 1'b0, // insert one cycle latency on subordinate B + parameter bit SpillAr = 1'b1, // insert one cycle latency on subordinate AR + parameter bit SpillR = 1'b0, // insert one cycle latency on subordinate R // Dependent parameters, DO NOT OVERRIDE! - parameter type select_t = logic [$clog2(NumMstPorts)-1:0] + parameter type select_t = logic [$clog2(NumMgrPorts)-1:0] ) ( input logic clk_i, input logic rst_ni, input logic test_i, - // slave port (AXI4-Lite input), connect master module here - input axi_lite_req_t slv_req_i, - input select_t slv_aw_select_i, - input select_t slv_ar_select_i, - output axi_lite_rsp_t slv_rsp_o, - // master ports (AXI4-Lite outputs), connect slave modules here - output axi_lite_req_t [NumMstPorts-1:0] mst_reqs_o, - input axi_lite_rsp_t [NumMstPorts-1:0] mst_rsps_i + // subordinate port (AXI4-Lite input), connect manager module here + input axi_lite_req_t sbr_req_i, + input select_t sbr_aw_select_i, + input select_t sbr_ar_select_i, + output axi_lite_rsp_t sbr_rsp_o, + // manager ports (AXI4-Lite outputs), connect subordinate modules here + output axi_lite_req_t [NumMgrPorts-1:0] mgr_reqs_o, + input axi_lite_rsp_t [NumMgrPorts-1:0] mgr_rsps_i ); //-------------------------------------- @@ -68,20 +68,20 @@ module axi_lite_demux #( select_t select; } ar_chan_select_t; - if (NumMstPorts == 32'd1) begin : gen_no_demux - // degenerate case, connect slave to master port + if (NumMgrPorts == 32'd1) begin : gen_no_demux + // degenerate case, connect subordinate to manager port spill_register #( .T ( aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.aw_valid ), - .ready_o ( slv_rsp_o.aw_ready ), - .data_i ( slv_req_i.aw ), - .valid_o ( mst_reqs_o[0].aw_valid ), - .ready_i ( mst_rsps_i[0].aw_ready ), - .data_o ( mst_reqs_o[0].aw ) + .valid_i ( sbr_req_i.aw_valid ), + .ready_o ( sbr_rsp_o.aw_ready ), + .data_i ( sbr_req_i.aw ), + .valid_o ( mgr_reqs_o[0].aw_valid ), + .ready_i ( mgr_rsps_i[0].aw_ready ), + .data_o ( mgr_reqs_o[0].aw ) ); spill_register #( .T ( w_chan_t ), @@ -89,12 +89,12 @@ module axi_lite_demux #( ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.w_valid ), - .ready_o ( slv_rsp_o.w_ready ), - .data_i ( slv_req_i.w ), - .valid_o ( mst_reqs_o[0].w_valid ), - .ready_i ( mst_rsps_i[0].w_ready ), - .data_o ( mst_reqs_o[0].w ) + .valid_i ( sbr_req_i.w_valid ), + .ready_o ( sbr_rsp_o.w_ready ), + .data_i ( sbr_req_i.w ), + .valid_o ( mgr_reqs_o[0].w_valid ), + .ready_i ( mgr_rsps_i[0].w_ready ), + .data_o ( mgr_reqs_o[0].w ) ); spill_register #( .T ( b_chan_t ), @@ -102,12 +102,12 @@ module axi_lite_demux #( ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsps_i[0].b_valid ), - .ready_o ( mst_reqs_o[0].b_ready ), - .data_i ( mst_rsps_i[0].b ), - .valid_o ( slv_rsp_o.b_valid ), - .ready_i ( slv_req_i.b_ready ), - .data_o ( slv_rsp_o.b ) + .valid_i ( mgr_rsps_i[0].b_valid ), + .ready_o ( mgr_reqs_o[0].b_ready ), + .data_i ( mgr_rsps_i[0].b ), + .valid_o ( sbr_rsp_o.b_valid ), + .ready_i ( sbr_req_i.b_ready ), + .data_o ( sbr_rsp_o.b ) ); spill_register #( .T ( ar_chan_t ), @@ -115,12 +115,12 @@ module axi_lite_demux #( ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.ar_valid ), - .ready_o ( slv_rsp_o.ar_ready ), - .data_i ( slv_req_i.ar ), - .valid_o ( mst_reqs_o[0].ar_valid ), - .ready_i ( mst_rsps_i[0].ar_ready ), - .data_o ( mst_reqs_o[0].ar ) + .valid_i ( sbr_req_i.ar_valid ), + .ready_o ( sbr_rsp_o.ar_ready ), + .data_i ( sbr_req_i.ar ), + .valid_o ( mgr_reqs_o[0].ar_valid ), + .ready_i ( mgr_rsps_i[0].ar_ready ), + .data_o ( mgr_reqs_o[0].ar ) ); spill_register #( .T ( r_chan_t ), @@ -128,12 +128,12 @@ module axi_lite_demux #( ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsps_i[0].r_valid ), - .ready_o ( mst_reqs_o[0].r_ready ), - .data_i ( mst_rsps_i[0].r ), - .valid_o ( slv_rsp_o.r_valid ), - .ready_i ( slv_req_i.r_ready ), - .data_o ( slv_rsp_o.r ) + .valid_i ( mgr_rsps_i[0].r_valid ), + .ready_o ( mgr_reqs_o[0].r_ready ), + .data_i ( mgr_rsps_i[0].r ), + .valid_o ( sbr_rsp_o.r_valid ), + .ready_i ( sbr_req_i.r_ready ), + .data_o ( sbr_rsp_o.r ) ); end else begin : gen_demux @@ -149,39 +149,39 @@ module axi_lite_demux #( //-------------------------------------- // Write Transaction //-------------------------------------- - aw_chan_select_t slv_aw_chan; - logic slv_aw_valid, slv_aw_ready; + aw_chan_select_t sbr_aw_chan; + logic sbr_aw_valid, sbr_aw_ready; - logic [NumMstPorts-1:0] mst_aw_valids, mst_aw_readies; + logic [NumMgrPorts-1:0] mgr_aw_valids, mgr_aw_readies; logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock; logic w_fifo_push, w_fifo_pop; logic w_fifo_full, w_fifo_empty; - w_chan_t slv_w_chan; + w_chan_t sbr_w_chan; select_t w_select; - logic slv_w_valid, slv_w_ready; + logic sbr_w_valid, sbr_w_ready; logic /*w_pop*/ b_fifo_pop; logic b_fifo_full, b_fifo_empty; - b_chan_t slv_b_chan; + b_chan_t sbr_b_chan; select_t b_select; - logic slv_b_valid, slv_b_ready; + logic sbr_b_valid, sbr_b_ready; //-------------------------------------- // Read Transaction //-------------------------------------- - ar_chan_select_t slv_ar_chan; - logic slv_ar_valid, slv_ar_ready; + ar_chan_select_t sbr_ar_chan; + logic sbr_ar_valid, sbr_ar_ready; logic r_fifo_push, r_fifo_pop; logic r_fifo_full, r_fifo_empty; - r_chan_t slv_r_chan; + r_chan_t sbr_r_chan; select_t r_select; - logic slv_r_valid, slv_r_ready; + logic sbr_r_valid, sbr_r_ready; //-------------------------------------- //-------------------------------------- @@ -201,29 +201,29 @@ module axi_lite_demux #( // generally. typedef aw_chan_select_t aw_chan_select_flat_t; `endif - aw_chan_select_flat_t slv_aw_chan_select_in_flat, - slv_aw_chan_select_out_flat; - assign slv_aw_chan_select_in_flat = {slv_req_i.aw, slv_aw_select_i}; + aw_chan_select_flat_t sbr_aw_chan_select_in_flat, + sbr_aw_chan_select_out_flat; + assign sbr_aw_chan_select_in_flat = {sbr_req_i.aw, sbr_aw_select_i}; spill_register #( .T ( aw_chan_select_flat_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.aw_valid ), - .ready_o ( slv_rsp_o.aw_ready ), - .data_i ( slv_aw_chan_select_in_flat ), - .valid_o ( slv_aw_valid ), - .ready_i ( slv_aw_ready ), - .data_o ( slv_aw_chan_select_out_flat ) + .valid_i ( sbr_req_i.aw_valid ), + .ready_o ( sbr_rsp_o.aw_ready ), + .data_i ( sbr_aw_chan_select_in_flat ), + .valid_o ( sbr_aw_valid ), + .ready_i ( sbr_aw_ready ), + .data_o ( sbr_aw_chan_select_out_flat ) ); - assign slv_aw_chan = slv_aw_chan_select_out_flat; + assign sbr_aw_chan = sbr_aw_chan_select_out_flat; // replicate AW channel to the request output - for (genvar i = 0; i < NumMstPorts; i++) begin : gen_mst_aw - assign mst_reqs_o[i].aw = slv_aw_chan.aw; - assign mst_reqs_o[i].aw_valid = mst_aw_valids[i]; - assign mst_aw_readies[i] = mst_rsps_i[i].aw_ready; + for (genvar i = 0; i < NumMgrPorts; i++) begin : gen_mgr_aw + assign mgr_reqs_o[i].aw = sbr_aw_chan.aw; + assign mgr_reqs_o[i].aw_valid = mgr_aw_valids[i]; + assign mgr_aw_readies[i] = mgr_rsps_i[i].aw_ready; end // AW channel handshake control @@ -232,28 +232,28 @@ module axi_lite_demux #( lock_aw_valid_d = lock_aw_valid_q; load_aw_lock = 1'b0; // handshake - slv_aw_ready = 1'b0; - mst_aw_valids = '0; + sbr_aw_ready = 1'b0; + mgr_aw_valids = '0; // W FIFO input control w_fifo_push = 1'b0; // control if (lock_aw_valid_q) begin // AW channel is locked and has valid output, fifo was pushed, as the new request was issued - mst_aw_valids[slv_aw_chan.select] = 1'b1; - if (mst_aw_readies[slv_aw_chan.select]) begin + mgr_aw_valids[sbr_aw_chan.select] = 1'b1; + if (mgr_aw_readies[sbr_aw_chan.select]) begin // transaction, go back to IDLE - slv_aw_ready = 1'b1; + sbr_aw_ready = 1'b1; lock_aw_valid_d = 1'b0; load_aw_lock = 1'b1; end end else begin - if (!w_fifo_full && slv_aw_valid) begin + if (!w_fifo_full && sbr_aw_valid) begin // new transaction, push select in the FIFO and then look if transaction happened w_fifo_push = 1'b1; - mst_aw_valids[slv_aw_chan.select] = 1'b1; // only set the valid when FIFO is not full - if (mst_aw_readies[slv_aw_chan.select]) begin - // transaction, notify slave port - slv_aw_ready = 1'b1; + mgr_aw_valids[sbr_aw_chan.select] = 1'b1; // only set the valid when FIFO is not full + if (mgr_aw_readies[sbr_aw_chan.select]) begin + // transaction, notify subordinate port + sbr_aw_ready = 1'b1; end else begin // no transaction, lock valid lock_aw_valid_d = 1'b1; @@ -279,7 +279,7 @@ module axi_lite_demux #( .full_o ( w_fifo_full ), .empty_o ( w_fifo_empty ), .usage_o ( /*not used*/ ), - .data_i ( slv_aw_chan.select ), + .data_i ( sbr_aw_chan.select ), .push_i ( w_fifo_push ), .data_o ( w_select ), .pop_i ( w_fifo_pop ) @@ -294,22 +294,22 @@ module axi_lite_demux #( ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.w_valid ), - .ready_o ( slv_rsp_o.w_ready ), - .data_i ( slv_req_i.w ), - .valid_o ( slv_w_valid ), - .ready_i ( slv_w_ready ), - .data_o ( slv_w_chan ) + .valid_i ( sbr_req_i.w_valid ), + .ready_o ( sbr_rsp_o.w_ready ), + .data_i ( sbr_req_i.w ), + .valid_o ( sbr_w_valid ), + .ready_i ( sbr_w_ready ), + .data_o ( sbr_w_chan ) ); // replicate W channel - for (genvar i = 0; i < NumMstPorts; i++) begin : gen_mst_w - assign mst_reqs_o[i].w = slv_w_chan; - assign mst_reqs_o[i].w_valid = ~w_fifo_empty & ~b_fifo_full & - slv_w_valid & (w_select == select_t'(i)); + for (genvar i = 0; i < NumMgrPorts; i++) begin : gen_mgr_w + assign mgr_reqs_o[i].w = sbr_w_chan; + assign mgr_reqs_o[i].w_valid = ~w_fifo_empty & ~b_fifo_full & + sbr_w_valid & (w_select == select_t'(i)); end - assign slv_w_ready = ~w_fifo_empty & ~b_fifo_full & mst_rsps_i[w_select].w_ready; - assign w_fifo_pop = slv_w_valid & slv_w_ready; + assign sbr_w_ready = ~w_fifo_empty & ~b_fifo_full & mgr_rsps_i[w_select].w_ready; + assign w_fifo_pop = sbr_w_valid & sbr_w_ready; fifo_v3 #( .FALL_THROUGH( FallThrough ), @@ -338,21 +338,21 @@ module axi_lite_demux #( ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_b_valid ), - .ready_o ( slv_b_ready ), - .data_i ( slv_b_chan ), - .valid_o ( slv_rsp_o.b_valid ), - .ready_i ( slv_req_i.b_ready ), - .data_o ( slv_rsp_o.b ) + .valid_i ( sbr_b_valid ), + .ready_o ( sbr_b_ready ), + .data_i ( sbr_b_chan ), + .valid_o ( sbr_rsp_o.b_valid ), + .ready_i ( sbr_req_i.b_ready ), + .data_o ( sbr_rsp_o.b ) ); // connect the response if the FIFO has valid data in it - assign slv_b_chan = (!b_fifo_empty) ? mst_rsps_i[b_select].b : '0; - assign slv_b_valid = ~b_fifo_empty & mst_rsps_i[b_select].b_valid; - for (genvar i = 0; i < NumMstPorts; i++) begin : gen_mst_b - assign mst_reqs_o[i].b_ready = ~b_fifo_empty & slv_b_ready & (b_select == select_t'(i)); + assign sbr_b_chan = (!b_fifo_empty) ? mgr_rsps_i[b_select].b : '0; + assign sbr_b_valid = ~b_fifo_empty & mgr_rsps_i[b_select].b_valid; + for (genvar i = 0; i < NumMgrPorts; i++) begin : gen_mgr_b + assign mgr_reqs_o[i].b_ready = ~b_fifo_empty & sbr_b_ready & (b_select == select_t'(i)); end - assign b_fifo_pop = slv_b_valid & slv_b_ready; + assign b_fifo_pop = sbr_b_valid & sbr_b_ready; //-------------------------------------- // AR Channel @@ -363,32 +363,32 @@ module axi_lite_demux #( `else typedef ar_chan_select_t ar_chan_select_flat_t; `endif - ar_chan_select_flat_t slv_ar_chan_select_in_flat, - slv_ar_chan_select_out_flat; - assign slv_ar_chan_select_in_flat = {slv_req_i.ar, slv_ar_select_i}; + ar_chan_select_flat_t sbr_ar_chan_select_in_flat, + sbr_ar_chan_select_out_flat; + assign sbr_ar_chan_select_in_flat = {sbr_req_i.ar, sbr_ar_select_i}; spill_register #( .T ( ar_chan_select_flat_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_req_i.ar_valid ), - .ready_o ( slv_rsp_o.ar_ready ), - .data_i ( slv_ar_chan_select_in_flat ), - .valid_o ( slv_ar_valid ), - .ready_i ( slv_ar_ready ), - .data_o ( slv_ar_chan_select_out_flat ) + .valid_i ( sbr_req_i.ar_valid ), + .ready_o ( sbr_rsp_o.ar_ready ), + .data_i ( sbr_ar_chan_select_in_flat ), + .valid_o ( sbr_ar_valid ), + .ready_i ( sbr_ar_ready ), + .data_o ( sbr_ar_chan_select_out_flat ) ); - assign slv_ar_chan = slv_ar_chan_select_out_flat; + assign sbr_ar_chan = sbr_ar_chan_select_out_flat; // replicate AR channel - for (genvar i = 0; i < NumMstPorts; i++) begin : gen_mst_ar - assign mst_reqs_o[i].ar = slv_ar_chan.ar; - assign mst_reqs_o[i].ar_valid = ~r_fifo_full & slv_ar_valid & - (slv_ar_chan.select == select_t'(i)); + for (genvar i = 0; i < NumMgrPorts; i++) begin : gen_mgr_ar + assign mgr_reqs_o[i].ar = sbr_ar_chan.ar; + assign mgr_reqs_o[i].ar_valid = ~r_fifo_full & sbr_ar_valid & + (sbr_ar_chan.select == select_t'(i)); end - assign slv_ar_ready = ~r_fifo_full & mst_rsps_i[slv_ar_chan.select].ar_ready; - assign r_fifo_push = slv_ar_valid & slv_ar_ready; + assign sbr_ar_ready = ~r_fifo_full & mgr_rsps_i[sbr_ar_chan.select].ar_ready; + assign r_fifo_push = sbr_ar_valid & sbr_ar_ready; fifo_v3 #( .FALL_THROUGH( FallThrough ), @@ -402,7 +402,7 @@ module axi_lite_demux #( .full_o ( r_fifo_full ), .empty_o ( r_fifo_empty ), .usage_o ( /*not used*/ ), - .data_i ( slv_ar_chan.select ), + .data_i ( sbr_ar_chan.select ), .push_i ( r_fifo_push ), .data_o ( r_select ), .pop_i ( r_fifo_pop ) @@ -417,52 +417,52 @@ module axi_lite_demux #( ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_r_valid ), - .ready_o ( slv_r_ready ), - .data_i ( slv_r_chan ), - .valid_o ( slv_rsp_o.r_valid ), - .ready_i ( slv_req_i.r_ready ), - .data_o ( slv_rsp_o.r ) + .valid_i ( sbr_r_valid ), + .ready_o ( sbr_r_ready ), + .data_i ( sbr_r_chan ), + .valid_o ( sbr_rsp_o.r_valid ), + .ready_i ( sbr_req_i.r_ready ), + .data_o ( sbr_rsp_o.r ) ); // connect the response if the FIFO has valid data in it always_comb begin - slv_r_chan = '0; - slv_r_valid = '0; + sbr_r_chan = '0; + sbr_r_valid = '0; if (!r_fifo_empty) begin - slv_r_chan = mst_rsps_i[r_select].r; - slv_r_valid = mst_rsps_i[r_select].r_valid; + sbr_r_chan = mgr_rsps_i[r_select].r; + sbr_r_valid = mgr_rsps_i[r_select].r_valid; end end - for (genvar i = 0; i < NumMstPorts; i++) begin : gen_mst_r - assign mst_reqs_o[i].r_ready = ~r_fifo_empty & slv_r_ready & (r_select == select_t'(i)); + for (genvar i = 0; i < NumMgrPorts; i++) begin : gen_mgr_r + assign mgr_reqs_o[i].r_ready = ~r_fifo_empty & sbr_r_ready & (r_select == select_t'(i)); end - assign r_fifo_pop = slv_r_valid & slv_r_ready; + assign r_fifo_pop = sbr_r_valid & sbr_r_ready; // pragma translate_off `ifndef VERILATOR default disable iff (!rst_ni); - aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> - (slv_aw_select_i < NumMstPorts))) else - $fatal(1, "slv_aw_select_i is %d: AW has selected a slave that is not defined.\ - NumMstPorts: %d", slv_aw_select_i, NumMstPorts); - ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |-> - (slv_ar_select_i < NumMstPorts))) else - $fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\ - NumMstPorts: %d", slv_ar_select_i, NumMstPorts); - aw_valid_stable: assert property( @(posedge clk_i) (slv_aw_valid && !slv_aw_ready) - |=> slv_aw_valid) else + aw_select: assume property( @(posedge clk_i) (sbr_req_i.aw_valid |-> + (sbr_aw_select_i < NumMgrPorts))) else + $fatal(1, "sbr_aw_select_i is %d: AW has selected a subordinate that is not defined.\ + NumMgrPorts: %d", sbr_aw_select_i, NumMgrPorts); + ar_select: assume property( @(posedge clk_i) (sbr_req_i.ar_valid |-> + (sbr_ar_select_i < NumMgrPorts))) else + $fatal(1, "sbr_ar_select_i is %d: AR has selected a subordinate that is not defined.\ + NumMgrPorts: %d", sbr_ar_select_i, NumMgrPorts); + aw_valid_stable: assert property( @(posedge clk_i) (sbr_aw_valid && !sbr_aw_ready) + |=> sbr_aw_valid) else $fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle."); - ar_valid_stable: assert property( @(posedge clk_i) (slv_ar_valid && !slv_ar_ready) - |=> slv_ar_valid) else + ar_valid_stable: assert property( @(posedge clk_i) (sbr_ar_valid && !sbr_ar_ready) + |=> sbr_ar_valid) else $fatal(1, "ar_valid was deasserted, when ar_ready = 0 in last cycle."); - aw_stable: assert property( @(posedge clk_i) (slv_aw_valid && !slv_aw_ready) - |=> $stable(slv_aw_chan)) else - $fatal(1, "slv_aw_chan_select unstable with valid set."); - ar_stable: assert property( @(posedge clk_i) (slv_ar_valid && !slv_ar_ready) - |=> $stable(slv_ar_chan)) else - $fatal(1, "slv_aw_chan_select unstable with valid set."); + aw_stable: assert property( @(posedge clk_i) (sbr_aw_valid && !sbr_aw_ready) + |=> $stable(sbr_aw_chan)) else + $fatal(1, "sbr_aw_chan_select unstable with valid set."); + ar_stable: assert property( @(posedge clk_i) (sbr_ar_valid && !sbr_ar_ready) + |=> $stable(sbr_ar_chan)) else + $fatal(1, "sbr_aw_chan_select unstable with valid set."); `endif // pragma translate_on end @@ -470,7 +470,7 @@ module axi_lite_demux #( // pragma translate_off `ifndef VERILATOR initial begin: p_assertions - NumPorts: assert (NumMstPorts > 0) else $fatal("Number of master ports must be at least 1!"); + NumPorts: assert (NumMgrPorts > 0) else $fatal("Number of manager ports must be at least 1!"); MaxTnx: assert (MaxTrans > 0) else $fatal("Number of transactions must be at least 1!"); end `endif @@ -483,7 +483,7 @@ endmodule module axi_lite_demux_intf #( parameter int unsigned AddrWidth = 32'd0, parameter int unsigned DataWidth = 32'd0, - parameter int unsigned NumMstPorts = 32'd0, + parameter int unsigned NumMgrPorts = 32'd0, parameter int unsigned MaxTrans = 32'd0, parameter bit FallThrough = 1'b0, parameter bit SpillAw = 1'b1, @@ -492,15 +492,15 @@ module axi_lite_demux_intf #( parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0, // Dependent parameters, DO NOT OVERRIDE! - parameter type select_t = logic [$clog2(NumMstPorts)-1:0] + parameter type select_t = logic [$clog2(NumMgrPorts)-1:0] ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Testmode enable - input select_t slv_aw_select_i, // has to be stable, when aw_valid - input select_t slv_ar_select_i, // has to be stable, when ar_valid - AXI_LITE.Slave slv, // slave port - AXI_LITE.Master mst [NumMstPorts-1:0]// master ports + input select_t sbr_aw_select_i, // has to be stable, when aw_valid + input select_t sbr_ar_select_i, // has to be stable, when ar_valid + AXI_LITE.Subordinate sbr, // subordinate port + AXI_LITE.Manager mgr [NumMgrPorts-1:0]// manager ports ); typedef logic [AddrWidth-1:0] addr_t; typedef logic [DataWidth-1:0] data_t; @@ -513,17 +513,17 @@ module axi_lite_demux_intf #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - axi_lite_req_t slv_req; - axi_lite_rsp_t slv_rsp; - axi_lite_req_t [NumMstPorts-1:0] mst_reqs; - axi_lite_rsp_t [NumMstPorts-1:0] mst_rsps; + axi_lite_req_t sbr_req; + axi_lite_rsp_t sbr_rsp; + axi_lite_req_t [NumMgrPorts-1:0] mgr_reqs; + axi_lite_rsp_t [NumMgrPorts-1:0] mgr_rsps; - `AXI_LITE_ASSIGN_TO_REQ(slv_req, slv) - `AXI_LITE_ASSIGN_FROM_RSP(slv, slv_rsp) + `AXI_LITE_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_LITE_ASSIGN_FROM_RSP(sbr, sbr_rsp) - for (genvar i = 0; i < NumMstPorts; i++) begin : gen_assign_mst_ports - `AXI_LITE_ASSIGN_FROM_REQ(mst[i], mst_reqs[i]) - `AXI_LITE_ASSIGN_TO_RSP(mst_rsps[i], mst[i]) + for (genvar i = 0; i < NumMgrPorts; i++) begin : gen_assign_mgr_ports + `AXI_LITE_ASSIGN_FROM_REQ(mgr[i], mgr_reqs[i]) + `AXI_LITE_ASSIGN_TO_RSP(mgr_rsps[i], mgr[i]) end axi_lite_demux #( @@ -534,7 +534,7 @@ module axi_lite_demux_intf #( .r_chan_t ( r_chan_t ), .axi_lite_req_t ( axi_lite_req_t ), .axi_lite_rsp_t ( axi_lite_rsp_t ), - .NumMstPorts ( NumMstPorts ), + .NumMgrPorts ( NumMgrPorts ), .MaxTrans ( MaxTrans ), .FallThrough ( FallThrough ), .SpillAw ( SpillAw ), @@ -546,14 +546,14 @@ module axi_lite_demux_intf #( .clk_i, .rst_ni, .test_i, - // slave Port - .slv_req_i ( slv_req ), - .slv_aw_select_i ( slv_aw_select_i ), // must be stable while slv_aw_valid_i - .slv_ar_select_i ( slv_ar_select_i ), // must be stable while slv_ar_valid_i - .slv_rsp_o ( slv_rsp ), - // mster ports - .mst_reqs_o ( mst_reqs ), - .mst_rsps_i ( mst_rsps ) + // subordinate Port + .sbr_req_i ( sbr_req ), + .sbr_aw_select_i ( sbr_aw_select_i ), // must be stable while sbr_aw_valid_i + .sbr_ar_select_i ( sbr_ar_select_i ), // must be stable while sbr_ar_valid_i + .sbr_rsp_o ( sbr_rsp ), + // mgrer ports + .mgr_reqs_o ( mgr_reqs ), + .mgr_rsps_i ( mgr_rsps ) ); // pragma translate_off diff --git a/src/axi_lite_from_mem.sv b/src/axi_lite_from_mem.sv index afaa6cf04..bec817f45 100644 --- a/src/axi_lite_from_mem.sv +++ b/src/axi_lite_from_mem.sv @@ -56,36 +56,36 @@ module axi_lite_from_mem #( input logic clk_i, /// Asynchronous reset, active low. input logic rst_ni, - /// Memory slave port, request is active. + /// Memory subordinate port, request is active. input logic mem_req_i, - /// Memory slave port, request address. + /// Memory subordinate port, request address. /// /// Byte address, will be extended or truncated to match `AddrWidth`. input mem_addr_t mem_addr_i, - /// Memory slave port, request is a write. + /// Memory subordinate port, request is a write. /// /// `0`: Read request. /// `1`: Write request. input logic mem_we_i, /// Memory salve port, write data for request. input data_t mem_wdata_i, - /// Memory slave port, write byte enable for request. + /// Memory subordinate port, write byte enable for request. /// /// Active high. input strb_t mem_be_i, /// Memory request is granted. output logic mem_gnt_o, - /// Memory slave port, response is valid. For each request, regardless if read or write, + /// Memory subordinate port, response is valid. For each request, regardless if read or write, /// this will be active once for one cycle. output logic mem_rsp_valid_o, - /// Memory slave port, response read data. This is forwarded directly from the AXI4-Lite + /// Memory subordinate port, response read data. This is forwarded directly from the AXI4-Lite /// `R` channel. Only valid for responses generated by a read request. output data_t mem_rsp_rdata_o, /// Memory request encountered an error. This is forwarded from the AXI4-Lite error response. output logic mem_rsp_error_o, - /// AXI4-Lite master port, request output. + /// AXI4-Lite manager port, request output. output axi_req_t axi_req_o, - /// AXI4-Lite master port, response input. + /// AXI4-Lite manager port, response input. input axi_rsp_t axi_rsp_i ); `include "common_cells/registers.svh" diff --git a/src/axi_lite_join.sv b/src/axi_lite_join.sv index e7779fbf2..e49dc97af 100644 --- a/src/axi_lite_join.sv +++ b/src/axi_lite_join.sv @@ -17,8 +17,8 @@ /// A connector that joins two AXI-Lite interfaces. module axi_lite_join_intf ( - AXI_LITE.Slave in, - AXI_LITE.Master out + AXI_LITE.Subordinate in, + AXI_LITE.Manager out ); `AXI_LITE_ASSIGN(out, in) diff --git a/src/axi_lite_lfsr.sv b/src/axi_lite_lfsr.sv index bf8e0f5e5..8eb678f5e 100644 --- a/src/axi_lite_lfsr.sv +++ b/src/axi_lite_lfsr.sv @@ -53,7 +53,7 @@ module axi_lite_lfsr #( logic w_lfsr_en; logic r_lfsr_en; - logic w_b_fifo_ready; + logic w_b_fifo_ready, w_b_fifo_valid; // LFSR outputs logic [DataWidth-1:0] w_data_in, w_data_out; diff --git a/src/axi_lite_mailbox.sv b/src/axi_lite_mailbox.sv index 56a10d498..232afa9b4 100644 --- a/src/axi_lite_mailbox.sv +++ b/src/axi_lite_mailbox.sv @@ -12,7 +12,7 @@ // - Wolfgang Roenninger // - Andreas Kurth -// Description: A mailbox with two AXI4-Lite slave ports and associated interrupt requests. +// Description: A mailbox with two AXI4-Lite subordinate ports and associated interrupt requests. // See `doc/axi_lite_mailbox.md` for the documentation, including the definition // of parameters and ports. @@ -32,9 +32,9 @@ module axi_lite_mailbox #( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Testmode enable - // slave ports [1:0] - input axi_lite_req_t [1:0] slv_reqs_i, - output axi_lite_rsp_t [1:0] slv_rsps_o, + // subordinate ports [1:0] + input axi_lite_req_t [1:0] sbr_reqs_i, + output axi_lite_rsp_t [1:0] sbr_rsps_o, output logic [1:0] irq_o, // interrupt output for each port input addr_t [1:0] base_addr_i // base address for each port ); @@ -50,11 +50,11 @@ module axi_lite_mailbox #( logic [1:0] w_mbox_flush, r_mbox_flush; // index is port data_t [1:0] mbox_w_data, mbox_r_data; // index is port usage_t [1:0] mbox_usage; // index is the instantiated mailbox FIFO - // interrupt request from this slave port, level triggered, active high --> convert - logic [1:0] slv_irq; + // interrupt request from this subordinate port, level triggered, active high --> convert + logic [1:0] sbr_irq; logic [1:0] clear_irq; - axi_lite_mailbox_slave #( + axi_lite_mailbox_subordinate #( .MailboxDepth ( MailboxDepth ), .AddrWidth ( AddrWidth ), .DataWidth ( DataWidth ), @@ -63,13 +63,13 @@ module axi_lite_mailbox #( .addr_t ( addr_t ), .data_t ( data_t ), .usage_t ( usage_t ) // fill pointer from MBOX FIFO - ) i_slv_port_0 ( + ) i_sbr_port_0 ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - // slave port - .slv_req_i ( slv_reqs_i[0] ), - .slv_rsp_o ( slv_rsps_o[0] ), - .base_addr_i ( base_addr_i[0] ), // base address for the slave port + // subordinate port + .sbr_req_i ( sbr_reqs_i[0] ), + .sbr_rsp_o ( sbr_rsps_o[0] ), + .base_addr_i ( base_addr_i[0] ), // base address for the subordinate port // write FIFO port .mbox_w_data_o ( mbox_w_data[0] ), .mbox_w_full_i ( mbox_full[0] ), @@ -83,11 +83,11 @@ module axi_lite_mailbox #( .mbox_r_flush_o ( r_mbox_flush[0] ), .mbox_r_usage_i ( mbox_usage[1] ), // interrupt output, level triggered, active high, conversion in top - .irq_o ( slv_irq[0] ), + .irq_o ( sbr_irq[0] ), .clear_irq_o ( clear_irq[0] ) ); - axi_lite_mailbox_slave #( + axi_lite_mailbox_subordinate #( .MailboxDepth ( MailboxDepth ), .AddrWidth ( AddrWidth ), .DataWidth ( DataWidth ), @@ -96,13 +96,13 @@ module axi_lite_mailbox #( .addr_t ( addr_t ), .data_t ( data_t ), .usage_t ( usage_t ) // fill pointer from MBOX FIFO - ) i_slv_port_1 ( + ) i_sbr_port_1 ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - // slave port - .slv_req_i ( slv_reqs_i[1] ), - .slv_rsp_o ( slv_rsps_o[1] ), - .base_addr_i ( base_addr_i[1] ), // base address for the slave port + // subordinate port + .sbr_req_i ( sbr_reqs_i[1] ), + .sbr_rsp_o ( sbr_rsps_o[1] ), + .base_addr_i ( base_addr_i[1] ), // base address for the subordinate port // write FIFO port .mbox_w_data_o ( mbox_w_data[1] ), .mbox_w_full_i ( mbox_full[1] ), @@ -116,7 +116,7 @@ module axi_lite_mailbox #( .mbox_r_flush_o ( r_mbox_flush[1] ), .mbox_r_usage_i ( mbox_usage[0] ), // interrupt output, level triggered, active high, conversion in top - .irq_o ( slv_irq[1] ), + .irq_o ( sbr_irq[1] ), .clear_irq_o ( clear_irq[1] ) ); @@ -174,7 +174,7 @@ module axi_lite_mailbox #( if (clear_irq[i]) begin irq_d = 1'b0; update_irq = 1'b1; - end else if (!irq_q && slv_irq[i]) begin + end else if (!irq_q && sbr_irq[i]) begin irq_d = 1'b1; update_irq = 1'b1; irq_o[i] = IrqActHigh; // on update of the register pulse the irq signal @@ -183,7 +183,7 @@ module axi_lite_mailbox #( `FFLARN(irq_q, irq_d, update_irq, '0, clk_i, rst_ni) end else begin : gen_irq_level - assign irq_o[i] = (IrqActHigh) ? slv_irq[i] : ~slv_irq[i]; + assign irq_o[i] = (IrqActHigh) ? sbr_irq[i] : ~sbr_irq[i]; end end @@ -200,8 +200,8 @@ endmodule `include "axi/typedef.svh" -// slave port module -module axi_lite_mailbox_slave #( +// subordinate port module +module axi_lite_mailbox_subordinate #( parameter int unsigned MailboxDepth = 32'd16, parameter int unsigned AddrWidth = 32'd32, parameter int unsigned DataWidth = 32'd32, @@ -213,10 +213,10 @@ module axi_lite_mailbox_slave #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - // slave port - input axi_lite_req_t slv_req_i, - output axi_lite_rsp_t slv_rsp_o, - input addr_t base_addr_i, // base address for the slave port + // subordinate port + input axi_lite_req_t sbr_req_i, + output axi_lite_rsp_t sbr_rsp_o, + input addr_t base_addr_i, // base address for the subordinate port // write FIFO port output data_t mbox_w_data_o, input logic mbox_w_full_i, @@ -300,7 +300,7 @@ module axi_lite_mailbox_slave #( // Mailbox FIFO data assignments for (genvar i = 0; i < (DataWidth/8); i++) begin : gen_w_mbox_data - assign mbox_w_data_o[i*8+:8] = slv_req_i.w.strb[i] ? slv_req_i.w.data[i*8+:8] : '0; + assign mbox_w_data_o[i*8+:8] = sbr_req_i.w.strb[i] ? sbr_req_i.w.data[i*8+:8] : '0; end // combinational mailbox register assignments, for the read only registers @@ -313,12 +313,12 @@ module axi_lite_mailbox_slave #( assign irq_o = |irqp_q; // generate an active-high level irq always_comb begin - // slave port channel outputs for the AW, W and R channel, other driven from spill register - slv_rsp_o.aw_ready = 1'b0; - slv_rsp_o.w_ready = 1'b0; + // subordinate port channel outputs for the AW, W and R channel, other driven from spill register + sbr_rsp_o.aw_ready = 1'b0; + sbr_rsp_o.w_ready = 1'b0; b_chan = '{resp: axi_pkg::RESP_SLVERR}; b_valid = 1'b0; - slv_rsp_o.ar_ready = 1'b0; + sbr_rsp_o.ar_ready = 1'b0; r_chan = '{data: '0, resp: axi_pkg::RESP_SLVERR}; r_valid = 1'b0; // Default assignments for the internal registers @@ -360,11 +360,11 @@ module axi_lite_mailbox_slave #( // it will generate a new irq when it is edge triggered, or the level will stay at its // active state. - // Check if there is a pending read request on the slave port. - if (slv_req_i.ar_valid) begin + // Check if there is a pending read request on the subordinate port. + if (sbr_req_i.ar_valid) begin // set the right read channel output depending on the address decoding if (dec_r_valid) begin - // when decode not valid, send the default slaveerror + // when decode not valid, send the default subordinateerror // read the right register when the transfer happens and decode is valid unique case (reg_e'(r_reg_idx)) MBOXW: r_chan = '{data: data_t'( 32'hFEEDC0DE ), resp: axi_pkg::RESP_OKAY}; @@ -397,7 +397,7 @@ module axi_lite_mailbox_slave #( end r_valid = 1'b1; if (r_ready) begin - slv_rsp_o.ar_ready = 1'b1; + sbr_rsp_o.ar_ready = 1'b1; end end // read register @@ -405,7 +405,7 @@ module axi_lite_mailbox_slave #( // Write registers // ------------------------------------------- // Wait for control and write data to be valid. - if (slv_req_i.aw_valid && slv_req_i.w_valid) begin + if (sbr_req_i.aw_valid && sbr_req_i.w_valid) begin // Can do the handshake here as the b response goes into a spill register with latency one. // Without the B spill register, the B channel would violate the AXI stable requirement. b_valid = 1'b1; @@ -429,7 +429,7 @@ module axi_lite_mailbox_slave #( // ERROR: read only WIRQT: begin for (int unsigned i = 0; i < DataWidth/8; i++) begin - wirqt_d[i*8+:8] = slv_req_i.w.strb[i] ? slv_req_i.w.data[i*8+:8] : 8'b0000_0000; + wirqt_d[i*8+:8] = sbr_req_i.w.strb[i] ? sbr_req_i.w.data[i*8+:8] : 8'b0000_0000; end if (wirqt_d >= data_t'(MailboxDepth)) begin // the `-1` is to have the interrupt fireing when the FIFO is comletely full @@ -440,7 +440,7 @@ module axi_lite_mailbox_slave #( end RIRQT: begin for (int unsigned i = 0; i < DataWidth/8; i++) begin - rirqt_d[i*8+:8] = slv_req_i.w.strb[i] ? slv_req_i.w.data[i*8+:8] : 8'b0000_0000; + rirqt_d[i*8+:8] = sbr_req_i.w.strb[i] ? sbr_req_i.w.data[i*8+:8] : 8'b0000_0000; end if (rirqt_d >= data_t'(MailboxDepth)) begin // Threshold to maximal value, minus two to prevent overflow in usage @@ -451,37 +451,37 @@ module axi_lite_mailbox_slave #( end IRQS: begin // Acknowledge and clear the register by asserting the respective one - if (slv_req_i.w.strb[0]) begin + if (sbr_req_i.w.strb[0]) begin // *_d signal is set in the beginning of this process, prevent accidental // overwrite of not acknowledged irq - irqs_d[2] = slv_req_i.w.data[2] ? 1'b0 : irqs_d[2]; // Error irq status - irqs_d[1] = slv_req_i.w.data[1] ? 1'b0 : irqs_d[1]; // Read irq status - irqs_d[0] = slv_req_i.w.data[0] ? 1'b0 : irqs_d[0]; // Write irq status + irqs_d[2] = sbr_req_i.w.data[2] ? 1'b0 : irqs_d[2]; // Error irq status + irqs_d[1] = sbr_req_i.w.data[1] ? 1'b0 : irqs_d[1]; // Read irq status + irqs_d[0] = sbr_req_i.w.data[0] ? 1'b0 : irqs_d[0]; // Write irq status clear_irq_o = 1'b1; update_regs = 1'b1; end b_chan = '{resp: axi_pkg::RESP_OKAY}; end IRQEN: begin - if (slv_req_i.w.strb[0]) begin - irqen_d[2:0] = slv_req_i.w.data[2:0]; // set the irq enable bits + if (sbr_req_i.w.strb[0]) begin + irqen_d[2:0] = sbr_req_i.w.data[2:0]; // set the irq enable bits update_regs = 1'b1; end b_chan = '{resp: axi_pkg::RESP_OKAY}; end // IRQP: read only CTRL: begin - if (slv_req_i.w.strb[0]) begin - mbox_r_flush_o = slv_req_i.w.data[1]; // Flush read FIFO - mbox_w_flush_o = slv_req_i.w.data[0]; // Flush write FIFO + if (sbr_req_i.w.strb[0]) begin + mbox_r_flush_o = sbr_req_i.w.data[1]; // Flush read FIFO + mbox_w_flush_o = sbr_req_i.w.data[0]; // Flush write FIFO end b_chan = '{resp: axi_pkg::RESP_OKAY}; end default : /* use default b_chan */; endcase end - slv_rsp_o.aw_ready = 1'b1; - slv_rsp_o.w_ready = 1'b1; + sbr_rsp_o.aw_ready = 1'b1; + sbr_rsp_o.w_ready = 1'b1; end // if (b_ready): Does not violate AXI spec, because the ready comes from an internal // spill register and does not propagate the ready from the b channel. end // write register @@ -495,7 +495,7 @@ module axi_lite_mailbox_slave #( .addr_t ( addr_t ), .rule_t ( rule_t ) ) i_waddr_decode ( - .addr_i ( slv_req_i.aw.addr ), + .addr_i ( sbr_req_i.aw.addr ), .addr_map_i ( addr_map ), .idx_o ( w_reg_idx ), .dec_valid_o ( dec_w_valid ), @@ -511,9 +511,9 @@ module axi_lite_mailbox_slave #( .valid_i ( b_valid ), .ready_o ( b_ready ), .data_i ( b_chan ), - .valid_o ( slv_rsp_o.b_valid ), - .ready_i ( slv_req_i.b_ready ), - .data_o ( slv_rsp_o.b ) + .valid_o ( sbr_rsp_o.b_valid ), + .ready_i ( sbr_req_i.b_ready ), + .data_o ( sbr_rsp_o.b ) ); addr_decode #( .NoIndices( NumRegs ), @@ -521,7 +521,7 @@ module axi_lite_mailbox_slave #( .addr_t ( addr_t ), .rule_t ( rule_t ) ) i_raddr_decode ( - .addr_i ( slv_req_i.ar.addr ), + .addr_i ( sbr_req_i.ar.addr ), .addr_map_i ( addr_map ), .idx_o ( r_reg_idx ), .dec_valid_o ( dec_r_valid ), @@ -537,17 +537,17 @@ module axi_lite_mailbox_slave #( .valid_i ( r_valid ), .ready_o ( r_ready ), .data_i ( r_chan ), - .valid_o ( slv_rsp_o.r_valid ), - .ready_i ( slv_req_i.r_ready ), - .data_o ( slv_rsp_o.r ) + .valid_o ( sbr_rsp_o.r_valid ), + .ready_i ( sbr_req_i.r_ready ), + .data_o ( sbr_rsp_o.r ) ); // pragma translate_off `ifndef VERILATOR initial begin : proc_check_params - assert (AddrWidth == $bits(slv_req_i.aw.addr)) else $fatal(1, "AW AddrWidth mismatch"); - assert (DataWidth == $bits(slv_req_i.w.data)) else $fatal(1, " W DataWidth mismatch"); - assert (AddrWidth == $bits(slv_req_i.ar.addr)) else $fatal(1, "AR AddrWidth mismatch"); - assert (DataWidth == $bits(slv_rsp_o.r.data)) else $fatal(1, " R DataWidth mismatch"); + assert (AddrWidth == $bits(sbr_req_i.aw.addr)) else $fatal(1, "AW AddrWidth mismatch"); + assert (DataWidth == $bits(sbr_req_i.w.data)) else $fatal(1, " W DataWidth mismatch"); + assert (AddrWidth == $bits(sbr_req_i.ar.addr)) else $fatal(1, "AR AddrWidth mismatch"); + assert (DataWidth == $bits(sbr_rsp_o.r.data)) else $fatal(1, " R DataWidth mismatch"); end `endif // pragma translate_on @@ -567,7 +567,7 @@ module axi_lite_mailbox_intf #( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Testmode enable - AXI_LITE.Slave slv [1:0], // slave ports [1:0] + AXI_LITE.Subordinate sbr [1:0], // subordinate ports [1:0] output logic [1:0] irq_o, // interrupt output for each port input addr_t [1:0] base_addr_i // base address for each port ); @@ -581,12 +581,12 @@ module axi_lite_mailbox_intf #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_lite_t, r_chan_lite_t) - axi_lite_req_t [1:0] slv_reqs; - axi_lite_rsp_t [1:0] slv_rsps; + axi_lite_req_t [1:0] sbr_reqs; + axi_lite_rsp_t [1:0] sbr_rsps; for (genvar i = 0; i < 2; i++) begin : gen_port_assign - `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) - `AXI_LITE_ASSIGN_FROM_RSP(slv[i], slv_rsps[i]) + `AXI_LITE_ASSIGN_TO_REQ(sbr_reqs[i], sbr[i]) + `AXI_LITE_ASSIGN_FROM_RSP(sbr[i], sbr_rsps[i]) end axi_lite_mailbox #( @@ -601,9 +601,9 @@ module axi_lite_mailbox_intf #( .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Testmode enable - // slave ports [1:0] - .slv_reqs_i ( slv_reqs ), - .slv_rsps_o ( slv_rsps ), + // subordinate ports [1:0] + .sbr_reqs_i ( sbr_reqs ), + .sbr_rsps_o ( sbr_rsps ), .irq_o, // interrupt output for each port .base_addr_i // base address for each port ); @@ -611,13 +611,13 @@ module axi_lite_mailbox_intf #( // pragma translate_off `ifndef VERILATOR initial begin - assert (slv[0].AXI_ADDR_WIDTH == AXI_ADDR_WIDTH) + assert (sbr[0].AXI_ADDR_WIDTH == AXI_ADDR_WIDTH) else $fatal(1, "LITE Interface [0] AXI_ADDR_WIDTH missmatch!"); - assert (slv[1].AXI_ADDR_WIDTH == AXI_ADDR_WIDTH) + assert (sbr[1].AXI_ADDR_WIDTH == AXI_ADDR_WIDTH) else $fatal(1, "LITE Interface [1] AXI_ADDR_WIDTH missmatch!"); - assert (slv[0].AXI_DATA_WIDTH == AXI_DATA_WIDTH) + assert (sbr[0].AXI_DATA_WIDTH == AXI_DATA_WIDTH) else $fatal(1, "LITE Interface [0] AXI_DATA_WIDTH missmatch!"); - assert (slv[1].AXI_DATA_WIDTH == AXI_DATA_WIDTH) + assert (sbr[1].AXI_DATA_WIDTH == AXI_DATA_WIDTH) else $fatal(1, "LITE Interface [1] AXI_DATA_WIDTH missmatch!"); end `endif diff --git a/src/axi_lite_mux.sv b/src/axi_lite_mux.sv index 7d0cb477e..3f87b80c9 100644 --- a/src/axi_lite_mux.sv +++ b/src/axi_lite_mux.sv @@ -13,7 +13,7 @@ // - Wolfgang Roenninger // - Andreas Kurth -// AXI4-Lite Multiplexer: This module multiplexes the AXI4-Lite slave ports down to one master port. +// AXI4-Lite Multiplexer: This module multiplexes the AXI4-Lite subordinate ports down to one manager port. // The multiplexing happens in a round robin fashion, responses get // sent back in order. @@ -29,43 +29,43 @@ module axi_lite_mux #( parameter type r_chan_t = logic, // R LITE Channel Type parameter type axi_lite_req_t = logic, // AXI4-Lite request type parameter type axi_lite_rsp_t = logic, // AXI4-Lite response type - parameter int unsigned NumSlvPorts = 32'd0, // Number of slave ports + parameter int unsigned NumSbrPorts = 32'd0, // Number of subordinate ports // Maximum number of outstanding transactions per write or read parameter int unsigned MaxTrans = 32'd0, // If enabled, this multiplexer is purely combinatorial parameter bit FallThrough = 1'b0, - // add spill register on write master port, adds a cycle latency on write channels + // add spill register on write manager port, adds a cycle latency on write channels parameter bit SpillAw = 1'b1, parameter bit SpillW = 1'b0, parameter bit SpillB = 1'b0, - // add spill register on read master port, adds a cycle latency on read channels + // add spill register on read manager port, adds a cycle latency on read channels parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0 ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Test Mode enable - // slave ports (AXI4-Lite inputs), connect master modules here - input axi_lite_req_t [NumSlvPorts-1:0] slv_reqs_i, - output axi_lite_rsp_t [NumSlvPorts-1:0] slv_rsps_o, - // master port (AXI4-Lite output), connect slave module here - output axi_lite_req_t mst_req_o, - input axi_lite_rsp_t mst_rsp_i + // subordinate ports (AXI4-Lite inputs), connect manager modules here + input axi_lite_req_t [NumSbrPorts-1:0] sbr_reqs_i, + output axi_lite_rsp_t [NumSbrPorts-1:0] sbr_rsps_o, + // manager port (AXI4-Lite output), connect subordinate module here + output axi_lite_req_t mgr_req_o, + input axi_lite_rsp_t mgr_rsp_i ); - // pass through if only one slave port - if (NumSlvPorts == 32'h1) begin : gen_no_mux + // pass through if only one subordinate port + if (NumSbrPorts == 32'h1) begin : gen_no_mux spill_register #( .T ( aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_reqs_i[0].aw_valid ), - .ready_o ( slv_rsps_o[0].aw_ready ), - .data_i ( slv_reqs_i[0].aw ), - .valid_o ( mst_req_o.aw_valid ), - .ready_i ( mst_rsp_i.aw_ready ), - .data_o ( mst_req_o.aw ) + .valid_i ( sbr_reqs_i[0].aw_valid ), + .ready_o ( sbr_rsps_o[0].aw_ready ), + .data_i ( sbr_reqs_i[0].aw ), + .valid_o ( mgr_req_o.aw_valid ), + .ready_i ( mgr_rsp_i.aw_ready ), + .data_o ( mgr_req_o.aw ) ); spill_register #( .T ( w_chan_t ), @@ -73,12 +73,12 @@ module axi_lite_mux #( ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_reqs_i[0].w_valid ), - .ready_o ( slv_rsps_o[0].w_ready ), - .data_i ( slv_reqs_i[0].w ), - .valid_o ( mst_req_o.w_valid ), - .ready_i ( mst_rsp_i.w_ready ), - .data_o ( mst_req_o.w ) + .valid_i ( sbr_reqs_i[0].w_valid ), + .ready_o ( sbr_rsps_o[0].w_ready ), + .data_i ( sbr_reqs_i[0].w ), + .valid_o ( mgr_req_o.w_valid ), + .ready_i ( mgr_rsp_i.w_ready ), + .data_o ( mgr_req_o.w ) ); spill_register #( .T ( b_chan_t ), @@ -86,12 +86,12 @@ module axi_lite_mux #( ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsp_i.b_valid ), - .ready_o ( mst_req_o.b_ready ), - .data_i ( mst_rsp_i.b ), - .valid_o ( slv_rsps_o[0].b_valid ), - .ready_i ( slv_reqs_i[0].b_ready ), - .data_o ( slv_rsps_o[0].b ) + .valid_i ( mgr_rsp_i.b_valid ), + .ready_o ( mgr_req_o.b_ready ), + .data_i ( mgr_rsp_i.b ), + .valid_o ( sbr_rsps_o[0].b_valid ), + .ready_i ( sbr_reqs_i[0].b_ready ), + .data_o ( sbr_rsps_o[0].b ) ); spill_register #( .T ( ar_chan_t ), @@ -99,12 +99,12 @@ module axi_lite_mux #( ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_reqs_i[0].ar_valid ), - .ready_o ( slv_rsps_o[0].ar_ready ), - .data_i ( slv_reqs_i[0].ar ), - .valid_o ( mst_req_o.ar_valid ), - .ready_i ( mst_rsp_i.ar_ready ), - .data_o ( mst_req_o.ar ) + .valid_i ( sbr_reqs_i[0].ar_valid ), + .ready_o ( sbr_rsps_o[0].ar_ready ), + .data_i ( sbr_reqs_i[0].ar ), + .valid_o ( mgr_req_o.ar_valid ), + .ready_i ( mgr_rsp_i.ar_ready ), + .data_o ( mgr_req_o.ar ) ); spill_register #( .T ( r_chan_t ), @@ -112,29 +112,29 @@ module axi_lite_mux #( ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsp_i.r_valid ), - .ready_o ( mst_req_o.r_ready ), - .data_i ( mst_rsp_i.r ), - .valid_o ( slv_rsps_o[0].r_valid ), - .ready_i ( slv_reqs_i[0].r_ready ), - .data_o ( slv_rsps_o[0].r ) + .valid_i ( mgr_rsp_i.r_valid ), + .ready_o ( mgr_req_o.r_ready ), + .data_i ( mgr_rsp_i.r ), + .valid_o ( sbr_rsps_o[0].r_valid ), + .ready_i ( sbr_reqs_i[0].r_ready ), + .data_o ( sbr_rsps_o[0].r ) ); // other non degenerate cases end else begin : gen_mux // typedef for the FIFO types - typedef logic [$clog2(NumSlvPorts)-1:0] select_t; + typedef logic [$clog2(NumSbrPorts)-1:0] select_t; // input to the AW arbitration tree, unpacked from request struct - aw_chan_t [NumSlvPorts-1:0] slv_aw_chans; - logic [NumSlvPorts-1:0] slv_aw_valids, slv_aw_readies; + aw_chan_t [NumSbrPorts-1:0] sbr_aw_chans; + logic [NumSbrPorts-1:0] sbr_aw_valids, sbr_aw_readies; // AW channel arb tree decision select_t aw_select; - aw_chan_t mst_aw_chan; - logic mst_aw_valid, mst_aw_ready; + aw_chan_t mgr_aw_chan; + logic mgr_aw_valid, mgr_aw_ready; - // AW master handshake internal, so that we are able to stall, if w_fifo is full + // AW manager handshake internal, so that we are able to stall, if w_fifo is full logic aw_valid, aw_ready; // FF to lock the AW valid signal, when a new arbitration decision is made the decision @@ -149,8 +149,8 @@ module axi_lite_mux #( // W channel spill reg select_t w_select; - w_chan_t mst_w_chan; - logic mst_w_valid, mst_w_ready; + w_chan_t mgr_w_chan; + logic mgr_w_valid, mgr_w_ready; // switching decision for the B response back routing select_t b_select; @@ -159,22 +159,22 @@ module axi_lite_mux #( logic /*w_fifo_pop*/b_fifo_pop; // B channel spill reg - b_chan_t mst_b_chan; - logic mst_b_valid, mst_b_ready; + b_chan_t mgr_b_chan; + logic mgr_b_valid, mgr_b_ready; // input to the AR arbitration tree, unpacked from request struct - ar_chan_t [NumSlvPorts-1:0] slv_ar_chans; - logic [NumSlvPorts-1:0] slv_ar_valids, slv_ar_readies; + ar_chan_t [NumSbrPorts-1:0] sbr_ar_chans; + logic [NumSbrPorts-1:0] sbr_ar_valids, sbr_ar_readies; // AR channel for when spill is enabled select_t ar_select; - ar_chan_t mst_ar_chan; - logic mst_ar_valid, mst_ar_ready; + ar_chan_t mgr_ar_chan; + logic mgr_ar_valid, mgr_ar_ready; - // AR master handshake internal, so that we are able to stall, if R_fifo is full + // AR manager handshake internal, so that we are able to stall, if R_fifo is full logic ar_valid, ar_ready; - // master ID in the r_id + // manager ID in the r_id select_t r_select; // signals for the FIFO that holds the last switching decision of the AR channel @@ -182,20 +182,20 @@ module axi_lite_mux #( logic r_fifo_push, r_fifo_pop; // R channel spill reg - r_chan_t mst_r_chan; - logic mst_r_valid, mst_r_ready; + r_chan_t mgr_r_chan; + logic mgr_r_valid, mgr_r_ready; //-------------------------------------- // AW Channel //-------------------------------------- // unpach AW channel from request/response array - for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_aw_arb_input - assign slv_aw_chans[i] = slv_reqs_i[i].aw; - assign slv_aw_valids[i] = slv_reqs_i[i].aw_valid; - assign slv_rsps_o[i].aw_ready = slv_aw_readies[i]; + for (genvar i = 0; i < NumSbrPorts; i++) begin : gen_aw_arb_input + assign sbr_aw_chans[i] = sbr_reqs_i[i].aw; + assign sbr_aw_valids[i] = sbr_reqs_i[i].aw_valid; + assign sbr_rsps_o[i].aw_ready = sbr_aw_readies[i]; end rr_arb_tree #( - .NumIn ( NumSlvPorts ), + .NumIn ( NumSbrPorts ), .DataType ( aw_chan_t ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) @@ -204,12 +204,12 @@ module axi_lite_mux #( .rst_ni ( rst_ni ), .flush_i( 1'b0 ), .rr_i ( '0 ), - .req_i ( slv_aw_valids ), - .gnt_o ( slv_aw_readies ), - .data_i ( slv_aw_chans ), + .req_i ( sbr_aw_valids ), + .gnt_o ( sbr_aw_readies ), + .data_i ( sbr_aw_chans ), .gnt_i ( aw_ready ), .req_o ( aw_valid ), - .data_o ( mst_aw_chan ), + .data_o ( mgr_aw_chan ), .idx_o ( aw_select ) ); @@ -219,22 +219,22 @@ module axi_lite_mux #( lock_aw_valid_d = lock_aw_valid_q; load_aw_lock = 1'b0; w_fifo_push = 1'b0; - mst_aw_valid = 1'b0; + mgr_aw_valid = 1'b0; aw_ready = 1'b0; // had a downstream stall, be valid and send the AW along if (lock_aw_valid_q) begin - mst_aw_valid = 1'b1; + mgr_aw_valid = 1'b1; // transaction - if (mst_aw_ready) begin + if (mgr_aw_ready) begin aw_ready = 1'b1; lock_aw_valid_d = 1'b0; load_aw_lock = 1'b1; end end else begin if (!w_fifo_full && aw_valid) begin - mst_aw_valid = 1'b1; + mgr_aw_valid = 1'b1; w_fifo_push = 1'b1; - if (mst_aw_ready) begin + if (mgr_aw_ready) begin aw_ready = 1'b1; end else begin // go to lock if transaction not in this cycle @@ -271,25 +271,25 @@ module axi_lite_mux #( ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_aw_valid ), - .ready_o ( mst_aw_ready ), - .data_i ( mst_aw_chan ), - .valid_o ( mst_req_o.aw_valid ), - .ready_i ( mst_rsp_i.aw_ready ), - .data_o ( mst_req_o.aw ) + .valid_i ( mgr_aw_valid ), + .ready_o ( mgr_aw_ready ), + .data_i ( mgr_aw_chan ), + .valid_o ( mgr_req_o.aw_valid ), + .ready_i ( mgr_rsp_i.aw_ready ), + .data_o ( mgr_req_o.aw ) ); //-------------------------------------- // W Channel //-------------------------------------- // multiplexer - assign mst_w_chan = slv_reqs_i[w_select].w; - assign mst_w_valid = (!w_fifo_empty && !b_fifo_full) ? slv_reqs_i[w_select].w_valid : 1'b0; - for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_slv_w_ready - assign slv_rsps_o[i].w_ready = mst_w_ready & ~w_fifo_empty & + assign mgr_w_chan = sbr_reqs_i[w_select].w; + assign mgr_w_valid = (!w_fifo_empty && !b_fifo_full) ? sbr_reqs_i[w_select].w_valid : 1'b0; + for (genvar i = 0; i < NumSbrPorts; i++) begin : gen_sbr_w_ready + assign sbr_rsps_o[i].w_ready = mgr_w_ready & ~w_fifo_empty & ~b_fifo_full & (w_select == select_t'(i)); end - assign w_fifo_pop = mst_w_valid & mst_w_ready; + assign w_fifo_pop = mgr_w_valid & mgr_w_ready; fifo_v3 #( .FALL_THROUGH ( FallThrough ), @@ -315,24 +315,24 @@ module axi_lite_mux #( ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_w_valid ), - .ready_o ( mst_w_ready ), - .data_i ( mst_w_chan ), - .valid_o ( mst_req_o.w_valid ), - .ready_i ( mst_rsp_i.w_ready ), - .data_o ( mst_req_o.w ) + .valid_i ( mgr_w_valid ), + .ready_o ( mgr_w_ready ), + .data_i ( mgr_w_chan ), + .valid_o ( mgr_req_o.w_valid ), + .ready_i ( mgr_rsp_i.w_ready ), + .data_o ( mgr_req_o.w ) ); //-------------------------------------- // B Channel //-------------------------------------- // replicate B channels - for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_slv_rsps_b - assign slv_rsps_o[i].b = mst_b_chan; - assign slv_rsps_o[i].b_valid = mst_b_valid & ~b_fifo_empty & (b_select == select_t'(i)); + for (genvar i = 0; i < NumSbrPorts; i++) begin : gen_sbr_resps_b + assign sbr_rsps_o[i].b = mgr_b_chan; + assign sbr_rsps_o[i].b_valid = mgr_b_valid & ~b_fifo_empty & (b_select == select_t'(i)); end - assign mst_b_ready = ~b_fifo_empty & slv_reqs_i[b_select].b_ready; - assign b_fifo_pop = mst_b_valid & mst_b_ready; + assign mgr_b_ready = ~b_fifo_empty & sbr_reqs_i[b_select].b_ready; + assign b_fifo_pop = mgr_b_valid & mgr_b_ready; spill_register #( .T ( b_chan_t ), @@ -340,25 +340,25 @@ module axi_lite_mux #( ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsp_i.b_valid ), - .ready_o ( mst_req_o.b_ready ), - .data_i ( mst_rsp_i.b ), - .valid_o ( mst_b_valid ), - .ready_i ( mst_b_ready ), - .data_o ( mst_b_chan ) + .valid_i ( mgr_rsp_i.b_valid ), + .ready_o ( mgr_req_o.b_ready ), + .data_i ( mgr_rsp_i.b ), + .valid_o ( mgr_b_valid ), + .ready_i ( mgr_b_ready ), + .data_o ( mgr_b_chan ) ); //-------------------------------------- // AR Channel //-------------------------------------- // unpack AR channel from request/response struct - for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_ar_arb_input - assign slv_ar_chans[i] = slv_reqs_i[i].ar; - assign slv_ar_valids[i] = slv_reqs_i[i].ar_valid; - assign slv_rsps_o[i].ar_ready = slv_ar_readies[i]; + for (genvar i = 0; i < NumSbrPorts; i++) begin : gen_ar_arb_input + assign sbr_ar_chans[i] = sbr_reqs_i[i].ar; + assign sbr_ar_valids[i] = sbr_reqs_i[i].ar_valid; + assign sbr_rsps_o[i].ar_ready = sbr_ar_readies[i]; end rr_arb_tree #( - .NumIn ( NumSlvPorts ), + .NumIn ( NumSbrPorts ), .DataType ( ar_chan_t ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) @@ -367,20 +367,20 @@ module axi_lite_mux #( .rst_ni ( rst_ni ), .flush_i( 1'b0 ), .rr_i ( '0 ), - .req_i ( slv_ar_valids ), - .gnt_o ( slv_ar_readies ), - .data_i ( slv_ar_chans ), + .req_i ( sbr_ar_valids ), + .gnt_o ( sbr_ar_readies ), + .data_i ( sbr_ar_chans ), .gnt_i ( ar_ready ), .req_o ( ar_valid ), - .data_o ( mst_ar_chan ), + .data_o ( mgr_ar_chan ), .idx_o ( ar_select ) ); // connect the handshake if there is space in the FIFO, no need for valid locking // as the R response is only allowed, when AR is transferred - assign mst_ar_valid = (!r_fifo_full) ? ar_valid : 1'b0; - assign ar_ready = (!r_fifo_full) ? mst_ar_ready : 1'b0; - assign r_fifo_push = mst_ar_valid & mst_ar_ready; + assign mgr_ar_valid = (!r_fifo_full) ? ar_valid : 1'b0; + assign ar_ready = (!r_fifo_full) ? mgr_ar_ready : 1'b0; + assign r_fifo_push = mgr_ar_valid & mgr_ar_ready; fifo_v3 #( .FALL_THROUGH ( FallThrough ), @@ -406,24 +406,24 @@ module axi_lite_mux #( ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_ar_valid ), - .ready_o ( mst_ar_ready ), - .data_i ( mst_ar_chan ), - .valid_o ( mst_req_o.ar_valid ), - .ready_i ( mst_rsp_i.ar_ready ), - .data_o ( mst_req_o.ar ) + .valid_i ( mgr_ar_valid ), + .ready_o ( mgr_ar_ready ), + .data_i ( mgr_ar_chan ), + .valid_o ( mgr_req_o.ar_valid ), + .ready_i ( mgr_rsp_i.ar_ready ), + .data_o ( mgr_req_o.ar ) ); //-------------------------------------- // R Channel //-------------------------------------- // replicate R channels - for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_slv_rsps_r - assign slv_rsps_o[i].r = mst_r_chan; - assign slv_rsps_o[i].r_valid = mst_r_valid & ~r_fifo_empty & (r_select == select_t'(i)); + for (genvar i = 0; i < NumSbrPorts; i++) begin : gen_sbr_rsps_r + assign sbr_rsps_o[i].r = mgr_r_chan; + assign sbr_rsps_o[i].r_valid = mgr_r_valid & ~r_fifo_empty & (r_select == select_t'(i)); end - assign mst_r_ready = ~r_fifo_empty & slv_reqs_i[r_select].r_ready; - assign r_fifo_pop = mst_r_valid & mst_r_ready; + assign mgr_r_ready = ~r_fifo_empty & sbr_reqs_i[r_select].r_ready; + assign r_fifo_pop = mgr_r_valid & mgr_r_ready; spill_register #( .T ( r_chan_t ), @@ -431,19 +431,19 @@ module axi_lite_mux #( ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsp_i.r_valid ), - .ready_o ( mst_req_o.r_ready ), - .data_i ( mst_rsp_i.r ), - .valid_o ( mst_r_valid ), - .ready_i ( mst_r_ready ), - .data_o ( mst_r_chan ) + .valid_i ( mgr_rsp_i.r_valid ), + .ready_o ( mgr_req_o.r_ready ), + .data_i ( mgr_rsp_i.r ), + .valid_o ( mgr_r_valid ), + .ready_i ( mgr_r_ready ), + .data_o ( mgr_r_chan ) ); end // pragma translate_off `ifndef VERILATOR initial begin: p_assertions - NumPorts: assert (NumSlvPorts > 0) else $fatal("Number of slave ports must be at least 1!"); + NumPorts: assert (NumSbrPorts > 0) else $fatal("Number of subordinate ports must be at least 1!"); MaxTnx: assert (MaxTrans > 0) else $fatal("Number of transactions must be at least 1!"); end `endif @@ -457,24 +457,24 @@ endmodule module axi_lite_mux_intf #( parameter int unsigned AddrWidth = 32'd0, parameter int unsigned DataWidth = 32'd0, - parameter int unsigned NumSlvPorts = 32'd0, // Number of slave ports + parameter int unsigned NumSbrPorts = 32'd0, // Number of subordinate ports // Maximum number of outstanding transactions per write parameter int unsigned MaxTrans = 32'd0, // if enabled, this multiplexer is purely combinatorial parameter bit FallThrough = 1'b0, - // add spill register on write master ports, adds a cycle latency on write channels + // add spill register on write manager ports, adds a cycle latency on write channels parameter bit SpillAw = 1'b1, parameter bit SpillW = 1'b0, parameter bit SpillB = 1'b0, - // add spill register on read master ports, adds a cycle latency on read channels + // add spill register on read manager ports, adds a cycle latency on read channels parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0 ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Testmode enable - AXI_LITE.Slave slv [NumSlvPorts-1:0], // slave ports - AXI_LITE.Master mst // master port + AXI_LITE.Subordinate sbr [NumSbrPorts-1:0], // subordinate ports + AXI_LITE.Manager mgr // manager port ); typedef logic [AddrWidth-1:0] addr_t; @@ -489,18 +489,18 @@ module axi_lite_mux_intf #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - axi_lite_req_t [NumSlvPorts-1:0] slv_reqs; - axi_lite_rsp_t [NumSlvPorts-1:0] slv_rsps; - axi_lite_req_t mst_req; - axi_lite_rsp_t mst_rsp; + axi_lite_req_t [NumSbrPorts-1:0] sbr_reqs; + axi_lite_rsp_t [NumSbrPorts-1:0] sbr_rsps; + axi_lite_req_t mgr_req; + axi_lite_rsp_t mgr_rsp; - for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_assign_slv_ports - `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) - `AXI_LITE_ASSIGN_FROM_RSP(slv[i], slv_rsps[i]) + for (genvar i = 0; i < NumSbrPorts; i++) begin : gen_assign_sbr_ports + `AXI_LITE_ASSIGN_TO_REQ(sbr_reqs[i], sbr[i]) + `AXI_LITE_ASSIGN_FROM_RSP(sbr[i], sbr_rsps[i]) end - `AXI_LITE_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_LITE_ASSIGN_TO_RSP(mst_rsp, mst) + `AXI_LITE_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_LITE_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_lite_mux #( .aw_chan_t ( aw_chan_t ), // AW Channel Type @@ -510,7 +510,7 @@ module axi_lite_mux_intf #( .r_chan_t ( r_chan_t ), // R Channel Type .axi_lite_req_t ( axi_lite_req_t ), .axi_lite_rsp_t ( axi_lite_rsp_t ), - .NumSlvPorts ( NumSlvPorts ), // Number of slave ports + .NumSbrPorts ( NumSbrPorts ), // Number of subordinate ports .MaxTrans ( MaxTrans ), .FallThrough ( FallThrough ), .SpillAw ( SpillAw ), @@ -522,10 +522,10 @@ module axi_lite_mux_intf #( .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Test Mode enable - .slv_reqs_i ( slv_reqs ), - .slv_rsps_o ( slv_rsps ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + .sbr_reqs_i ( sbr_reqs ), + .sbr_rsps_o ( sbr_rsps ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); // pragma translate_off diff --git a/src/axi_lite_regs.sv b/src/axi_lite_regs.sv index 4caf1c74b..2d269531e 100644 --- a/src/axi_lite_regs.sv +++ b/src/axi_lite_regs.sv @@ -19,7 +19,7 @@ /// /// This module contains a parametrizable number of bytes in flip-flops (FFs) and makes them /// accessible on two interfaces: -/// - as memory-mapped AXI4-Lite slave (ports `axi_req_i` and `axi_rsp_o`), and +/// - as memory-mapped AXI4-Lite subordinate (ports `axi_req_i` and `axi_rsp_o`), and /// - as wires to directly attach other hardware logic (ports `reg_d_i`, `reg_load_i`, `reg_q_o`, /// `wr_active_o`, `rd_active_o`). /// @@ -100,9 +100,9 @@ module axi_lite_regs #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// AXI4-Lite slave request + /// AXI4-Lite subordinate request input axi_lite_req_t axi_req_i, - /// AXI4-Lite slave response + /// AXI4-Lite subordinate response output axi_lite_rsp_t axi_rsp_o, /// Signals that a byte is being written from the AXI4-Lite port in the current clock cycle. This /// signal is asserted regardless of the value of `ReadOnly` and can therefore be used by @@ -347,7 +347,7 @@ module axi_lite_regs #( .default_idx_i ( '0 ) ); - // Add a cycle delay on AXI response, cut all comb paths between slave port inputs and outputs. + // Add a cycle delay on AXI response, cut all comb paths between subordinate port inputs and outputs. spill_register #( .T ( b_chan_lite_t ), .Bypass ( 1'b0 ) @@ -362,7 +362,7 @@ module axi_lite_regs #( .data_o ( axi_rsp_o.b ) ); - // Add a cycle delay on AXI response, cut all comb paths between slave port inputs and outputs. + // Add a cycle delay on AXI response, cut all comb paths between subordinate port inputs and outputs. spill_register #( .T ( r_chan_lite_t ), .Bypass ( 1'b0 ) @@ -422,7 +422,7 @@ module axi_lite_regs_intf #( ) ( input logic clk_i, input logic rst_ni, - AXI_LITE.Slave slv, + AXI_LITE.Subordinate sbr, output logic [REG_NUM_BYTES-1:0] wr_active_o, output logic [REG_NUM_BYTES-1:0] rd_active_o, input byte_t [REG_NUM_BYTES-1:0] reg_d_i, @@ -444,8 +444,8 @@ module axi_lite_regs_intf #( axi_lite_req_t axi_lite_req; axi_lite_rsp_t axi_lite_rsp; - `AXI_LITE_ASSIGN_TO_REQ(axi_lite_req, slv) - `AXI_LITE_ASSIGN_FROM_RSP(slv, axi_lite_rsp) + `AXI_LITE_ASSIGN_TO_REQ(axi_lite_req, sbr) + `AXI_LITE_ASSIGN_FROM_RSP(sbr, axi_lite_rsp) axi_lite_regs #( .RegNumBytes ( REG_NUM_BYTES ), @@ -473,10 +473,10 @@ module axi_lite_regs_intf #( // pragma translate_off `ifndef VERILATOR initial begin: p_assertions - assert (AXI_ADDR_WIDTH == $bits(slv.aw_addr)) - else $fatal(1, "AXI_ADDR_WIDTH does not match slv interface!"); - assert (AXI_DATA_WIDTH == $bits(slv.w_data)) - else $fatal(1, "AXI_DATA_WIDTH does not match slv interface!"); + assert (AXI_ADDR_WIDTH == $bits(sbr.aw_addr)) + else $fatal(1, "AXI_ADDR_WIDTH does not match sbr interface!"); + assert (AXI_DATA_WIDTH == $bits(sbr.w_data)) + else $fatal(1, "AXI_DATA_WIDTH does not match sbr interface!"); end `endif // pragma translate_on diff --git a/src/axi_lite_to_apb.sv b/src/axi_lite_to_apb.sv index 919172892..441eefcb0 100644 --- a/src/axi_lite_to_apb.sv +++ b/src/axi_lite_to_apb.sv @@ -15,7 +15,7 @@ // Description: AXI4-Lite to APB4 bridge // -// This module has one AXI4-Lite slave port and is capable of generating +// This module has one AXI4-Lite subordinate port and is capable of generating // APB4 requests for multiple APB4 slave modules. The address and data widths // of AXI4-Lite and APB4 have to be the same for both ports and are enforced over assertions. // The selection of the APB4 slave is handled by the `addr_decode` module from `common_cells`. @@ -62,7 +62,7 @@ module axi_lite_to_apb #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - // AXI LITE slave port + // AXI LITE subordinate port input axi_lite_req_t axi_lite_req_i, output axi_lite_rsp_t axi_lite_rsp_o, // APB master port @@ -96,7 +96,7 @@ module axi_lite_to_apb #( } apb_state_e; - // Signals from AXI4-Lite slave to arbitration tree + // Signals from AXI4-Lite subordinate to arbitration tree int_req_t [1:0] axi_req; logic [1:0] axi_req_valid, axi_req_ready; @@ -107,7 +107,7 @@ module axi_lite_to_apb #( logic axi_rresp_valid, axi_rresp_ready; // ----------------------------------------------------------------------------------------------- - // AXI4-Lite slave + // AXI4-Lite subordinate // ----------------------------------------------------------------------------------------------- // read request assign axi_req[RD] = '{ @@ -396,8 +396,8 @@ module axi_lite_to_apb_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - // AXI LITE slave port - AXI_LITE.Slave slv, + // AXI LITE subordinate port + AXI_LITE.Subordinate sbr, // APB master port output addr_t paddr_o, output logic [2:0] pprot_o, @@ -444,8 +444,8 @@ module axi_lite_to_apb_intf #( apb_rsp_t [NumApbSlaves-1:0] apb_rsp; logic [SelIdxWidth-1:0] apb_sel; - `AXI_LITE_ASSIGN_TO_REQ(axi_req, slv) - `AXI_LITE_ASSIGN_FROM_RSP(slv, axi_rsp) + `AXI_LITE_ASSIGN_TO_REQ(axi_req, sbr) + `AXI_LITE_ASSIGN_FROM_RSP(sbr, axi_rsp) onehot_to_bin #( .ONEHOT_WIDTH ( NumApbSlaves ) @@ -482,7 +482,7 @@ module axi_lite_to_apb_intf #( ) i_axi_lite_to_apb ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - // AXI LITE slave port + // AXI LITE subordinate port .axi_lite_req_i ( axi_req ), .axi_lite_rsp_o ( axi_rsp ), // APB master port diff --git a/src/axi_lite_to_axi.sv b/src/axi_lite_to_axi.sv index 8a16beade..f7061efcc 100644 --- a/src/axi_lite_to_axi.sv +++ b/src/axi_lite_to_axi.sv @@ -24,64 +24,64 @@ module axi_lite_to_axi #( parameter type axi_req_t = logic, parameter type axi_rsp_t = logic ) ( - // Slave AXI LITE port - input axi_lite_req_t slv_req_lite_i, - output axi_lite_rsp_t slv_rsp_lite_o, - input axi_pkg::cache_t slv_aw_cache_i, - input axi_pkg::cache_t slv_ar_cache_i, - // Master AXI port - output axi_req_t mst_req_o, - input axi_rsp_t mst_rsp_i + // Subordinate AXI LITE port + input axi_lite_req_t sbr_req_lite_i, + output axi_lite_rsp_t sbr_rsp_lite_o, + input axi_pkg::cache_t sbr_aw_cache_i, + input axi_pkg::cache_t sbr_ar_cache_i, + // Manager AXI port + output axi_req_t mgr_req_o, + input axi_rsp_t mgr_rsp_i ); localparam int unsigned Size = axi_pkg::size_t'($unsigned($clog2(DataWidth/8))); // request assign - assign mst_req_o = '{ + assign mgr_req_o = '{ aw: '{ - addr: slv_req_lite_i.aw.addr, - prot: slv_req_lite_i.aw.prot, + addr: sbr_req_lite_i.aw.addr, + prot: sbr_req_lite_i.aw.prot, size: Size, burst: axi_pkg::BURST_FIXED, - cache: slv_aw_cache_i, + cache: sbr_aw_cache_i, default: '0 }, - aw_valid: slv_req_lite_i.aw_valid, + aw_valid: sbr_req_lite_i.aw_valid, w: '{ - data: slv_req_lite_i.w.data, - strb: slv_req_lite_i.w.strb, + data: sbr_req_lite_i.w.data, + strb: sbr_req_lite_i.w.strb, last: 1'b1, default: '0 }, - w_valid: slv_req_lite_i.w_valid, - b_ready: slv_req_lite_i.b_ready, + w_valid: sbr_req_lite_i.w_valid, + b_ready: sbr_req_lite_i.b_ready, ar: '{ - addr: slv_req_lite_i.ar.addr, - prot: slv_req_lite_i.ar.prot, + addr: sbr_req_lite_i.ar.addr, + prot: sbr_req_lite_i.ar.prot, size: Size, burst: axi_pkg::BURST_FIXED, - cache: slv_ar_cache_i, + cache: sbr_ar_cache_i, default: '0 }, - ar_valid: slv_req_lite_i.ar_valid, - r_ready: slv_req_lite_i.r_ready, + ar_valid: sbr_req_lite_i.ar_valid, + r_ready: sbr_req_lite_i.r_ready, default: '0 }; // response assign - assign slv_rsp_lite_o = '{ - aw_ready: mst_rsp_i.aw_ready, - w_ready: mst_rsp_i.w_ready, + assign sbr_rsp_lite_o = '{ + aw_ready: mgr_rsp_i.aw_ready, + w_ready: mgr_rsp_i.w_ready, b: '{ - resp: mst_rsp_i.b.resp, + resp: mgr_rsp_i.b.resp, default: '0 }, - b_valid: mst_rsp_i.b_valid, - ar_ready: mst_rsp_i.ar_ready, + b_valid: mgr_rsp_i.b_valid, + ar_ready: mgr_rsp_i.ar_ready, r: '{ - data: mst_rsp_i.r.data, - resp: mst_rsp_i.r.resp, + data: mgr_rsp_i.r.data, + resp: mgr_rsp_i.r.resp, default: '0 }, - r_valid: mst_rsp_i.r_valid, + r_valid: mgr_rsp_i.r_valid, default: '0 }; @@ -97,10 +97,10 @@ endmodule module axi_lite_to_axi_intf #( parameter int unsigned AXI_DATA_WIDTH = 32'd0 ) ( - AXI_LITE.Slave in, - input axi_pkg::cache_t slv_aw_cache_i, - input axi_pkg::cache_t slv_ar_cache_i, - AXI_BUS.Master out + AXI_LITE.Subordinate in, + input axi_pkg::cache_t sbr_aw_cache_i, + input axi_pkg::cache_t sbr_ar_cache_i, + AXI_BUS.Manager out ); localparam int unsigned Size = axi_pkg::size_t'($unsigned($clog2(AXI_DATA_WIDTH/8))); @@ -118,7 +118,7 @@ module axi_lite_to_axi_intf #( assign out.aw_size = Size; assign out.aw_burst = axi_pkg::BURST_FIXED; assign out.aw_lock = '0; - assign out.aw_cache = slv_aw_cache_i; + assign out.aw_cache = sbr_aw_cache_i; assign out.aw_prot = '0; assign out.aw_qos = '0; assign out.aw_region = '0; @@ -144,7 +144,7 @@ module axi_lite_to_axi_intf #( assign out.ar_size = Size; assign out.ar_burst = axi_pkg::BURST_FIXED; assign out.ar_lock = '0; - assign out.ar_cache = slv_ar_cache_i; + assign out.ar_cache = sbr_ar_cache_i; assign out.ar_prot = '0; assign out.ar_qos = '0; assign out.ar_region = '0; diff --git a/src/axi_lite_xbar.sv b/src/axi_lite_xbar.sv index 623abd34b..b53f89674 100644 --- a/src/axi_lite_xbar.sv +++ b/src/axi_lite_xbar.sv @@ -30,26 +30,26 @@ module axi_lite_xbar #( parameter type axi_lite_rsp_t = logic, parameter type rule_t = axi_pkg::xbar_rule_64_t, // DEPENDENT PARAMETERS, DO NOT OVERWRITE! - parameter int unsigned MstIdxWidth = (Cfg.NumMstPorts > 32'd1) ? $clog2(Cfg.NumMstPorts) : 32'd1 + parameter int unsigned MgrIdxWidth = (Cfg.NumMgrPorts > 32'd1) ? $clog2(Cfg.NumMgrPorts) : 32'd1 ) ( input logic clk_i, input logic rst_ni, input logic test_i, - input axi_lite_req_t [Cfg.NumSlvPorts-1:0] slv_ports_req_i, - output axi_lite_rsp_t [Cfg.NumSlvPorts-1:0] slv_ports_rsp_o, - output axi_lite_req_t [Cfg.NumMstPorts-1:0] mst_ports_req_o, - input axi_lite_rsp_t [Cfg.NumMstPorts-1:0] mst_ports_rsp_i, + input axi_lite_req_t [Cfg.NumSbrPorts-1:0] sbr_ports_req_i, + output axi_lite_rsp_t [Cfg.NumSbrPorts-1:0] sbr_ports_rsp_o, + output axi_lite_req_t [Cfg.NumMgrPorts-1:0] mgr_ports_req_o, + input axi_lite_rsp_t [Cfg.NumMgrPorts-1:0] mgr_ports_rsp_i, input rule_t [Cfg.NumAddrRules-1:0] addr_map_i, - input logic [Cfg.NumSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NumSlvPorts-1:0][MstIdxWidth-1:0] default_mst_port_i + input logic [Cfg.NumSbrPorts-1:0] en_default_mgr_port_i, + input logic [Cfg.NumSbrPorts-1:0][MgrIdxWidth-1:0] default_mgr_port_i ); typedef logic [Cfg.AddrWidth-1:0] addr_t; typedef logic [Cfg.DataWidth-1:0] data_t; typedef logic [Cfg.DataWidth/8-1:0] strb_t; - // to account for the decoding error slave - typedef logic [$clog2(Cfg.NumMstPorts + 1)-1:0] mst_port_idx_t; - // full AXI typedef for the decode error slave, id_t and user_t are logic and will be + // to account for the decoding error subordinate + typedef logic [$clog2(Cfg.NumMgrPorts + 1)-1:0] mgr_port_idx_t; + // full AXI typedef for the decode error subordinate, id_t and user_t are logic and will be // removed during logic optimization as they are stable `AXI_TYPEDEF_AW_CHAN_T(full_aw_chan_t, addr_t, logic, logic) `AXI_TYPEDEF_W_CHAN_T(full_w_chan_t, data_t, strb_t, logic) @@ -60,16 +60,16 @@ module axi_lite_xbar #( `AXI_TYPEDEF_RSP_T(full_rsp_t, full_b_chan_t, full_r_chan_t) // signals from the axi_lite_demuxes, one index more for decode error routing - axi_lite_req_t [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts:0] slv_reqs; - axi_lite_rsp_t [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts:0] slv_rsps; + axi_lite_req_t [Cfg.NumSbrPorts-1:0][Cfg.NumMgrPorts:0] sbr_reqs; + axi_lite_rsp_t [Cfg.NumSbrPorts-1:0][Cfg.NumMgrPorts:0] sbr_rsps; - // signals into the axi_lite_muxes, are of type slave as the multiplexer extends the ID - axi_lite_req_t [Cfg.NumMstPorts-1:0][Cfg.NumSlvPorts-1:0] mst_reqs; - axi_lite_rsp_t [Cfg.NumMstPorts-1:0][Cfg.NumSlvPorts-1:0] mst_rsps; + // signals into the axi_lite_muxes, are of type subordinate as the multiplexer extends the ID + axi_lite_req_t [Cfg.NumMgrPorts-1:0][Cfg.NumSbrPorts-1:0] mgr_reqs; + axi_lite_rsp_t [Cfg.NumMgrPorts-1:0][Cfg.NumSbrPorts-1:0] mgr_rsps; - for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_slv_port_demux - logic [MstIdxWidth-1:0] dec_aw, dec_ar; - mst_port_idx_t slv_aw_select, slv_ar_select; + for (genvar i = 0; i < Cfg.NumSbrPorts; i++) begin : gen_sbr_port_demux + logic [MgrIdxWidth-1:0] dec_aw, dec_ar; + mgr_port_idx_t sbr_aw_select, sbr_ar_select; logic dec_aw_error; logic dec_ar_error; @@ -77,64 +77,64 @@ module axi_lite_xbar #( full_rsp_t decerr_rsp; addr_decode #( - .NoIndices ( Cfg.NumMstPorts ), + .NoIndices ( Cfg.NumMgrPorts ), .NoRules ( Cfg.NumAddrRules ), .addr_t ( addr_t ), .rule_t ( rule_t ) ) i_axi_aw_decode ( - .addr_i ( slv_ports_req_i[i].aw.addr ), + .addr_i ( sbr_ports_req_i[i].aw.addr ), .addr_map_i ( addr_map_i ), .idx_o ( dec_aw ), .dec_valid_o ( /*not used*/ ), .dec_error_o ( dec_aw_error ), - .en_default_idx_i ( en_default_mst_port_i[i] ), - .default_idx_i ( default_mst_port_i[i] ) + .en_default_idx_i ( en_default_mgr_port_i[i] ), + .default_idx_i ( default_mgr_port_i[i] ) ); addr_decode #( - .NoIndices ( Cfg.NumMstPorts ), + .NoIndices ( Cfg.NumMgrPorts ), .addr_t ( addr_t ), .NoRules ( Cfg.NumAddrRules ), .rule_t ( rule_t ) ) i_axi_ar_decode ( - .addr_i ( slv_ports_req_i[i].ar.addr ), + .addr_i ( sbr_ports_req_i[i].ar.addr ), .addr_map_i ( addr_map_i ), .idx_o ( dec_ar ), .dec_valid_o ( /*not used*/ ), .dec_error_o ( dec_ar_error ), - .en_default_idx_i ( en_default_mst_port_i[i] ), - .default_idx_i ( default_mst_port_i[i] ) + .en_default_idx_i ( en_default_mgr_port_i[i] ), + .default_idx_i ( default_mgr_port_i[i] ) ); - assign slv_aw_select = (dec_aw_error) ? - mst_port_idx_t'(Cfg.NumMstPorts) : mst_port_idx_t'(dec_aw); - assign slv_ar_select = (dec_ar_error) ? - mst_port_idx_t'(Cfg.NumMstPorts) : mst_port_idx_t'(dec_ar); + assign sbr_aw_select = (dec_aw_error) ? + mgr_port_idx_t'(Cfg.NumMgrPorts) : mgr_port_idx_t'(dec_aw); + assign sbr_ar_select = (dec_ar_error) ? + mgr_port_idx_t'(Cfg.NumMgrPorts) : mgr_port_idx_t'(dec_ar); - // make sure that the default slave does not get changed, if there is an unserved Ax + // make sure that the default subordinate does not get changed, if there is an unserved Ax // pragma translate_off `ifndef VERILATOR default disable iff (~rst_ni); - default_aw_mst_port_en: assert property( - @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_rsp_o[i].aw_ready) - |=> $stable(en_default_mst_port_i[i])) - else $fatal (1, $sformatf("It is not allowed to change the default mst port\ - enable, when there is an unserved Aw beat. Slave Port: %0d", i)); - default_aw_mst_port: assert property( - @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_rsp_o[i].aw_ready) - |=> $stable(default_mst_port_i[i])) - else $fatal (1, $sformatf("It is not allowed to change the default mst port\ - when there is an unserved Aw beat. Slave Port: %0d", i)); - default_ar_mst_port_en: assert property( - @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_rsp_o[i].ar_ready) - |=> $stable(en_default_mst_port_i[i])) + default_aw_mgr_port_en: assert property( + @(posedge clk_i) (sbr_ports_req_i[i].aw_valid && !sbr_ports_rsp_o[i].aw_ready) + |=> $stable(en_default_mgr_port_i[i])) + else $fatal (1, $sformatf("It is not allowed to change the default mgr port\ + enable, when there is an unserved Aw beat. Subordinate Port: %0d", i)); + default_aw_mgr_port: assert property( + @(posedge clk_i) (sbr_ports_req_i[i].aw_valid && !sbr_ports_rsp_o[i].aw_ready) + |=> $stable(default_mgr_port_i[i])) + else $fatal (1, $sformatf("It is not allowed to change the default mgr port\ + when there is an unserved Aw beat. Subordinate Port: %0d", i)); + default_ar_mgr_port_en: assert property( + @(posedge clk_i) (sbr_ports_req_i[i].ar_valid && !sbr_ports_rsp_o[i].ar_ready) + |=> $stable(en_default_mgr_port_i[i])) else $fatal (1, $sformatf("It is not allowed to change the enable, when\ - there is an unserved Ar beat. Slave Port: %0d", i)); - default_ar_mst_port: assert property( - @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_rsp_o[i].ar_ready) - |=> $stable(default_mst_port_i[i])) - else $fatal (1, $sformatf("It is not allowed to change the default mst port\ - when there is an unserved Ar beat. Slave Port: %0d", i)); + there is an unserved Ar beat. Subordinate Port: %0d", i)); + default_ar_mgr_port: assert property( + @(posedge clk_i) (sbr_ports_req_i[i].ar_valid && !sbr_ports_rsp_o[i].ar_ready) + |=> $stable(default_mgr_port_i[i])) + else $fatal (1, $sformatf("It is not allowed to change the default mgr port\ + when there is an unserved Ar beat. Subordinate Port: %0d", i)); `endif // pragma translate_on axi_lite_demux #( @@ -145,8 +145,8 @@ module axi_lite_xbar #( .r_chan_t ( r_chan_t ), // R Channel Type .axi_lite_req_t ( axi_lite_req_t ), .axi_lite_rsp_t ( axi_lite_rsp_t ), - .NumMstPorts ( Cfg.NumMstPorts + 1 ), - .MaxTrans ( Cfg.MaxMstTrans ), + .NumMgrPorts ( Cfg.NumMgrPorts + 1 ), + .MaxTrans ( Cfg.MaxMgrTrans ), .FallThrough ( Cfg.FallThrough ), .SpillAw ( Cfg.LatencyMode[9] ), .SpillW ( Cfg.LatencyMode[8] ), @@ -157,16 +157,16 @@ module axi_lite_xbar #( .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Testmode enable - .slv_req_i ( slv_ports_req_i[i] ), - .slv_aw_select_i ( slv_aw_select ), - .slv_ar_select_i ( slv_ar_select ), - .slv_rsp_o ( slv_ports_rsp_o[i] ), - .mst_reqs_o ( slv_reqs[i] ), - .mst_rsps_i ( slv_rsps[i] ) + .sbr_req_i ( sbr_ports_req_i[i] ), + .sbr_aw_select_i ( sbr_aw_select ), + .sbr_ar_select_i ( sbr_ar_select ), + .sbr_rsp_o ( sbr_ports_rsp_o[i] ), + .mgr_reqs_o ( sbr_reqs[i] ), + .mgr_rsps_i ( sbr_rsps[i] ) ); - // connect the decode error module to the last index of the demux master port - // typedef as the decode error slave uses full axi + // connect the decode error module to the last index of the demux manager port + // typedef as the decode error subordinate uses full axi axi_lite_to_axi #( .DataWidth ( Cfg.DataWidth ), .axi_lite_req_t ( axi_lite_req_t ), @@ -174,41 +174,41 @@ module axi_lite_xbar #( .axi_req_t ( full_req_t ), .axi_rsp_t ( full_rsp_t ) ) i_dec_err_conv ( - .slv_req_lite_i ( slv_reqs[i][Cfg.NumMstPorts] ), - .slv_rsp_lite_o ( slv_rsps[i][Cfg.NumMstPorts] ), - .slv_aw_cache_i ( 4'd0 ), - .slv_ar_cache_i ( 4'd0 ), - .mst_req_o ( decerr_req ), - .mst_rsp_i ( decerr_rsp ) + .sbr_req_lite_i ( sbr_reqs[i][Cfg.NumMgrPorts] ), + .sbr_rsp_lite_o ( sbr_rsps[i][Cfg.NumMgrPorts] ), + .sbr_aw_cache_i ( 4'd0 ), + .sbr_ar_cache_i ( 4'd0 ), + .mgr_req_o ( decerr_req ), + .mgr_rsp_i ( decerr_rsp ) ); - axi_err_slv #( + axi_err_sbr #( .IdWidth ( 32'd1 ), // ID width is one as defined as logic above .axi_req_t ( full_req_t ), // AXI request struct .axi_rsp_t ( full_rsp_t ), // AXI response struct .Resp ( axi_pkg::RESP_DECERR ), .ATOPs ( 1'b0 ), // no ATOPs in AXI4-Lite - .MaxTrans ( 1 ) // Transactions terminate at this slave, and AXI4-Lite + .MaxTrans ( 1 ) // Transactions terminate at this subordinate, and AXI4-Lite // transactions have only a single beat. - ) i_axi_err_slv ( + ) i_axi_err_sbr ( .clk_i ( clk_i ), // Clock .rst_ni ( rst_ni ), // Asynchronous reset active low .test_i ( test_i ), // Testmode enable - // slave port - .slv_req_i ( decerr_req ), - .slv_rsp_o ( decerr_rsp ) + // subordinate port + .sbr_req_i ( decerr_req ), + .sbr_rsp_o ( decerr_rsp ) ); end // cross all channels - for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_xbar_slv_cross - for (genvar j = 0; j < Cfg.NumMstPorts; j++) begin : gen_xbar_mst_cross - assign mst_reqs[j][i] = slv_reqs[i][j]; - assign slv_rsps[i][j] = mst_rsps[j][i]; + for (genvar i = 0; i < Cfg.NumSbrPorts; i++) begin : gen_xbar_sbr_cross + for (genvar j = 0; j < Cfg.NumMgrPorts; j++) begin : gen_xbar_mgr_cross + assign mgr_reqs[j][i] = sbr_reqs[i][j]; + assign sbr_rsps[i][j] = mgr_rsps[j][i]; end end - for (genvar i = 0; i < Cfg.NumMstPorts; i++) begin : gen_mst_port_mux + for (genvar i = 0; i < Cfg.NumMgrPorts; i++) begin : gen_mgr_port_mux axi_lite_mux #( .aw_chan_t ( aw_chan_t ), // AW Channel Type .w_chan_t ( w_chan_t ), // W Channel Type @@ -217,8 +217,8 @@ module axi_lite_xbar #( .r_chan_t ( r_chan_t ), // R Channel Type .axi_lite_req_t ( axi_lite_req_t ), .axi_lite_rsp_t ( axi_lite_rsp_t ), - .NumSlvPorts ( Cfg.NumSlvPorts ), // Number of Masters for the module - .MaxTrans ( Cfg.MaxSlvTrans ), + .NumSbrPorts ( Cfg.NumSbrPorts ), // Number of Managers for the module + .MaxTrans ( Cfg.MaxSbrTrans ), .FallThrough ( Cfg.FallThrough ), .SpillAw ( Cfg.LatencyMode[4] ), .SpillW ( Cfg.LatencyMode[3] ), @@ -229,10 +229,10 @@ module axi_lite_xbar #( .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Test Mode enable - .slv_reqs_i ( mst_reqs[i] ), - .slv_rsps_o ( mst_rsps[i] ), - .mst_req_o ( mst_ports_req_o[i] ), - .mst_rsp_i ( mst_ports_rsp_i[i] ) + .sbr_reqs_i ( mgr_reqs[i] ), + .sbr_rsps_o ( mgr_rsps[i] ), + .mgr_req_o ( mgr_ports_req_o[i] ), + .mgr_rsp_i ( mgr_ports_rsp_i[i] ) ); end endmodule @@ -246,11 +246,11 @@ module axi_lite_xbar_intf #( input logic clk_i, input logic rst_ni, input logic test_i, - AXI_LITE.Slave slv_ports [Cfg.NumSlvPorts-1:0], - AXI_LITE.Master mst_ports [Cfg.NumMstPorts-1:0], + AXI_LITE.Subordinate sbr_ports [Cfg.NumSbrPorts-1:0], + AXI_LITE.Manager mgr_ports [Cfg.NumMgrPorts-1:0], input rule_t [Cfg.NumAddrRules-1:0] addr_map_i, - input logic [Cfg.NumSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NumSlvPorts-1:0][$clog2(Cfg.NumMstPorts)-1:0] default_mst_port_i + input logic [Cfg.NumSbrPorts-1:0] en_default_mgr_port_i, + input logic [Cfg.NumSbrPorts-1:0][$clog2(Cfg.NumMgrPorts)-1:0] default_mgr_port_i ); typedef logic [Cfg.AddrWidth -1:0] addr_t; @@ -264,19 +264,19 @@ module axi_lite_xbar_intf #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - axi_lite_req_t [Cfg.NumMstPorts-1:0] mst_reqs; - axi_lite_rsp_t [Cfg.NumMstPorts-1:0] mst_rsps; - axi_lite_req_t [Cfg.NumSlvPorts-1:0] slv_reqs; - axi_lite_rsp_t [Cfg.NumSlvPorts-1:0] slv_rsps; + axi_lite_req_t [Cfg.NumMgrPorts-1:0] mgr_reqs; + axi_lite_rsp_t [Cfg.NumMgrPorts-1:0] mgr_rsps; + axi_lite_req_t [Cfg.NumSbrPorts-1:0] sbr_reqs; + axi_lite_rsp_t [Cfg.NumSbrPorts-1:0] sbr_rsps; - for (genvar i = 0; i < Cfg.NumMstPorts; i++) begin : gen_assign_mst - `AXI_LITE_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) - `AXI_LITE_ASSIGN_TO_RSP(mst_rsps[i], mst_ports[i]) + for (genvar i = 0; i < Cfg.NumMgrPorts; i++) begin : gen_assign_mgr + `AXI_LITE_ASSIGN_FROM_REQ(mgr_ports[i], mgr_reqs[i]) + `AXI_LITE_ASSIGN_TO_RSP(mgr_rsps[i], mgr_ports[i]) end - for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_assign_slv - `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) - `AXI_LITE_ASSIGN_FROM_RSP(slv_ports[i], slv_rsps[i]) + for (genvar i = 0; i < Cfg.NumSbrPorts; i++) begin : gen_assign_sbr + `AXI_LITE_ASSIGN_TO_REQ(sbr_reqs[i], sbr_ports[i]) + `AXI_LITE_ASSIGN_FROM_RSP(sbr_ports[i], sbr_rsps[i]) end axi_lite_xbar #( @@ -293,13 +293,13 @@ module axi_lite_xbar_intf #( .clk_i, .rst_ni, .test_i, - .slv_ports_req_i (slv_reqs), - .slv_ports_rsp_o (slv_rsps), - .mst_ports_req_o (mst_reqs), - .mst_ports_rsp_i (mst_rsps), + .sbr_ports_req_i (sbr_reqs), + .sbr_ports_rsp_o (sbr_rsps), + .mgr_ports_req_o (mgr_reqs), + .mgr_ports_rsp_i (mgr_rsps), .addr_map_i, - .en_default_mst_port_i, - .default_mst_port_i + .en_default_mgr_port_i, + .default_mgr_port_i ); endmodule diff --git a/src/axi_modify_address.sv b/src/axi_modify_address.sv index 3af649c3d..ac6c1cba3 100644 --- a/src/axi_modify_address.sv +++ b/src/axi_modify_address.sv @@ -16,69 +16,69 @@ /// Modify addresses on an AXI4 bus module axi_modify_address #( - /// Request type of the slave port - parameter type slv_port_axi_req_t = logic, - /// Address type of the master port - parameter type mst_addr_t = logic, - /// Request type of the master port - parameter type mst_port_axi_req_t = logic, - /// Response type of slave and master port + /// Request type of the subordinate port + parameter type sbr_port_axi_req_t = logic, + /// Address type of the manager port + parameter type mgr_addr_t = logic, + /// Request type of the manager port + parameter type mgr_port_axi_req_t = logic, + /// Response type of subordinate and manager port parameter type axi_rsp_t = logic ) ( - /// Slave port request - input slv_port_axi_req_t slv_req_i, - /// Slave port response - output axi_rsp_t slv_rsp_o, - /// AW address on master port; must remain stable while an AW handshake is pending. - input mst_addr_t mst_aw_addr_i, - /// AR address on master port; must remain stable while an AR handshake is pending. - input mst_addr_t mst_ar_addr_i, - /// Master port request - output mst_port_axi_req_t mst_req_o, - /// Master port response - input axi_rsp_t mst_rsp_i + /// Subordinate port request + input sbr_port_axi_req_t sbr_req_i, + /// Subordinate port response + output axi_rsp_t sbr_rsp_o, + /// AW address on manager port; must remain stable while an AW handshake is pending. + input mgr_addr_t mgr_aw_addr_i, + /// AR address on manager port; must remain stable while an AR handshake is pending. + input mgr_addr_t mgr_ar_addr_i, + /// Manager port request + output mgr_port_axi_req_t mgr_req_o, + /// Manager port response + input axi_rsp_t mgr_rsp_i ); - assign mst_req_o = '{ + assign mgr_req_o = '{ aw: '{ - id: slv_req_i.aw.id, - addr: mst_aw_addr_i, - len: slv_req_i.aw.len, - size: slv_req_i.aw.size, - burst: slv_req_i.aw.burst, - lock: slv_req_i.aw.lock, - cache: slv_req_i.aw.cache, - prot: slv_req_i.aw.prot, - qos: slv_req_i.aw.qos, - region: slv_req_i.aw.region, - atop: slv_req_i.aw.atop, - user: slv_req_i.aw.user, + id: sbr_req_i.aw.id, + addr: mgr_aw_addr_i, + len: sbr_req_i.aw.len, + size: sbr_req_i.aw.size, + burst: sbr_req_i.aw.burst, + lock: sbr_req_i.aw.lock, + cache: sbr_req_i.aw.cache, + prot: sbr_req_i.aw.prot, + qos: sbr_req_i.aw.qos, + region: sbr_req_i.aw.region, + atop: sbr_req_i.aw.atop, + user: sbr_req_i.aw.user, default: '0 }, - aw_valid: slv_req_i.aw_valid, - w: slv_req_i.w, - w_valid: slv_req_i.w_valid, - b_ready: slv_req_i.b_ready, + aw_valid: sbr_req_i.aw_valid, + w: sbr_req_i.w, + w_valid: sbr_req_i.w_valid, + b_ready: sbr_req_i.b_ready, ar: '{ - id: slv_req_i.ar.id, - addr: mst_ar_addr_i, - len: slv_req_i.ar.len, - size: slv_req_i.ar.size, - burst: slv_req_i.ar.burst, - lock: slv_req_i.ar.lock, - cache: slv_req_i.ar.cache, - prot: slv_req_i.ar.prot, - qos: slv_req_i.ar.qos, - region: slv_req_i.ar.region, - user: slv_req_i.ar.user, + id: sbr_req_i.ar.id, + addr: mgr_ar_addr_i, + len: sbr_req_i.ar.len, + size: sbr_req_i.ar.size, + burst: sbr_req_i.ar.burst, + lock: sbr_req_i.ar.lock, + cache: sbr_req_i.ar.cache, + prot: sbr_req_i.ar.prot, + qos: sbr_req_i.ar.qos, + region: sbr_req_i.ar.region, + user: sbr_req_i.ar.user, default: '0 }, - ar_valid: slv_req_i.ar_valid, - r_ready: slv_req_i.r_ready, + ar_valid: sbr_req_i.ar_valid, + r_ready: sbr_req_i.r_ready, default: '0 }; - assign slv_rsp_o = mst_rsp_i; + assign sbr_rsp_o = mgr_rsp_i; endmodule @@ -87,75 +87,75 @@ endmodule /// Interface variant of [`axi_modify_address`](module.axi_modify_address) module axi_modify_address_intf #( - /// Address width of slave port - parameter int unsigned AXI_SLV_PORT_ADDR_WIDTH = 0, - /// Address width of master port - parameter int unsigned AXI_MST_PORT_ADDR_WIDTH = AXI_SLV_PORT_ADDR_WIDTH, - /// Data width of slave and master port + /// Address width of subordinate port + parameter int unsigned AXI_SBR_PORT_ADDR_WIDTH = 0, + /// Address width of manager port + parameter int unsigned AXI_MGR_PORT_ADDR_WIDTH = AXI_SBR_PORT_ADDR_WIDTH, + /// Data width of subordinate and manager port parameter int unsigned AXI_DATA_WIDTH = 0, - /// ID width of slave and master port + /// ID width of subordinate and manager port parameter int unsigned AXI_ID_WIDTH = 0, - /// User signal width of slave and master port + /// User signal width of subordinate and manager port parameter int unsigned AXI_USER_WIDTH = 0, - /// Derived (=DO NOT OVERRIDE) type of master port addresses - type mst_addr_t = logic [AXI_MST_PORT_ADDR_WIDTH-1:0] + /// Derived (=DO NOT OVERRIDE) type of manager port addresses + type mgr_addr_t = logic [AXI_MGR_PORT_ADDR_WIDTH-1:0] ) ( - /// Slave port - AXI_BUS.Slave slv, - /// AW address on master port; must remain stable while an AW handshake is pending. - input mst_addr_t mst_aw_addr_i, - /// AR address on master port; must remain stable while an AR handshake is pending. - input mst_addr_t mst_ar_addr_i, - /// Master port - AXI_BUS.Master mst + /// Subordinate port + AXI_BUS.Subordinate sbr, + /// AW address on manager port; must remain stable while an AW handshake is pending. + input mgr_addr_t mgr_aw_addr_i, + /// AR address on manager port; must remain stable while an AR handshake is pending. + input mgr_addr_t mgr_ar_addr_i, + /// Manager port + AXI_BUS.Manager mgr ); typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_SLV_PORT_ADDR_WIDTH-1:0] slv_addr_t; + typedef logic [AXI_SBR_PORT_ADDR_WIDTH-1:0] sbr_addr_t; typedef logic [AXI_DATA_WIDTH-1:0] data_t; typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; typedef logic [AXI_USER_WIDTH-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, slv_addr_t, id_t, user_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, mst_addr_t, id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(sbr_aw_chan_t, sbr_addr_t, id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mgr_aw_chan_t, mgr_addr_t, id_t, user_t) `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, slv_addr_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, mst_addr_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(sbr_ar_chan_t, sbr_addr_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mgr_ar_chan_t, mgr_addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_REQ_T(sbr_port_axi_req_t, sbr_aw_chan_t, w_chan_t, sbr_ar_chan_t) + `AXI_TYPEDEF_REQ_T(mgr_port_axi_req_t, mgr_aw_chan_t, w_chan_t, mgr_ar_chan_t) `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - slv_port_axi_req_t slv_req; - mst_port_axi_req_t mst_req; - axi_rsp_t slv_rsp, mst_rsp; + sbr_port_axi_req_t sbr_req; + mgr_port_axi_req_t mgr_req; + axi_rsp_t sbr_rsp, mgr_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, slv_rsp) + `AXI_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, sbr_rsp) - `AXI_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, mst) + `AXI_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_modify_address #( - .slv_port_axi_req_t ( slv_port_axi_req_t ), - .mst_addr_t ( mst_addr_t ), - .mst_port_axi_req_t ( mst_port_axi_req_t ), + .sbr_port_axi_req_t ( sbr_port_axi_req_t ), + .mgr_addr_t ( mgr_addr_t ), + .mgr_port_axi_req_t ( mgr_port_axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_axi_modify_address ( - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ), - .mst_aw_addr_i, - .mst_ar_addr_i + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ), + .mgr_aw_addr_i, + .mgr_ar_addr_i ); // pragma translate_off `ifndef VERILATOR initial begin - assert(AXI_SLV_PORT_ADDR_WIDTH > 0); - assert(AXI_MST_PORT_ADDR_WIDTH > 0); + assert(AXI_SBR_PORT_ADDR_WIDTH > 0); + assert(AXI_MGR_PORT_ADDR_WIDTH > 0); assert(AXI_DATA_WIDTH > 0); assert(AXI_ID_WIDTH > 0); end diff --git a/src/axi_multicut.sv b/src/axi_multicut.sv index 6a0b3e3e1..e6f6cec9c 100644 --- a/src/axi_multicut.sv +++ b/src/axi_multicut.sv @@ -32,26 +32,26 @@ module axi_multicut #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - // slave port - input axi_req_t slv_req_i, - output axi_rsp_t slv_rsp_o, - // master port - output axi_req_t mst_req_o, - input axi_rsp_t mst_rsp_i + // subordinate port + input axi_req_t sbr_req_i, + output axi_rsp_t sbr_rsp_o, + // manager port + output axi_req_t mgr_req_o, + input axi_rsp_t mgr_rsp_i ); if (NumCuts == '0) begin : gen_no_cut // degenerate case, connect input to output - assign mst_req_o = slv_req_i; - assign slv_rsp_o = mst_rsp_i; + assign mgr_req_o = sbr_req_i; + assign sbr_rsp_o = mgr_rsp_i; end else begin : gen_axi_cut // instantiate all needed cuts axi_req_t [NumCuts:0] cut_req; axi_rsp_t [NumCuts:0] cut_rsp; - // connect slave to the lowest index - assign cut_req[0] = slv_req_i; - assign slv_rsp_o = cut_rsp[0]; + // connect subordinate to the lowest index + assign cut_req[0] = sbr_req_i; + assign sbr_rsp_o = cut_rsp[0]; // AXI cuts for (genvar i = 0; i < NumCuts; i++) begin : gen_axi_cuts @@ -67,16 +67,16 @@ module axi_multicut #( ) i_cut ( .clk_i, .rst_ni, - .slv_req_i ( cut_req[i] ), - .slv_rsp_o ( cut_rsp[i] ), - .mst_req_o ( cut_req[i+1] ), - .mst_rsp_i ( cut_rsp[i+1] ) + .sbr_req_i ( cut_req[i] ), + .sbr_rsp_o ( cut_rsp[i] ), + .mgr_req_o ( cut_req[i+1] ), + .mgr_rsp_i ( cut_rsp[i+1] ) ); end - // connect master to the highest index - assign mst_req_o = cut_req[NumCuts]; - assign cut_rsp[NumCuts] = mst_rsp_i; + // connect manager to the highest index + assign mgr_req_o = cut_req[NumCuts]; + assign cut_rsp[NumCuts] = mgr_rsp_i; end // Check the invariants @@ -102,8 +102,8 @@ module axi_multicut_intf #( ) ( input logic clk_i, input logic rst_ni, - AXI_BUS.Slave in, - AXI_BUS.Master out + AXI_BUS.Subordinate in, + AXI_BUS.Manager out ); typedef logic [ID_WIDTH-1:0] id_t; @@ -120,14 +120,14 @@ module axi_multicut_intf #( `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_rsp_t slv_rsp, mst_rsp; + axi_req_t sbr_req, mgr_req; + axi_rsp_t sbr_rsp, mgr_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, in) - `AXI_ASSIGN_FROM_RSP(in, slv_rsp) + `AXI_ASSIGN_TO_REQ(sbr_req, in) + `AXI_ASSIGN_FROM_RSP(in, sbr_rsp) - `AXI_ASSIGN_FROM_REQ(out, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, out) + `AXI_ASSIGN_FROM_REQ(out, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, out) axi_multicut #( .NumCuts ( NUM_CUTS ), @@ -141,10 +141,10 @@ module axi_multicut_intf #( ) i_axi_multicut ( .clk_i, .rst_ni, - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); // Check the invariants. @@ -178,8 +178,8 @@ module axi_lite_multicut_intf #( ) ( input logic clk_i , input logic rst_ni , - AXI_LITE.Slave in , - AXI_LITE.Master out + AXI_LITE.Subordinate in , + AXI_LITE.Manager out ); typedef logic [ADDR_WIDTH-1:0] addr_t; @@ -194,14 +194,14 @@ module axi_lite_multicut_intf #( `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_rsp_t slv_rsp, mst_rsp; + axi_req_t sbr_req, mgr_req; + axi_rsp_t sbr_rsp, mgr_rsp; - `AXI_LITE_ASSIGN_TO_REQ(slv_req, in) - `AXI_LITE_ASSIGN_FROM_RSP(in, slv_rsp) + `AXI_LITE_ASSIGN_TO_REQ(sbr_req, in) + `AXI_LITE_ASSIGN_FROM_RSP(in, sbr_rsp) - `AXI_LITE_ASSIGN_FROM_REQ(out, mst_req) - `AXI_LITE_ASSIGN_TO_RSP(mst_rsp, out) + `AXI_LITE_ASSIGN_FROM_REQ(out, mgr_req) + `AXI_LITE_ASSIGN_TO_RSP(mgr_rsp, out) axi_multicut #( .NumCuts ( NUM_CUTS ), @@ -215,10 +215,10 @@ module axi_lite_multicut_intf #( ) i_axi_multicut ( .clk_i, .rst_ni, - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); // Check the invariants. diff --git a/src/axi_mux.sv b/src/axi_mux.sv index 6c6a6bbaa..843fa28c1 100644 --- a/src/axi_mux.sv +++ b/src/axi_mux.sv @@ -13,13 +13,13 @@ // - Wolfgang Roenninger // - Andreas Kurth -// AXI Multiplexer: This module multiplexes the AXI4 slave ports down to one master port. -// The AXI IDs from the slave ports get extended with the respective slave port index. -// The extension width can be calculated with `$clog2(NumSlvPorts)`. This means the AXI -// ID for the master port has to be this `$clog2(NumSlvPorts)` wider than the ID for the -// slave ports. -// Responses are switched based on these bits. For example, with 4 slave ports -// a response with ID `6'b100110` will be forwarded to slave port 2 (`2'b10`). +// AXI Multiplexer: This module multiplexes the AXI4 subordinate ports down to one manager port. +// The AXI IDs from the subordinate ports get extended with the respective subordinate port index. +// The extension width can be calculated with `$clog2(NumSbrPorts)`. This means the AXI +// ID for the manager port has to be this `$clog2(NumSbrPorts)` wider than the ID for the +// subordinate ports. +// Responses are switched based on these bits. For example, with 4 subordinate ports +// a response with ID `6'b100110` will be forwarded to subordinate port 2 (`2'b10`). // register macros `include "common_cells/assertions.svh" @@ -27,61 +27,61 @@ module axi_mux #( // AXI parameter and channel types - parameter int unsigned SlvIDWidth = 32'd0, // AXI ID width, slave ports - parameter type slv_aw_chan_t = logic, // AW Channel Type, slave ports - parameter type mst_aw_chan_t = logic, // AW Channel Type, master port + parameter int unsigned SbrIDWidth = 32'd0, // AXI ID width, subordinate ports + parameter type sbr_aw_chan_t = logic, // AW Channel Type, subordinate ports + parameter type mgr_aw_chan_t = logic, // AW Channel Type, manager port parameter type w_chan_t = logic, // W Channel Type, all ports - parameter type slv_b_chan_t = logic, // B Channel Type, slave ports - parameter type mst_b_chan_t = logic, // B Channel Type, master port - parameter type slv_ar_chan_t = logic, // AR Channel Type, slave ports - parameter type mst_ar_chan_t = logic, // AR Channel Type, master port - parameter type slv_r_chan_t = logic, // R Channel Type, slave ports - parameter type mst_r_chan_t = logic, // R Channel Type, master port - parameter type slv_port_axi_req_t = logic, // Slave port request type - parameter type slv_port_axi_rsp_t = logic, // Slave port response type - parameter type mst_port_axi_req_t = logic, // Master ports request type - parameter type mst_port_axi_rsp_t = logic, // Master ports response type - parameter int unsigned NumSlvPorts = 32'd0, // Number of slave ports + parameter type sbr_b_chan_t = logic, // B Channel Type, subordinate ports + parameter type mgr_b_chan_t = logic, // B Channel Type, manager port + parameter type sbr_ar_chan_t = logic, // AR Channel Type, subordinate ports + parameter type mgr_ar_chan_t = logic, // AR Channel Type, manager port + parameter type sbr_r_chan_t = logic, // R Channel Type, subordinate ports + parameter type mgr_r_chan_t = logic, // R Channel Type, manager port + parameter type sbr_port_axi_req_t = logic, // Subordinate port request type + parameter type sbr_port_axi_rsp_t = logic, // Subordinate port response type + parameter type mgr_port_axi_req_t = logic, // Manager ports request type + parameter type mgr_port_axi_rsp_t = logic, // Manager ports response type + parameter int unsigned NumSbrPorts = 32'd0, // Number of subordinate ports // Maximum number of outstanding transactions per write parameter int unsigned MaxWTrans = 32'd8, // If enabled, this multiplexer is purely combinatorial parameter bit FallThrough = 1'b0, - // add spill register on write master ports, adds a cycle latency on write channels + // add spill register on write manager ports, adds a cycle latency on write channels parameter bit SpillAw = 1'b1, parameter bit SpillW = 1'b0, parameter bit SpillB = 1'b0, - // add spill register on read master ports, adds a cycle latency on read channels + // add spill register on read manager ports, adds a cycle latency on read channels parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0 ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Test Mode enable - // slave ports (AXI inputs), connect master modules here - input slv_port_axi_req_t [NumSlvPorts-1:0] slv_reqs_i, - output slv_port_axi_rsp_t [NumSlvPorts-1:0] slv_rsps_o, - // master port (AXI outputs), connect slave modules here - output mst_port_axi_req_t mst_req_o, - input mst_port_axi_rsp_t mst_rsp_i + // subordinate ports (AXI inputs), connect manager modules here + input sbr_port_axi_req_t [NumSbrPorts-1:0] sbr_reqs_i, + output sbr_port_axi_rsp_t [NumSbrPorts-1:0] sbr_rsps_o, + // manager port (AXI outputs), connect subordinate modules here + output mgr_port_axi_req_t mgr_req_o, + input mgr_port_axi_rsp_t mgr_rsp_i ); - localparam int unsigned MstIdxBits = $clog2(NumSlvPorts); - localparam int unsigned MstIDWidth = SlvIDWidth + MstIdxBits; + localparam int unsigned MgrIdxBits = $clog2(NumSbrPorts); + localparam int unsigned MgrIDWidth = SbrIDWidth + MgrIdxBits; - // pass through if only one slave port - if (NumSlvPorts == 32'h1) begin : gen_no_mux + // pass through if only one subordinate port + if (NumSbrPorts == 32'h1) begin : gen_no_mux spill_register #( - .T ( mst_aw_chan_t ), + .T ( mgr_aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_reqs_i[0].aw_valid ), - .ready_o ( slv_rsps_o[0].aw_ready ), - .data_i ( slv_reqs_i[0].aw ), - .valid_o ( mst_req_o.aw_valid ), - .ready_i ( mst_rsp_i.aw_ready ), - .data_o ( mst_req_o.aw ) + .valid_i ( sbr_reqs_i[0].aw_valid ), + .ready_o ( sbr_rsps_o[0].aw_ready ), + .data_i ( sbr_reqs_i[0].aw ), + .valid_o ( mgr_req_o.aw_valid ), + .ready_i ( mgr_rsp_i.aw_ready ), + .data_o ( mgr_req_o.aw ) ); spill_register #( .T ( w_chan_t ), @@ -89,87 +89,87 @@ module axi_mux #( ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_reqs_i[0].w_valid ), - .ready_o ( slv_rsps_o[0].w_ready ), - .data_i ( slv_reqs_i[0].w ), - .valid_o ( mst_req_o.w_valid ), - .ready_i ( mst_rsp_i.w_ready ), - .data_o ( mst_req_o.w ) + .valid_i ( sbr_reqs_i[0].w_valid ), + .ready_o ( sbr_rsps_o[0].w_ready ), + .data_i ( sbr_reqs_i[0].w ), + .valid_o ( mgr_req_o.w_valid ), + .ready_i ( mgr_rsp_i.w_ready ), + .data_o ( mgr_req_o.w ) ); spill_register #( - .T ( mst_b_chan_t ), + .T ( mgr_b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsp_i.b_valid ), - .ready_o ( mst_req_o.b_ready ), - .data_i ( mst_rsp_i.b ), - .valid_o ( slv_rsps_o[0].b_valid ), - .ready_i ( slv_reqs_i[0].b_ready ), - .data_o ( slv_rsps_o[0].b ) + .valid_i ( mgr_rsp_i.b_valid ), + .ready_o ( mgr_req_o.b_ready ), + .data_i ( mgr_rsp_i.b ), + .valid_o ( sbr_rsps_o[0].b_valid ), + .ready_i ( sbr_reqs_i[0].b_ready ), + .data_o ( sbr_rsps_o[0].b ) ); spill_register #( - .T ( mst_ar_chan_t ), + .T ( mgr_ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( slv_reqs_i[0].ar_valid ), - .ready_o ( slv_rsps_o[0].ar_ready ), - .data_i ( slv_reqs_i[0].ar ), - .valid_o ( mst_req_o.ar_valid ), - .ready_i ( mst_rsp_i.ar_ready ), - .data_o ( mst_req_o.ar ) + .valid_i ( sbr_reqs_i[0].ar_valid ), + .ready_o ( sbr_rsps_o[0].ar_ready ), + .data_i ( sbr_reqs_i[0].ar ), + .valid_o ( mgr_req_o.ar_valid ), + .ready_i ( mgr_rsp_i.ar_ready ), + .data_o ( mgr_req_o.ar ) ); spill_register #( - .T ( mst_r_chan_t ), + .T ( mgr_r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsp_i.r_valid ), - .ready_o ( mst_req_o.r_ready ), - .data_i ( mst_rsp_i.r ), - .valid_o ( slv_rsps_o[0].r_valid ), - .ready_i ( slv_reqs_i[0].r_ready ), - .data_o ( slv_rsps_o[0].r ) + .valid_i ( mgr_rsp_i.r_valid ), + .ready_o ( mgr_req_o.r_ready ), + .data_i ( mgr_rsp_i.r ), + .valid_o ( sbr_rsps_o[0].r_valid ), + .ready_i ( sbr_reqs_i[0].r_ready ), + .data_o ( sbr_rsps_o[0].r ) ); // Validate parameters. // pragma translate_off - `ASSERT_INIT(CorrectIdWidthSlvAw, $bits(slv_reqs_i[0].aw.id) == SlvIDWidth) - `ASSERT_INIT(CorrectIdWidthSlvB, $bits(slv_rsps_o[0].b.id) == SlvIDWidth) - `ASSERT_INIT(CorrectIdWidthSlvAr, $bits(slv_reqs_i[0].ar.id) == SlvIDWidth) - `ASSERT_INIT(CorrectIdWidthSlvR, $bits(slv_rsps_o[0].r.id) == SlvIDWidth) - `ASSERT_INIT(CorrectIdWidthMstAw, $bits(mst_req_o.aw.id) == SlvIDWidth) - `ASSERT_INIT(CorrectIdWidthMstB, $bits(mst_rsp_i.b.id) == SlvIDWidth) - `ASSERT_INIT(CorrectIdWidthMstAr, $bits(mst_req_o.ar.id) == SlvIDWidth) - `ASSERT_INIT(CorrectIdWidthMstR, $bits(mst_rsp_i.r.id) == SlvIDWidth) + `ASSERT_INIT(CorrectIdWidthSbrAw, $bits(sbr_reqs_i[0].aw.id) == SbrIDWidth) + `ASSERT_INIT(CorrectIdWidthSbrB, $bits(sbr_rsps_o[0].b.id) == SbrIDWidth) + `ASSERT_INIT(CorrectIdWidthSbrAr, $bits(sbr_reqs_i[0].ar.id) == SbrIDWidth) + `ASSERT_INIT(CorrectIdWidthSbrR, $bits(sbr_rsps_o[0].r.id) == SbrIDWidth) + `ASSERT_INIT(CorrectIdWidthMgrAw, $bits(mgr_req_o.aw.id) == SbrIDWidth) + `ASSERT_INIT(CorrectIdWidthMgrB, $bits(mgr_rsp_i.b.id) == SbrIDWidth) + `ASSERT_INIT(CorrectIdWidthMgrAr, $bits(mgr_req_o.ar.id) == SbrIDWidth) + `ASSERT_INIT(CorrectIdWidthMgrR, $bits(mgr_rsp_i.r.id) == SbrIDWidth) // pragma translate_on // other non degenerate cases end else begin : gen_mux - typedef logic [MstIdxBits-1:0] switch_id_t; + typedef logic [MgrIdxBits-1:0] switch_id_t; // AXI channels between the ID prepend unit and the rest of the multiplexer - mst_aw_chan_t [NumSlvPorts-1:0] slv_aw_chans; - logic [NumSlvPorts-1:0] slv_aw_valids, slv_aw_readies; - w_chan_t [NumSlvPorts-1:0] slv_w_chans; - logic [NumSlvPorts-1:0] slv_w_valids, slv_w_readies; - mst_b_chan_t [NumSlvPorts-1:0] slv_b_chans; - logic [NumSlvPorts-1:0] slv_b_valids, slv_b_readies; - mst_ar_chan_t [NumSlvPorts-1:0] slv_ar_chans; - logic [NumSlvPorts-1:0] slv_ar_valids, slv_ar_readies; - mst_r_chan_t [NumSlvPorts-1:0] slv_r_chans; - logic [NumSlvPorts-1:0] slv_r_valids, slv_r_readies; + mgr_aw_chan_t [NumSbrPorts-1:0] sbr_aw_chans; + logic [NumSbrPorts-1:0] sbr_aw_valids, sbr_aw_readies; + w_chan_t [NumSbrPorts-1:0] sbr_w_chans; + logic [NumSbrPorts-1:0] sbr_w_valids, sbr_w_readies; + mgr_b_chan_t [NumSbrPorts-1:0] sbr_b_chans; + logic [NumSbrPorts-1:0] sbr_b_valids, sbr_b_readies; + mgr_ar_chan_t [NumSbrPorts-1:0] sbr_ar_chans; + logic [NumSbrPorts-1:0] sbr_ar_valids, sbr_ar_readies; + mgr_r_chan_t [NumSbrPorts-1:0] sbr_r_chans; + logic [NumSbrPorts-1:0] sbr_r_valids, sbr_r_readies; // These signals are all ID prepended // AW channel - mst_aw_chan_t mst_aw_chan; - logic mst_aw_valid, mst_aw_ready; + mgr_aw_chan_t mgr_aw_chan; + logic mgr_aw_valid, mgr_aw_ready; - // AW master handshake internal, so that we are able to stall, if w_fifo is full + // AW manager handshake internal, so that we are able to stall, if w_fifo is full logic aw_valid, aw_ready; // FF to lock the AW valid signal, when a new arbitration decision is made the decision @@ -184,77 +184,77 @@ module axi_mux #( switch_id_t w_fifo_data; // W channel spill reg - w_chan_t mst_w_chan; - logic mst_w_valid, mst_w_ready; + w_chan_t mgr_w_chan; + logic mgr_w_valid, mgr_w_ready; - // master ID in the b_id + // manager ID in the b_id switch_id_t switch_b_id; // B channel spill reg - mst_b_chan_t mst_b_chan; - logic mst_b_valid; + mgr_b_chan_t mgr_b_chan; + logic mgr_b_valid; // AR channel for when spill is enabled - mst_ar_chan_t mst_ar_chan; + mgr_ar_chan_t mgr_ar_chan; logic ar_valid, ar_ready; - // master ID in the r_id + // manager ID in the r_id switch_id_t switch_r_id; // R channel spill reg - mst_r_chan_t mst_r_chan; - logic mst_r_valid; + mgr_r_chan_t mgr_r_chan; + logic mgr_r_valid; //-------------------------------------- - // ID prepend for all slave ports + // ID prepend for all subordinate ports //-------------------------------------- - for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_id_prepend + for (genvar i = 0; i < NumSbrPorts; i++) begin : gen_id_prepend axi_id_prepend #( - .NumBus ( 32'd1 ), // one AXI bus per slave port - .IdWidthSlvPort( SlvIDWidth ), - .IdWidthMstPort( MstIDWidth ), - .slv_aw_chan_t ( slv_aw_chan_t ), - .slv_w_chan_t ( w_chan_t ), - .slv_b_chan_t ( slv_b_chan_t ), - .slv_ar_chan_t ( slv_ar_chan_t ), - .slv_r_chan_t ( slv_r_chan_t ), - .mst_aw_chan_t ( mst_aw_chan_t ), - .mst_w_chan_t ( w_chan_t ), - .mst_b_chan_t ( mst_b_chan_t ), - .mst_ar_chan_t ( mst_ar_chan_t ), - .mst_r_chan_t ( mst_r_chan_t ) + .NumBus ( 32'd1 ), // one AXI bus per subordinate port + .IdWidthSbrPort( SbrIDWidth ), + .IdWidthMgrPort( MgrIDWidth ), + .sbr_aw_chan_t ( sbr_aw_chan_t ), + .sbr_w_chan_t ( w_chan_t ), + .sbr_b_chan_t ( sbr_b_chan_t ), + .sbr_ar_chan_t ( sbr_ar_chan_t ), + .sbr_r_chan_t ( sbr_r_chan_t ), + .mgr_aw_chan_t ( mgr_aw_chan_t ), + .mgr_w_chan_t ( w_chan_t ), + .mgr_b_chan_t ( mgr_b_chan_t ), + .mgr_ar_chan_t ( mgr_ar_chan_t ), + .mgr_r_chan_t ( mgr_r_chan_t ) ) i_id_prepend ( .pre_id_i ( switch_id_t'(i) ), - .slv_aw_chans_i ( slv_reqs_i[i].aw ), - .slv_aw_valids_i ( slv_reqs_i[i].aw_valid ), - .slv_aw_readies_o ( slv_rsps_o[i].aw_ready ), - .slv_w_chans_i ( slv_reqs_i[i].w ), - .slv_w_valids_i ( slv_reqs_i[i].w_valid ), - .slv_w_readies_o ( slv_rsps_o[i].w_ready ), - .slv_b_chans_o ( slv_rsps_o[i].b ), - .slv_b_valids_o ( slv_rsps_o[i].b_valid ), - .slv_b_readies_i ( slv_reqs_i[i].b_ready ), - .slv_ar_chans_i ( slv_reqs_i[i].ar ), - .slv_ar_valids_i ( slv_reqs_i[i].ar_valid ), - .slv_ar_readies_o ( slv_rsps_o[i].ar_ready ), - .slv_r_chans_o ( slv_rsps_o[i].r ), - .slv_r_valids_o ( slv_rsps_o[i].r_valid ), - .slv_r_readies_i ( slv_reqs_i[i].r_ready ), - .mst_aw_chans_o ( slv_aw_chans[i] ), - .mst_aw_valids_o ( slv_aw_valids[i] ), - .mst_aw_readies_i ( slv_aw_readies[i] ), - .mst_w_chans_o ( slv_w_chans[i] ), - .mst_w_valids_o ( slv_w_valids[i] ), - .mst_w_readies_i ( slv_w_readies[i] ), - .mst_b_chans_i ( slv_b_chans[i] ), - .mst_b_valids_i ( slv_b_valids[i] ), - .mst_b_readies_o ( slv_b_readies[i] ), - .mst_ar_chans_o ( slv_ar_chans[i] ), - .mst_ar_valids_o ( slv_ar_valids[i] ), - .mst_ar_readies_i ( slv_ar_readies[i] ), - .mst_r_chans_i ( slv_r_chans[i] ), - .mst_r_valids_i ( slv_r_valids[i] ), - .mst_r_readies_o ( slv_r_readies[i] ) + .sbr_aw_chans_i ( sbr_reqs_i[i].aw ), + .sbr_aw_valids_i ( sbr_reqs_i[i].aw_valid ), + .sbr_aw_readies_o ( sbr_rsps_o[i].aw_ready ), + .sbr_w_chans_i ( sbr_reqs_i[i].w ), + .sbr_w_valids_i ( sbr_reqs_i[i].w_valid ), + .sbr_w_readies_o ( sbr_rsps_o[i].w_ready ), + .sbr_b_chans_o ( sbr_rsps_o[i].b ), + .sbr_b_valids_o ( sbr_rsps_o[i].b_valid ), + .sbr_b_readies_i ( sbr_reqs_i[i].b_ready ), + .sbr_ar_chans_i ( sbr_reqs_i[i].ar ), + .sbr_ar_valids_i ( sbr_reqs_i[i].ar_valid ), + .sbr_ar_readies_o ( sbr_rsps_o[i].ar_ready ), + .sbr_r_chans_o ( sbr_rsps_o[i].r ), + .sbr_r_valids_o ( sbr_rsps_o[i].r_valid ), + .sbr_r_readies_i ( sbr_reqs_i[i].r_ready ), + .mgr_aw_chans_o ( sbr_aw_chans[i] ), + .mgr_aw_valids_o ( sbr_aw_valids[i] ), + .mgr_aw_readies_i ( sbr_aw_readies[i] ), + .mgr_w_chans_o ( sbr_w_chans[i] ), + .mgr_w_valids_o ( sbr_w_valids[i] ), + .mgr_w_readies_i ( sbr_w_readies[i] ), + .mgr_b_chans_i ( sbr_b_chans[i] ), + .mgr_b_valids_i ( sbr_b_valids[i] ), + .mgr_b_readies_o ( sbr_b_readies[i] ), + .mgr_ar_chans_o ( sbr_ar_chans[i] ), + .mgr_ar_valids_o ( sbr_ar_valids[i] ), + .mgr_ar_readies_i ( sbr_ar_readies[i] ), + .mgr_r_chans_i ( sbr_r_chans[i] ), + .mgr_r_valids_i ( sbr_r_valids[i] ), + .mgr_r_readies_o ( sbr_r_readies[i] ) ); end @@ -262,8 +262,8 @@ module axi_mux #( // AW Channel //-------------------------------------- rr_arb_tree #( - .NumIn ( NumSlvPorts ), - .DataType ( mst_aw_chan_t ), + .NumIn ( NumSbrPorts ), + .DataType ( mgr_aw_chan_t ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) ) i_aw_arbiter ( @@ -271,12 +271,12 @@ module axi_mux #( .rst_ni ( rst_ni ), .flush_i( 1'b0 ), .rr_i ( '0 ), - .req_i ( slv_aw_valids ), - .gnt_o ( slv_aw_readies ), - .data_i ( slv_aw_chans ), + .req_i ( sbr_aw_valids ), + .gnt_o ( sbr_aw_readies ), + .data_i ( sbr_aw_chans ), .gnt_i ( aw_ready ), .req_o ( aw_valid ), - .data_o ( mst_aw_chan ), + .data_o ( mgr_aw_chan ), .idx_o ( ) ); @@ -286,22 +286,22 @@ module axi_mux #( lock_aw_valid_d = lock_aw_valid_q; load_aw_lock = 1'b0; w_fifo_push = 1'b0; - mst_aw_valid = 1'b0; + mgr_aw_valid = 1'b0; aw_ready = 1'b0; // had a downstream stall, be valid and send the AW along if (lock_aw_valid_q) begin - mst_aw_valid = 1'b1; + mgr_aw_valid = 1'b1; // transaction - if (mst_aw_ready) begin + if (mgr_aw_ready) begin aw_ready = 1'b1; lock_aw_valid_d = 1'b0; load_aw_lock = 1'b1; end end else begin if (!w_fifo_full && aw_valid) begin - mst_aw_valid = 1'b1; + mgr_aw_valid = 1'b1; w_fifo_push = 1'b1; - if (mst_aw_ready) begin + if (mgr_aw_ready) begin aw_ready = 1'b1; end else begin // go to lock if transaction not in this cycle @@ -326,43 +326,43 @@ module axi_mux #( .full_o ( w_fifo_full ), .empty_o ( w_fifo_empty ), .usage_o ( ), - .data_i ( mst_aw_chan.id[SlvIDWidth+:MstIdxBits] ), + .data_i ( mgr_aw_chan.id[SbrIDWidth+:MgrIdxBits] ), .push_i ( w_fifo_push ), .data_o ( w_fifo_data ), .pop_i ( w_fifo_pop ) ); spill_register #( - .T ( mst_aw_chan_t ), + .T ( mgr_aw_chan_t ), .Bypass ( ~SpillAw ) // Param indicated that we want a spill reg ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_aw_valid ), - .ready_o ( mst_aw_ready ), - .data_i ( mst_aw_chan ), - .valid_o ( mst_req_o.aw_valid ), - .ready_i ( mst_rsp_i.aw_ready ), - .data_o ( mst_req_o.aw ) + .valid_i ( mgr_aw_valid ), + .ready_o ( mgr_aw_ready ), + .data_i ( mgr_aw_chan ), + .valid_o ( mgr_req_o.aw_valid ), + .ready_i ( mgr_rsp_i.aw_ready ), + .data_o ( mgr_req_o.aw ) ); //-------------------------------------- // W Channel //-------------------------------------- // multiplexer - assign mst_w_chan = slv_w_chans[w_fifo_data]; + assign mgr_w_chan = sbr_w_chans[w_fifo_data]; always_comb begin // default assignments - mst_w_valid = 1'b0; - slv_w_readies = '0; + mgr_w_valid = 1'b0; + sbr_w_readies = '0; w_fifo_pop = 1'b0; // control if (!w_fifo_empty) begin // connect the handshake - mst_w_valid = slv_w_valids[w_fifo_data]; - slv_w_readies[w_fifo_data] = mst_w_ready; + mgr_w_valid = sbr_w_valids[w_fifo_data]; + sbr_w_readies[w_fifo_data] = mgr_w_ready; // pop FIFO on a last transaction - w_fifo_pop = slv_w_valids[w_fifo_data] & mst_w_ready & mst_w_chan.last; + w_fifo_pop = sbr_w_valids[w_fifo_data] & mgr_w_ready & mgr_w_chan.last; end end @@ -372,43 +372,43 @@ module axi_mux #( ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_w_valid ), - .ready_o ( mst_w_ready ), - .data_i ( mst_w_chan ), - .valid_o ( mst_req_o.w_valid ), - .ready_i ( mst_rsp_i.w_ready ), - .data_o ( mst_req_o.w ) + .valid_i ( mgr_w_valid ), + .ready_o ( mgr_w_ready ), + .data_i ( mgr_w_chan ), + .valid_o ( mgr_req_o.w_valid ), + .ready_i ( mgr_rsp_i.w_ready ), + .data_o ( mgr_req_o.w ) ); //-------------------------------------- // B Channel //-------------------------------------- // replicate B channels - assign slv_b_chans = {NumSlvPorts{mst_b_chan}}; + assign sbr_b_chans = {NumSbrPorts{mgr_b_chan}}; // control B channel handshake - assign switch_b_id = mst_b_chan.id[SlvIDWidth+:MstIdxBits]; - assign slv_b_valids = (mst_b_valid) ? (1 << switch_b_id) : '0; + assign switch_b_id = mgr_b_chan.id[SbrIDWidth+:MgrIdxBits]; + assign sbr_b_valids = (mgr_b_valid) ? (1 << switch_b_id) : '0; spill_register #( - .T ( mst_b_chan_t ), + .T ( mgr_b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsp_i.b_valid ), - .ready_o ( mst_req_o.b_ready ), - .data_i ( mst_rsp_i.b ), - .valid_o ( mst_b_valid ), - .ready_i ( slv_b_readies[switch_b_id] ), - .data_o ( mst_b_chan ) + .valid_i ( mgr_rsp_i.b_valid ), + .ready_o ( mgr_req_o.b_ready ), + .data_i ( mgr_rsp_i.b ), + .valid_o ( mgr_b_valid ), + .ready_i ( sbr_b_readies[switch_b_id] ), + .data_o ( mgr_b_chan ) ); //-------------------------------------- // AR Channel //-------------------------------------- rr_arb_tree #( - .NumIn ( NumSlvPorts ), - .DataType ( mst_ar_chan_t ), + .NumIn ( NumSbrPorts ), + .DataType ( mgr_ar_chan_t ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) ) i_ar_arbiter ( @@ -416,79 +416,79 @@ module axi_mux #( .rst_ni ( rst_ni ), .flush_i( 1'b0 ), .rr_i ( '0 ), - .req_i ( slv_ar_valids ), - .gnt_o ( slv_ar_readies ), - .data_i ( slv_ar_chans ), + .req_i ( sbr_ar_valids ), + .gnt_o ( sbr_ar_readies ), + .data_i ( sbr_ar_chans ), .gnt_i ( ar_ready ), .req_o ( ar_valid ), - .data_o ( mst_ar_chan ), + .data_o ( mgr_ar_chan ), .idx_o ( ) ); spill_register #( - .T ( mst_ar_chan_t ), + .T ( mgr_ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .valid_i ( ar_valid ), .ready_o ( ar_ready ), - .data_i ( mst_ar_chan ), - .valid_o ( mst_req_o.ar_valid ), - .ready_i ( mst_rsp_i.ar_ready ), - .data_o ( mst_req_o.ar ) + .data_i ( mgr_ar_chan ), + .valid_o ( mgr_req_o.ar_valid ), + .ready_i ( mgr_rsp_i.ar_ready ), + .data_o ( mgr_req_o.ar ) ); //-------------------------------------- // R Channel //-------------------------------------- // replicate R channels - assign slv_r_chans = {NumSlvPorts{mst_r_chan}}; + assign sbr_r_chans = {NumSbrPorts{mgr_r_chan}}; // R channel handshake control - assign switch_r_id = mst_r_chan.id[SlvIDWidth+:MstIdxBits]; - assign slv_r_valids = (mst_r_valid) ? (1 << switch_r_id) : '0; + assign switch_r_id = mgr_r_chan.id[SbrIDWidth+:MgrIdxBits]; + assign sbr_r_valids = (mgr_r_valid) ? (1 << switch_r_id) : '0; spill_register #( - .T ( mst_r_chan_t ), + .T ( mgr_r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( mst_rsp_i.r_valid ), - .ready_o ( mst_req_o.r_ready ), - .data_i ( mst_rsp_i.r ), - .valid_o ( mst_r_valid ), - .ready_i ( slv_r_readies[switch_r_id] ), - .data_o ( mst_r_chan ) + .valid_i ( mgr_rsp_i.r_valid ), + .ready_o ( mgr_req_o.r_ready ), + .data_i ( mgr_rsp_i.r ), + .valid_o ( mgr_r_valid ), + .ready_i ( sbr_r_readies[switch_r_id] ), + .data_o ( mgr_r_chan ) ); end // pragma translate_off `ifndef VERILATOR initial begin - assert (SlvIDWidth > 0) else $fatal(1, "AXI ID width of slave ports must be non-zero!"); - assert (NumSlvPorts > 0) else $fatal(1, "Number of slave ports must be non-zero!"); + assert (SbrIDWidth > 0) else $fatal(1, "AXI ID width of subordinate ports must be non-zero!"); + assert (NumSbrPorts > 0) else $fatal(1, "Number of subordinate ports must be non-zero!"); assert (MaxWTrans > 0) else $fatal(1, "Maximum number of outstanding writes must be non-zero!"); - assert (MstIDWidth >= SlvIDWidth + $clog2(NumSlvPorts)) - else $fatal(1, "AXI ID width of master ports must be wide enough to identify slave ports!"); - // Assert ID widths (one slave is sufficient since they all have the same type). - assert ($unsigned($bits(slv_reqs_i[0].aw.id)) == SlvIDWidth) - else $fatal(1, "ID width of AW channel of slave ports does not match parameter!"); - assert ($unsigned($bits(slv_reqs_i[0].ar.id)) == SlvIDWidth) - else $fatal(1, "ID width of AR channel of slave ports does not match parameter!"); - assert ($unsigned($bits(slv_rsps_o[0].b.id)) == SlvIDWidth) - else $fatal(1, "ID width of B channel of slave ports does not match parameter!"); - assert ($unsigned($bits(slv_rsps_o[0].r.id)) == SlvIDWidth) - else $fatal(1, "ID width of R channel of slave ports does not match parameter!"); - assert ($unsigned($bits(mst_req_o.aw.id)) == MstIDWidth) - else $fatal(1, "ID width of AW channel of master port is wrong!"); - assert ($unsigned($bits(mst_req_o.ar.id)) == MstIDWidth) - else $fatal(1, "ID width of AR channel of master port is wrong!"); - assert ($unsigned($bits(mst_rsp_i.b.id)) == MstIDWidth) - else $fatal(1, "ID width of B channel of master port is wrong!"); - assert ($unsigned($bits(mst_rsp_i.r.id)) == MstIDWidth) - else $fatal(1, "ID width of R channel of master port is wrong!"); + assert (MgrIDWidth >= SbrIDWidth + $clog2(NumSbrPorts)) + else $fatal(1, "AXI ID width of manager ports must be wide enough to identify subordinate ports!"); + // Assert ID widths (one subordinate is sufficient since they all have the same type). + assert ($unsigned($bits(sbr_reqs_i[0].aw.id)) == SbrIDWidth) + else $fatal(1, "ID width of AW channel of subordinate ports does not match parameter!"); + assert ($unsigned($bits(sbr_reqs_i[0].ar.id)) == SbrIDWidth) + else $fatal(1, "ID width of AR channel of subordinate ports does not match parameter!"); + assert ($unsigned($bits(sbr_rsps_o[0].b.id)) == SbrIDWidth) + else $fatal(1, "ID width of B channel of subordinate ports does not match parameter!"); + assert ($unsigned($bits(sbr_rsps_o[0].r.id)) == SbrIDWidth) + else $fatal(1, "ID width of R channel of subordinate ports does not match parameter!"); + assert ($unsigned($bits(mgr_req_o.aw.id)) == MgrIDWidth) + else $fatal(1, "ID width of AW channel of manager port is wrong!"); + assert ($unsigned($bits(mgr_req_o.ar.id)) == MgrIDWidth) + else $fatal(1, "ID width of AR channel of manager port is wrong!"); + assert ($unsigned($bits(mgr_rsp_i.b.id)) == MgrIDWidth) + else $fatal(1, "ID width of B channel of manager port is wrong!"); + assert ($unsigned($bits(mgr_rsp_i.r.id)) == MgrIDWidth) + else $fatal(1, "ID width of R channel of manager port is wrong!"); end `endif // pragma translate_on @@ -498,87 +498,87 @@ endmodule `include "axi/assign.svh" `include "axi/typedef.svh" module axi_mux_intf #( - parameter int unsigned SLV_AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params - parameter int unsigned MST_AXI_ID_WIDTH = 32'd0, + parameter int unsigned SBR_AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params + parameter int unsigned MGR_AXI_ID_WIDTH = 32'd0, parameter int unsigned AXI_ADDR_WIDTH = 32'd0, parameter int unsigned AXI_DATA_WIDTH = 32'd0, parameter int unsigned AXI_USER_WIDTH = 32'd0, - parameter int unsigned NO_SLV_PORTS = 32'd0, // Number of slave ports + parameter int unsigned NO_SBR_PORTS = 32'd0, // Number of subordinate ports // Maximum number of outstanding transactions per write parameter int unsigned MAX_W_TRANS = 32'd8, // if enabled, this multiplexer is purely combinatorial parameter bit FALL_THROUGH = 1'b0, - // add spill register on write master ports, adds a cycle latency on write channels + // add spill register on write manager ports, adds a cycle latency on write channels parameter bit SPILL_AW = 1'b1, parameter bit SPILL_W = 1'b0, parameter bit SPILL_B = 1'b0, - // add spill register on read master ports, adds a cycle latency on read channels + // add spill register on read manager ports, adds a cycle latency on read channels parameter bit SPILL_AR = 1'b1, parameter bit SPILL_R = 1'b0 ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Testmode enable - AXI_BUS.Slave slv [NO_SLV_PORTS-1:0], // slave ports - AXI_BUS.Master mst // master port + AXI_BUS.Subordinate sbr [NO_SBR_PORTS-1:0], // subordinate ports + AXI_BUS.Manager mgr // manager port ); - typedef logic [SLV_AXI_ID_WIDTH-1:0] slv_id_t; - typedef logic [MST_AXI_ID_WIDTH-1:0] mst_id_t; + typedef logic [SBR_AXI_ID_WIDTH-1:0] sbr_id_t; + typedef logic [MGR_AXI_ID_WIDTH-1:0] mgr_id_t; typedef logic [AXI_ADDR_WIDTH -1:0] addr_t; typedef logic [AXI_DATA_WIDTH-1:0] data_t; typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; typedef logic [AXI_USER_WIDTH-1:0] user_t; // channels typedef - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(sbr_aw_chan_t, addr_t, sbr_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mgr_aw_chan_t, addr_t, mgr_id_t, user_t) `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(sbr_b_chan_t, sbr_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mgr_b_chan_t, mgr_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(sbr_ar_chan_t, addr_t, sbr_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mgr_ar_chan_t, addr_t, mgr_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(sbr_r_chan_t, data_t, sbr_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mgr_r_chan_t, data_t, mgr_id_t, user_t) - `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_REQ_T(sbr_port_axi_req_t, sbr_aw_chan_t, w_chan_t, sbr_ar_chan_t) + `AXI_TYPEDEF_RSP_T(sbr_port_axi_rsp_t, sbr_b_chan_t, sbr_r_chan_t) - `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) - `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_REQ_T(mgr_port_axi_req_t, mgr_aw_chan_t, w_chan_t, mgr_ar_chan_t) + `AXI_TYPEDEF_RSP_T(mgr_port_axi_rsp_t, mgr_b_chan_t, mgr_r_chan_t) - slv_port_axi_req_t [NO_SLV_PORTS-1:0] slv_reqs; - slv_port_axi_rsp_t [NO_SLV_PORTS-1:0] slv_rsps; - mst_port_axi_req_t mst_req; - mst_port_axi_rsp_t mst_rsp; + sbr_port_axi_req_t [NO_SBR_PORTS-1:0] sbr_reqs; + sbr_port_axi_rsp_t [NO_SBR_PORTS-1:0] sbr_rsps; + mgr_port_axi_req_t mgr_req; + mgr_port_axi_rsp_t mgr_rsp; - for (genvar i = 0; i < NO_SLV_PORTS; i++) begin : gen_assign_slv_ports - `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) - `AXI_ASSIGN_FROM_RSP(slv[i], slv_rsps[i]) + for (genvar i = 0; i < NO_SBR_PORTS; i++) begin : gen_assign_sbr_ports + `AXI_ASSIGN_TO_REQ(sbr_reqs[i], sbr[i]) + `AXI_ASSIGN_FROM_RSP(sbr[i], sbr_rsps[i]) end - `AXI_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, mst) + `AXI_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_mux #( - .SlvIDWidth ( SLV_AXI_ID_WIDTH ), - .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports - .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port + .SbrIDWidth ( SBR_AXI_ID_WIDTH ), + .sbr_aw_chan_t ( sbr_aw_chan_t ), // AW Channel Type, subordinate ports + .mgr_aw_chan_t ( mgr_aw_chan_t ), // AW Channel Type, manager port .w_chan_t ( w_chan_t ), // W Channel Type, all ports - .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports - .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port - .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports - .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port - .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports - .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port - .slv_port_axi_req_t ( slv_port_axi_req_t ), - .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), - .mst_port_axi_req_t ( mst_port_axi_req_t ), - .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), - .NumSlvPorts ( NO_SLV_PORTS ), // Number of slave ports + .sbr_b_chan_t ( sbr_b_chan_t ), // B Channel Type, subordinate ports + .mgr_b_chan_t ( mgr_b_chan_t ), // B Channel Type, manager port + .sbr_ar_chan_t ( sbr_ar_chan_t ), // AR Channel Type, subordinate ports + .mgr_ar_chan_t ( mgr_ar_chan_t ), // AR Channel Type, manager port + .sbr_r_chan_t ( sbr_r_chan_t ), // R Channel Type, subordinate ports + .mgr_r_chan_t ( mgr_r_chan_t ), // R Channel Type, manager port + .sbr_port_axi_req_t ( sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t ( sbr_port_axi_rsp_t ), + .mgr_port_axi_req_t ( mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t ( mgr_port_axi_rsp_t ), + .NumSbrPorts ( NO_SBR_PORTS ), // Number of subordinate ports .MaxWTrans ( MAX_W_TRANS ), .FallThrough ( FALL_THROUGH ), .SpillAw ( SPILL_AW ), @@ -590,9 +590,9 @@ module axi_mux_intf #( .clk_i ( clk_i ), // Clock .rst_ni ( rst_ni ), // Asynchronous reset active low .test_i ( test_i ), // Test Mode enable - .slv_reqs_i ( slv_reqs ), - .slv_rsps_o ( slv_rsps ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + .sbr_reqs_i ( sbr_reqs ), + .sbr_rsps_o ( sbr_rsps ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); endmodule diff --git a/src/axi_pkg.sv b/src/axi_pkg.sv index d708a5649..2069272a3 100644 --- a/src/axi_pkg.sv +++ b/src/axi_pkg.sv @@ -90,11 +90,11 @@ package axi_pkg; /// Exclusive access okay. Indicates that either the read or write portion of an exclusive access /// has been successful. localparam RESP_EXOKAY = 2'b01; - /// Slave error. Used when the access has reached the slave successfully, but the slave wishes to - /// return an error condition to the originating master. + /// Subordinate error. Used when the access has reached the subordinate successfully, but the subordinate wishes to + /// return an error condition to the originating manager. localparam RESP_SLVERR = 2'b10; /// Decode error. Generated, typically by an interconnect component, to indicate that there is no - /// slave at the transaction address. + /// subordinate at the transaction address. localparam RESP_DECERR = 2'b11; /// When this bit is asserted, the interconnect, or any component, can delay the transaction @@ -281,8 +281,8 @@ package axi_pkg; /// successful. /// - Both DECERR and SLVERR mean (part of) a transaction were unsuccessful, whereas OKAY means an /// entire transaction was successful. Thus both DECERR and SLVERR precede OKAY. - /// - DECERR means (part of) a transactions could not be routed to a slave component, whereas - /// SLVERR means the transaction reached a slave component but lead to an error condition there. + /// - DECERR means (part of) a transactions could not be routed to a subordinate component, whereas + /// SLVERR means the transaction reached a subordinate component but lead to an error condition there. /// Thus DECERR precedes SLVERR because DECERR happens earlier in the handling of a transaction. function automatic resp_t resp_precedence(resp_t resp_a, resp_t resp_b); unique case (resp_a) @@ -465,28 +465,28 @@ package axi_pkg; /// Latency configuration for `axi_xbar`. typedef enum logic [9:0] { NO_LATENCY = 10'b000_00_000_00, - CUT_SLV_AX = DemuxAw | DemuxAr, - CUT_MST_AX = MuxAw | MuxAr, + CUT_SBR_AX = DemuxAw | DemuxAr, + CUT_MGR_AX = MuxAw | MuxAr, CUT_ALL_AX = DemuxAw | DemuxAr | MuxAw | MuxAr, - CUT_SLV_PORTS = DemuxAw | DemuxW | DemuxB | DemuxAr | DemuxR, - CUT_MST_PORTS = MuxAw | MuxW | MuxB | MuxAr | MuxR, + CUT_SBR_PORTS = DemuxAw | DemuxW | DemuxB | DemuxAr | DemuxR, + CUT_MGR_PORTS = MuxAw | MuxW | MuxB | MuxAr | MuxR, CUT_ALL_PORTS = 10'b111_11_111_11 } xbar_latency_e; /// Configuration for `axi_xbar`. typedef struct packed { - /// Number of slave ports of the crossbar. - /// This many master modules are connected to it. - int unsigned NumSlvPorts; - /// Number of master ports of the crossbar. - /// This many slave modules are connected to it. - int unsigned NumMstPorts; - /// Maximum number of open transactions each master connected to the crossbar can have in + /// Number of subordinate ports of the crossbar. + /// This many manager modules are connected to it. + int unsigned NumSbrPorts; + /// Number of manager ports of the crossbar. + /// This many subordinate modules are connected to it. + int unsigned NumMgrPorts; + /// Maximum number of open transactions each manager connected to the crossbar can have in /// flight at the same time. - int unsigned MaxMstTrans; - /// Maximum number of open transactions each slave connected to the crossbar can have in + int unsigned MaxMgrTrans; + /// Maximum number of open transactions each subordinate connected to the crossbar can have in /// flight at the same time. - int unsigned MaxSlvTrans; + int unsigned MaxSbrTrans; /// Determine if the internal FIFOs of the crossbar are instantiated in fallthrough mode. /// 0: No fallthrough /// 1: Fallthrough @@ -498,12 +498,12 @@ package axi_pkg; /// This is the number of `axi_multicut` stages instantiated in the line cross of the channels. /// Having multiple stages can potentially add a large number of FFs! int unsigned PipelineStages; - /// AXI ID width of the salve ports. The ID width of the master ports is determined + /// AXI ID width of the salve ports. The ID width of the manager ports is determined /// Automatically. See `axi_mux` for details. - int unsigned IdWidthSlvPorts; + int unsigned IdWidthSbrPorts; /// The used ID portion to determine if a different salve is used for the same ID. /// See `axi_demux` for details. - int unsigned IdUsedSlvPorts; + int unsigned IdUsedSbrPorts; /// Are IDs unique? bit UniqueIds; /// AXI4+ATOP address field width. @@ -511,7 +511,7 @@ package axi_pkg; /// AXI4+ATOP data field width. int unsigned DataWidth; /// The number of address rules defined for routing of the transactions. - /// Each master port can have multiple rules, should have however at least one. + /// Each manager port can have multiple rules, should have however at least one. /// If a transaction can not be routed the xbar will answer with an `axi_pkg::RESP_DECERR`. int unsigned NumAddrRules; } xbar_cfg_t; diff --git a/src/axi_rw_join.sv b/src/axi_rw_join.sv index a18ab52b8..334ff19bd 100644 --- a/src/axi_rw_join.sv +++ b/src/axi_rw_join.sv @@ -15,27 +15,27 @@ `include "axi/assign.svh" `include "common_cells/assertions.svh" -/// Joins a read and a write slave into one single read / write master +/// Joins a read and a write subordinate into one single read / write manager /// -/// Connects the ar and r channel of the read slave to the read / write master -/// and the aw, w and b channel of the write slave to the read / write master +/// Connects the ar and r channel of the read subordinate to the read / write manager +/// and the aw, w and b channel of the write subordinate to the read / write manager module axi_rw_join #( parameter type axi_req_t = logic, parameter type axi_rsp_t = logic ) ( input logic clk_i, input logic rst_ni, - // Read Slave - input axi_req_t slv_read_req_i, - output axi_rsp_t slv_read_rsp_o, + // Read Subordinate + input axi_req_t sbr_read_req_i, + output axi_rsp_t sbr_read_rsp_o, - // Write Slave - input axi_req_t slv_write_req_i, - output axi_rsp_t slv_write_rsp_o, + // Write Subordinate + input axi_req_t sbr_write_req_i, + output axi_rsp_t sbr_write_rsp_o, - // Read / Write Master - output axi_req_t mst_req_o, - input axi_rsp_t mst_rsp_i + // Read / Write Manager + output axi_req_t mgr_req_o, + input axi_rsp_t mgr_rsp_i ); //-------------------------------------- @@ -43,11 +43,11 @@ module axi_rw_join #( //-------------------------------------- // Assign Read Structs - `AXI_ASSIGN_AR_STRUCT ( mst_req_o.ar , slv_read_req_i.ar ) - `AXI_ASSIGN_R_STRUCT ( slv_read_rsp_o.r , mst_rsp_i.r ) + `AXI_ASSIGN_AR_STRUCT ( mgr_req_o.ar , sbr_read_req_i.ar ) + `AXI_ASSIGN_R_STRUCT ( sbr_read_rsp_o.r , mgr_rsp_i.r ) // Read B channel data - assign slv_read_rsp_o.b = '0; + assign sbr_read_rsp_o.b = '0; //-------------------------------------- @@ -55,33 +55,33 @@ module axi_rw_join #( //-------------------------------------- // Read AR channel handshake - assign mst_req_o.ar_valid = slv_read_req_i.ar_valid; - assign slv_read_rsp_o.ar_ready = mst_rsp_i.ar_ready; + assign mgr_req_o.ar_valid = sbr_read_req_i.ar_valid; + assign sbr_read_rsp_o.ar_ready = mgr_resp_i.ar_ready; // Read R channel handshake - assign slv_read_rsp_o.r_valid = mst_rsp_i.r_valid; - assign mst_req_o.r_ready = slv_read_req_i.r_ready; + assign sbr_read_rsp_o.r_valid = mgr_resp_i.r_valid; + assign mgr_req_o.r_ready = sbr_read_req_i.r_ready; // Read AW, W and B handshake - assign slv_read_rsp_o.aw_ready = 1'b0; - assign slv_read_rsp_o.w_ready = 1'b0; - assign slv_read_rsp_o.b_valid = 1'b0; + assign sbr_read_rsp_o.aw_ready = 1'b0; + assign sbr_read_rsp_o.w_ready = 1'b0; + assign sbr_read_rsp_o.b_valid = 1'b0; // check for AW and W never to be valid - `ASSERT_NEVER(slv_read_req_aw_valid, slv_read_req_i.aw_valid, clk_i, !rst_ni) - `ASSERT_NEVER(slv_read_req_w_valid, slv_read_req_i.w_valid, clk_i, !rst_ni) + `ASSERT_NEVER(sbr_read_req_aw_valid, sbr_read_req_i.aw_valid, clk_i, !rst_ni) + `ASSERT_NEVER(sbr_read_req_w_valid, sbr_read_req_i.w_valid, clk_i, !rst_ni) //-------------------------------------- // Write channel data //-------------------------------------- // Assign Write Structs - `AXI_ASSIGN_AW_STRUCT ( mst_req_o.aw , slv_write_req_i.aw ) - `AXI_ASSIGN_W_STRUCT ( mst_req_o.w , slv_write_req_i.w ) - `AXI_ASSIGN_B_STRUCT ( slv_write_rsp_o.b , mst_rsp_i.b ) + `AXI_ASSIGN_AW_STRUCT ( mgr_req_o.aw , sbr_write_req_i.aw ) + `AXI_ASSIGN_W_STRUCT ( mgr_req_o.w , sbr_write_req_i.w ) + `AXI_ASSIGN_B_STRUCT ( sbr_write_resp_o.b , mgr_rsp_i.b ) // Write R channel data - assign slv_write_rsp_o.r = '0; + assign sbr_write_rsp_o.r = '0; //-------------------------------------- @@ -89,22 +89,22 @@ module axi_rw_join #( //-------------------------------------- // Write AR and R channel handshake - assign slv_write_rsp_o.ar_ready = 1'b0; - assign slv_write_rsp_o.r_valid = 1'b0; + assign sbr_write_rsp_o.ar_ready = 1'b0; + assign sbr_write_rsp_o.r_valid = 1'b0; // check for AR to never be valid - `ASSERT_NEVER(slv_write_req_ar_valid, slv_write_req_i.ar_valid, clk_i, !rst_ni) + `ASSERT_NEVER(sbr_write_req_ar_valid, sbr_write_req_i.ar_valid, clk_i, !rst_ni) // Write AW channel handshake - assign mst_req_o.aw_valid = slv_write_req_i.aw_valid; - assign slv_write_rsp_o.aw_ready = mst_rsp_i.aw_ready; + assign mgr_req_o.aw_valid = sbr_write_req_i.aw_valid; + assign sbr_write_rsp_o.aw_ready = mgr_rsp_i.aw_ready; // Write W channel handshake - assign mst_req_o.w_valid = slv_write_req_i.w_valid; - assign slv_write_rsp_o.w_ready = mst_rsp_i.w_ready; + assign mgr_req_o.w_valid = sbr_write_req_i.w_valid; + assign sbr_write_rsp_o.w_ready = mgr_rsp_i.w_ready; // Write B channel handshake - assign slv_write_rsp_o.b_valid = mst_rsp_i.b_valid; - assign mst_req_o.b_ready = slv_write_req_i.b_ready; + assign sbr_write_rsp_o.b_valid = mgr_rsp_i.b_valid; + assign mgr_req_o.b_ready = sbr_write_req_i.b_ready; endmodule : axi_rw_join diff --git a/src/axi_rw_split.sv b/src/axi_rw_split.sv index c44d4426e..7d15ae616 100644 --- a/src/axi_rw_split.sv +++ b/src/axi_rw_split.sv @@ -15,27 +15,27 @@ `include "axi/assign.svh" `include "common_cells/assertions.svh" -/// Splits a single read / write slave into one read and one write master +/// Splits a single read / write subordinate into one read and one write manager /// -/// Connects the ar and r channel of the read / write slave to the read master -/// and the aw, w and b channel of the read / write slave to the write master +/// Connects the ar and r channel of the read / write subordinate to the read manager +/// and the aw, w and b channel of the read / write subordinate to the write manager module axi_rw_split #( parameter type axi_req_t = logic, parameter type axi_rsp_t = logic ) ( input logic clk_i, input logic rst_ni, - // Read / Write Slave - input axi_req_t slv_req_i, - output axi_rsp_t slv_rsp_o, + // Read / Write Subordinate + input axi_req_t sbr_req_i, + output axi_rsp_t sbr_rsp_o, - // Read Master - output axi_req_t mst_read_req_o, - input axi_rsp_t mst_read_rsp_i, + // Read Manager + output axi_req_t mgr_read_req_o, + input axi_rsp_t mgr_read_rsp_i, - // Write Master - output axi_req_t mst_write_req_o, - input axi_rsp_t mst_write_rsp_i + // Write Manager + output axi_req_t mgr_write_req_o, + input axi_rsp_t mgr_write_rsp_i ); //-------------------------------------- @@ -43,12 +43,12 @@ module axi_rw_split #( //-------------------------------------- // Assign Read channel structs - `AXI_ASSIGN_AR_STRUCT ( mst_read_req_o.ar , slv_req_i.ar ) - `AXI_ASSIGN_R_STRUCT ( slv_rsp_o.r , mst_read_rsp_i.r ) + `AXI_ASSIGN_AR_STRUCT ( mgr_read_req_o.ar , sbr_req_i.ar ) + `AXI_ASSIGN_R_STRUCT ( sbr_rsp_o.r , mgr_read_rsp_i.r ) // Read AW and W channel data - assign mst_read_req_o.aw = '0; - assign mst_read_req_o.w = '0; + assign mgr_read_req_o.aw = '0; + assign mgr_read_req_o.w = '0; //-------------------------------------- @@ -56,20 +56,20 @@ module axi_rw_split #( //-------------------------------------- // Read AR channel handshake - assign mst_read_req_o.ar_valid = slv_req_i.ar_valid; - assign slv_rsp_o.ar_ready = mst_read_rsp_i.ar_ready; + assign mgr_read_req_o.ar_valid = sbr_req_i.ar_valid; + assign sbr_rsp_o.ar_ready = mgr_read_rsp_i.ar_ready; // Read R channel handshake - assign slv_rsp_o.r_valid = mst_read_rsp_i.r_valid; - assign mst_read_req_o.r_ready = slv_req_i.r_ready; + assign sbr_rsp_o.r_valid = mgr_read_rsp_i.r_valid; + assign mgr_read_req_o.r_ready = sbr_req_i.r_ready; // Read AW, W and B handshake - assign mst_read_req_o.aw_valid = 1'b0; - assign mst_read_req_o.w_valid = 1'b0; - assign mst_read_req_o.b_ready = 1'b0; + assign mgr_read_req_o.aw_valid = 1'b0; + assign mgr_read_req_o.w_valid = 1'b0; + assign mgr_read_req_o.b_ready = 1'b0; // check for B never to be valid - `ASSERT_NEVER(mst_read_rsp_b_valid, mst_read_rsp_i.b_valid, clk_i, !rst_ni) + `ASSERT_NEVER(mgr_read_rsp_b_valid, mgr_read_rsp_i.b_valid, clk_i, !rst_ni) //-------------------------------------- @@ -77,12 +77,12 @@ module axi_rw_split #( //-------------------------------------- // Assign Write channel structs - `AXI_ASSIGN_AW_STRUCT ( mst_write_req_o.aw , slv_req_i.aw ) - `AXI_ASSIGN_W_STRUCT ( mst_write_req_o.w , slv_req_i.w ) - `AXI_ASSIGN_B_STRUCT ( slv_rsp_o.b , mst_write_rsp_i.b ) + `AXI_ASSIGN_AW_STRUCT ( mgr_write_req_o.aw , sbr_req_i.aw ) + `AXI_ASSIGN_W_STRUCT ( mgr_write_req_o.w , sbr_req_i.w ) + `AXI_ASSIGN_B_STRUCT ( sbr_rsp_o.b , mgr_write_rsp_i.b ) // Write AR channel data - assign mst_write_req_o.ar = '0; + assign mgr_write_req_o.ar = '0; //-------------------------------------- @@ -90,22 +90,22 @@ module axi_rw_split #( //-------------------------------------- // Write AR and R channel handshake - assign mst_write_req_o.ar_valid = 1'b0; - assign mst_write_req_o.r_ready = 1'b0; + assign mgr_write_req_o.ar_valid = 1'b0; + assign mgr_write_req_o.r_ready = 1'b0; // check for R never to be valid - `ASSERT_NEVER(mst_read_rsp_r_valid, mst_read_rsp_i.r_valid, clk_i, !rst_ni) + `ASSERT_NEVER(mgr_read_rsp_r_valid, mgr_read_rsp_i.r_valid, clk_i, !rst_ni) // Write AW channel handshake - assign mst_write_req_o.aw_valid = slv_req_i.aw_valid; - assign slv_rsp_o.aw_ready = mst_write_rsp_i.aw_ready; + assign mgr_write_req_o.aw_valid = sbr_req_i.aw_valid; + assign sbr_rsp_o.aw_ready = mgr_write_rsp_i.aw_ready; // Write W channel handshake - assign mst_write_req_o.w_valid = slv_req_i.w_valid; - assign slv_rsp_o.w_ready = mst_write_rsp_i.w_ready; + assign mgr_write_req_o.w_valid = sbr_req_i.w_valid; + assign sbr_rsp_o.w_ready = mgr_write_rsp_i.w_ready; // Write B channel handshake - assign slv_rsp_o.b_valid = mst_write_rsp_i.b_valid; - assign mst_write_req_o.b_ready = slv_req_i.b_ready; + assign sbr_rsp_o.b_valid = mgr_write_rsp_i.b_valid; + assign mgr_write_req_o.b_ready = sbr_req_i.b_ready; endmodule : axi_rw_split diff --git a/src/axi_serializer.sv b/src/axi_serializer.sv index b1310938d..6e11da131 100644 --- a/src/axi_serializer.sv +++ b/src/axi_serializer.sv @@ -16,8 +16,8 @@ /// Serialize all AXI transactions to a single ID (zero). /// -/// This module contains one queue with slave port IDs for the read direction and one for the write -/// direction. These queues are used to reconstruct the ID of responses at the slave port. The +/// This module contains one queue with subordinate port IDs for the read direction and one for the write +/// direction. These queues are used to reconstruct the ID of responses at the subordinate port. The /// depth of each queue is defined by `MaxReadTxns` and `MaxWriteTxns`, respectively. module axi_serializer #( /// Maximum number of in flight read transactions. @@ -35,14 +35,14 @@ module axi_serializer #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Slave port request - input axi_req_t slv_req_i, - /// Slave port response - output axi_rsp_t slv_rsp_o, - /// Master port request - output axi_req_t mst_req_o, - /// Master port response - input axi_rsp_t mst_rsp_i + /// Subordinate port request + input axi_req_t sbr_req_i, + /// Subordinate port response + output axi_rsp_t sbr_rsp_o, + /// Manager port request + output axi_req_t mgr_req_o, + /// Manager port response + input axi_rsp_t mgr_rsp_i ); typedef logic [IdWidth-1:0] id_t; @@ -65,23 +65,23 @@ module axi_serializer #( wr_fifo_push = 1'b0; // Default, connect the channels - mst_req_o = slv_req_i; - slv_rsp_o = mst_rsp_i; + mgr_req_o = sbr_req_i; + sbr_rsp_o = mgr_rsp_i; // Serialize transactions -> tie downstream IDs to zero. - mst_req_o.aw.id = '0; - mst_req_o.ar.id = '0; + mgr_req_o.aw.id = '0; + mgr_req_o.ar.id = '0; // Reflect upstream ID in response. - ar_id = slv_req_i.ar.id; - slv_rsp_o.b.id = b_id; - slv_rsp_o.r.id = r_id; + ar_id = sbr_req_i.ar.id; + sbr_rsp_o.b.id = b_id; + sbr_rsp_o.r.id = r_id; // Default, cut the AW/AR handshaking - mst_req_o.ar_valid = 1'b0; - slv_rsp_o.ar_ready = 1'b0; - mst_req_o.aw_valid = 1'b0; - slv_rsp_o.aw_ready = 1'b0; + mgr_req_o.ar_valid = 1'b0; + sbr_rsp_o.ar_ready = 1'b0; + mgr_req_o.aw_valid = 1'b0; + sbr_rsp_o.aw_ready = 1'b0; unique case (state_q) AtopIdle, AtopExecute: begin @@ -98,20 +98,20 @@ module axi_serializer #( // response has been transmitted. if ((state_q == AtopIdle) || (state_d == AtopIdle)) begin // Gate AR handshake with ready output of Read FIFO. - mst_req_o.ar_valid = slv_req_i.ar_valid & ~rd_fifo_full; - slv_rsp_o.ar_ready = mst_rsp_i.ar_ready & ~rd_fifo_full; - rd_fifo_push = mst_req_o.ar_valid & mst_rsp_i.ar_ready; - if (slv_req_i.aw_valid) begin - if (slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) begin + mgr_req_o.ar_valid = sbr_req_i.ar_valid & ~rd_fifo_full; + sbr_rsp_o.ar_ready = mgr_resp_i.ar_ready & ~rd_fifo_full; + rd_fifo_push = mgr_req_o.ar_valid & mgr_rsp_i.ar_ready; + if (sbr_req_i.aw_valid) begin + if (sbr_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) begin // Normal operation // Gate AW handshake with ready output of Write FIFO. - mst_req_o.aw_valid = ~wr_fifo_full; - slv_rsp_o.aw_ready = mst_rsp_i.aw_ready & ~wr_fifo_full; - wr_fifo_push = mst_req_o.aw_valid & mst_rsp_i.aw_ready; + mgr_req_o.aw_valid = ~wr_fifo_full; + sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready & ~wr_fifo_full; + wr_fifo_push = mgr_req_o.aw_valid & mgr_rsp_i.aw_ready; end else begin // Atomic Operation received, go to drain state, when both channels are ready // Wait for finished or no AR beat - if (!mst_req_o.ar_valid || (mst_req_o.ar_valid && mst_rsp_i.ar_ready)) begin + if (!mgr_req_o.ar_valid || (mgr_req_o.ar_valid && mgr_rsp_i.ar_ready)) begin state_d = AtopDrain; end end @@ -121,15 +121,15 @@ module axi_serializer #( AtopDrain: begin // Send the ATOP AW when the last open transaction terminates if (wr_fifo_empty && rd_fifo_empty) begin - mst_req_o.aw_valid = 1'b1; - slv_rsp_o.aw_ready = mst_rsp_i.aw_ready; - wr_fifo_push = mst_rsp_i.aw_ready; - if (slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin + mgr_req_o.aw_valid = 1'b1; + sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready; + wr_fifo_push = mgr_rsp_i.aw_ready; + if (sbr_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // Overwrite the read ID with the one from AW - ar_id = slv_req_i.aw.id; - rd_fifo_push = mst_rsp_i.aw_ready; + ar_id = sbr_req_i.aw.id; + rd_fifo_push = mgr_rsp_i.aw_ready; end - if (mst_rsp_i.aw_ready) begin + if (mgr_rsp_i.aw_ready) begin state_d = AtopExecute; end end @@ -138,12 +138,12 @@ module axi_serializer #( endcase // Gate B handshake with empty flag output of Write FIFO. - slv_rsp_o.b_valid = mst_rsp_i.b_valid & ~wr_fifo_empty; - mst_req_o.b_ready = slv_req_i.b_ready & ~wr_fifo_empty; + sbr_rsp_o.b_valid = mgr_rsp_i.b_valid & ~wr_fifo_empty; + mgr_req_o.b_ready = sbr_req_i.b_ready & ~wr_fifo_empty; // Gate R handshake with empty flag output of Read FIFO. - slv_rsp_o.r_valid = mst_rsp_i.r_valid & ~rd_fifo_empty; - mst_req_o.r_ready = slv_req_i.r_ready & ~rd_fifo_empty; + sbr_rsp_o.r_valid = mgr_rsp_i.r_valid & ~rd_fifo_empty; + mgr_req_o.r_ready = sbr_req_i.r_ready & ~rd_fifo_empty; end fifo_v3 #( @@ -164,7 +164,7 @@ module axi_serializer #( .usage_o ( /*not used*/ ) ); // Assign as this condition is needed in FSM - assign rd_fifo_pop = slv_rsp_o.r_valid & slv_req_i.r_ready & slv_rsp_o.r.last; + assign rd_fifo_pop = sbr_rsp_o.r_valid & sbr_req_i.r_ready & sbr_rsp_o.r.last; fifo_v3 #( .FALL_THROUGH ( 1'b0 ), @@ -175,7 +175,7 @@ module axi_serializer #( .rst_ni, .flush_i ( 1'b0 ), .testmode_i ( 1'b0 ), - .data_i ( slv_req_i.aw.id ), + .data_i ( sbr_req_i.aw.id ), .push_i ( wr_fifo_push ), .full_o ( wr_fifo_full ), .data_o ( b_id ), @@ -184,7 +184,7 @@ module axi_serializer #( .usage_o ( /*not used*/ ) ); // Assign as this condition is needed in FSM - assign wr_fifo_pop = slv_rsp_o.b_valid & slv_req_i.b_ready; + assign wr_fifo_pop = sbr_rsp_o.b_valid & sbr_req_i.b_ready; `FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni) @@ -199,19 +199,19 @@ module axi_serializer #( end default disable iff (~rst_ni); aw_lost : assert property( @(posedge clk_i) - (slv_req_i.aw_valid & slv_rsp_o.aw_ready |-> mst_req_o.aw_valid & mst_rsp_i.aw_ready)) + (sbr_req_i.aw_valid & sbr_rsp_o.aw_ready |-> mgr_req_o.aw_valid & mgr_rsp_i.aw_ready)) else $error("AW beat lost."); w_lost : assert property( @(posedge clk_i) - (slv_req_i.w_valid & slv_rsp_o.w_ready |-> mst_req_o.w_valid & mst_rsp_i.w_ready)) + (sbr_req_i.w_valid & sbr_rsp_o.w_ready |-> mgr_req_o.w_valid & mgr_rsp_i.w_ready)) else $error("W beat lost."); b_lost : assert property( @(posedge clk_i) - (mst_rsp_i.b_valid & mst_req_o.b_ready |-> slv_rsp_o.b_valid & slv_req_i.b_ready)) + (mgr_rsp_i.b_valid & mgr_req_o.b_ready |-> sbr_rsp_o.b_valid & sbr_req_i.b_ready)) else $error("B beat lost."); ar_lost : assert property( @(posedge clk_i) - (slv_req_i.ar_valid & slv_rsp_o.ar_ready |-> mst_req_o.ar_valid & mst_rsp_i.ar_ready)) + (sbr_req_i.ar_valid & sbr_rsp_o.ar_ready |-> mgr_req_o.ar_valid & mgr_rsp_i.ar_ready)) else $error("AR beat lost."); r_lost : assert property( @(posedge clk_i) - (mst_rsp_i.r_valid & mst_req_o.r_ready |-> slv_rsp_o.r_valid & slv_req_i.r_ready)) + (mgr_rsp_i.r_valid & mgr_req_o.r_ready |-> sbr_rsp_o.r_valid & sbr_req_i.r_ready)) else $error("R beat lost."); `endif // pragma translate_on @@ -238,10 +238,10 @@ module axi_serializer_intf #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// AXI4+ATOP Slave modport - AXI_BUS.Slave slv, - /// AXI4+ATOP Master modport - AXI_BUS.Master mst + /// AXI4+ATOP Subordinate modport + AXI_BUS.Subordinate sbr, + /// AXI4+ATOP Manager modport + AXI_BUS.Manager mgr ); typedef logic [AXI_ID_WIDTH -1:0] id_t; @@ -256,12 +256,12 @@ module axi_serializer_intf #( `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t slv_req, mst_req; - axi_rsp_t slv_rsp, mst_rsp; - `AXI_ASSIGN_TO_REQ(slv_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, slv_rsp) - `AXI_ASSIGN_FROM_REQ(mst, mst_req) - `AXI_ASSIGN_TO_RSP(mst_rsp, mst) + axi_req_t sbr_req, mgr_req; + axi_rsp_t sbr_rsp, mgr_rsp; + `AXI_ASSIGN_TO_REQ(sbr_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, sbr_rsp) + `AXI_ASSIGN_FROM_REQ(mgr, mgr_req) + `AXI_ASSIGN_TO_RSP(mgr_rsp, mgr) axi_serializer #( .MaxReadTxns ( MAX_READ_TXNS ), @@ -272,10 +272,10 @@ module axi_serializer_intf #( ) i_axi_serializer ( .clk_i, .rst_ni, - .slv_req_i ( slv_req ), - .slv_rsp_o ( slv_rsp ), - .mst_req_o ( mst_req ), - .mst_rsp_i ( mst_rsp ) + .sbr_req_i ( sbr_req ), + .sbr_rsp_o ( sbr_rsp ), + .mgr_req_o ( mgr_req ), + .mgr_rsp_i ( mgr_rsp ) ); // pragma translate_off diff --git a/src/axi_sim_mem.sv b/src/axi_sim_mem.sv index ac468996e..98f319c1e 100644 --- a/src/axi_sim_mem.sv +++ b/src/axi_sim_mem.sv @@ -9,7 +9,7 @@ `include "axi/typedef.svh" -/// Infinite (Simulation-Only) Memory with AXI Slave Port +/// Infinite (Simulation-Only) Memory with AXI Subordinate Port /// /// The memory array is named `mem`, and it is *not* initialized or reset. This makes it possible to /// load the memory of this module in simulation with an external `$readmem*` command, e.g., @@ -348,7 +348,7 @@ module axi_sim_mem_intf #( ) ( input logic clk_i, input logic rst_ni, - AXI_BUS.Slave axi_slv, + AXI_BUS.Subordinate axi_sbr, output logic mon_w_valid_o, output logic [AXI_ADDR_WIDTH-1:0] mon_w_addr_o, output logic [AXI_DATA_WIDTH-1:0] mon_w_data_o, @@ -375,8 +375,8 @@ module axi_sim_mem_intf #( axi_req_t axi_req; axi_rsp_t axi_rsp; - `AXI_ASSIGN_TO_REQ(axi_req, axi_slv) - `AXI_ASSIGN_FROM_RSP(axi_slv, axi_rsp) + `AXI_ASSIGN_TO_REQ(axi_req, axi_sbr) + `AXI_ASSIGN_FROM_RSP(axi_sbr, axi_rsp) axi_sim_mem #( .AddrWidth (AXI_ADDR_WIDTH), diff --git a/src/axi_slave_compare.sv b/src/axi_subordinate_compare.sv similarity index 83% rename from src/axi_slave_compare.sv rename to src/axi_subordinate_compare.sv index 07a2b4b10..aabbe843e 100644 --- a/src/axi_slave_compare.sv +++ b/src/axi_subordinate_compare.sv @@ -13,11 +13,11 @@ // - Thomas Benz `include "axi/assign.svh" -/// Synthesizable test module comparing two AXI slaves of the same type. -/// The reference response is always passed to the master, whereas the test response +/// Synthesizable test module comparing two AXI subordinates of the same type. +/// The reference response is always passed to the manager, whereas the test response /// is discarded after handshaking. /// This module is meant to be used in FPGA-based verification. -module axi_slave_compare #( +module axi_subordinate_compare #( /// ID width of the AXI4+ATOP interface parameter int unsigned IdWidth = 32'd0, /// FIFO depth @@ -32,9 +32,9 @@ module axi_slave_compare #( parameter type axi_ar_chan_t = logic, /// R channel type of the AXI4+ATOP interface parameter type axi_r_chan_t = logic, - /// Request struct type of the AXI4+ATOP slave port + /// Request struct type of the AXI4+ATOP subordinate port parameter type axi_req_t = logic, - /// Response struct type of the AXI4+ATOP slave port + /// Response struct type of the AXI4+ATOP subordinate port parameter type axi_rsp_t = logic, /// ID type (*do not overwrite*) parameter type id_t = logic [2**IdWidth-1:0] @@ -46,9 +46,9 @@ module axi_slave_compare #( /// Testmode input logic testmode_i, /// AXI4+ATOP channel request in - input axi_req_t axi_mst_req_i, + input axi_req_t axi_mgr_req_i, /// AXI4+ATOP channel response out - output axi_rsp_t axi_mst_rsp_o, + output axi_rsp_t axi_mgr_rsp_o, /// AXI4+ATOP reference channel request out output axi_req_t axi_ref_req_o, /// AXI4+ATOP reference channel response in @@ -84,17 +84,17 @@ module axi_slave_compare #( logic w_valid_test, w_ready_test; logic ar_valid_test, ar_ready_test; - logic aw_ready_mst; - logic w_ready_mst; - logic ar_ready_mst; + logic aw_ready_mgr; + logic w_ready_mgr; + logic ar_ready_mgr; stream_fork #( .N_OUP ( 32'd2 ) ) i_stream_fork_aw ( .clk_i, .rst_ni, - .valid_i ( axi_mst_req_i.aw_valid ), - .ready_o ( aw_ready_mst ), + .valid_i ( axi_mgr_req_i.aw_valid ), + .ready_o ( aw_ready_mgr ), .valid_o ( { aw_valid_ref, aw_valid_test } ), .ready_i ( { aw_ready_ref, aw_ready_test } ) ); @@ -104,8 +104,8 @@ module axi_slave_compare #( ) i_stream_fork_ar ( .clk_i, .rst_ni, - .valid_i ( axi_mst_req_i.ar_valid ), - .ready_o ( ar_ready_mst ), + .valid_i ( axi_mgr_req_i.ar_valid ), + .ready_o ( ar_ready_mgr ), .valid_o ( { ar_valid_ref, ar_valid_test } ), .ready_i ( { ar_ready_ref, ar_ready_test } ) ); @@ -115,8 +115,8 @@ module axi_slave_compare #( ) i_stream_fork_w ( .clk_i, .rst_ni, - .valid_i ( axi_mst_req_i.w_valid ), - .ready_o ( w_ready_mst ), + .valid_i ( axi_mgr_req_i.w_valid ), + .ready_o ( w_ready_mgr ), .valid_o ( { w_valid_ref, w_valid_test } ), .ready_i ( { w_ready_ref, w_ready_test } ) ); @@ -124,8 +124,8 @@ module axi_slave_compare #( // assemble buses always_comb begin // request - `AXI_SET_REQ_STRUCT(axi_ref_req_in, axi_mst_req_i) - `AXI_SET_REQ_STRUCT(axi_test_req_in, axi_mst_req_i) + `AXI_SET_REQ_STRUCT(axi_ref_req_in, axi_mgr_req_i) + `AXI_SET_REQ_STRUCT(axi_test_req_in, axi_mgr_req_i) // overwrite valids in requests axi_ref_req_in.aw_valid = aw_valid_ref; axi_ref_req_in.ar_valid = ar_valid_ref; @@ -141,11 +141,11 @@ module axi_slave_compare #( ar_ready_test = axi_test_rsp_in.ar_ready; w_ready_test = axi_test_rsp_in.w_ready; // response - `AXI_SET_RSP_STRUCT(axi_mst_rsp_o, axi_ref_rsp_in) + `AXI_SET_RSP_STRUCT(axi_mgr_rsp_o, axi_ref_rsp_in) // overwrite readies - axi_mst_rsp_o.aw_ready = aw_ready_mst; - axi_mst_rsp_o.w_ready = w_ready_mst; - axi_mst_rsp_o.ar_ready = ar_ready_mst; + axi_mgr_rsp_o.aw_ready = aw_ready_mgr; + axi_mgr_rsp_o.w_ready = w_ready_mgr; + axi_mgr_rsp_o.ar_ready = ar_ready_mgr; // b interface is not used axi_test_req_in.r_ready = '1; axi_test_req_in.b_ready = '1; diff --git a/src/axi_test.sv b/src/axi_test.sv index b680fc3f8..858a44504 100644 --- a/src/axi_test.sv +++ b/src/axi_test.sv @@ -42,7 +42,7 @@ package axi_test; this.axi = axi; endfunction - function void reset_master(); + function void reset_manager(); axi.aw_addr <= '0; axi.aw_prot <= '0; axi.aw_valid <= '0; @@ -56,7 +56,7 @@ package axi_test; axi.r_ready <= '0; endfunction - function void reset_slave(); + function void reset_subordinate(); axi.aw_ready <= '0; axi.w_ready <= '0; axi.b_resp <= '0; @@ -310,7 +310,7 @@ package axi_test; this.axi = axi; endfunction - function void reset_master(); + function void reset_manager(); axi.aw_id <= '0; axi.aw_addr <= '0; axi.aw_len <= '0; @@ -345,7 +345,7 @@ package axi_test; axi.r_ready <= '0; endfunction - function void reset_slave(); + function void reset_subordinate(); axi.aw_ready <= '0; axi.w_ready <= '0; axi.b_id <= '0; @@ -678,7 +678,7 @@ package axi_test; endclass - class axi_rand_master #( + class axi_rand_manager #( // AXI interface parameters parameter int AW = 32, parameter int DW = 32, @@ -794,7 +794,7 @@ package axi_test; endfunction function void reset(); - drv.reset_master(); + drv.reset_manager(); r_flight_cnt = '{default: 0}; w_flight_cnt = '{default: 0}; tot_r_flight_cnt = 0; @@ -1060,7 +1060,7 @@ package axi_test; )) return 1'b0; end if (UNIQUE_IDS) begin - // This master may only emit transactions with an ID that is unique among all in-flight + // This manager may only emit transactions with an ID that is unique among all in-flight // transactions in the same direction. if (is_read && r_flight_cnt[beat.ax_id] != 0) return 1'b0; if (!is_read && w_flight_cnt[beat.ax_id] != 0) return 1'b0; @@ -1258,7 +1258,7 @@ package axi_test; endclass - class axi_rand_slave #( + class axi_rand_subordinate #( // AXI interface parameters parameter int AW = 32, parameter int DW = 32, @@ -1318,7 +1318,7 @@ package axi_test; endfunction function void reset(); - this.drv.reset_slave(); + this.drv.reset_subordinate(); this.memory_q.delete(); endfunction @@ -1490,8 +1490,8 @@ package axi_test; endclass - // AXI4-Lite random master and slave - class axi_lite_rand_master #( + // AXI4-Lite random manager and subordinate + class axi_lite_rand_manager #( // AXI interface parameters parameter int unsigned AW = 0, parameter int unsigned DW = 0, @@ -1540,7 +1540,7 @@ package axi_test; endfunction function void reset(); - drv.reset_master(); + drv.reset_manager(); endfunction task automatic rand_wait(input int unsigned min, max); @@ -1660,7 +1660,7 @@ package axi_test; endtask : read endclass - class axi_lite_rand_slave #( + class axi_lite_rand_subordinate #( // AXI interface parameters parameter int unsigned AW = 0, parameter int unsigned DW = 0, @@ -1703,7 +1703,7 @@ package axi_test; endfunction function void reset(); - this.drv.reset_slave(); + this.drv.reset_subordinate(); endfunction task automatic rand_wait(input int unsigned min, max); diff --git a/src/axi_to_axi_lite.sv b/src/axi_to_axi_lite.sv index 259a229df..d0de1a38f 100644 --- a/src/axi_to_axi_lite.sv +++ b/src/axi_to_axi_lite.sv @@ -31,12 +31,12 @@ module axi_to_axi_lite #( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Testmode enable - // slave port full AXI4+ATOP - input axi_req_t slv_req_i, - output axi_rsp_t slv_rsp_o, - // master port AXI4-Lite - output axi_lite_req_t mst_req_o, - input axi_lite_rsp_t mst_rsp_i + // subordinate port full AXI4+ATOP + input axi_req_t sbr_req_i, + output axi_rsp_t sbr_rsp_o, + // manager port AXI4-Lite + output axi_lite_req_t mgr_req_o, + input axi_lite_rsp_t mgr_rsp_i ); // full bus declarations axi_req_t filtered_req, splitted_req; @@ -51,10 +51,10 @@ module axi_to_axi_lite #( ) i_axi_atop_filter( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .slv_req_i ( slv_req_i ), - .slv_rsp_o ( slv_rsp_o ), - .mst_req_o ( filtered_req ), - .mst_rsp_i ( filtered_rsp ) + .sbr_req_i ( sbr_req_i ), + .sbr_rsp_o ( sbr_rsp_o ), + .mgr_req_o ( filtered_req ), + .mgr_rsp_i ( filtered_rsp ) ); // burst splitter so that the id reflect module has no burst accessing it @@ -70,10 +70,10 @@ module axi_to_axi_lite #( ) i_axi_burst_splitter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .slv_req_i ( filtered_req ), - .slv_rsp_o ( filtered_rsp ), - .mst_req_o ( splitted_req ), - .mst_rsp_i ( splitted_rsp ) + .sbr_req_i ( filtered_req ), + .sbr_rsp_o ( filtered_rsp ), + .mgr_req_o ( splitted_req ), + .mgr_rsp_i ( splitted_rsp ) ); // ID reflect module handles the conversion from the full AXI to AXI lite on the wireing @@ -90,10 +90,10 @@ module axi_to_axi_lite #( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .test_i ( test_i ), - .slv_req_i ( splitted_req ), - .slv_rsp_o ( splitted_rsp ), - .mst_req_o ( mst_req_o ), - .mst_rsp_i ( mst_rsp_i ) + .sbr_req_i ( splitted_req ), + .sbr_rsp_o ( splitted_rsp ), + .mgr_req_o ( mgr_req_o ), + .mgr_rsp_i ( mgr_rsp_i ) ); // Assertions, check params @@ -126,12 +126,12 @@ module axi_to_axi_lite_id_reflect #( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Testmode enable - // slave port full AXI - input axi_req_t slv_req_i, - output axi_rsp_t slv_rsp_o, - // master port AXI LITE - output axi_lite_req_t mst_req_o, - input axi_lite_rsp_t mst_rsp_i + // subordinate port full AXI + input axi_req_t sbr_req_i, + output axi_rsp_t sbr_rsp_o, + // manager port AXI LITE + output axi_lite_req_t mgr_req_o, + input axi_lite_rsp_t mgr_rsp_i ); typedef logic [IdWidth-1:0] id_t; @@ -139,30 +139,30 @@ module axi_to_axi_lite_id_reflect #( logic aw_full, aw_empty, aw_push, aw_pop, ar_full, ar_empty, ar_push, ar_pop; id_t aw_reflect_id, ar_reflect_id; - assign slv_rsp_o = '{ - aw_ready: mst_rsp_i.aw_ready & ~aw_full, - w_ready: mst_rsp_i.w_ready, + assign sbr_rsp_o = '{ + aw_ready: mgr_rsp_i.aw_ready & ~aw_full, + w_ready: mgr_rsp_i.w_ready, b: '{ id: aw_reflect_id, - resp: mst_rsp_i.b.resp, + resp: mgr_rsp_i.b.resp, default: '0 }, - b_valid: mst_rsp_i.b_valid & ~aw_empty, - ar_ready: mst_rsp_i.ar_ready & ~ar_full, + b_valid: mgr_rsp_i.b_valid & ~aw_empty, + ar_ready: mgr_rsp_i.ar_ready & ~ar_full, r: '{ id: ar_reflect_id, - data: mst_rsp_i.r.data, - resp: mst_rsp_i.r.resp, + data: mgr_rsp_i.r.data, + resp: mgr_rsp_i.r.resp, last: 1'b1, default: '0 }, - r_valid: mst_rsp_i.r_valid & ~ar_empty, + r_valid: mgr_rsp_i.r_valid & ~ar_empty, default: '0 }; // Write ID reflection - assign aw_push = mst_req_o.aw_valid & slv_rsp_o.aw_ready; - assign aw_pop = slv_rsp_o.b_valid & mst_req_o.b_ready; + assign aw_push = mgr_req_o.aw_valid & sbr_rsp_o.aw_ready; + assign aw_pop = sbr_rsp_o.b_valid & mgr_req_o.b_ready; fifo_v3 #( .FALL_THROUGH ( FallThrough ), .DEPTH ( MaxWriteTxns ), @@ -175,15 +175,15 @@ module axi_to_axi_lite_id_reflect #( .full_o ( aw_full ), .empty_o ( aw_empty ), .usage_o ( /*not used*/ ), - .data_i ( slv_req_i.aw.id ), + .data_i ( sbr_req_i.aw.id ), .push_i ( aw_push ), .data_o ( aw_reflect_id ), .pop_i ( aw_pop ) ); // Read ID reflection - assign ar_push = mst_req_o.ar_valid & slv_rsp_o.ar_ready; - assign ar_pop = slv_rsp_o.r_valid & mst_req_o.r_ready; + assign ar_push = mgr_req_o.ar_valid & sbr_rsp_o.ar_ready; + assign ar_pop = sbr_rsp_o.r_valid & mgr_req_o.r_ready; fifo_v3 #( .FALL_THROUGH ( FallThrough ), .DEPTH ( MaxReadTxns ), @@ -196,30 +196,30 @@ module axi_to_axi_lite_id_reflect #( .full_o ( ar_full ), .empty_o ( ar_empty ), .usage_o ( /*not used*/ ), - .data_i ( slv_req_i.ar.id ), + .data_i ( sbr_req_i.ar.id ), .push_i ( ar_push ), .data_o ( ar_reflect_id ), .pop_i ( ar_pop ) ); - assign mst_req_o = '{ + assign mgr_req_o = '{ aw: '{ - addr: slv_req_i.aw.addr, - prot: slv_req_i.aw.prot + addr: sbr_req_i.aw.addr, + prot: sbr_req_i.aw.prot }, - aw_valid: slv_req_i.aw_valid & ~aw_full, + aw_valid: sbr_req_i.aw_valid & ~aw_full, w: '{ - data: slv_req_i.w.data, - strb: slv_req_i.w.strb + data: sbr_req_i.w.data, + strb: sbr_req_i.w.strb }, - w_valid: slv_req_i.w_valid, - b_ready: slv_req_i.b_ready & ~aw_empty, + w_valid: sbr_req_i.w_valid, + b_ready: sbr_req_i.b_ready & ~aw_empty, ar: '{ - addr: slv_req_i.ar.addr, - prot: slv_req_i.ar.prot + addr: sbr_req_i.ar.addr, + prot: sbr_req_i.ar.prot }, - ar_valid: slv_req_i.ar_valid & ~ar_full, - r_ready: slv_req_i.r_ready & ~ar_empty, + ar_valid: sbr_req_i.ar_valid & ~ar_full, + r_ready: sbr_req_i.r_ready & ~ar_empty, default: '0 }; @@ -227,17 +227,17 @@ module axi_to_axi_lite_id_reflect #( // pragma translate_off `ifndef VERILATOR aw_atop: assume property( @(posedge clk_i) disable iff (~rst_ni) - slv_req_i.aw_valid |-> (slv_req_i.aw.atop == '0)) else - $fatal(1, "Module does not support atomics. Value observed: %0b", slv_req_i.aw.atop); + sbr_req_i.aw_valid |-> (sbr_req_i.aw.atop == '0)) else + $fatal(1, "Module does not support atomics. Value observed: %0b", sbr_req_i.aw.atop); aw_axi_len: assume property( @(posedge clk_i) disable iff (~rst_ni) - slv_req_i.aw_valid |-> (slv_req_i.aw.len == '0)) else - $fatal(1, "AW request length has to be zero. Value observed: %0b", slv_req_i.aw.len); + sbr_req_i.aw_valid |-> (sbr_req_i.aw.len == '0)) else + $fatal(1, "AW request length has to be zero. Value observed: %0b", sbr_req_i.aw.len); w_axi_last: assume property( @(posedge clk_i) disable iff (~rst_ni) - slv_req_i.w_valid |-> (slv_req_i.w.last == 1'b1)) else - $fatal(1, "W last signal has to be one. Value observed: %0b", slv_req_i.w.last); + sbr_req_i.w_valid |-> (sbr_req_i.w.last == 1'b1)) else + $fatal(1, "W last signal has to be one. Value observed: %0b", sbr_req_i.w.last); ar_axi_len: assume property( @(posedge clk_i) disable iff (~rst_ni) - slv_req_i.ar_valid |-> (slv_req_i.ar.len == '0)) else - $fatal(1, "AR request length has to be zero. Value observed: %0b", slv_req_i.ar.len); + sbr_req_i.ar_valid |-> (sbr_req_i.ar.len == '0)) else + $fatal(1, "AR request length has to be zero. Value observed: %0b", sbr_req_i.ar.len); `endif // pragma translate_on endmodule @@ -260,8 +260,8 @@ module axi_to_axi_lite_intf #( input logic clk_i, input logic rst_ni, input logic testmode_i, - AXI_BUS.Slave slv, - AXI_LITE.Master mst + AXI_BUS.Subordinate sbr, + AXI_LITE.Manager mgr ); typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; typedef logic [AXI_DATA_WIDTH-1:0] data_t; @@ -290,11 +290,11 @@ module axi_to_axi_lite_intf #( axi_lite_req_t lite_req; axi_lite_rsp_t lite_rsp; - `AXI_ASSIGN_TO_REQ(full_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, full_rsp) + `AXI_ASSIGN_TO_REQ(full_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, full_rsp) - `AXI_LITE_ASSIGN_FROM_REQ(mst, lite_req) - `AXI_LITE_ASSIGN_TO_RSP(lite_rsp, mst) + `AXI_LITE_ASSIGN_FROM_REQ(mgr, lite_req) + `AXI_LITE_ASSIGN_TO_RSP(lite_rsp, mgr) axi_to_axi_lite #( .AddrWidth ( AXI_ADDR_WIDTH ), @@ -312,11 +312,11 @@ module axi_to_axi_lite_intf #( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .test_i ( testmode_i ), - // slave port full AXI4+ATOP - .slv_req_i ( full_req ), - .slv_rsp_o ( full_rsp ), - // master port AXI4-Lite - .mst_req_o ( lite_req ), - .mst_rsp_i ( lite_rsp ) + // subordinate port full AXI4+ATOP + .sbr_req_i ( full_req ), + .sbr_rsp_o ( full_rsp ), + // manager port AXI4-Lite + .mgr_req_o ( lite_req ), + .mgr_rsp_i ( lite_rsp ) ); endmodule diff --git a/src/axi_to_mem.sv b/src/axi_to_mem.sv index df01b6b8c..a37d4f3bd 100644 --- a/src/axi_to_mem.sv +++ b/src/axi_to_mem.sv @@ -12,7 +12,7 @@ // - Michael Rogenmoser `include "common_cells/registers.svh" -/// AXI4+ATOP slave module which translates AXI bursts into a memory stream. +/// AXI4+ATOP subordinate module which translates AXI bursts into a memory stream. /// If both read and write channels of the AXI4+ATOP are active, both will have an /// utilization of 50%. module axi_to_mem #( @@ -49,28 +49,28 @@ module axi_to_mem #( input logic rst_ni, /// The unit is busy handling an AXI4+ATOP request. output logic busy_o, - /// AXI4+ATOP slave port, request input. + /// AXI4+ATOP subordinate port, request input. input axi_req_t axi_req_i, - /// AXI4+ATOP slave port, response output. + /// AXI4+ATOP subordinate port, response output. output axi_rsp_t axi_rsp_o, - /// Memory stream master, request is valid for this bank. + /// Memory stream manager, request is valid for this bank. output logic [NumBanks-1:0] mem_req_o, - /// Memory stream master, request can be granted by this bank. + /// Memory stream manager, request can be granted by this bank. input logic [NumBanks-1:0] mem_gnt_i, - /// Memory stream master, byte address of the request. + /// Memory stream manager, byte address of the request. output addr_t [NumBanks-1:0] mem_addr_o, - /// Memory stream master, write data for this bank. Valid when `mem_req_o`. + /// Memory stream manager, write data for this bank. Valid when `mem_req_o`. output mem_data_t [NumBanks-1:0] mem_wdata_o, - /// Memory stream master, byte-wise strobe (byte enable). + /// Memory stream manager, byte-wise strobe (byte enable). output mem_strb_t [NumBanks-1:0] mem_strb_o, - /// Memory stream master, `axi_pkg::atop_t` signal associated with this request. + /// Memory stream manager, `axi_pkg::atop_t` signal associated with this request. output axi_pkg::atop_t [NumBanks-1:0] mem_atop_o, - /// Memory stream master, write enable. Then asserted store of `mem_w_data` is requested. + /// Memory stream manager, write enable. Then asserted store of `mem_w_data` is requested. output logic [NumBanks-1:0] mem_we_o, - /// Memory stream master, response is valid. This module expects always a response valid for a + /// Memory stream manager, response is valid. This module expects always a response valid for a /// request regardless if the request was a write or a read. input logic [NumBanks-1:0] mem_rvalid_i, - /// Memory stream master, read response data. + /// Memory stream manager, read response data. input mem_data_t [NumBanks-1:0] mem_rdata_i ); @@ -495,8 +495,8 @@ module axi_to_mem_intf #( input logic rst_ni, /// See `axi_to_mem`, port `busy_o`. output logic busy_o, - /// AXI4+ATOP slave interface port. - AXI_BUS.Slave slv, + /// AXI4+ATOP subordinate interface port. + AXI_BUS.Subordinate sbr, /// See `axi_to_mem`, port `mem_req_o`. output logic [NUM_BANKS-1:0] mem_req_o, /// See `axi_to_mem`, port `mem_gnt_i`. @@ -527,10 +527,10 @@ module axi_to_mem_intf #( `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RSP_T(rsp_t, b_chan_t, r_chan_t) - req_t req; + req_t req; rsp_t rsp; - `AXI_ASSIGN_TO_REQ(req, slv) - `AXI_ASSIGN_FROM_RSP(slv, rsp) + `AXI_ASSIGN_TO_REQ(req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, rsp) axi_to_mem #( .axi_req_t ( req_t ), .axi_rsp_t ( rsp_t ), diff --git a/src/axi_to_mem_banked.sv b/src/axi_to_mem_banked.sv index a505f1516..ac2b56eb0 100644 --- a/src/axi_to_mem_banked.sv +++ b/src/axi_to_mem_banked.sv @@ -12,7 +12,7 @@ // - Wolfgang Rönninger // - Michael Rogenmoser -/// AXI4+ATOP to banked SRAM memory slave. Allows for parallel read and write transactions. +/// AXI4+ATOP to banked SRAM memory subordinate. Allows for parallel read and write transactions. /// Has higher throughput than `axi_to_mem`, however needs more hardware. /// /// The used address space starts at 0x0 and ends at the capacity of all memory banks combined. @@ -70,9 +70,9 @@ module axi_to_mem_banked #( input logic rst_ni, /// Testmode enable input logic test_i, - /// AXI4+ATOP slave port, request struct + /// AXI4+ATOP subordinate port, request struct input axi_req_t axi_req_i, - /// AXI4+ATOP slave port, response struct + /// AXI4+ATOP subordinate port, response struct output axi_rsp_t axi_rsp_o, /// Memory bank request output logic [MemNumBanks-1:0] mem_req_o, @@ -146,8 +146,8 @@ module axi_to_mem_banked #( .ar_chan_t ( axi_ar_chan_t ), .r_chan_t ( axi_r_chan_t ), .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ), - .NumMstPorts ( 32'd2 ), + .axi_rsp_t ( axi_rsp_t ), + .NumMgrPorts ( 32'd2 ), .MaxTrans ( MemLatency+2 ), // allow multiple Ax vectors to not starve W channel .LookBits ( 32'd1 ), // select is fixed, do not need it .UniqueIds ( 1'b0 ), @@ -160,12 +160,12 @@ module axi_to_mem_banked #( .clk_i, .rst_ni, .test_i, - .slv_req_i ( axi_req_i ), - .slv_aw_select_i ( WriteAccess ), - .slv_ar_select_i ( ReadAccess ), - .slv_rsp_o ( axi_rsp_o ), - .mst_reqs_o ( mem_axi_reqs ), - .mst_rsps_i ( mem_axi_rsps ) + .sbr_req_i ( axi_req_i ), + .sbr_aw_select_i ( WriteAccess ), + .sbr_ar_select_i ( ReadAccess ), + .sbr_rsp_o ( axi_rsp_o ), + .mgr_reqs_o ( mem_axi_reqs ), + .mgr_rsps_i ( mem_axi_rsps ) ); xbar_payload_t [1:0][BanksPerAxiChannel-1:0] inter_payload; @@ -347,8 +347,8 @@ module axi_to_mem_banked_intf #( input logic rst_ni, /// Testmode enable input logic test_i, - /// AXI4+ATOP slave port - AXI_BUS.Slave slv, + /// AXI4+ATOP subordinate port + AXI_BUS.Subordinate sbr, /// Memory bank request output logic [MEM_NUM_BANKS-1:0] mem_req_o, /// Memory request grant @@ -384,8 +384,8 @@ module axi_to_mem_banked_intf #( axi_req_t mem_axi_req; axi_rsp_t mem_axi_rsp; - `AXI_ASSIGN_TO_REQ(mem_axi_req, slv) - `AXI_ASSIGN_FROM_RSP(slv, mem_axi_rsp) + `AXI_ASSIGN_TO_REQ(mem_axi_req, sbr) + `AXI_ASSIGN_FROM_RSP(sbr, mem_axi_rsp) axi_to_mem_banked #( .IdWidth ( AXI_ID_WIDTH ), diff --git a/src/axi_to_mem_interleaved.sv b/src/axi_to_mem_interleaved.sv index 5e03870c6..85f029cb0 100644 --- a/src/axi_to_mem_interleaved.sv +++ b/src/axi_to_mem_interleaved.sv @@ -13,7 +13,7 @@ // - Thomas Benz // - Michael Rogenmoser -/// AXI4+ATOP to SRAM memory slave. Allows for parallel read and write transactions. +/// AXI4+ATOP to SRAM memory subordinate. Allows for parallel read and write transactions. /// Allows reads to bypass writes, in contrast to `axi_to_mem`, however needs more hardware. module axi_to_mem_interleaved #( /// AXI4+ATOP request type. See `include/axi/typedef.svh`. @@ -49,28 +49,28 @@ module axi_to_mem_interleaved #( input logic rst_ni, /// The unit is busy handling an AXI4+ATOP request. output logic busy_o, - /// AXI4+ATOP slave port, request input. + /// AXI4+ATOP subordinate port, request input. input axi_req_t axi_req_i, - /// AXI4+ATOP slave port, response output. + /// AXI4+ATOP subordinate port, response output. output axi_rsp_t axi_rsp_o, - /// Memory stream master, request is valid for this bank. + /// Memory stream manager, request is valid for this bank. output logic [NumBanks-1:0] mem_req_o, - /// Memory stream master, request can be granted by this bank. + /// Memory stream manager, request can be granted by this bank. input logic [NumBanks-1:0] mem_gnt_i, - /// Memory stream master, byte address of the request. + /// Memory stream manager, byte address of the request. output addr_t [NumBanks-1:0] mem_addr_o, - /// Memory stream master, write data for this bank. Valid when `mem_req_o`. + /// Memory stream manager, write data for this bank. Valid when `mem_req_o`. output mem_data_t [NumBanks-1:0] mem_wdata_o, - /// Memory stream master, byte-wise strobe (byte enable). + /// Memory stream manager, byte-wise strobe (byte enable). output mem_strb_t [NumBanks-1:0] mem_strb_o, - /// Memory stream master, `axi_pkg::atop_t` signal associated with this request. + /// Memory stream manager, `axi_pkg::atop_t` signal associated with this request. output axi_pkg::atop_t [NumBanks-1:0] mem_atop_o, - /// Memory stream master, write enable. Then asserted store of `mem_w_data` is requested. + /// Memory stream manager, write enable. Then asserted store of `mem_w_data` is requested. output logic [NumBanks-1:0] mem_we_o, - /// Memory stream master, response is valid. This module expects always a response valid for a + /// Memory stream manager, response is valid. This module expects always a response valid for a /// request regardless if the request was a write or a read. input logic [NumBanks-1:0] mem_rvalid_i, - /// Memory stream master, read response data. + /// Memory stream manager, read response data. input mem_data_t [NumBanks-1:0] mem_rdata_i ); diff --git a/src/axi_to_mem_split.sv b/src/axi_to_mem_split.sv index b351eaded..a6b6483f5 100644 --- a/src/axi_to_mem_split.sv +++ b/src/axi_to_mem_split.sv @@ -51,28 +51,28 @@ module axi_to_mem_split #( input logic rst_ni, /// The unit is busy handling an AXI4+ATOP request. output logic busy_o, - /// AXI4+ATOP slave port, request input. + /// AXI4+ATOP subordinate port, request input. input axi_req_t axi_req_i, - /// AXI4+ATOP slave port, response output. + /// AXI4+ATOP subordinate port, response output. output axi_rsp_t axi_rsp_o, - /// Memory stream master, request is valid for this bank. + /// Memory stream manager, request is valid for this bank. output logic [NumMemPorts-1:0] mem_req_o, - /// Memory stream master, request can be granted by this bank. + /// Memory stream manager, request can be granted by this bank. input logic [NumMemPorts-1:0] mem_gnt_i, - /// Memory stream master, byte address of the request. + /// Memory stream manager, byte address of the request. output addr_t [NumMemPorts-1:0] mem_addr_o, // byte address - /// Memory stream master, write data for this bank. Valid when `mem_req_o`. + /// Memory stream manager, write data for this bank. Valid when `mem_req_o`. output mem_data_t [NumMemPorts-1:0] mem_wdata_o, // write data - /// Memory stream master, byte-wise strobe (byte enable). + /// Memory stream manager, byte-wise strobe (byte enable). output mem_strb_t [NumMemPorts-1:0] mem_strb_o, // byte-wise strobe - /// Memory stream master, `axi_pkg::atop_t` signal associated with this request. + /// Memory stream manager, `axi_pkg::atop_t` signal associated with this request. output axi_pkg::atop_t [NumMemPorts-1:0] mem_atop_o, // atomic operation - /// Memory stream master, write enable. Then asserted store of `mem_w_data` is requested. + /// Memory stream manager, write enable. Then asserted store of `mem_w_data` is requested. output logic [NumMemPorts-1:0] mem_we_o, // write enable - /// Memory stream master, response is valid. This module expects always a response valid for a + /// Memory stream manager, response is valid. This module expects always a response valid for a /// request regardless if the request was a write or a read. input logic [NumMemPorts-1:0] mem_rvalid_i, // response valid - /// Memory stream master, read response data. + /// Memory stream manager, read response data. input mem_data_t [NumMemPorts-1:0] mem_rdata_i // read data ); @@ -87,12 +87,12 @@ module axi_to_mem_split #( ) i_axi_rw_split ( .clk_i, .rst_ni, - .slv_req_i ( axi_req_i ), - .slv_rsp_o ( axi_rsp_o ), - .mst_read_req_o ( axi_read_req ), - .mst_read_rsp_i ( axi_read_rsp ), - .mst_write_req_o ( axi_write_req ), - .mst_write_rsp_i ( axi_write_rsp ) + .sbr_req_i ( axi_req_i ), + .sbr_rsp_o ( axi_rsp_o ), + .mgr_read_req_o ( axi_read_req ), + .mgr_read_rsp_i ( axi_read_rsp ), + .mgr_write_req_o ( axi_write_req ), + .mgr_write_rsp_i ( axi_write_rsp ) ); assign busy_o = read_busy || write_busy; @@ -187,8 +187,8 @@ module axi_to_mem_split_intf #( input logic rst_ni, /// See `axi_to_mem_split`, port `busy_o`. output logic busy_o, - /// AXI4+ATOP slave interface port. - AXI_BUS.Slave axi_bus, + /// AXI4+ATOP subordinate interface port. + AXI_BUS.Subordinate axi_bus, /// See `axi_to_mem_split`, port `mem_req_o`. output logic [NUM_MEM_PORTS-1:0] mem_req_o, /// See `axi_to_mem_split`, port `mem_gnt_i`. diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv index 52a48535b..d9e7712a8 100644 --- a/src/axi_xbar.sv +++ b/src/axi_xbar.sv @@ -13,7 +13,7 @@ // - Andreas Kurth // - Florian Zaruba -/// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. +/// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of subordinate and manager ports. /// See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports. module axi_xbar import cf_math_pkg::idx_width; @@ -23,33 +23,33 @@ import cf_math_pkg::idx_width; /// Enable atomic operations support. parameter bit ATOPs = 1'b1, /// Connectivity matrix - parameter bit [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts-1:0] Connectivity = '1, - /// AXI4+ATOP AW channel struct type for the slave ports. - parameter type slv_aw_chan_t = logic, - /// AXI4+ATOP AW channel struct type for the master ports. - parameter type mst_aw_chan_t = logic, + parameter bit [Cfg.NumSbrPorts-1:0][Cfg.NumMgrPorts-1:0] Connectivity = '1, + /// AXI4+ATOP AW channel struct type for the subordinate ports. + parameter type sbr_aw_chan_t = logic, + /// AXI4+ATOP AW channel struct type for the manager ports. + parameter type mgr_aw_chan_t = logic, /// AXI4+ATOP W channel struct type for all ports. parameter type w_chan_t = logic, - /// AXI4+ATOP B channel struct type for the slave ports. - parameter type slv_b_chan_t = logic, - /// AXI4+ATOP B channel struct type for the master ports. - parameter type mst_b_chan_t = logic, - /// AXI4+ATOP AR channel struct type for the slave ports. - parameter type slv_ar_chan_t = logic, - /// AXI4+ATOP AR channel struct type for the master ports. - parameter type mst_ar_chan_t = logic, - /// AXI4+ATOP R channel struct type for the slave ports. - parameter type slv_r_chan_t = logic, - /// AXI4+ATOP R channel struct type for the master ports. - parameter type mst_r_chan_t = logic, - /// AXI4+ATOP request struct type for the slave ports. - parameter type slv_port_axi_req_t = logic, - /// AXI4+ATOP response struct type for the slave ports. - parameter type slv_port_axi_rsp_t = logic, - /// AXI4+ATOP request struct type for the master ports. - parameter type mst_port_axi_req_t = logic, - /// AXI4+ATOP response struct type for the master ports - parameter type mst_port_axi_rsp_t = logic, + /// AXI4+ATOP B channel struct type for the subordinate ports. + parameter type sbr_b_chan_t = logic, + /// AXI4+ATOP B channel struct type for the manager ports. + parameter type mgr_b_chan_t = logic, + /// AXI4+ATOP AR channel struct type for the subordinate ports. + parameter type sbr_ar_chan_t = logic, + /// AXI4+ATOP AR channel struct type for the manager ports. + parameter type mgr_ar_chan_t = logic, + /// AXI4+ATOP R channel struct type for the subordinate ports. + parameter type sbr_r_chan_t = logic, + /// AXI4+ATOP R channel struct type for the manager ports. + parameter type mgr_r_chan_t = logic, + /// AXI4+ATOP request struct type for the subordinate ports. + parameter type sbr_port_axi_req_t = logic, + /// AXI4+ATOP response struct type for the subordinate ports. + parameter type sbr_port_axi_rsp_t = logic, + /// AXI4+ATOP request struct type for the manager ports. + parameter type mgr_port_axi_req_t = logic, + /// AXI4+ATOP response struct type for the manager ports + parameter type mgr_port_axi_rsp_t = logic, /// Address rule type for the address decoders from `common_cells:addr_decode`. /// Example types are provided in `axi_pkg`. /// Required struct fields: @@ -62,8 +62,8 @@ import cf_math_pkg::idx_width; /// ``` parameter type rule_t = axi_pkg::xbar_rule_64_t `ifdef VCS - , localparam int unsigned MstPortsIdxWidth = - (Cfg.NumMstPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NumMstPorts)) + , localparam int unsigned MgrPortsIdxWidth = + (Cfg.NumMgrPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NumMgrPorts)) `endif ) ( /// Clock, positive edge triggered. @@ -72,141 +72,141 @@ import cf_math_pkg::idx_width; input logic rst_ni, /// Testmode enable, active high. input logic test_i, - /// AXI4+ATOP requests to the slave ports. - input slv_port_axi_req_t [Cfg.NumSlvPorts-1:0] slv_ports_req_i, - /// AXI4+ATOP responses of the slave ports. - output slv_port_axi_rsp_t [Cfg.NumSlvPorts-1:0] slv_ports_rsp_o, - /// AXI4+ATOP requests of the master ports. - output mst_port_axi_req_t [Cfg.NumMstPorts-1:0] mst_ports_req_o, - /// AXI4+ATOP responses to the master ports. - input mst_port_axi_rsp_t [Cfg.NumMstPorts-1:0] mst_ports_rsp_i, + /// AXI4+ATOP requests to the subordinate ports. + input sbr_port_axi_req_t [Cfg.NumSbrPorts-1:0] sbr_ports_req_i, + /// AXI4+ATOP responses of the subordinate ports. + output sbr_port_axi_rsp_t [Cfg.NumSbrPorts-1:0] sbr_ports_rsp_o, + /// AXI4+ATOP requests of the manager ports. + output mgr_port_axi_req_t [Cfg.NumMgrPorts-1:0] mgr_ports_req_o, + /// AXI4+ATOP responses to the manager ports. + input mgr_port_axi_rsp_t [Cfg.NumMgrPorts-1:0] mgr_ports_rsp_i, /// Address map array input for the crossbar. This map is global for the whole module. - /// It is used for routing the transactions to the respective master ports. - /// Each master port can have multiple different rules. + /// It is used for routing the transactions to the respective manager ports. + /// Each manager port can have multiple different rules. input rule_t [Cfg.NumAddrRules-1:0] addr_map_i, - /// Enable default master port. - input logic [Cfg.NumSlvPorts-1:0] en_default_mst_port_i, + /// Enable default manager port. + input logic [Cfg.NumSbrPorts-1:0] en_default_mgr_port_i, `ifdef VCS - /// Enables a default master port for each slave port. When this is enabled unmapped - /// transactions get issued at the master port given by `default_mst_port_i`. + /// Enables a default manager port for each subordinate port. When this is enabled unmapped + /// transactions get issued at the manager port given by `default_mgr_port_i`. /// When not used, tie to `'0`. - input logic [Cfg.NumSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i + input logic [Cfg.NumSbrPorts-1:0][MgrPortsIdxWidth-1:0] default_mgr_port_i `else - /// Enables a default master port for each slave port. When this is enabled unmapped - /// transactions get issued at the master port given by `default_mst_port_i`. + /// Enables a default manager port for each subordinate port. When this is enabled unmapped + /// transactions get issued at the manager port given by `default_mgr_port_i`. /// When not used, tie to `'0`. - input logic [Cfg.NumSlvPorts-1:0][idx_width(Cfg.NumMstPorts)-1:0] default_mst_port_i + input logic [Cfg.NumSbrPorts-1:0][idx_width(Cfg.NumMgrPorts)-1:0] default_mgr_port_i `endif ); // Address tpye for inidvidual address signals typedef logic [Cfg.AddrWidth-1:0] addr_t; - // to account for the decoding error slave + // to account for the decoding error subordinate `ifdef VCS - localparam int unsigned MstPortsIdxWidthOne = - (Cfg.NumMstPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NumMstPorts + 1)); - typedef logic [MstPortsIdxWidthOne-1:0] mst_port_idx_t; + localparam int unsigned MgrPortsIdxWidthOne = + (Cfg.NumMgrPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NumMgrPorts + 1)); + typedef logic [MgrPortsIdxWidthOne-1:0] mgr_port_idx_t; `else - typedef logic [idx_width(Cfg.NumMstPorts + 1)-1:0] mst_port_idx_t; + typedef logic [idx_width(Cfg.NumMgrPorts + 1)-1:0] mgr_port_idx_t; `endif // signals from the axi_demuxes, one index more for decode error - slv_port_axi_req_t [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts:0] slv_reqs; - slv_port_axi_rsp_t [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts:0] slv_rsps; + sbr_port_axi_req_t [Cfg.NumSbrPorts-1:0][Cfg.NumMgrPorts:0] sbr_reqs; + sbr_port_axi_rsp_t [Cfg.NumSbrPorts-1:0][Cfg.NumMgrPorts:0] sbr_rsps; // workaround for issue #133 (problem with vsim 10.6c) - localparam int unsigned cfg_NumMstPorts = Cfg.NumMstPorts; + localparam int unsigned cfg_NumMgrPorts = Cfg.NumMgrPorts; - // signals into the axi_muxes, are of type slave as the multiplexer extends the ID - slv_port_axi_req_t [Cfg.NumMstPorts-1:0][Cfg.NumSlvPorts-1:0] mst_reqs; - slv_port_axi_rsp_t [Cfg.NumMstPorts-1:0][Cfg.NumSlvPorts-1:0] mst_rsps; + // signals into the axi_muxes, are of type subordinate as the multiplexer extends the ID + sbr_port_axi_req_t [Cfg.NumMgrPorts-1:0][Cfg.NumSbrPorts-1:0] mgr_reqs; + sbr_port_axi_rsp_t [Cfg.NumMgrPorts-1:0][Cfg.NumSbrPorts-1:0] mgr_rsps; - for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_slv_port_demux + for (genvar i = 0; i < Cfg.NumSbrPorts; i++) begin : gen_sbr_port_demux `ifdef VCS - logic [MstPortsIdxWidth-1:0] dec_aw, dec_ar; + logic [MgrPortsIdxWidth-1:0] dec_aw, dec_ar; `else - logic [idx_width(Cfg.NumMstPorts)-1:0] dec_aw, dec_ar; + logic [idx_width(Cfg.NumMgrPorts)-1:0] dec_aw, dec_ar; `endif - mst_port_idx_t slv_aw_select, slv_ar_select; + mgr_port_idx_t sbr_aw_select, sbr_ar_select; logic dec_aw_valid, dec_aw_error; logic dec_ar_valid, dec_ar_error; addr_decode #( - .NoIndices ( Cfg.NumMstPorts ), + .NoIndices ( Cfg.NumMgrPorts ), .NoRules ( Cfg.NumAddrRules ), .addr_t ( addr_t ), .rule_t ( rule_t ) ) i_axi_aw_decode ( - .addr_i ( slv_ports_req_i[i].aw.addr ), + .addr_i ( sbr_ports_req_i[i].aw.addr ), .addr_map_i ( addr_map_i ), .idx_o ( dec_aw ), .dec_valid_o ( dec_aw_valid ), .dec_error_o ( dec_aw_error ), - .en_default_idx_i ( en_default_mst_port_i[i] ), - .default_idx_i ( default_mst_port_i[i] ) + .en_default_idx_i ( en_default_mgr_port_i[i] ), + .default_idx_i ( default_mgr_port_i[i] ) ); addr_decode #( - .NoIndices ( Cfg.NumMstPorts ), + .NoIndices ( Cfg.NumMgrPorts ), .addr_t ( addr_t ), .NoRules ( Cfg.NumAddrRules ), .rule_t ( rule_t ) ) i_axi_ar_decode ( - .addr_i ( slv_ports_req_i[i].ar.addr ), + .addr_i ( sbr_ports_req_i[i].ar.addr ), .addr_map_i ( addr_map_i ), .idx_o ( dec_ar ), .dec_valid_o ( dec_ar_valid ), .dec_error_o ( dec_ar_error ), - .en_default_idx_i ( en_default_mst_port_i[i] ), - .default_idx_i ( default_mst_port_i[i] ) + .en_default_idx_i ( en_default_mgr_port_i[i] ), + .default_idx_i ( default_mgr_port_i[i] ) ); - assign slv_aw_select = (dec_aw_error) ? - mst_port_idx_t'(Cfg.NumMstPorts) : mst_port_idx_t'(dec_aw); - assign slv_ar_select = (dec_ar_error) ? - mst_port_idx_t'(Cfg.NumMstPorts) : mst_port_idx_t'(dec_ar); + assign sbr_aw_select = (dec_aw_error) ? + mgr_port_idx_t'(Cfg.NumMgrPorts) : mgr_port_idx_t'(dec_aw); + assign sbr_ar_select = (dec_ar_error) ? + mgr_port_idx_t'(Cfg.NumMgrPorts) : mgr_port_idx_t'(dec_ar); - // make sure that the default slave does not get changed, if there is an unserved Ax + // make sure that the default subordinate does not get changed, if there is an unserved Ax // pragma translate_off `ifndef VERILATOR `ifndef XSIM default disable iff (~rst_ni); - default_aw_mst_port_en: assert property( - @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_rsp_o[i].aw_ready) - |=> $stable(en_default_mst_port_i[i])) - else $fatal (1, $sformatf("It is not allowed to change the default mst port\ - enable, when there is an unserved Aw beat. Slave Port: %0d", i)); - default_aw_mst_port: assert property( - @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_rsp_o[i].aw_ready) - |=> $stable(default_mst_port_i[i])) - else $fatal (1, $sformatf("It is not allowed to change the default mst port\ - when there is an unserved Aw beat. Slave Port: %0d", i)); - default_ar_mst_port_en: assert property( - @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_rsp_o[i].ar_ready) - |=> $stable(en_default_mst_port_i[i])) + default_aw_mgr_port_en: assert property( + @(posedge clk_i) (sbr_ports_req_i[i].aw_valid && !sbr_ports_rsp_o[i].aw_ready) + |=> $stable(en_default_mgr_port_i[i])) + else $fatal (1, $sformatf("It is not allowed to change the default mgr port\ + enable, when there is an unserved Aw beat. Subordinate Port: %0d", i)); + default_aw_mgr_port: assert property( + @(posedge clk_i) (sbr_ports_req_i[i].aw_valid && !sbr_ports_rsp_o[i].aw_ready) + |=> $stable(default_mgr_port_i[i])) + else $fatal (1, $sformatf("It is not allowed to change the default mgr port\ + when there is an unserved Aw beat. Subordinate Port: %0d", i)); + default_ar_mgr_port_en: assert property( + @(posedge clk_i) (sbr_ports_req_i[i].ar_valid && !sbr_ports_rsp_o[i].ar_ready) + |=> $stable(en_default_mgr_port_i[i])) else $fatal (1, $sformatf("It is not allowed to change the enable, when\ - there is an unserved Ar beat. Slave Port: %0d", i)); - default_ar_mst_port: assert property( - @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_rsp_o[i].ar_ready) - |=> $stable(default_mst_port_i[i])) - else $fatal (1, $sformatf("It is not allowed to change the default mst port\ - when there is an unserved Ar beat. Slave Port: %0d", i)); + there is an unserved Ar beat. Subordinate Port: %0d", i)); + default_ar_mgr_port: assert property( + @(posedge clk_i) (sbr_ports_req_i[i].ar_valid && !sbr_ports_rsp_o[i].ar_ready) + |=> $stable(default_mgr_port_i[i])) + else $fatal (1, $sformatf("It is not allowed to change the default mgr port\ + when there is an unserved Ar beat. Subordinate Port: %0d", i)); `endif `endif // pragma translate_on axi_demux #( - .IdWidth ( Cfg.IdWidthSlvPorts ), // ID Width + .IdWidth ( Cfg.IdWidthSbrPorts ), // ID Width .AtopSupport ( ATOPs ), - .aw_chan_t ( slv_aw_chan_t ), // AW Channel Type + .aw_chan_t ( sbr_aw_chan_t ), // AW Channel Type .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( slv_b_chan_t ), // B Channel Type - .ar_chan_t ( slv_ar_chan_t ), // AR Channel Type - .r_chan_t ( slv_r_chan_t ), // R Channel Type - .axi_req_t ( slv_port_axi_req_t ), - .axi_rsp_t ( slv_port_axi_rsp_t ), - .NumMstPorts ( Cfg.NumMstPorts + 1 ), - .MaxTrans ( Cfg.MaxMstTrans ), - .LookBits ( Cfg.IdUsedSlvPorts ), + .b_chan_t ( sbr_b_chan_t ), // B Channel Type + .ar_chan_t ( sbr_ar_chan_t ), // AR Channel Type + .r_chan_t ( sbr_r_chan_t ), // R Channel Type + .axi_req_t ( sbr_port_axi_req_t ), + .axi_rsp_t ( sbr_port_axi_rsp_t ), + .NumMgrPorts ( Cfg.NumMgrPorts + 1 ), + .MaxTrans ( Cfg.MaxMgrTrans ), + .LookBits ( Cfg.IdUsedSbrPorts ), .UniqueIds ( Cfg.UniqueIds ), .FallThrough ( Cfg.FallThrough ), .SpillAw ( Cfg.LatencyMode[9] ), @@ -218,93 +218,93 @@ import cf_math_pkg::idx_width; .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Testmode enable - .slv_req_i ( slv_ports_req_i[i] ), - .slv_aw_select_i ( slv_aw_select ), - .slv_ar_select_i ( slv_ar_select ), - .slv_rsp_o ( slv_ports_rsp_o[i] ), - .mst_reqs_o ( slv_reqs[i] ), - .mst_rsps_i ( slv_rsps[i] ) + .sbr_req_i ( sbr_ports_req_i[i] ), + .sbr_aw_select_i ( sbr_aw_select ), + .sbr_ar_select_i ( sbr_ar_select ), + .sbr_rsp_o ( sbr_ports_rsp_o[i] ), + .mgr_reqs_o ( sbr_reqs[i] ), + .mgr_rsps_i ( sbr_rsps[i] ) ); - axi_err_slv #( - .IdWidth ( Cfg.IdWidthSlvPorts ), - .axi_req_t ( slv_port_axi_req_t ), - .axi_rsp_t ( slv_port_axi_rsp_t ), + axi_err_sbr #( + .IdWidth ( Cfg.IdWidthSbrPorts ), + .axi_req_t ( sbr_port_axi_req_t ), + .axi_rsp_t ( sbr_port_axi_rsp_t ), .Resp ( axi_pkg::RESP_DECERR ), .ATOPs ( ATOPs ), - .MaxTrans ( 4 ) // Transactions terminate at this slave, so minimize + .MaxTrans ( 4 ) // Transactions terminate at this subordinate, so minimize // resource consumption by accepting only a few // transactions at a time. - ) i_axi_err_slv ( + ) i_axi_err_sbr ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Testmode enable - // slave port - .slv_req_i ( slv_reqs[i][Cfg.NumMstPorts] ), - .slv_rsp_o ( slv_rsps[i][cfg_NumMstPorts] ) + // subordinate port + .sbr_req_i ( sbr_reqs[i][Cfg.NumMgrPorts] ), + .sbr_rsp_o ( sbr_rsps[i][cfg_NumMgrPorts] ) ); end // cross all channels - for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_xbar_slv_cross - for (genvar j = 0; j < Cfg.NumMstPorts; j++) begin : gen_xbar_mst_cross + for (genvar i = 0; i < Cfg.NumSbrPorts; i++) begin : gen_xbar_sbr_cross + for (genvar j = 0; j < Cfg.NumMgrPorts; j++) begin : gen_xbar_mgr_cross if (Connectivity[i][j]) begin : gen_connection axi_multicut #( - .NumCuts ( Cfg.PipelineStages ), - .aw_chan_t ( slv_aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( slv_b_chan_t ), - .ar_chan_t ( slv_ar_chan_t ), - .r_chan_t ( slv_r_chan_t ), - .axi_req_t ( slv_port_axi_req_t ), - .axi_rsp_t ( slv_port_axi_rsp_t ) + .NumCuts ( Cfg.PipelineStages ), + .aw_chan_t ( sbr_aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( sbr_b_chan_t ), + .ar_chan_t ( sbr_ar_chan_t ), + .r_chan_t ( sbr_r_chan_t ), + .axi_req_t ( sbr_port_axi_req_t ), + .axi_rsp_t ( sbr_port_axi_rsp_t ) ) i_axi_multicut_xbar_pipeline ( .clk_i, .rst_ni, - .slv_req_i ( slv_reqs[i][j] ), - .slv_rsp_o ( slv_rsps[i][j] ), - .mst_req_o ( mst_reqs[j][i] ), - .mst_rsp_i ( mst_rsps[j][i] ) + .sbr_req_i ( sbr_reqs[i][j] ), + .sbr_rsp_o ( sbr_rsps[i][j] ), + .mgr_req_o ( mgr_reqs[j][i] ), + .mgr_rsp_i ( mgr_rsps[j][i] ) ); end else begin : gen_no_connection - assign mst_reqs[j][i] = '0; - axi_err_slv #( - .IdWidth ( Cfg.IdWidthSlvPorts ), - .axi_req_t ( slv_port_axi_req_t ), - .axi_rsp_t ( slv_port_axi_rsp_t ), - .Resp ( axi_pkg::RESP_DECERR ), - .ATOPs ( ATOPs ), - .MaxTrans ( 1 ) - ) i_axi_err_slv ( + assign mgr_reqs[j][i] = '0; + axi_err_sbr #( + .IdWidth ( Cfg.IdWidthSbrPorts ), + .axi_req_t ( sbr_port_axi_req_t ), + .axi_rsp_t ( sbr_port_axi_rsp_t ), + .Resp ( axi_pkg::RESP_DECERR ), + .ATOPs ( ATOPs ), + .MaxTrans ( 1 ) + ) i_axi_err_sbr ( .clk_i, .rst_ni, .test_i, - .slv_req_i ( slv_reqs[i][j] ), - .slv_rsp_o ( slv_rsps[i][j] ) + .sbr_req_i ( sbr_reqs[i][j] ), + .sbr_rsp_o ( sbr_rsps[i][j] ) ); end end end - for (genvar i = 0; i < Cfg.NumMstPorts; i++) begin : gen_mst_port_mux + for (genvar i = 0; i < Cfg.NumMgrPorts; i++) begin : gen_mgr_port_mux axi_mux #( - .SlvIDWidth ( Cfg.IdWidthSlvPorts ), // ID width of the slave ports - .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports - .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port + .SbrIDWidth ( Cfg.IdWidthSbrPorts ), // ID width of the subordinate ports + .sbr_aw_chan_t ( sbr_aw_chan_t ), // AW Channel Type, subordinate ports + .mgr_aw_chan_t ( mgr_aw_chan_t ), // AW Channel Type, manager port .w_chan_t ( w_chan_t ), // W Channel Type, all ports - .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports - .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port - .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports - .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port - .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports - .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port - .slv_port_axi_req_t ( slv_port_axi_req_t ), - .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), - .mst_port_axi_req_t ( mst_port_axi_req_t ), - .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), - .NumSlvPorts ( Cfg.NumSlvPorts ), // Number of Masters for the module - .MaxWTrans ( Cfg.MaxSlvTrans ), + .sbr_b_chan_t ( sbr_b_chan_t ), // B Channel Type, subordinate ports + .mgr_b_chan_t ( mgr_b_chan_t ), // B Channel Type, manager port + .sbr_ar_chan_t ( sbr_ar_chan_t ), // AR Channel Type, subordinate ports + .mgr_ar_chan_t ( mgr_ar_chan_t ), // AR Channel Type, manager port + .sbr_r_chan_t ( sbr_r_chan_t ), // R Channel Type, subordinate ports + .mgr_r_chan_t ( mgr_r_chan_t ), // R Channel Type, manager port + .sbr_port_axi_req_t ( sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t ( sbr_port_axi_rsp_t ), + .mgr_port_axi_req_t ( mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t ( mgr_port_axi_rsp_t ), + .NumSbrPorts ( Cfg.NumSbrPorts ), // Number of Managers for the module + .MaxWTrans ( Cfg.MaxSbrTrans ), .FallThrough ( Cfg.FallThrough ), .SpillAw ( Cfg.LatencyMode[4] ), .SpillW ( Cfg.LatencyMode[3] ), @@ -315,10 +315,10 @@ import cf_math_pkg::idx_width; .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Test Mode enable - .slv_reqs_i ( mst_reqs[i] ), - .slv_rsps_o ( mst_rsps[i] ), - .mst_req_o ( mst_ports_req_o[i] ), - .mst_rsp_i ( mst_ports_rsp_i[i] ) + .sbr_reqs_i ( mgr_reqs[i] ), + .sbr_rsps_o ( mgr_rsps[i] ), + .mgr_req_o ( mgr_ports_req_o[i] ), + .mgr_rsp_i ( mgr_ports_rsp_i[i] ) ); end @@ -326,10 +326,10 @@ import cf_math_pkg::idx_width; `ifndef VERILATOR `ifndef XSIM initial begin : check_params - id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.IdWidthSlvPorts) else - $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); - id_slv_rsp_ports: assert ($bits(slv_ports_rsp_o[0].r.id) == Cfg.IdWidthSlvPorts) else - $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); + id_sbr_req_ports: assert ($bits(sbr_ports_req_i[0].aw.id ) == Cfg.IdWidthSbrPorts) else + $fatal(1, $sformatf("Sbr_req and aw_chan id width not equal.")); + id_sbr_rsp_ports: assert ($bits(sbr_ports_rsp_o[0].r.id) == Cfg.IdWidthSbrPorts) else + $fatal(1, $sformatf("Sbr_req and aw_chan id width not equal.")); end `endif `endif @@ -345,94 +345,94 @@ import cf_math_pkg::idx_width; parameter int unsigned AXI_USER_WIDTH = 0, parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter bit ATOPS = 1'b1, - parameter bit [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts-1:0] CONNECTIVITY = '1, + parameter bit [Cfg.NumSbrPorts-1:0][Cfg.NumMgrPorts-1:0] CONNECTIVITY = '1, parameter type rule_t = axi_pkg::xbar_rule_64_t `ifdef VCS - , localparam int unsigned MstPortsIdxWidth = - (Cfg.NumMstPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NumMstPorts)) + , localparam int unsigned MgrPortsIdxWidth = + (Cfg.NumMgrPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NumMgrPorts)) `endif ) ( input logic clk_i, input logic rst_ni, input logic test_i, - AXI_BUS.Slave slv_ports [Cfg.NumSlvPorts-1:0], - AXI_BUS.Master mst_ports [Cfg.NumMstPorts-1:0], + AXI_BUS.Subordinate sbr_ports [Cfg.NumSbrPorts-1:0], + AXI_BUS.Manager mgr_ports [Cfg.NumMgrPorts-1:0], input rule_t [Cfg.NumAddrRules-1:0] addr_map_i, - input logic [Cfg.NumSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NumSbrPorts-1:0] en_default_mgr_port_i, `ifdef VCS - input logic [Cfg.NumSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i + input logic [Cfg.NumSbrPorts-1:0][MgrPortsIdxWidth-1:0] default_mgr_port_i `else - input logic [Cfg.NumSlvPorts-1:0][idx_width(Cfg.NumMstPorts)-1:0] default_mst_port_i + input logic [Cfg.NumSbrPorts-1:0][idx_width(Cfg.NumMgrPorts)-1:0] default_mgr_port_i `endif ); - localparam int unsigned IdWidthMstPorts = Cfg.IdWidthSlvPorts + $clog2(Cfg.NumSlvPorts); + localparam int unsigned IdWidthMgrPorts = Cfg.IdWidthSbrPorts + $clog2(Cfg.NumSbrPorts); - typedef logic [IdWidthMstPorts -1:0] id_mst_t; - typedef logic [Cfg.IdWidthSlvPorts -1:0] id_slv_t; + typedef logic [IdWidthMgrPorts -1:0] id_mgr_t; + typedef logic [Cfg.IdWidthSbrPorts -1:0] id_sbr_t; typedef logic [Cfg.AddrWidth -1:0] addr_t; typedef logic [Cfg.DataWidth -1:0] data_t; typedef logic [Cfg.DataWidth/8 -1:0] strb_t; typedef logic [AXI_USER_WIDTH -1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, id_mst_t, user_t) - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mgr_aw_chan_t, addr_t, id_mgr_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(sbr_aw_chan_t, addr_t, id_sbr_t, user_t) `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, id_mst_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, id_slv_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, id_mst_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, id_slv_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, id_mst_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, id_slv_t, user_t) - `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) - `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_chan_t, mst_r_chan_t) - `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_B_CHAN_T(mgr_b_chan_t, id_mgr_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(sbr_b_chan_t, id_sbr_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mgr_ar_chan_t, addr_t, id_mgr_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(sbr_ar_chan_t, addr_t, id_sbr_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mgr_r_chan_t, data_t, id_mgr_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(sbr_r_chan_t, data_t, id_sbr_t, user_t) + `AXI_TYPEDEF_REQ_T(mgr_port_axi_req_t, mgr_aw_chan_t, w_chan_t, mgr_ar_chan_t) + `AXI_TYPEDEF_REQ_T(sbr_port_axi_req_t, sbr_aw_chan_t, w_chan_t, sbr_ar_chan_t) + `AXI_TYPEDEF_RSP_T(mgr_port_axi_rsp_t, mgr_b_chan_t, mgr_r_chan_t) + `AXI_TYPEDEF_RSP_T(sbr_port_axi_rsp_t, sbr_b_chan_t, sbr_r_chan_t) - mst_port_axi_req_t [Cfg.NumMstPorts-1:0] mst_reqs; - mst_port_axi_rsp_t [Cfg.NumMstPorts-1:0] mst_rsps; - slv_port_axi_req_t [Cfg.NumSlvPorts-1:0] slv_reqs; - slv_port_axi_rsp_t [Cfg.NumSlvPorts-1:0] slv_rsps; + mgr_port_axi_req_t [Cfg.NumMgrPorts-1:0] mgr_reqs; + mgr_port_axi_rsp_t [Cfg.NumMgrPorts-1:0] mgr_rsps; + sbr_port_axi_req_t [Cfg.NumSbrPorts-1:0] sbr_reqs; + sbr_port_axi_rsp_t [Cfg.NumSbrPorts-1:0] sbr_rsps; - for (genvar i = 0; i < Cfg.NumMstPorts; i++) begin : gen_assign_mst - `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) - `AXI_ASSIGN_TO_RSP(mst_rsps[i], mst_ports[i]) + for (genvar i = 0; i < Cfg.NumMgrPorts; i++) begin : gen_assign_mgr + `AXI_ASSIGN_FROM_REQ(mgr_ports[i], mgr_reqs[i]) + `AXI_ASSIGN_TO_RSP(mgr_rsps[i], mgr_ports[i]) end - for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_assign_slv - `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) - `AXI_ASSIGN_FROM_RSP(slv_ports[i], slv_rsps[i]) + for (genvar i = 0; i < Cfg.NumSbrPorts; i++) begin : gen_assign_sbr + `AXI_ASSIGN_TO_REQ(sbr_reqs[i], sbr_ports[i]) + `AXI_ASSIGN_FROM_RSP(sbr_ports[i], sbr_rsps[i]) end axi_xbar #( .Cfg (Cfg), .ATOPs ( ATOPS ), .Connectivity ( CONNECTIVITY ), - .slv_aw_chan_t ( slv_aw_chan_t ), - .mst_aw_chan_t ( mst_aw_chan_t ), + .sbr_aw_chan_t ( sbr_aw_chan_t ), + .mgr_aw_chan_t ( mgr_aw_chan_t ), .w_chan_t ( w_chan_t ), - .slv_b_chan_t ( slv_b_chan_t ), - .mst_b_chan_t ( mst_b_chan_t ), - .slv_ar_chan_t ( slv_ar_chan_t ), - .mst_ar_chan_t ( mst_ar_chan_t ), - .slv_r_chan_t ( slv_r_chan_t ), - .mst_r_chan_t ( mst_r_chan_t ), - .slv_port_axi_req_t ( slv_port_axi_req_t ), - .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), - .mst_port_axi_req_t ( mst_port_axi_req_t ), - .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), + .sbr_b_chan_t ( sbr_b_chan_t ), + .mgr_b_chan_t ( mgr_b_chan_t ), + .sbr_ar_chan_t ( sbr_ar_chan_t ), + .mgr_ar_chan_t ( mgr_ar_chan_t ), + .sbr_r_chan_t ( sbr_r_chan_t ), + .mgr_r_chan_t ( mgr_r_chan_t ), + .sbr_port_axi_req_t ( sbr_port_axi_req_t ), + .sbr_port_axi_rsp_t ( sbr_port_axi_rsp_t ), + .mgr_port_axi_req_t ( mgr_port_axi_req_t ), + .mgr_port_axi_rsp_t ( mgr_port_axi_rsp_t ), .rule_t ( rule_t ) ) i_xbar ( .clk_i, .rst_ni, .test_i, - .slv_ports_req_i (slv_reqs), - .slv_ports_rsp_o (slv_rsps), - .mst_ports_req_o (mst_reqs), - .mst_ports_rsp_i (mst_rsps), + .sbr_ports_req_i (sbr_reqs), + .sbr_ports_rsp_o (sbr_rsps), + .mgr_ports_req_o (mgr_reqs), + .mgr_ports_rsp_i (mgr_rsps), .addr_map_i, - .en_default_mst_port_i, - .default_mst_port_i + .en_default_mgr_port_i, + .default_mgr_port_i ); endmodule diff --git a/src/axi_xp.sv b/src/axi_xp.sv index 83d8f6720..c3fa5238a 100644 --- a/src/axi_xp.sv +++ b/src/axi_xp.sv @@ -16,20 +16,20 @@ `include "axi/typedef.svh" -/// AXI Crosspoint (XP) with homomorphous slave and master ports. +/// AXI Crosspoint (XP) with homomorphous subordinate and manager ports. module axi_xp #( // Atomic operations settings parameter bit ATOPs = 1'b1, // xbar configuration parameter axi_pkg::xbar_cfg_t Cfg = '0, - /// Number of slave ports. - parameter int unsigned NumSlvPorts = 32'd0, - /// Number of master ports. - parameter int unsigned NumMstPorts = 32'd0, - /// Connectivity from a slave port to the master ports. A `1'b1` in `Connectivity[i][j]` means - /// that slave port `i` is connected to master port `j`. By default, all slave ports are - /// connected to all master ports. - parameter bit [NumSlvPorts-1:0][NumMstPorts-1:0] Connectivity = '1, + /// Number of subordinate ports. + parameter int unsigned NumSbrPorts = 32'd0, + /// Number of manager ports. + parameter int unsigned NumMgrPorts = 32'd0, + /// Connectivity from a subordinate port to the manager ports. A `1'b1` in `Connectivity[i][j]` means + /// that subordinate port `i` is connected to manager port `j`. By default, all subordinate ports are + /// connected to all manager ports. + parameter bit [NumSbrPorts-1:0][NumMgrPorts-1:0] Connectivity = '1, /// Address width of all ports. parameter int unsigned AddrWidth = 32'd0, /// Data width of all ports. @@ -38,39 +38,39 @@ module axi_xp #( parameter int unsigned IdWidth = 32'd0, /// User signal width of all ports. parameter int unsigned UserWidth = 32'd0, - /// Maximum number of different IDs that can be in flight at each slave port. Reads and writes + /// Maximum number of different IDs that can be in flight at each subordinate port. Reads and writes /// are counted separately (except for ATOPs, which count as both read and write). /// /// It is legal for upstream to have transactions with more unique IDs than the maximum given by /// this parameter in flight, but a transaction exceeding the maximum will be stalled until all /// transactions of another ID complete. - parameter int unsigned SlvPortMaxUniqIds = 32'd0, - /// Maximum number of in-flight transactions with the same ID at the slave port. + parameter int unsigned SbrPortMaxUniqIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID at the subordinate port. /// - /// This parameter is only relevant if `SlvPortMaxUniqIds <= 2**MstPortIdWidth`. In that + /// This parameter is only relevant if `SbrPortMaxUniqIds <= 2**MgrPortIdWidth`. In that /// case, this parameter is passed to [`axi_id_remap` as `MaxTxnsPerId` /// parameter](module.axi_id_remap#parameter.MaxTxnsPerId). - parameter int unsigned SlvPortMaxTxnsPerId = 32'd0, - /// Maximum number of in-flight transactions at the slave port. Reads and writes are counted + parameter int unsigned SbrPortMaxTxnsPerId = 32'd0, + /// Maximum number of in-flight transactions at the subordinate port. Reads and writes are counted /// separately (except for ATOPs, which count as both read and write). /// - /// This parameter is only relevant if `SlvPortMaxUniqIds > 2**MstPortIdWidth`. In that + /// This parameter is only relevant if `SbrPortMaxUniqIds > 2**MgrPortIdWidth`. In that /// case, this parameter is passed to - /// [`axi_id_serialize`](module.axi_id_serialize#parameter.SlvPortMaxTxns). - parameter int unsigned SlvPortMaxTxns = 32'd0, - /// Maximum number of different IDs that can be in flight at the master port. Reads and writes + /// [`axi_id_serialize`](module.axi_id_serialize#parameter.SbrPortMaxTxns). + parameter int unsigned SbrPortMaxTxns = 32'd0, + /// Maximum number of different IDs that can be in flight at the manager port. Reads and writes /// are counted separately (except for ATOPs, which count as both read and write). /// - /// This parameter is only relevant if `SlvPortMaxUniqIds > 2**MstPortIdWidth`. In that + /// This parameter is only relevant if `SbrPortMaxUniqIds > 2**MgrPortIdWidth`. In that /// case, this parameter is passed to - /// [`axi_id_serialize`](module.axi_id_serialize#parameter.MstPortMaxUniqIds). - parameter int unsigned MstPortMaxUniqIds = 32'd0, - /// Maximum number of in-flight transactions with the same ID at the master port. + /// [`axi_id_serialize`](module.axi_id_serialize#parameter.MgrPortMaxUniqIds). + parameter int unsigned MgrPortMaxUniqIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID at the manager port. /// - /// This parameter is only relevant if `SlvPortMaxUniqIds > 2**MstPortIdWidth`. In that + /// This parameter is only relevant if `SbrPortMaxUniqIds > 2**MgrPortIdWidth`. In that /// case, this parameter is passed to - /// [`axi_id_serialize`](module.axi_id_serialize#parameter.MstPortMaxTxnsPerId). - parameter int unsigned MstPortMaxTxnsPerId = 32'd0, + /// [`axi_id_serialize`](module.axi_id_serialize#parameter.MgrPortMaxTxnsPerId). + parameter int unsigned MgrPortMaxTxnsPerId = 32'd0, /// Number of rules in the address map. parameter int unsigned NumAddrRules = 32'd0, /// Request struct type of the AXI4+ATOP @@ -86,20 +86,20 @@ module axi_xp #( input logic rst_ni, /// Test mode enable input logic test_en_i, - /// Slave ports request - input axi_req_t [NumSlvPorts-1:0] slv_req_i, - /// Slave ports response - output axi_rsp_t [NumSlvPorts-1:0] slv_rsp_o, - /// Master ports request - output axi_req_t [NumMstPorts-1:0] mst_req_o, - /// Master ports response - input axi_rsp_t [NumMstPorts-1:0] mst_rsp_i, - /// Address map for transferring transactions from slave to master ports + /// Subordinate ports request + input axi_req_t [NumSbrPorts-1:0] sbr_req_i, + /// Subordinate ports response + output axi_rsp_t [NumSbrPorts-1:0] sbr_rsp_o, + /// Manager ports request + output axi_req_t [NumMgrPorts-1:0] mgr_req_o, + /// Manager ports response + input axi_rsp_t [NumMgrPorts-1:0] mgr_rsp_i, + /// Address map for transferring transactions from subordinate to manager ports input rule_t [NumAddrRules-1:0] addr_map_i ); - // The master port of the Xbar has a different ID width than the slave ports. - parameter int unsigned XbarIdWidth = IdWidth + $clog2(NumSlvPorts); + // The manager port of the Xbar has a different ID width than the subordinate ports. + parameter int unsigned XbarIdWidth = IdWidth + $clog2(NumSbrPorts); typedef logic [AddrWidth-1:0] addr_t; typedef logic [DataWidth-1:0] data_t; typedef logic [IdWidth-1:0] id_t; @@ -111,57 +111,57 @@ module axi_xp #( `AXI_TYPEDEF_ALL(xp, addr_t, id_t, data_t, strb_t, user_t) `AXI_TYPEDEF_ALL(xbar, addr_t, xbar_id_t, data_t, strb_t, user_t) - xbar_req_t [NumMstPorts-1:0] xbar_req; - xbar_rsp_t [NumMstPorts-1:0] xbar_rsp; + xbar_req_t [NumMgrPorts-1:0] xbar_req; + xbar_rsp_t [NumMgrPorts-1:0] xbar_rsp; axi_xbar #( .Cfg ( Cfg ), .ATOPs ( ATOPs ), .Connectivity ( Connectivity ), - .slv_aw_chan_t ( xp_aw_chan_t ), - .mst_aw_chan_t ( xbar_aw_chan_t ), + .sbr_aw_chan_t ( xp_aw_chan_t ), + .mgr_aw_chan_t ( xbar_aw_chan_t ), .w_chan_t ( xp_w_chan_t ), - .slv_b_chan_t ( xp_b_chan_t ), - .mst_b_chan_t ( xbar_b_chan_t ), - .slv_ar_chan_t ( xp_ar_chan_t ), - .mst_ar_chan_t ( xbar_ar_chan_t ), - .slv_r_chan_t ( xp_r_chan_t ), - .mst_r_chan_t ( xbar_r_chan_t ), - .slv_req_t ( axi_req_t ), - .slv_rsp_t ( axi_rsp_t ), - .mst_req_t ( xbar_req_t ), - .mst_rsp_t ( xbar_rsp_t ), + .sbr_b_chan_t ( xp_b_chan_t ), + .mgr_b_chan_t ( xbar_b_chan_t ), + .sbr_ar_chan_t ( xp_ar_chan_t ), + .mgr_ar_chan_t ( xbar_ar_chan_t ), + .sbr_r_chan_t ( xp_r_chan_t ), + .mgr_r_chan_t ( xbar_r_chan_t ), + .sbr_req_t ( axi_req_t ), + .sbr_rsp_t ( axi_rsp_t ), + .mgr_req_t ( xbar_req_t ), + .mgr_rsp_t ( xbar_rsp_t ), .rule_t ( rule_t ) ) i_xbar ( .clk_i, .rst_ni, .test_i ( test_en_i ), - .slv_ports_req_i ( slv_req_i ), - .slv_ports_rsp_o ( slv_rsp_o ), - .mst_ports_req_o ( xbar_req ), - .mst_ports_rsp_i ( xbar_rsp ), + .sbr_ports_req_i ( sbr_req_i ), + .sbr_ports_rsp_o ( sbr_rsp_o ), + .mgr_ports_req_o ( xbar_req ), + .mgr_ports_rsp_i ( xbar_rsp ), .addr_map_i, - .en_default_mst_port_i ( '0 ), - .default_mst_port_i ( '0 ) + .en_default_mgr_port_i ( '0 ), + .default_mgr_port_i ( '0 ) ); - for (genvar i = 0; i < NumMstPorts; i++) begin : gen_remap + for (genvar i = 0; i < NumMgrPorts; i++) begin : gen_remap axi_id_remap #( - .SlvPortIdWidth ( XbarIdWidth ), - .SlvPortMaxUniqIds ( SlvPortMaxUniqIds ), - .MaxTxnsPerId ( SlvPortMaxTxnsPerId ), - .MstPortIdWidth ( IdWidth ), - .slv_req_t ( xbar_req_t ), - .slv_rsp_t ( xbar_rsp_t ), - .mst_req_t ( axi_req_t ), - .mst_rsp_t ( axi_rsp_t ) + .SbrPortIdWidth ( XbarIdWidth ), + .SbrPortMaxUniqIds ( SbrPortMaxUniqIds ), + .MaxTxnsPerId ( SbrPortMaxTxnsPerId ), + .MgrPortIdWidth ( IdWidth ), + .sbr_req_t ( xbar_req_t ), + .sbr_rsp_t ( xbar_rsp_t ), + .mgr_req_t ( axi_req_t ), + .mgr_rsp_t ( axi_rsp_t ) ) i_axi_id_remap ( .clk_i, .rst_ni, - .slv_req_i ( xbar_req[i] ), - .slv_rsp_o ( xbar_rsp[i] ), - .mst_req_o ( mst_req_o[i] ), - .mst_rsp_i ( mst_rsp_i[i] ) + .sbr_req_i ( xbar_req[i] ), + .sbr_rsp_o ( xbar_rsp[i] ), + .mgr_req_o ( mgr_req_o[i] ), + .mgr_rsp_i ( mgr_rsp_i[i] ) ); end @@ -175,30 +175,30 @@ import cf_math_pkg::idx_width; #( parameter bit ATOPs = 1'b1, parameter axi_pkg::xbar_cfg_t Cfg = '0, - parameter int unsigned NumSlvPorts = 32'd0, - parameter int unsigned NumMstPorts = 32'd0, - parameter bit [NumSlvPorts-1:0][NumMstPorts-1:0] Connectivity = '1, + parameter int unsigned NumSbrPorts = 32'd0, + parameter int unsigned NumMgrPorts = 32'd0, + parameter bit [NumSbrPorts-1:0][NumMgrPorts-1:0] Connectivity = '1, parameter int unsigned AddrWidth = 32'd0, parameter int unsigned DataWidth = 32'd0, parameter int unsigned IdWidth = 32'd0, parameter int unsigned UserWidth = 32'd0, - parameter int unsigned SlvPortMaxUniqIds = 32'd0, - parameter int unsigned SlvPortMaxTxnsPerId = 32'd0, - parameter int unsigned SlvPortMaxTxns = 32'd0, - parameter int unsigned MstPortMaxUniqIds = 32'd0, - parameter int unsigned MstPortMaxTxnsPerId = 32'd0, + parameter int unsigned SbrPortMaxUniqIds = 32'd0, + parameter int unsigned SbrPortMaxTxnsPerId = 32'd0, + parameter int unsigned SbrPortMaxTxns = 32'd0, + parameter int unsigned MgrPortMaxUniqIds = 32'd0, + parameter int unsigned MgrPortMaxTxnsPerId = 32'd0, parameter int unsigned NumAddrRules = 32'd0, parameter type rule_t = axi_pkg::xbar_rule_64_t ) ( input logic clk_i, input logic rst_ni, input logic test_en_i, - AXI_BUS.Slave slv_ports [NumSlvPorts-1:0], - AXI_BUS.Master mst_ports [NumMstPorts-1:0], + AXI_BUS.Subordinate sbr_ports [NumSbrPorts-1:0], + AXI_BUS.Manager mgr_ports [NumMgrPorts-1:0], input rule_t [NumAddrRules-1:0] addr_map_i ); - // localparam int unsigned AxiIdWidthMstPorts = AxiIdWidth + $clog2(NumSlvPorts); + // localparam int unsigned IdWidthMgrPorts = IdWidth + $clog2(NumSbrPorts); typedef logic [IdWidth -1:0] id_t; typedef logic [AddrWidth -1:0] addr_t; @@ -208,36 +208,36 @@ import cf_math_pkg::idx_width; `AXI_TYPEDEF_ALL(axi, addr_t, id_t, data_t, strb_t, user_t) - axi_req_t [NumMstPorts-1:0] mst_reqs; - axi_rsp_t [NumMstPorts-1:0] mst_rsps; - axi_req_t [NumSlvPorts-1:0] slv_reqs; - axi_rsp_t [NumSlvPorts-1:0] slv_rsps; + axi_req_t [NumMgrPorts-1:0] mgr_reqs; + axi_rsp_t [NumMgrPorts-1:0] mgr_rsps; + axi_req_t [NumSbrPorts-1:0] sbr_reqs; + axi_rsp_t [NumSbrPorts-1:0] sbr_rsps; - for (genvar i = 0; i < NumMstPorts; i++) begin : gen_assign_mst - `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) - `AXI_ASSIGN_TO_RSP(mst_rsps[i], mst_ports[i]) + for (genvar i = 0; i < NumMgrPorts; i++) begin : gen_assign_mgr + `AXI_ASSIGN_FROM_REQ(mgr_ports[i], mgr_reqs[i]) + `AXI_ASSIGN_TO_RSP(mgr_rsps[i], mgr_ports[i]) end - for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_assign_slv - `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) - `AXI_ASSIGN_FROM_RSP(slv_ports[i], slv_rsps[i]) + for (genvar i = 0; i < NumSbrPorts; i++) begin : gen_assign_sbr + `AXI_ASSIGN_TO_REQ(sbr_reqs[i], sbr_ports[i]) + `AXI_ASSIGN_FROM_RSP(sbr_ports[i], sbr_rsps[i]) end axi_xp #( .ATOPs ( ATOPs ), .Cfg ( Cfg ), - .NumSlvPorts ( NumSlvPorts ), - .NumMstPorts ( NumMstPorts ), + .NumSbrPorts ( NumSbrPorts ), + .NumMgrPorts ( NumMgrPorts ), .Connectivity ( Connectivity ), .AddrWidth ( AddrWidth ), .DataWidth ( DataWidth ), .IdWidth ( IdWidth ), .UserWidth ( UserWidth ), - .SlvPortMaxUniqIds ( SlvPortMaxUniqIds ), - .SlvPortMaxTxnsPerId ( SlvPortMaxTxnsPerId ), - .SlvPortMaxTxns ( SlvPortMaxTxns ), - .MstPortMaxUniqIds ( MstPortMaxUniqIds ), - .MstPortMaxTxnsPerId ( MstPortMaxTxnsPerId ), + .SbrPortMaxUniqIds ( SbrPortMaxUniqIds ), + .SbrPortMaxTxnsPerId ( SbrPortMaxTxnsPerId ), + .SbrPortMaxTxns ( SbrPortMaxTxns ), + .MgrPortMaxUniqIds ( MgrPortMaxUniqIds ), + .MgrPortMaxTxnsPerId ( MgrPortMaxTxnsPerId ), .NumAddrRules ( NumAddrRules ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ), @@ -246,10 +246,10 @@ import cf_math_pkg::idx_width; .clk_i, .rst_ni, .test_en_i, - .slv_req_i (slv_reqs), - .slv_rsp_o (slv_rsps), - .mst_req_o (mst_reqs), - .mst_rsp_i (mst_rsps), + .sbr_req_i (sbr_reqs), + .sbr_rsp_o (sbr_rsps), + .mgr_req_o (mgr_reqs), + .mgr_rsp_i (mgr_rsps), .addr_map_i ); diff --git a/src_files.yml b/src_files.yml index 7c3743e41..e33e6da61 100644 --- a/src_files.yml +++ b/src_files.yml @@ -43,12 +43,12 @@ axi: - src/axi_rw_join.sv - src/axi_rw_split.sv - src/axi_serializer.sv - - src/axi_slave_compare.sv + - src/axi_subordinate_compare.sv - src/axi_throttle.sv - src/axi_to_mem.sv # Level 3 - src/axi_cdc.sv - - src/axi_err_slv.sv + - src/axi_err_sbr.sv - src/axi_from_mem.sv - src/axi_dw_converter.sv - src/axi_id_serialize.sv diff --git a/test/axi_synth_bench.sv b/test/axi_synth_bench.sv index bcb68e20c..e653623de 100644 --- a/test/axi_synth_bench.sv +++ b/test/axi_synth_bench.sv @@ -22,7 +22,7 @@ module axi_synth_bench ( localparam int AXI_ADDR_WIDTH[6] = '{32, 64, 1, 2, 42, 129}; localparam int AXI_ID_USER_WIDTH[3] = '{0, 1, 8}; - localparam int NUM_SLAVE_MASTER[3] = '{1, 2, 4}; + localparam int NUM_SUBORDINATE_MANAGER[3] = '{1, 2, 4}; // AXI_DATA_WIDTH = {8, 16, 32, 64, 128, 256, 512, 1024} for (genvar i = 0; i < 8; i++) begin @@ -61,7 +61,7 @@ module axi_synth_bench ( // AXI4-Lite crossbar for (genvar i = 0; i < 3; i++) begin synth_axi_lite_xbar #( - .NumSlvMst ( NUM_SLAVE_MASTER[i] ) + .NumSbrMgr ( NUM_SUBORDINATE_MANAGER[i] ) ) i_lite_xbar (.*); end @@ -84,7 +84,7 @@ module axi_synth_bench ( localparam int unsigned DataWidth = (2**i_data) * 8; for (genvar i_slv = 0; i_slv < 3; i_slv++) begin synth_axi_lite_to_apb #( - .NumApbSlaves ( NUM_SLAVE_MASTER[i_slv] ), + .NumApbSlaves ( NUM_SUBORDINATE_MANAGER[i_slv] ), .DataWidth ( DataWidth ) ) i_axi_lite_to_apb (.*); end @@ -116,14 +116,14 @@ module axi_synth_bench ( end for (genvar i = 0; i < 6; i++) begin - localparam int unsigned SLV_PORT_ADDR_WIDTH = AXI_ADDR_WIDTH[i]; - if (SLV_PORT_ADDR_WIDTH > 12) begin + localparam int unsigned SBR_PORT_ADDR_WIDTH = AXI_ADDR_WIDTH[i]; + if (SBR_PORT_ADDR_WIDTH > 12) begin for (genvar j = 0; j < 6; j++) begin - localparam int unsigned MST_PORT_ADDR_WIDTH = AXI_ADDR_WIDTH[j]; - if (MST_PORT_ADDR_WIDTH > 12) begin + localparam int unsigned MGR_PORT_ADDR_WIDTH = AXI_ADDR_WIDTH[j]; + if (MGR_PORT_ADDR_WIDTH > 12) begin synth_axi_modify_address #( - .AXI_SLV_PORT_ADDR_WIDTH (SLV_PORT_ADDR_WIDTH), - .AXI_MST_PORT_ADDR_WIDTH (MST_PORT_ADDR_WIDTH), + .AXI_SBR_PORT_ADDR_WIDTH (SBR_PORT_ADDR_WIDTH), + .AXI_MGR_PORT_ADDR_WIDTH (MGR_PORT_ADDR_WIDTH), .AXI_DATA_WIDTH (128), .AXI_ID_WIDTH (5), .AXI_USER_WIDTH (2) @@ -161,13 +161,13 @@ module axi_synth_bench ( localparam int unsigned IdWidthDs = AXI_ID_USER_WIDTH[i_iwds] + 1; localparam int unsigned TableSize = 2**IdWidthDs; synth_axi_iw_converter # ( - .SlvPortIdWidth ( IdWidthUs ), - .MstPortIdWidth ( IdWidthDs ), - .SlvPortMaxUniqIds ( 2**IdWidthUs ), - .SlvPortMaxTxnsPerId ( 13 ), - .SlvPortMaxTxns ( 81 ), - .MstPortMaxUniqIds ( 2**IdWidthDs ), - .MstPortMaxTxnsPerId ( 11 ), + .SbrPortIdWidth ( IdWidthUs ), + .MgrPortIdWidth ( IdWidthDs ), + .SbrPortMaxUniqIds ( 2**IdWidthUs ), + .SbrPortMaxTxnsPerId ( 13 ), + .SbrPortMaxTxns ( 81 ), + .MgrPortMaxUniqIds ( 2**IdWidthDs ), + .MgrPortMaxTxnsPerId ( 11 ), .AddrWidth ( 32'd64 ), .DataWidth ( 32'd512 ), .UserWidth ( 32'd10 ) @@ -175,7 +175,7 @@ module axi_synth_bench ( end end - // AXI4+ATOP on chip memory slave banked + // AXI4+ATOP on chip memory subordinate banked for (genvar i = 0; i < 5; i++) begin : gen_axi_to_mem_banked_data for (genvar j = 0; j < 4; j++) begin : gen_axi_to_mem_banked_bank_num for (genvar k = 0; k < 2; k++) begin : gen_axi_to_mem_banked_bank_addr @@ -231,16 +231,16 @@ module synth_slice #( .clk_i (clk_i), .rst_ni (rst_ni), .testmode_i (1'b0), - .slv (a_full.Slave), - .mst (a_lite.Master) + .sbr (a_full.Subordinate), + .mgr (a_lite.Manager) ); axi_lite_to_axi_intf #( .AXI_DATA_WIDTH (DW) ) b ( - .in (b_lite.Slave), - .slv_aw_cache_i ('0), - .slv_ar_cache_i ('0), - .out (b_full.Master) + .in (b_lite.Subordinate), + .sbr_aw_cache_i ('0), + .sbr_ar_cache_i ('0), + .out (b_full.Manager) ); endmodule @@ -277,8 +277,8 @@ module synth_axi_atop_filter #( ) dut ( .clk_i (clk_i), .rst_ni (rst_ni), - .slv (upstream), - .mst (downstream) + .sbr (upstream), + .mgr (downstream) ); endmodule @@ -393,7 +393,7 @@ endmodule `include "axi/typedef.svh" module synth_axi_lite_xbar #( - parameter int unsigned NumSlvMst = 32'd1 + parameter int unsigned NumSbrMgr = 32'd1 ) ( input logic clk_i, // Clock input logic rst_ni // Asynchronous reset active low @@ -410,22 +410,22 @@ module synth_axi_lite_xbar #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) localparam axi_pkg::xbar_cfg_t XbarCfg = '{ - NumSlvPorts: NumSlvMst, - NumMstPorts: NumSlvMst, - MaxMstTrans: 32'd5, - MaxSlvTrans: 32'd5, + NumSbrPorts: NumSbrMgr, + NumMgrPorts: NumSbrMgr, + MaxMgrTrans: 32'd5, + MaxSbrTrans: 32'd5, FallThrough: 1'b1, LatencyMode: axi_pkg::CUT_ALL_PORTS, AddrWidth: 32'd32, DataWidth: 32'd32, - NumAddrRules: NumSlvMst, + NumAddrRules: NumSbrMgr, default: '0 }; - axi_pkg::xbar_rule_32_t [NumSlvMst-1:0] addr_map; + axi_pkg::xbar_rule_32_t [NumSbrMgr-1:0] addr_map; logic test; - axi_lite_req_t [NumSlvMst-1:0] mst_reqs, slv_reqs; - axi_lite_rsp_t [NumSlvMst-1:0] mst_rsps, slv_rsps; + axi_lite_req_t [NumSbrMgr-1:0] mgr_reqs, sbr_reqs; + axi_lite_rsp_t [NumSbrMgr-1:0] mgr_rsps, sbr_rsps; axi_lite_xbar #( .Cfg ( XbarCfg ), @@ -438,16 +438,16 @@ module synth_axi_lite_xbar #( .axi_lite_rsp_t ( axi_lite_rsp_t ), .rule_t ( axi_pkg::xbar_rule_32_t ) ) i_xbar_dut ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_i ( test ), - .slv_ports_req_i ( mst_reqs ), - .slv_ports_rsp_o ( mst_rsps ), - .mst_ports_req_o ( slv_reqs ), - .mst_ports_rsp_i ( slv_rsps ), - .addr_map_i ( addr_map ), - .en_default_mst_port_i ( '0 ), - .default_mst_port_i ( '0 ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_i ( test ), + .sbr_ports_req_i ( mgr_reqs ), + .sbr_ports_rsp_o ( mgr_rsps ), + .mgr_ports_req_o ( sbr_reqs ), + .mgr_ports_rsp_i ( sbr_rsps ), + .addr_map_i ( addr_map ), + .en_default_mgr_port_i ( '0 ), + .default_mgr_port_i ( '0 ) ); endmodule @@ -464,7 +464,7 @@ module synth_axi_lite_mailbox #( AXI_LITE #( .AXI_ADDR_WIDTH (32'd32), .AXI_DATA_WIDTH (32'd32) - ) slv [1:0] (); + ) sbr [1:0] (); logic test; logic [1:0] irq; @@ -480,8 +480,8 @@ module synth_axi_lite_mailbox #( .clk_i ( clk_i ), // Clock .rst_ni ( rst_ni ), // Asynchronous reset active low .test_i ( test ), // Testmode enable - // slave ports [1:0] - .slv ( slv ), + // subordinate ports [1:0] + .sbr ( sbr ), .irq_o ( irq ), // interrupt output for each port .base_addr_i ( base_addr ) // base address for each port ); @@ -516,48 +516,48 @@ module synth_axi_isolate #( ) i_axi_isolate_dut ( .clk_i, .rst_ni, - .slv ( axi[0] ), // slave port - .mst ( axi[1] ), // master port - .isolate_i ( isolate ), // isolate master port from slave port - .isolated_o ( isolated ) // master port is isolated from slave port + .sbr ( axi[0] ), // subordinate port + .mgr ( axi[1] ), // manager port + .isolate_i ( isolate ), // isolate manager port from subordinate port + .isolated_o ( isolated ) // manager port is isolated from subordinate port ); endmodule module synth_axi_modify_address #( - parameter int unsigned AXI_SLV_PORT_ADDR_WIDTH = 0, - parameter int unsigned AXI_MST_PORT_ADDR_WIDTH = 0, + parameter int unsigned AXI_SBR_PORT_ADDR_WIDTH = 0, + parameter int unsigned AXI_MGR_PORT_ADDR_WIDTH = 0, parameter int unsigned AXI_DATA_WIDTH = 0, parameter int unsigned AXI_ID_WIDTH = 0, parameter int unsigned AXI_USER_WIDTH = 0 ) (); AXI_BUS #( - .AXI_ADDR_WIDTH (AXI_SLV_PORT_ADDR_WIDTH), + .AXI_ADDR_WIDTH (AXI_SBR_PORT_ADDR_WIDTH), .AXI_DATA_WIDTH (AXI_DATA_WIDTH), .AXI_ID_WIDTH (AXI_ID_WIDTH), .AXI_USER_WIDTH (AXI_USER_WIDTH) ) upstream (); AXI_BUS #( - .AXI_ADDR_WIDTH (AXI_MST_PORT_ADDR_WIDTH), + .AXI_ADDR_WIDTH (AXI_MGR_PORT_ADDR_WIDTH), .AXI_DATA_WIDTH (AXI_DATA_WIDTH), .AXI_ID_WIDTH (AXI_ID_WIDTH), .AXI_USER_WIDTH (AXI_USER_WIDTH) ) downstream (); - logic [AXI_MST_PORT_ADDR_WIDTH-1:0] mst_aw_addr, - mst_ar_addr; + logic [AXI_MGR_PORT_ADDR_WIDTH-1:0] mgr_aw_addr, + mgr_ar_addr; axi_modify_address_intf #( - .AXI_SLV_PORT_ADDR_WIDTH (AXI_SLV_PORT_ADDR_WIDTH), - .AXI_MST_PORT_ADDR_WIDTH (AXI_MST_PORT_ADDR_WIDTH), + .AXI_SBR_PORT_ADDR_WIDTH (AXI_SBR_PORT_ADDR_WIDTH), + .AXI_MGR_PORT_ADDR_WIDTH (AXI_MGR_PORT_ADDR_WIDTH), .AXI_DATA_WIDTH (AXI_DATA_WIDTH), .AXI_ID_WIDTH (AXI_ID_WIDTH), .AXI_USER_WIDTH (AXI_USER_WIDTH) ) dut ( - .slv (upstream), - .mst_aw_addr_i (mst_aw_addr), - .mst_ar_addr_i (mst_ar_addr), - .mst (downstream) + .sbr (upstream), + .mgr_aw_addr_i (mgr_aw_addr), + .mgr_ar_addr_i (mgr_ar_addr), + .mgr (downstream) ); endmodule @@ -589,8 +589,8 @@ module synth_axi_serializer #( ) i_axi_isolate_dut ( .clk_i, .rst_ni, - .slv ( axi[0] ), // slave port - .mst ( axi[1] ) // master port + .sbr ( axi[0] ), // subordinate port + .mgr ( axi[1] ) // manager port ); endmodule @@ -607,7 +607,7 @@ module synth_axi_lite_regs #( AXI_LITE #( .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ) - ) slv (); + ) sbr (); logic [REG_NUM_BYTES-1:0] wr_active, rd_active; byte_t [REG_NUM_BYTES-1:0] reg_d, reg_q; @@ -624,7 +624,7 @@ module synth_axi_lite_regs #( ) i_axi_lite_regs ( .clk_i, .rst_ni, - .slv ( slv ), + .sbr ( sbr ), .wr_active_o ( wr_active ), .rd_active_o ( rd_active ), .reg_d_i ( reg_d ), @@ -634,13 +634,13 @@ module synth_axi_lite_regs #( endmodule module synth_axi_iw_converter # ( - parameter int unsigned SlvPortIdWidth = 32'd0, - parameter int unsigned MstPortIdWidth = 32'd0, - parameter int unsigned SlvPortMaxUniqIds = 32'd0, - parameter int unsigned SlvPortMaxTxnsPerId = 32'd0, - parameter int unsigned SlvPortMaxTxns = 32'd0, - parameter int unsigned MstPortMaxUniqIds = 32'd0, - parameter int unsigned MstPortMaxTxnsPerId = 32'd0, + parameter int unsigned SbrPortIdWidth = 32'd0, + parameter int unsigned MgrPortIdWidth = 32'd0, + parameter int unsigned SbrPortMaxUniqIds = 32'd0, + parameter int unsigned SbrPortMaxTxnsPerId = 32'd0, + parameter int unsigned SbrPortMaxTxns = 32'd0, + parameter int unsigned MgrPortMaxUniqIds = 32'd0, + parameter int unsigned MgrPortMaxTxnsPerId = 32'd0, parameter int unsigned AddrWidth = 32'd0, parameter int unsigned DataWidth = 32'd0, parameter int unsigned UserWidth = 32'd0 @@ -651,32 +651,32 @@ module synth_axi_iw_converter # ( AXI_BUS #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), - .AXI_ID_WIDTH ( SlvPortIdWidth ), + .AXI_ID_WIDTH ( SbrPortIdWidth ), .AXI_USER_WIDTH ( UserWidth ) ) upstream (); AXI_BUS #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), - .AXI_ID_WIDTH ( MstPortIdWidth ), + .AXI_ID_WIDTH ( MgrPortIdWidth ), .AXI_USER_WIDTH ( UserWidth ) ) downstream (); axi_iw_converter_intf #( - .AXI_SLV_PORT_ID_WIDTH (SlvPortIdWidth ), - .AXI_MST_PORT_ID_WIDTH (MstPortIdWidth ), - .AXI_SLV_PORT_MAX_UNIQ_IDS (MstPortIdWidth ), - .AXI_SLV_PORT_MAX_TXNS_PER_ID (SlvPortMaxTxnsPerId ), - .AXI_SLV_PORT_MAX_TXNS (SlvPortMaxTxns ), - .AXI_MST_PORT_MAX_UNIQ_IDS (MstPortMaxUniqIds ), - .AXI_MST_PORT_MAX_TXNS_PER_ID (MstPortMaxTxnsPerId ), + .AXI_SBR_PORT_ID_WIDTH (SbrPortIdWidth ), + .AXI_MGR_PORT_ID_WIDTH (MgrPortIdWidth ), + .AXI_SBR_PORT_MAX_UNIQ_IDS (MgrPortIdWidth ), + .AXI_SBR_PORT_MAX_TXNS_PER_ID (SbrPortMaxTxnsPerId ), + .AXI_SBR_PORT_MAX_TXNS (SbrPortMaxTxns ), + .AXI_MGR_PORT_MAX_UNIQ_IDS (MgrPortMaxUniqIds ), + .AXI_MGR_PORT_MAX_TXNS_PER_ID (MgrPortMaxTxnsPerId ), .AXI_ADDR_WIDTH (AddrWidth ), .AXI_DATA_WIDTH (DataWidth ), .AXI_USER_WIDTH (UserWidth ) ) i_axi_iw_converter_dut ( .clk_i, .rst_ni, - .slv ( upstream ), - .mst ( downstream ) + .sbr ( upstream ), + .mgr ( downstream ) ); endmodule @@ -734,7 +734,7 @@ module synth_axi_to_mem_banked #( .clk_i, .rst_ni, .test_i ( test ), - .slv ( axi ), + .sbr ( axi ), .mem_req_o ( mem_req ), .mem_gnt_i ( mem_gnt ), .mem_add_o ( mem_addr ), diff --git a/test/tb_axi_addr_test.sv b/test/tb_axi_addr_test.sv index f4fc00c35..e9c49402b 100644 --- a/test/tb_axi_addr_test.sv +++ b/test/tb_axi_addr_test.sv @@ -45,7 +45,7 @@ module tb_axi_addr_test #( rand axi_pkg::burst_t burst = '0; endclass - // Random master no Transactions + // Random manager no Transactions localparam int unsigned NumPendingDut = 16; // timing parameters @@ -53,7 +53,7 @@ module tb_axi_addr_test #( localparam time ApplTime = 2ns; localparam time TestTime = 8ns; - typedef axi_test::axi_rand_master #( + typedef axi_test::axi_rand_manager #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), @@ -66,8 +66,8 @@ module tb_axi_addr_test #( .AXI_BURST_FIXED ( 1'b1 ), .AXI_BURST_INCR ( 1'b1 ), .AXI_BURST_WRAP ( 1'b1 ) - ) axi_rand_master_t; - typedef axi_test::axi_rand_slave #( + ) axi_rand_manager_t; + typedef axi_test::axi_rand_subordinate #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), @@ -76,7 +76,7 @@ module tb_axi_addr_test #( // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) axi_rand_slave_t; + ) axi_rand_subordinate_t; // ------------- // DUT signals // ------------- @@ -89,15 +89,15 @@ module tb_axi_addr_test #( .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidth ), .AXI_USER_WIDTH ( UserWidth ) - ) master_dv (clk); + ) manager_dv (clk); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidth ), .AXI_USER_WIDTH ( UserWidth ) - ) slave_dv (clk); + ) subordinate_dv (clk); - `AXI_ASSIGN(slave_dv, master_dv) + `AXI_ASSIGN(subordinate_dv, manager_dv) //----------------------------------- // Clock generator @@ -110,25 +110,25 @@ module tb_axi_addr_test #( .rst_no(rst_n) ); - initial begin : proc_axi_master - automatic axi_rand_master_t axi_rand_master = new(master_dv); + initial begin : proc_axi_manager + automatic axi_rand_manager_t axi_rand_manager = new(manager_dv); end_of_sim <= 1'b0; - axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::DEVICE_NONBUFFERABLE); - axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WTHRU_NOALLOCATE); - axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WBACK_RWALLOCATE); - axi_rand_master.reset(); + axi_rand_manager.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_manager.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WTHRU_NOALLOCATE); + axi_rand_manager.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WBACK_RWALLOCATE); + axi_rand_manager.reset(); @(posedge rst_n); - axi_rand_master.run(0, NumTests); + axi_rand_manager.run(0, NumTests); end_of_sim <= 1'b1; repeat (10000) @(posedge clk); $stop(); end - initial begin : proc_axi_slave - automatic axi_rand_slave_t axi_rand_slave = new(slave_dv); - axi_rand_slave.reset(); + initial begin : proc_axi_subordinate + automatic axi_rand_subordinate_t axi_rand_subordinate = new(subordinate_dv); + axi_rand_subordinate.reset(); @(posedge rst_n); - axi_rand_slave.run(); + axi_rand_subordinate.run(); end initial begin : proc_sim_progress @@ -142,10 +142,10 @@ module tb_axi_addr_test #( forever begin @(posedge clk); #TestTime; - if (master_dv.aw_valid && master_dv.aw_ready) begin + if (manager_dv.aw_valid && manager_dv.aw_ready) begin aw++; end - if (master_dv.ar_valid && master_dv.ar_ready) begin + if (manager_dv.ar_valid && manager_dv.ar_ready) begin ar++; end @@ -183,12 +183,12 @@ module tb_axi_addr_test #( forever begin @(posedge clk); #TestTime; - if (master_dv.aw_valid && master_dv.aw_ready) begin + if (manager_dv.aw_valid && manager_dv.aw_ready) begin ax_beat = new; - ax_beat.addr = master_dv.aw_addr; - ax_beat.len = master_dv.aw_len; - ax_beat.size = master_dv.aw_size; - ax_beat.burst = master_dv.aw_burst; + ax_beat.addr = manager_dv.aw_addr; + ax_beat.len = manager_dv.aw_len; + ax_beat.size = manager_dv.aw_size; + ax_beat.burst = manager_dv.aw_burst; ax_queue.push_back(ax_beat); end diff --git a/test/tb_axi_atop_filter.sv b/test/tb_axi_atop_filter.sv index 1f5d89a6b..993ea6ffb 100644 --- a/test/tb_axi_atop_filter.sv +++ b/test/tb_axi_atop_filter.sv @@ -104,19 +104,19 @@ module tb_axi_atop_filter #( ) dut ( .clk_i (clk), .rst_ni (rst_n), - .slv (upstream), - .mst (downstream) + .sbr (upstream), + .mgr (downstream) ); typedef logic [TB_AXI_ID_WIDTH-1:0] axi_id_t; - // AXI Master - logic mst_done = 1'b0; - axi_test::axi_rand_master #( + // AXI Manager + logic mgr_done = 1'b0; + axi_test::axi_rand_manager #( .AW(TB_AXI_ADDR_WIDTH), .DW(TB_AXI_DATA_WIDTH), .IW(TB_AXI_ID_WIDTH), .UW(TB_AXI_USER_WIDTH), .TA(TB_TA), .TT(TB_TT), .MAX_READ_TXNS (TB_AXI_MAX_READ_TXNS), - .MAX_WRITE_TXNS (TB_AXI_MAX_WRITE_TXNS+2), // master is not required to comply + .MAX_WRITE_TXNS (TB_AXI_MAX_WRITE_TXNS+2), // manager is not required to comply .AX_MIN_WAIT_CYCLES (TB_REQ_MIN_WAIT_CYCLES), .AX_MAX_WAIT_CYCLES (TB_REQ_MAX_WAIT_CYCLES), .W_MIN_WAIT_CYCLES (TB_REQ_MIN_WAIT_CYCLES), @@ -124,22 +124,22 @@ module tb_axi_atop_filter #( .RESP_MIN_WAIT_CYCLES (TB_RESP_MIN_WAIT_CYCLES), .RESP_MAX_WAIT_CYCLES (TB_RESP_MAX_WAIT_CYCLES), .AXI_ATOPS (1'b1) - ) axi_master = new(upstream_dv); + ) axi_manager = new(upstream_dv); initial begin - axi_master.reset(); + axi_manager.reset(); wait(rst_n); - axi_master.add_memory_region({TB_AXI_ADDR_WIDTH{1'b0}}, {TB_AXI_ADDR_WIDTH{1'b1}}, axi_pkg::WTHRU_NOALLOCATE); - axi_master.run(TB_N_TXNS, TB_N_TXNS); - mst_done = 1'b1; + axi_manager.add_memory_region({TB_AXI_ADDR_WIDTH{1'b0}}, {TB_AXI_ADDR_WIDTH{1'b1}}, axi_pkg::WTHRU_NOALLOCATE); + axi_manager.run(TB_N_TXNS, TB_N_TXNS); + mgr_done = 1'b1; end initial begin - wait (mst_done); + wait (mgr_done); $finish(); end - // AXI Slave - axi_test::axi_rand_slave #( + // AXI Subordinate + axi_test::axi_rand_subordinate #( .AW(TB_AXI_ADDR_WIDTH), .DW(TB_AXI_DATA_WIDTH), .IW(TB_AXI_ID_WIDTH), .UW(TB_AXI_USER_WIDTH), .TA(TB_TA), .TT(TB_TT), .AX_MIN_WAIT_CYCLES (TB_RESP_MIN_WAIT_CYCLES), @@ -148,11 +148,11 @@ module tb_axi_atop_filter #( .R_MAX_WAIT_CYCLES (TB_RESP_MAX_WAIT_CYCLES), .RESP_MIN_WAIT_CYCLES (TB_RESP_MIN_WAIT_CYCLES), .RESP_MAX_WAIT_CYCLES (TB_RESP_MAX_WAIT_CYCLES) - ) axi_slave = new(downstream_dv); + ) axi_subordinate = new(downstream_dv); initial begin - axi_slave.reset(); + axi_subordinate.reset(); wait (rst_n); - axi_slave.run(); + axi_subordinate.run(); end typedef struct packed { diff --git a/test/tb_axi_bus_compare.sv b/test/tb_axi_bus_compare.sv index 81eb00b9f..30ec7eb62 100644 --- a/test/tb_axi_bus_compare.sv +++ b/test/tb_axi_bus_compare.sv @@ -209,10 +209,10 @@ module tb_axi_bus_compare #( ) i_axi_multicut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .slv_req_i ( axi_req_b_out ), - .slv_rsp_o ( axi_rsp_b_out ), - .mst_req_o ( axi_req_b_dly ), - .mst_rsp_i ( axi_rsp_b_dly ) + .sbr_req_i ( axi_req_b_out ), + .sbr_rsp_o ( axi_rsp_b_out ), + .mgr_req_o ( axi_req_b_dly ), + .mgr_rsp_i ( axi_rsp_b_dly ) ); axi_sim_mem #( @@ -254,7 +254,7 @@ module tb_axi_bus_compare #( automatic drv_t::w_beat_t w_beat = new; automatic drv_t::b_beat_t b_beat; automatic drv_t::r_beat_t r_beat; - drv.reset_master(); + drv.reset_manager(); wait (rst_n); // AW `ifdef XSIM diff --git a/test/tb_axi_cdc.sv b/test/tb_axi_cdc.sv index 3d51ab9d8..93204e641 100644 --- a/test/tb_axi_cdc.sv +++ b/test/tb_axi_cdc.sv @@ -130,7 +130,7 @@ module tb_axi_cdc #( .dst (downstream) ); - typedef axi_test::axi_rand_master #( + typedef axi_test::axi_rand_manager #( .AW (AXI_AW), .DW (AXI_DW), .IW (AXI_IW), @@ -146,15 +146,15 @@ module tb_axi_cdc #( .RESP_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES), .RESP_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES), .AXI_MAX_BURST_LEN (16) - ) axi_master_t; - axi_master_t axi_master = new(upstream_dv); + ) axi_manager_t; + axi_manager_t axi_manager = new(upstream_dv); initial begin wait (upstream_rst_n); - axi_master.run(N_RD_TXNS, N_WR_TXNS); + axi_manager.run(N_RD_TXNS, N_WR_TXNS); end - typedef axi_test::axi_rand_slave #( + typedef axi_test::axi_rand_subordinate #( .AW (AXI_AW), .DW (AXI_DW), .IW (AXI_IW), @@ -167,32 +167,32 @@ module tb_axi_cdc #( .R_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES), .RESP_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES), .RESP_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES) - ) axi_slave_t; - axi_slave_t axi_slave = new(downstream_dv); + ) axi_subordinate_t; + axi_subordinate_t axi_subordinate = new(downstream_dv); initial begin wait (downstream_rst_n); - axi_slave.run(); + axi_subordinate.run(); end - ar_chan_t mst_ar, slv_ar, ar_queue[$]; - aw_chan_t mst_aw, slv_aw, aw_queue[$]; - b_chan_t mst_b, slv_b, b_queue[$]; - r_chan_t mst_r, slv_r, r_queue[$]; - w_chan_t mst_w, slv_w, w_queue[$]; + ar_chan_t mgr_ar, sbr_ar, ar_queue[$]; + aw_chan_t mgr_aw, sbr_aw, aw_queue[$]; + b_chan_t mgr_b, sbr_b, b_queue[$]; + r_chan_t mgr_r, sbr_r, r_queue[$]; + w_chan_t mgr_w, sbr_w, w_queue[$]; - `AXI_ASSIGN_TO_AR(mst_ar, upstream) - `AXI_ASSIGN_TO_AR(slv_ar, downstream) - `AXI_ASSIGN_TO_AW(mst_aw, upstream) - `AXI_ASSIGN_TO_AW(slv_aw, downstream) - `AXI_ASSIGN_TO_B(mst_b, upstream) - `AXI_ASSIGN_TO_B(slv_b, downstream) - `AXI_ASSIGN_TO_R(mst_r, upstream) - `AXI_ASSIGN_TO_R(slv_r, downstream) - `AXI_ASSIGN_TO_W(mst_w, upstream) - `AXI_ASSIGN_TO_W(slv_w, downstream) + `AXI_ASSIGN_TO_AR(mgr_ar, upstream) + `AXI_ASSIGN_TO_AR(sbr_ar, downstream) + `AXI_ASSIGN_TO_AW(mgr_aw, upstream) + `AXI_ASSIGN_TO_AW(sbr_aw, downstream) + `AXI_ASSIGN_TO_B(mgr_b, upstream) + `AXI_ASSIGN_TO_B(sbr_b, downstream) + `AXI_ASSIGN_TO_R(mgr_r, upstream) + `AXI_ASSIGN_TO_R(sbr_r, downstream) + `AXI_ASSIGN_TO_W(mgr_w, upstream) + `AXI_ASSIGN_TO_W(sbr_w, downstream) - logic mst_done = 1'b0; + logic mgr_done = 1'b0; // Monitor and check upstream initial begin automatic b_chan_t exp_b; @@ -202,28 +202,28 @@ module tb_axi_cdc #( @(posedge upstream_clk); #(TT_UPSTREAM); if (upstream.aw_valid && upstream.aw_ready) begin - aw_queue.push_back(mst_aw); + aw_queue.push_back(mgr_aw); end if (upstream.w_valid && upstream.w_ready) begin - w_queue.push_back(mst_w); + w_queue.push_back(mgr_w); end if (upstream.b_valid && upstream.b_ready) begin exp_b = b_queue.pop_front(); - assert (mst_b == exp_b); + assert (mgr_b == exp_b); wr_cnt++; end if (upstream.ar_valid && upstream.ar_ready) begin - ar_queue.push_back(mst_ar); + ar_queue.push_back(mgr_ar); end if (upstream.r_valid && upstream.r_ready) begin exp_r = r_queue.pop_front(); - assert (mst_r == exp_r); + assert (mgr_r == exp_r); if (upstream.r_last) begin rd_cnt++; end end if (rd_cnt == N_RD_TXNS && wr_cnt == N_WR_TXNS) begin - mst_done = 1'b1; + mgr_done = 1'b1; end end end @@ -238,28 +238,28 @@ module tb_axi_cdc #( #(TT_DOWNSTREAM); if (downstream.aw_valid && downstream.aw_ready) begin exp_aw = aw_queue.pop_front(); - assert (slv_aw == exp_aw); + assert (sbr_aw == exp_aw); end if (downstream.w_valid && downstream.w_ready) begin exp_w = w_queue.pop_front(); - assert (slv_w == exp_w); + assert (sbr_w == exp_w); end if (downstream.b_valid && downstream.b_ready) begin - b_queue.push_back(slv_b); + b_queue.push_back(sbr_b); end if (downstream.ar_valid && downstream.ar_ready) begin exp_ar = ar_queue.pop_front(); - assert (slv_ar == exp_ar); + assert (sbr_ar == exp_ar); end if (downstream.r_valid && downstream.r_ready) begin - r_queue.push_back(slv_r); + r_queue.push_back(sbr_r); end end end // Terminate simulation after all transactions have completed. initial begin - wait (mst_done); + wait (mgr_done); #(10*TCLK_UPSTREAM); $finish(); end diff --git a/test/tb_axi_delayer.sv b/test/tb_axi_delayer.sv index 5b9c15dc4..336c9b5dd 100644 --- a/test/tb_axi_delayer.sv +++ b/test/tb_axi_delayer.sv @@ -33,15 +33,15 @@ module tb_axi_delayer; .AXI_DATA_WIDTH(DW), .AXI_ID_WIDTH(IW), .AXI_USER_WIDTH(UW) - ) axi_slave_dv(clk), axi_master_dv(clk); + ) axi_subordinate_dv(clk), axi_manager_dv(clk); AXI_BUS #( .AXI_ADDR_WIDTH(AW), .AXI_DATA_WIDTH(DW), .AXI_ID_WIDTH(IW), .AXI_USER_WIDTH(UW) - ) axi_slave(), axi_master(); - `AXI_ASSIGN(axi_slave_dv, axi_slave) - `AXI_ASSIGN(axi_master, axi_master_dv) + ) axi_subordinate(), axi_manager(); + `AXI_ASSIGN(axi_subordinate_dv, axi_subordinate) + `AXI_ASSIGN(axi_manager, axi_manager_dv) axi_delayer_intf #( .AXI_ADDR_WIDTH ( AW ), @@ -53,12 +53,12 @@ module tb_axi_delayer; ) i_axi_delayer ( .clk_i ( clk ), .rst_ni ( rst ), - .slv ( axi_master ), - .mst ( axi_slave ) + .sbr ( axi_manager ), + .mgr ( axi_subordinate ) ); - axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(200ps), .TT(700ps)) axi_slave_drv = new(axi_slave_dv); - axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(200ps), .TT(700ps)) axi_master_drv = new(axi_master_dv); + axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(200ps), .TT(700ps)) axi_subordinate_drv = new(axi_subordinate_dv); + axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(200ps), .TT(700ps)) axi_manager_drv = new(axi_manager_dv); initial begin #tCK; @@ -79,7 +79,7 @@ module tb_axi_delayer; automatic axi_test::axi_w_beat #(.DW(DW), .UW(UW)) w_beat = new; automatic axi_test::axi_b_beat #(.IW(IW), .UW(UW)) b_beat; automatic logic rand_success; - axi_master_drv.reset_master(); + axi_manager_drv.reset_manager(); @(posedge clk); repeat (200) begin @(posedge clk); @@ -90,12 +90,12 @@ module tb_axi_delayer; `else rand_success = ax_beat.randomize(); assert(rand_success); `endif - axi_master_drv.send_aw(ax_beat); + axi_manager_drv.send_aw(ax_beat); w_beat.w_data = 'hcafebabe; - axi_master_drv.send_w(w_beat); + axi_manager_drv.send_w(w_beat); end - repeat (200) axi_master_drv.recv_b(b_beat); + repeat (200) axi_manager_drv.recv_b(b_beat); done = 1; end @@ -105,18 +105,18 @@ module tb_axi_delayer; automatic axi_test::axi_w_beat #(.DW(DW), .UW(UW)) w_beat; automatic axi_test::axi_b_beat #(.IW(IW), .UW(UW)) b_beat = new; automatic int b_id_queue[$]; - axi_slave_drv.reset_slave(); + axi_subordinate_drv.reset_subordinate(); @(posedge clk); repeat (200) begin - axi_slave_drv.recv_aw(ax_beat); + axi_subordinate_drv.recv_aw(ax_beat); $info("AXI AW: addr %h", ax_beat.ax_addr); - axi_slave_drv.recv_w(w_beat); + axi_subordinate_drv.recv_w(w_beat); $info("AXI W: data %h, strb %h", w_beat.w_data, w_beat.w_strb); b_id_queue.push_back(ax_beat.ax_id); end while (b_id_queue.size() != 0) begin b_beat.b_id = b_id_queue.pop_front(); - axi_slave_drv.send_b(b_beat); + axi_subordinate_drv.send_b(b_beat); end end // vsim -voptargs=+acc work.tb_axi_delayer diff --git a/test/tb_axi_dw_downsizer.do b/test/tb_axi_dw_downsizer.do index 3d120bbd6..e7719903c 100644 --- a/test/tb_axi_dw_downsizer.do +++ b/test/tb_axi_dw_downsizer.do @@ -1,4 +1,4 @@ add wave -position insertpoint \ - sim:/tb_axi_dw_downsizer/i_dw_converter/i_axi_dw_converter/gen_dw_downsize/i_axi_dw_downsizer/SlvPortDataWidth \ - sim:/tb_axi_dw_downsizer/i_dw_converter/i_axi_dw_converter/gen_dw_downsize/i_axi_dw_downsizer/MstPortDataWidth \ + sim:/tb_axi_dw_downsizer/i_dw_converter/i_axi_dw_converter/gen_dw_downsize/i_axi_dw_downsizer/SbrPortDataWidth \ + sim:/tb_axi_dw_downsizer/i_dw_converter/i_axi_dw_converter/gen_dw_downsize/i_axi_dw_downsizer/MgrPortDataWidth \ sim:/tb_axi_dw_downsizer/i_dw_converter/i_axi_dw_converter/gen_dw_downsize/i_axi_dw_downsizer/* diff --git a/test/tb_axi_dw_downsizer.sv b/test/tb_axi_dw_downsizer.sv index 25ad3edd7..db4ef66df 100644 --- a/test/tb_axi_dw_downsizer.sv +++ b/test/tb_axi_dw_downsizer.sv @@ -18,8 +18,8 @@ module tb_axi_dw_downsizer #( // AXI Parameters parameter int unsigned TbAddrWidth = 64 , parameter int unsigned TbIdWidth = 4 , - parameter int unsigned TbSlvPortDataWidth = 64 , - parameter int unsigned TbMstPortDataWidth = 32 , + parameter int unsigned TbSbrPortDataWidth = 64 , + parameter int unsigned TbMgrPortDataWidth = 32 , parameter int unsigned TbUserWidth = 8 , // TB Parameters parameter time TbCyclTime = 10ns, @@ -47,29 +47,29 @@ module tb_axi_dw_downsizer #( * AXI * *********/ - // Master port + // Manager port AXI_BUS_DV #( .AXI_ADDR_WIDTH(TbAddrWidth ), - .AXI_DATA_WIDTH(TbSlvPortDataWidth), + .AXI_DATA_WIDTH(TbSbrPortDataWidth), .AXI_ID_WIDTH (TbIdWidth ), .AXI_USER_WIDTH(TbUserWidth ) - ) master_dv ( + ) manager_dv ( .clk_i(clk) ); AXI_BUS #( .AXI_ADDR_WIDTH(TbAddrWidth ), - .AXI_DATA_WIDTH(TbSlvPortDataWidth), + .AXI_DATA_WIDTH(TbSbrPortDataWidth), .AXI_ID_WIDTH (TbIdWidth ), .AXI_USER_WIDTH(TbUserWidth ) - ) master (); + ) manager (); - `AXI_ASSIGN(master, master_dv) + `AXI_ASSIGN(manager, manager_dv) - axi_test::axi_rand_master #( + axi_test::axi_rand_manager #( .AW (TbAddrWidth ), - .DW (TbSlvPortDataWidth), + .DW (TbSbrPortDataWidth), .IW (TbIdWidth ), .UW (TbUserWidth ), .TA (TbApplTime ), @@ -78,36 +78,36 @@ module tb_axi_dw_downsizer #( .MAX_WRITE_TXNS (8 ), .AXI_BURST_FIXED(1'b0 ), .AXI_ATOPS (1'b1 ) - ) master_drv = new (master_dv); + ) manager_drv = new (manager_dv); - // Slave port + // Subordinate port AXI_BUS_DV #( .AXI_ADDR_WIDTH(TbAddrWidth ), - .AXI_DATA_WIDTH(TbMstPortDataWidth), + .AXI_DATA_WIDTH(TbMgrPortDataWidth), .AXI_ID_WIDTH (TbIdWidth ), .AXI_USER_WIDTH(TbUserWidth ) - ) slave_dv ( + ) subordinate_dv ( .clk_i(clk) ); AXI_BUS #( .AXI_ADDR_WIDTH(TbAddrWidth ), - .AXI_DATA_WIDTH(TbMstPortDataWidth), + .AXI_DATA_WIDTH(TbMgrPortDataWidth), .AXI_ID_WIDTH (TbIdWidth ), .AXI_USER_WIDTH(TbUserWidth ) - ) slave (); + ) subordinate (); - axi_test::axi_rand_slave #( + axi_test::axi_rand_subordinate #( .AW(TbAddrWidth ), - .DW(TbMstPortDataWidth), + .DW(TbMgrPortDataWidth), .IW(TbIdWidth ), .UW(TbUserWidth ), .TA(TbApplTime ), .TT(TbTestTime ) - ) slave_drv = new (slave_dv); + ) subordinate_drv = new (subordinate_dv); - `AXI_ASSIGN(slave_dv, slave) + `AXI_ASSIGN(subordinate_dv, subordinate) /********* * DUT * @@ -117,14 +117,14 @@ module tb_axi_dw_downsizer #( .AXI_MAX_READS (4 ), .AXI_ADDR_WIDTH (TbAddrWidth ), .AXI_ID_WIDTH (TbIdWidth ), - .AXI_SLV_PORT_DATA_WIDTH(TbSlvPortDataWidth), - .AXI_MST_PORT_DATA_WIDTH(TbMstPortDataWidth), + .AXI_SBR_PORT_DATA_WIDTH(TbSbrPortDataWidth), + .AXI_MGR_PORT_DATA_WIDTH(TbMgrPortDataWidth), .AXI_USER_WIDTH (TbUserWidth ) ) i_dw_converter ( .clk_i (clk ), .rst_ni(rst_n ), - .slv (master), - .mst (slave ) + .sbr (manager), + .mgr (subordinate ) ); /************* @@ -135,17 +135,17 @@ module tb_axi_dw_downsizer #( eos = 1'b0; // Configuration - slave_drv.reset() ; - master_drv.reset() ; - master_drv.add_memory_region({TbAddrWidth{1'b0}}, {TbAddrWidth{1'b1}}, axi_pkg::WTHRU_NOALLOCATE); + subordinate_drv.reset() ; + manager_drv.reset() ; + manager_drv.add_memory_region({TbAddrWidth{1'b0}}, {TbAddrWidth{1'b1}}, axi_pkg::WTHRU_NOALLOCATE); // Wait for the reset before sending requests @(posedge rst_n); fork // Act as a sink - slave_drv.run() ; - master_drv.run(200, 200); + subordinate_drv.run() ; + manager_drv.run(200, 200); join_any // Done @@ -160,12 +160,12 @@ module tb_axi_dw_downsizer #( initial begin : proc_monitor static tb_axi_dw_pkg::axi_dw_downsizer_monitor #( .AddrWidth (TbAddrWidth ), - .MstPortDataWidth(TbMstPortDataWidth), - .SlvPortDataWidth(TbSlvPortDataWidth), + .MgrPortDataWidth(TbMgrPortDataWidth), + .SbrPortDataWidth(TbSbrPortDataWidth), .IdWidth (TbIdWidth ), .UserWidth (TbUserWidth ), .TimeTest (TbTestTime ) - ) monitor = new (master_dv, slave_dv); + ) monitor = new (manager_dv, subordinate_dv); fork monitor.run(); forever begin diff --git a/test/tb_axi_dw_pkg.sv b/test/tb_axi_dw_pkg.sv index 16a0320b6..43b0d412e 100644 --- a/test/tb_axi_dw_pkg.sv +++ b/test/tb_axi_dw_pkg.sv @@ -12,7 +12,7 @@ // - Matheus Cavalcante // `axi_dw_upsizer_monitor` implements an AXI bus monitor that is tuned -// for the AXI Data Width Converters. It snoops on the slave and master port +// for the AXI Data Width Converters. It snoops on the subordinate and manager port // of the DWCs and populates FIFOs and ID queues to validate that no // AXI beats get lost. @@ -29,27 +29,27 @@ package tb_axi_dw_pkg ; class axi_dw_monitor #( parameter int unsigned AddrWidth , - parameter int unsigned SlvPortDataWidth, - parameter int unsigned MstPortDataWidth, + parameter int unsigned SbrPortDataWidth, + parameter int unsigned MgrPortDataWidth, parameter int unsigned IdWidth , parameter int unsigned UserWidth , // Stimuli application and test time parameter time TimeTest ); - localparam SlvPortStrbWidth = SlvPortDataWidth / 8; - localparam MstPortStrbWidth = MstPortDataWidth / 8; + localparam SbrPortStrbWidth = SbrPortDataWidth / 8; + localparam MgrPortStrbWidth = MgrPortDataWidth / 8; - localparam SlvPortMaxSize = $clog2(SlvPortStrbWidth); - localparam MstPortMaxSize = $clog2(MstPortStrbWidth); + localparam SbrPortMaxSize = $clog2(SbrPortStrbWidth); + localparam MgrPortMaxSize = $clog2(MgrPortStrbWidth); typedef logic [IdWidth-1:0] axi_id_t ; typedef logic [AddrWidth-1:0] axi_addr_t; - typedef logic [SlvPortDataWidth-1:0] slv_port_data_t; - typedef logic [SlvPortStrbWidth-1:0] slv_port_strb_t; - typedef logic [MstPortDataWidth-1:0] mst_port_data_t; - typedef logic [MstPortStrbWidth-1:0] mst_port_strb_t; + typedef logic [SbrPortDataWidth-1:0] sbr_port_data_t; + typedef logic [SbrPortStrbWidth-1:0] sbr_port_strb_t; + typedef logic [MgrPortDataWidth-1:0] mgr_port_data_t; + typedef logic [MgrPortStrbWidth-1:0] mgr_port_strb_t; typedef struct packed { axi_id_t axi_id; @@ -57,16 +57,16 @@ package tb_axi_dw_pkg ; } exp_b_t; typedef struct packed { axi_id_t axi_id ; - slv_port_data_t axi_data; - slv_port_strb_t axi_strb; + sbr_port_data_t axi_data; + sbr_port_strb_t axi_strb; logic axi_last ; - } exp_slv_rw_t; + } exp_sbr_rw_t; typedef struct packed { axi_id_t axi_id ; - mst_port_data_t axi_data; - mst_port_strb_t axi_strb; + mgr_port_data_t axi_data; + mgr_port_strb_t axi_strb; logic axi_last ; - } exp_mst_rw_t; + } exp_mgr_rw_t; typedef struct packed { axi_id_t axi_id ; axi_addr_t axi_addr; @@ -85,13 +85,13 @@ package tb_axi_dw_pkg ; .ID_WIDTH(IdWidth) ) b_queue_t; typedef rand_id_queue_pkg::rand_id_queue #( - .data_t (exp_slv_rw_t), + .data_t (exp_sbr_rw_t), .ID_WIDTH(IdWidth ) - ) slv_r_queue_t; + ) sbr_r_queue_t; typedef rand_id_queue_pkg::rand_id_queue #( - .data_t (exp_mst_rw_t), + .data_t (exp_mgr_rw_t), .ID_WIDTH(IdWidth ) - ) mst_r_queue_t; + ) mgr_r_queue_t; /********************** * Helper functions * @@ -116,16 +116,16 @@ package tb_axi_dw_pkg ; virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AddrWidth ), - .AXI_DATA_WIDTH(SlvPortDataWidth), + .AXI_DATA_WIDTH(SbrPortDataWidth), .AXI_ID_WIDTH (IdWidth ), .AXI_USER_WIDTH(UserWidth ) - ) slv_port_axi; + ) sbr_port_axi; virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AddrWidth ), - .AXI_DATA_WIDTH(MstPortDataWidth), + .AXI_DATA_WIDTH(MgrPortDataWidth), .AXI_ID_WIDTH (IdWidth ), .AXI_USER_WIDTH(UserWidth ) - ) mst_port_axi; + ) mgr_port_axi; /***************** * Bookkeeping * @@ -139,20 +139,20 @@ package tb_axi_dw_pkg ; // Queues and FIFOs to hold the expected AXIDs // Write transactions - ax_queue_t exp_mst_port_aw_queue; - exp_ax_t act_mst_port_aw_queue [$]; - exp_ax_t act_slv_port_aw_queue [$]; - exp_mst_rw_t exp_mst_port_w_queue [$]; - exp_mst_rw_t act_mst_port_w_queue [$]; - exp_slv_rw_t act_slv_port_w_queue [$]; - b_queue_t exp_slv_port_b_queue; + ax_queue_t exp_mgr_port_aw_queue; + exp_ax_t act_mgr_port_aw_queue [$]; + exp_ax_t act_sbr_port_aw_queue [$]; + exp_mgr_rw_t exp_mgr_port_w_queue [$]; + exp_mgr_rw_t act_mgr_port_w_queue [$]; + exp_sbr_rw_t act_sbr_port_w_queue [$]; + b_queue_t exp_sbr_port_b_queue; // Read transactions - ax_queue_t exp_mst_port_ar_queue; - ax_queue_t act_mst_port_ar_queue; - ax_queue_t act_slv_port_ar_queue; - exp_slv_rw_t act_slv_port_r_queue [$]; - slv_r_queue_t exp_slv_port_r_queue; + ax_queue_t exp_mgr_port_ar_queue; + ax_queue_t act_mgr_port_ar_queue; + ax_queue_t act_sbr_port_ar_queue; + exp_sbr_rw_t act_sbr_port_r_queue [$]; + sbr_r_queue_t exp_sbr_port_r_queue; /***************** * Constructor * @@ -161,29 +161,29 @@ package tb_axi_dw_pkg ; function new ( virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AddrWidth ), - .AXI_DATA_WIDTH(SlvPortDataWidth), + .AXI_DATA_WIDTH(SbrPortDataWidth), .AXI_ID_WIDTH (IdWidth ), .AXI_USER_WIDTH(UserWidth ) - ) slv_port_vif, + ) sbr_port_vif, virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AddrWidth ), - .AXI_DATA_WIDTH(MstPortDataWidth), + .AXI_DATA_WIDTH(MgrPortDataWidth), .AXI_ID_WIDTH (IdWidth ), .AXI_USER_WIDTH(UserWidth ) - ) mst_port_vif + ) mgr_port_vif ); begin - this.slv_port_axi = slv_port_vif; - this.mst_port_axi = mst_port_vif; + this.sbr_port_axi = sbr_port_vif; + this.mgr_port_axi = mgr_port_vif; this.tests_expected = 0 ; this.tests_conducted = 0 ; this.tests_failed = 0 ; - this.exp_slv_port_b_queue = new ; - this.exp_slv_port_r_queue = new ; - this.exp_mst_port_aw_queue = new ; - this.exp_mst_port_ar_queue = new ; - this.act_mst_port_ar_queue = new ; - this.act_slv_port_ar_queue = new ; + this.exp_sbr_port_b_queue = new ; + this.exp_sbr_port_r_queue = new ; + this.exp_mgr_port_aw_queue = new ; + this.exp_mgr_port_ar_queue = new ; + this.act_mgr_port_ar_queue = new ; + this.act_sbr_port_ar_queue = new ; this.cnt_sem = new(1) ; end endfunction @@ -193,7 +193,7 @@ package tb_axi_dw_pkg ; endtask: cycle_start task cycle_end; - @(posedge slv_port_axi.clk_i); + @(posedge sbr_port_axi.clk_i); endtask: cycle_end /************** @@ -202,304 +202,304 @@ package tb_axi_dw_pkg ; /* * You need to override this task. Use it to push the expected AW requests on - * the slave side, and the B and R responses expected on the master side. + * the subordinate side, and the B and R responses expected on the manager side. */ - virtual task automatic mon_slv_port_aw () ; + virtual task automatic mon_sbr_port_aw () ; $error("This task needs to be overridden."); - endtask : mon_slv_port_aw + endtask : mon_sbr_port_aw /* * You need to override this task. Use it to push the expected W requests on - * the slave side. + * the subordinate side. */ - virtual task automatic mon_slv_port_w () ; + virtual task automatic mon_sbr_port_w () ; $error("This task needs to be overridden."); - endtask : mon_slv_port_w + endtask : mon_sbr_port_w /* * You need to override this task. Use it to push the expected R responses on - * the master side. + * the manager side. */ - virtual task automatic mon_mst_port_r () ; + virtual task automatic mon_mgr_port_r () ; $error("This task needs to be overridden."); - endtask : mon_mst_port_r + endtask : mon_mgr_port_r /* * You need to override this task. Use it to push the expected AR requests on - * the slave side, and the R responses expected on the master side. + * the subordinate side, and the R responses expected on the manager side. */ - virtual task automatic mon_slv_port_ar () ; + virtual task automatic mon_sbr_port_ar () ; $error("This task needs to be overridden."); - endtask : mon_slv_port_ar + endtask : mon_sbr_port_ar /* * This tasks stores the beats seen by the AR, AW and W channels * into the respective queues. */ virtual task automatic store_channels (); - if (slv_port_axi.ar_valid && slv_port_axi.ar_ready) - act_slv_port_ar_queue.push(slv_port_axi.ar_id, + if (sbr_port_axi.ar_valid && sbr_port_axi.ar_ready) + act_sbr_port_ar_queue.push(sbr_port_axi.ar_id, '{ - axi_id : slv_port_axi.ar_id , - axi_burst: slv_port_axi.ar_burst, - axi_size : slv_port_axi.ar_size , - axi_addr : slv_port_axi.ar_addr , - axi_len : slv_port_axi.ar_len , - axi_cache: slv_port_axi.ar_cache + axi_id : sbr_port_axi.ar_id , + axi_burst: sbr_port_axi.ar_burst, + axi_size : sbr_port_axi.ar_size , + axi_addr : sbr_port_axi.ar_addr , + axi_len : sbr_port_axi.ar_len , + axi_cache: sbr_port_axi.ar_cache }); - if (slv_port_axi.aw_valid && slv_port_axi.aw_ready) begin - act_slv_port_aw_queue.push_back('{ - axi_id : slv_port_axi.aw_id , - axi_burst: slv_port_axi.aw_burst, - axi_size : slv_port_axi.aw_size , - axi_addr : slv_port_axi.aw_addr , - axi_len : slv_port_axi.aw_len , - axi_cache: slv_port_axi.aw_cache + if (sbr_port_axi.aw_valid && sbr_port_axi.aw_ready) begin + act_sbr_port_aw_queue.push_back('{ + axi_id : sbr_port_axi.aw_id , + axi_burst: sbr_port_axi.aw_burst, + axi_size : sbr_port_axi.aw_size , + axi_addr : sbr_port_axi.aw_addr , + axi_len : sbr_port_axi.aw_len , + axi_cache: sbr_port_axi.aw_cache }); // This request generates an R response. // Push this to the AR queue. - if (slv_port_axi.aw_atop[axi_pkg::ATOP_R_RESP]) - act_slv_port_ar_queue.push(slv_port_axi.aw_id, + if (sbr_port_axi.aw_atop[axi_pkg::ATOP_R_RESP]) + act_sbr_port_ar_queue.push(sbr_port_axi.aw_id, '{ - axi_id : slv_port_axi.aw_id , - axi_burst: slv_port_axi.aw_burst, - axi_size : slv_port_axi.aw_size , - axi_addr : slv_port_axi.aw_addr , - axi_len : slv_port_axi.aw_len , - axi_cache: slv_port_axi.aw_cache + axi_id : sbr_port_axi.aw_id , + axi_burst: sbr_port_axi.aw_burst, + axi_size : sbr_port_axi.aw_size , + axi_addr : sbr_port_axi.aw_addr , + axi_len : sbr_port_axi.aw_len , + axi_cache: sbr_port_axi.aw_cache }); end - if (slv_port_axi.w_valid && slv_port_axi.w_ready) - this.act_slv_port_w_queue.push_back('{ + if (sbr_port_axi.w_valid && sbr_port_axi.w_ready) + this.act_sbr_port_w_queue.push_back('{ axi_id : {IdWidth{1'b?}} , - axi_data: slv_port_axi.w_data, - axi_strb: slv_port_axi.w_strb, - axi_last: slv_port_axi.w_last + axi_data: sbr_port_axi.w_data, + axi_strb: sbr_port_axi.w_strb, + axi_last: sbr_port_axi.w_last }); - if (slv_port_axi.r_valid && slv_port_axi.r_ready) - this.act_slv_port_r_queue.push_back('{ - axi_id : slv_port_axi.r_id , - axi_data: slv_port_axi.r_data , - axi_strb: {SlvPortStrbWidth{1'b?}}, - axi_last: slv_port_axi.r_last + if (sbr_port_axi.r_valid && sbr_port_axi.r_ready) + this.act_sbr_port_r_queue.push_back('{ + axi_id : sbr_port_axi.r_id , + axi_data: sbr_port_axi.r_data , + axi_strb: {SbrPortStrbWidth{1'b?}}, + axi_last: sbr_port_axi.r_last }); - if (mst_port_axi.ar_valid && mst_port_axi.ar_ready) - act_mst_port_ar_queue.push(mst_port_axi.ar_id, + if (mgr_port_axi.ar_valid && mgr_port_axi.ar_ready) + act_mgr_port_ar_queue.push(mgr_port_axi.ar_id, '{ - axi_id : mst_port_axi.ar_id , - axi_burst: mst_port_axi.ar_burst, - axi_size : mst_port_axi.ar_size , - axi_addr : mst_port_axi.ar_addr , - axi_len : mst_port_axi.ar_len , - axi_cache: mst_port_axi.ar_cache + axi_id : mgr_port_axi.ar_id , + axi_burst: mgr_port_axi.ar_burst, + axi_size : mgr_port_axi.ar_size , + axi_addr : mgr_port_axi.ar_addr , + axi_len : mgr_port_axi.ar_len , + axi_cache: mgr_port_axi.ar_cache }); - if (mst_port_axi.aw_valid && mst_port_axi.aw_ready) begin - act_mst_port_aw_queue.push_back('{ - axi_id : mst_port_axi.aw_id , - axi_burst: mst_port_axi.aw_burst, - axi_size : mst_port_axi.aw_size , - axi_addr : mst_port_axi.aw_addr , - axi_len : mst_port_axi.aw_len , - axi_cache: mst_port_axi.aw_cache + if (mgr_port_axi.aw_valid && mgr_port_axi.aw_ready) begin + act_mgr_port_aw_queue.push_back('{ + axi_id : mgr_port_axi.aw_id , + axi_burst: mgr_port_axi.aw_burst, + axi_size : mgr_port_axi.aw_size , + axi_addr : mgr_port_axi.aw_addr , + axi_len : mgr_port_axi.aw_len , + axi_cache: mgr_port_axi.aw_cache }); // This request generates an R response. // Push this to the AR queue. - if (mst_port_axi.aw_atop[axi_pkg::ATOP_R_RESP]) - act_mst_port_ar_queue.push(mst_port_axi.aw_id, + if (mgr_port_axi.aw_atop[axi_pkg::ATOP_R_RESP]) + act_mgr_port_ar_queue.push(mgr_port_axi.aw_id, '{ - axi_id : mst_port_axi.aw_id , - axi_burst: mst_port_axi.aw_burst, - axi_size : mst_port_axi.aw_size , - axi_addr : mst_port_axi.aw_addr , - axi_len : mst_port_axi.aw_len , - axi_cache: mst_port_axi.aw_cache + axi_id : mgr_port_axi.aw_id , + axi_burst: mgr_port_axi.aw_burst, + axi_size : mgr_port_axi.aw_size , + axi_addr : mgr_port_axi.aw_addr , + axi_len : mgr_port_axi.aw_len , + axi_cache: mgr_port_axi.aw_cache }); end - if (mst_port_axi.w_valid && mst_port_axi.w_ready) - this.act_mst_port_w_queue.push_back('{ + if (mgr_port_axi.w_valid && mgr_port_axi.w_ready) + this.act_mgr_port_w_queue.push_back('{ axi_id : {IdWidth{1'b?}} , - axi_data: mst_port_axi.w_data, - axi_strb: mst_port_axi.w_strb, - axi_last: mst_port_axi.w_last + axi_data: mgr_port_axi.w_data, + axi_strb: mgr_port_axi.w_strb, + axi_last: mgr_port_axi.w_last }); endtask /* - * This task monitors the master port of the DW converter. Every time it gets an AW transaction, + * This task monitors the manager port of the DW converter. Every time it gets an AW transaction, * it gets checked for its contents against the expected beat on the `exp_aw_queue`. */ - task automatic mon_mst_port_aw (); + task automatic mon_mgr_port_aw (); exp_ax_t exp_aw; - if (mst_port_axi.aw_valid && mst_port_axi.aw_ready) begin + if (mgr_port_axi.aw_valid && mgr_port_axi.aw_ready) begin // Test if the AW beat was expected - exp_aw = this.exp_mst_port_aw_queue.pop_id(mst_port_axi.aw_id); - if (exp_aw.axi_id != mst_port_axi.aw_id) begin + exp_aw = this.exp_mgr_port_aw_queue.pop_id(mgr_port_axi.aw_id); + if (exp_aw.axi_id != mgr_port_axi.aw_id) begin incr_failed_tests(1) ; - $warning("Slave: Unexpected AW with ID: %b", mst_port_axi.aw_id); + $warning("Subordinate: Unexpected AW with ID: %b", mgr_port_axi.aw_id); end - if (exp_aw.axi_addr != mst_port_axi.aw_addr) begin + if (exp_aw.axi_addr != mgr_port_axi.aw_addr) begin incr_failed_tests(1); - $warning("Slave: Unexpected AW with ID: %b and ADDR: %h, exp: %h", - mst_port_axi.aw_id, mst_port_axi.aw_addr, exp_aw.axi_addr); + $warning("Subordinate: Unexpected AW with ID: %b and ADDR: %h, exp: %h", + mgr_port_axi.aw_id, mgr_port_axi.aw_addr, exp_aw.axi_addr); end - if (exp_aw.axi_len != mst_port_axi.aw_len) begin + if (exp_aw.axi_len != mgr_port_axi.aw_len) begin incr_failed_tests(1); - $warning("Slave: Unexpected AW with ID: %b and LEN: %h, exp: %h", - mst_port_axi.aw_id, mst_port_axi.aw_len, exp_aw.axi_len); + $warning("Subordinate: Unexpected AW with ID: %b and LEN: %h, exp: %h", + mgr_port_axi.aw_id, mgr_port_axi.aw_len, exp_aw.axi_len); end - if (exp_aw.axi_burst != mst_port_axi.aw_burst) begin + if (exp_aw.axi_burst != mgr_port_axi.aw_burst) begin incr_failed_tests(1); - $warning("Slave: Unexpected AW with ID: %b and BURST: %h, exp: %h", - mst_port_axi.aw_id, mst_port_axi.aw_burst, exp_aw.axi_burst); + $warning("Subordinate: Unexpected AW with ID: %b and BURST: %h, exp: %h", + mgr_port_axi.aw_id, mgr_port_axi.aw_burst, exp_aw.axi_burst); end - if (exp_aw.axi_size != mst_port_axi.aw_size) begin + if (exp_aw.axi_size != mgr_port_axi.aw_size) begin incr_failed_tests(1); - $warning("Slave: Unexpected AW with ID: %b and SIZE: %h, exp: %h", - mst_port_axi.aw_id, mst_port_axi.aw_size, exp_aw.axi_size); + $warning("Subordinate: Unexpected AW with ID: %b and SIZE: %h, exp: %h", + mgr_port_axi.aw_id, mgr_port_axi.aw_size, exp_aw.axi_size); end - if (exp_aw.axi_cache != mst_port_axi.aw_cache) begin + if (exp_aw.axi_cache != mgr_port_axi.aw_cache) begin incr_failed_tests(1); - $warning("Slave: Unexpected AW with ID: %b and CACHE: %b, exp: %b", - mst_port_axi.aw_id, mst_port_axi.aw_cache, exp_aw.axi_cache); + $warning("Subordinate: Unexpected AW with ID: %b and CACHE: %b, exp: %b", + mgr_port_axi.aw_id, mgr_port_axi.aw_cache, exp_aw.axi_cache); end incr_conducted_tests(6); end - endtask : mon_mst_port_aw + endtask : mon_mgr_port_aw /* - * This task compares the expected and actual W beats on the master port. + * This task compares the expected and actual W beats on the manager port. */ - task automatic mon_mst_port_w (); - exp_mst_rw_t exp_w, act_w; - while (this.exp_mst_port_w_queue.size() != 0 && this.act_mst_port_w_queue.size() != 0) begin - exp_w = this.exp_mst_port_w_queue.pop_front(); - act_w = this.act_mst_port_w_queue.pop_front(); + task automatic mon_mgr_port_w (); + exp_mgr_rw_t exp_w, act_w; + while (this.exp_mgr_port_w_queue.size() != 0 && this.act_mgr_port_w_queue.size() != 0) begin + exp_w = this.exp_mgr_port_w_queue.pop_front(); + act_w = this.act_mgr_port_w_queue.pop_front(); // Do the checks if (exp_w.axi_data != act_w.axi_data) begin incr_failed_tests(1); - $warning("Slave: Unexpected W with DATA: %h, exp: %h", + $warning("Subordinate: Unexpected W with DATA: %h, exp: %h", act_w.axi_data, exp_w.axi_data); end if (exp_w.axi_strb != act_w.axi_strb) begin incr_failed_tests(1); - $warning("Slave: Unexpected W with STRB: %h, exp: %h", + $warning("Subordinate: Unexpected W with STRB: %h, exp: %h", act_w.axi_strb, exp_w.axi_strb); end if (exp_w.axi_last != act_w.axi_last) begin incr_failed_tests(1); - $warning("Slave: Unexpected W with LAST: %b, exp: %b", + $warning("Subordinate: Unexpected W with LAST: %b, exp: %b", act_w.axi_last, exp_w.axi_last); end incr_conducted_tests(3); end - endtask : mon_mst_port_w + endtask : mon_mgr_port_w /* - * This task checks if a B response is allowed on a slave port of the DW converter. + * This task checks if a B response is allowed on a subordinate port of the DW converter. */ - task automatic mon_slv_port_b (); + task automatic mon_sbr_port_b (); exp_b_t exp_b; axi_id_t axi_b_id; - if (slv_port_axi.b_valid && slv_port_axi.b_ready) begin + if (sbr_port_axi.b_valid && sbr_port_axi.b_ready) begin incr_conducted_tests(1); - axi_b_id = slv_port_axi.b_id; - $display("%0tns > Master: Got last B with ID: %b", + axi_b_id = sbr_port_axi.b_id; + $display("%0tns > Manager: Got last B with ID: %b", $time, axi_b_id); - if (this.exp_slv_port_b_queue.is_empty()) begin + if (this.exp_sbr_port_b_queue.is_empty()) begin incr_failed_tests(1) ; - $warning("Master: unexpected B beat with ID: %b detected!", axi_b_id); + $warning("Manager: unexpected B beat with ID: %b detected!", axi_b_id); end else begin - exp_b = this.exp_slv_port_b_queue.pop_id(axi_b_id); + exp_b = this.exp_sbr_port_b_queue.pop_id(axi_b_id); if (axi_b_id != exp_b.axi_id) begin incr_failed_tests(1) ; - $warning("Master: got unexpected B with ID: %b", axi_b_id); + $warning("Manager: got unexpected B with ID: %b", axi_b_id); end end end - endtask : mon_slv_port_b + endtask : mon_sbr_port_b /* - * This task monitors a the master port of the DW converter and checks + * This task monitors a the manager port of the DW converter and checks * if the AR beats were all expected. */ - task automatic mon_mst_port_ar (); + task automatic mon_mgr_port_ar (); exp_ax_t exp_ar; - if (mst_port_axi.ar_valid && mst_port_axi.ar_ready) begin + if (mgr_port_axi.ar_valid && mgr_port_axi.ar_ready) begin // Test if the AR beat was expected - exp_ar = this.exp_mst_port_ar_queue.pop_id(mst_port_axi.ar_id); - if (exp_ar.axi_id != mst_port_axi.ar_id) begin + exp_ar = this.exp_mgr_port_ar_queue.pop_id(mgr_port_axi.ar_id); + if (exp_ar.axi_id != mgr_port_axi.ar_id) begin incr_failed_tests(1) ; - $warning("Slave: Unexpected AR with ID: %b", mst_port_axi.ar_id); + $warning("Subordinate: Unexpected AR with ID: %b", mgr_port_axi.ar_id); end - if (exp_ar.axi_addr != mst_port_axi.ar_addr) begin + if (exp_ar.axi_addr != mgr_port_axi.ar_addr) begin incr_failed_tests(1); - $warning("Slave: Unexpected AR with ID: %b and ADDR: %h, exp: %h", - mst_port_axi.ar_id, mst_port_axi.ar_addr, exp_ar.axi_addr); + $warning("Subordinate: Unexpected AR with ID: %b and ADDR: %h, exp: %h", + mgr_port_axi.ar_id, mgr_port_axi.ar_addr, exp_ar.axi_addr); end - if (exp_ar.axi_len != mst_port_axi.ar_len) begin + if (exp_ar.axi_len != mgr_port_axi.ar_len) begin incr_failed_tests(1); - $warning("Slave: Unexpected AR with ID: %b and LEN: %h, exp: %h", - mst_port_axi.ar_id, mst_port_axi.ar_len, exp_ar.axi_len); + $warning("Subordinate: Unexpected AR with ID: %b and LEN: %h, exp: %h", + mgr_port_axi.ar_id, mgr_port_axi.ar_len, exp_ar.axi_len); end - if (exp_ar.axi_burst != mst_port_axi.ar_burst) begin + if (exp_ar.axi_burst != mgr_port_axi.ar_burst) begin incr_failed_tests(1); - $warning("Slave: Unexpected AR with ID: %b and BURST: %h, exp: %h", - mst_port_axi.ar_id, mst_port_axi.ar_burst, exp_ar.axi_burst); + $warning("Subordinate: Unexpected AR with ID: %b and BURST: %h, exp: %h", + mgr_port_axi.ar_id, mgr_port_axi.ar_burst, exp_ar.axi_burst); end - if (exp_ar.axi_size != mst_port_axi.ar_size) begin + if (exp_ar.axi_size != mgr_port_axi.ar_size) begin incr_failed_tests(1); - $warning("Slave: Unexpected AR with ID: %b and SIZE: %h, exp: %h", - mst_port_axi.ar_id, mst_port_axi.ar_size, exp_ar.axi_size); + $warning("Subordinate: Unexpected AR with ID: %b and SIZE: %h, exp: %h", + mgr_port_axi.ar_id, mgr_port_axi.ar_size, exp_ar.axi_size); end - if (exp_ar.axi_cache != mst_port_axi.ar_cache) begin + if (exp_ar.axi_cache != mgr_port_axi.ar_cache) begin incr_failed_tests(1); - $warning("Slave: Unexpected AR with ID: %b and CACHE: %b, exp: %b", - mst_port_axi.ar_id, mst_port_axi.ar_cache, exp_ar.axi_cache); + $warning("Subordinate: Unexpected AR with ID: %b and CACHE: %b, exp: %b", + mgr_port_axi.ar_id, mgr_port_axi.ar_cache, exp_ar.axi_cache); end incr_conducted_tests(6); end - endtask : mon_mst_port_ar + endtask : mon_mgr_port_ar /* - * This task does the R channel monitoring on a slave port. It compares the last flags, + * This task does the R channel monitoring on a subordinate port. It compares the last flags, * which are determined by the sequence of previously sent AR vectors. */ - task automatic mon_slv_port_r (); - exp_slv_rw_t exp_r; - if (act_slv_port_r_queue.size() != 0) begin - exp_slv_rw_t act_r = act_slv_port_r_queue[0] ; - if (exp_slv_port_r_queue.queues[act_r.axi_id].size() != 0) begin - exp_r = exp_slv_port_r_queue.pop_id(act_r.axi_id); - void'(act_slv_port_r_queue.pop_front()); + task automatic mon_sbr_port_r (); + exp_sbr_rw_t exp_r; + if (act_sbr_port_r_queue.size() != 0) begin + exp_sbr_rw_t act_r = act_sbr_port_r_queue[0] ; + if (exp_sbr_port_r_queue.queues[act_r.axi_id].size() != 0) begin + exp_r = exp_sbr_port_r_queue.pop_id(act_r.axi_id); + void'(act_sbr_port_r_queue.pop_front()); // Do the checks if (exp_r.axi_id != act_r.axi_id) begin incr_failed_tests(1); - $warning("Slave: Unexpected R with ID: %b", + $warning("Subordinate: Unexpected R with ID: %b", act_r.axi_id); end if (exp_r.axi_last != act_r.axi_last) begin incr_failed_tests(1); - $warning("Slave: Unexpected R with ID: %b and LAST: %b, exp: %b", + $warning("Subordinate: Unexpected R with ID: %b and LAST: %b, exp: %b", act_r.axi_id, act_r.axi_last, exp_r.axi_last); end if (exp_r.axi_data != act_r.axi_data) begin incr_failed_tests(1); - $warning("Slave: Unexpected R with ID: %b and DATA: %h, exp: %h", + $warning("Subordinate: Unexpected R with ID: %b and DATA: %h, exp: %h", act_r.axi_id, act_r.axi_data, exp_r.axi_data); end incr_conducted_tests(3); end end - endtask : mon_slv_port_r + endtask : mon_sbr_port_r // Some tasks to manage bookkeeping of the tests conducted. task incr_expected_tests(input int unsigned times); @@ -532,23 +532,23 @@ package tb_axi_dw_pkg ; // Execute all processes that push something into the queues PushMon: fork - proc_mst_aw : mon_slv_port_aw(); - proc_mst_ar : mon_slv_port_ar(); - proc_mst_w : mon_slv_port_w() ; - proc_slv_r : mon_mst_port_r() ; + proc_mgr_aw : mon_sbr_port_aw(); + proc_mgr_ar : mon_sbr_port_ar(); + proc_mgr_w : mon_sbr_port_w() ; + proc_sbr_r : mon_mgr_port_r() ; proc_store_channel: store_channels() ; join: PushMon // These only pop something from the queues PopMon: fork - proc_slv_aw: mon_mst_port_aw(); - proc_mst_b : mon_slv_port_b() ; - proc_slv_ar: mon_mst_port_ar(); - proc_mst_r : mon_slv_port_r() ; + proc_sbr_aw: mon_mgr_port_aw(); + proc_mgr_b : mon_sbr_port_b() ; + proc_sbr_ar: mon_mgr_port_ar(); + proc_mgr_r : mon_sbr_port_r() ; join : PopMon - // Check the slave W FIFOs last - proc_check_slv_w: mon_mst_port_w(); + // Check the subordinate W FIFOs last + proc_check_sbr_w: mon_mgr_port_w(); cycle_end(); end @@ -572,27 +572,27 @@ package tb_axi_dw_pkg ; class axi_dw_upsizer_monitor #( parameter int unsigned AddrWidth , - parameter int unsigned SlvPortDataWidth, - parameter int unsigned MstPortDataWidth, + parameter int unsigned SbrPortDataWidth, + parameter int unsigned MgrPortDataWidth, parameter int unsigned IdWidth , parameter int unsigned UserWidth , // Stimuli application and test time parameter time TimeTest ) extends axi_dw_monitor #( .AddrWidth (AddrWidth ), - .SlvPortDataWidth(SlvPortDataWidth), - .MstPortDataWidth(MstPortDataWidth), + .SbrPortDataWidth(SbrPortDataWidth), + .MgrPortDataWidth(MgrPortDataWidth), .IdWidth (IdWidth ), .UserWidth (UserWidth ), .TimeTest (TimeTest ) ); - local static shortint unsigned slv_port_r_cnt[axi_id_t]; - local static shortint unsigned mst_port_r_cnt[axi_id_t]; - local static shortint unsigned slv_port_w_cnt; - local static shortint unsigned mst_port_w_cnt; - local static exp_mst_rw_t mst_port_w; - local static shortint unsigned mst_port_w_pnt; + local static shortint unsigned sbr_port_r_cnt[axi_id_t]; + local static shortint unsigned mgr_port_r_cnt[axi_id_t]; + local static shortint unsigned sbr_port_w_cnt; + local static shortint unsigned mgr_port_w_cnt; + local static exp_mgr_rw_t mgr_port_w; + local static shortint unsigned mgr_port_w_pnt; /***************** * Constructor * @@ -601,26 +601,26 @@ package tb_axi_dw_pkg ; function new ( virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AddrWidth ), - .AXI_DATA_WIDTH(SlvPortDataWidth), + .AXI_DATA_WIDTH(SbrPortDataWidth), .AXI_ID_WIDTH (IdWidth ), .AXI_USER_WIDTH(UserWidth ) - ) slv_port_vif, + ) sbr_port_vif, virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AddrWidth ), - .AXI_DATA_WIDTH(MstPortDataWidth), + .AXI_DATA_WIDTH(MgrPortDataWidth), .AXI_ID_WIDTH (IdWidth ), .AXI_USER_WIDTH(UserWidth ) - ) mst_port_vif + ) mgr_port_vif ); begin - super.new(slv_port_vif, mst_port_vif); - slv_port_w_cnt = '0; - mst_port_w_cnt = '0; - mst_port_w_pnt = '1; - mst_port_w = '0; + super.new(sbr_port_vif, mgr_port_vif); + sbr_port_w_cnt = '0; + mgr_port_w_cnt = '0; + mgr_port_w_pnt = '1; + mgr_port_w = '0; for (int unsigned id = 0; id < 2**IdWidth; id++) begin - slv_port_r_cnt[id] = '0; - mst_port_r_cnt[id] = '0; + sbr_port_r_cnt[id] = '0; + mgr_port_r_cnt[id] = '0; end end endfunction @@ -629,48 +629,48 @@ package tb_axi_dw_pkg ; * Monitors * **************/ - task automatic mon_slv_port_aw (); + task automatic mon_sbr_port_aw (); exp_ax_t exp_aw; - if (slv_port_axi.aw_valid && slv_port_axi.aw_ready) begin + if (sbr_port_axi.aw_valid && sbr_port_axi.aw_ready) begin // Non-modifiable transaction - if (!axi_pkg::modifiable(slv_port_axi.aw_cache)) begin + if (!axi_pkg::modifiable(sbr_port_axi.aw_cache)) begin // We expect that the transaction will not be modified exp_aw = '{ - axi_id : slv_port_axi.aw_id , - axi_addr : slv_port_axi.aw_addr , - axi_len : slv_port_axi.aw_len , - axi_burst: slv_port_axi.aw_burst, - axi_size : slv_port_axi.aw_size , - axi_cache: slv_port_axi.aw_cache + axi_id : sbr_port_axi.aw_id , + axi_addr : sbr_port_axi.aw_addr , + axi_len : sbr_port_axi.aw_len , + axi_burst: sbr_port_axi.aw_burst, + axi_size : sbr_port_axi.aw_size , + axi_cache: sbr_port_axi.aw_cache } ; end // Modifiable transaction else begin - case (slv_port_axi.aw_burst) + case (sbr_port_axi.aw_burst) // Passthrough upsize axi_pkg::BURST_FIXED: begin exp_aw = '{ - axi_id : slv_port_axi.aw_id , - axi_addr : slv_port_axi.aw_addr , - axi_len : slv_port_axi.aw_len , - axi_burst: slv_port_axi.aw_burst, - axi_size : slv_port_axi.aw_size , - axi_cache: slv_port_axi.aw_cache + axi_id : sbr_port_axi.aw_id , + axi_addr : sbr_port_axi.aw_addr , + axi_len : sbr_port_axi.aw_len , + axi_burst: sbr_port_axi.aw_burst, + axi_size : sbr_port_axi.aw_size , + axi_cache: sbr_port_axi.aw_cache }; end // INCR upsize axi_pkg::BURST_INCR: begin - automatic axi_addr_t aligned_start = axi_pkg::aligned_addr(slv_port_axi.aw_addr, MstPortMaxSize) ; - automatic axi_addr_t aligned_end = axi_pkg::aligned_addr(axi_pkg::aligned_addr(slv_port_axi.aw_addr, slv_port_axi.aw_size) + (unsigned'(slv_port_axi.aw_len) << slv_port_axi.aw_size), MstPortMaxSize); + automatic axi_addr_t aligned_start = axi_pkg::aligned_addr(sbr_port_axi.aw_addr, MgrPortMaxSize) ; + automatic axi_addr_t aligned_end = axi_pkg::aligned_addr(axi_pkg::aligned_addr(sbr_port_axi.aw_addr, sbr_port_axi.aw_size) + (unsigned'(sbr_port_axi.aw_len) << sbr_port_axi.aw_size), MgrPortMaxSize); exp_aw = '{ - axi_id : slv_port_axi.aw_id , - axi_addr : slv_port_axi.aw_addr , - axi_len : (aligned_end - aligned_start) >> MstPortMaxSize , - axi_burst: slv_port_axi.aw_burst , - axi_size : slv_port_axi.aw_len == 0 ? slv_port_axi.aw_size : MstPortMaxSize, - axi_cache: slv_port_axi.aw_cache + axi_id : sbr_port_axi.aw_id , + axi_addr : sbr_port_axi.aw_addr , + axi_len : (aligned_end - aligned_start) >> MgrPortMaxSize , + axi_burst: sbr_port_axi.aw_burst , + axi_size : sbr_port_axi.aw_len == 0 ? sbr_port_axi.aw_size : MgrPortMaxSize, + axi_cache: sbr_port_axi.aw_cache }; end // WRAP upsize @@ -679,223 +679,223 @@ package tb_axi_dw_pkg ; $warning("WRAP bursts are not supported."); end endcase - this.exp_mst_port_aw_queue.push(slv_port_axi.aw_id, exp_aw); + this.exp_mgr_port_aw_queue.push(sbr_port_axi.aw_id, exp_aw); incr_expected_tests(6) ; - $display("%0tns > Master: AW with ID: %b", - $time, slv_port_axi.aw_id); + $display("%0tns > Manager: AW with ID: %b", + $time, sbr_port_axi.aw_id); end // Populate the expected B responses - this.exp_slv_port_b_queue.push(slv_port_axi.aw_id, '{ - axi_id : slv_port_axi.aw_id, + this.exp_sbr_port_b_queue.push(sbr_port_axi.aw_id, '{ + axi_id : sbr_port_axi.aw_id, axi_last: 1'b1 }) ; incr_expected_tests(1) ; $display(" Expect B response.") ; end - endtask : mon_slv_port_aw + endtask : mon_sbr_port_aw - task automatic mon_slv_port_w (); - if (act_slv_port_w_queue.size() != 0) begin - exp_slv_rw_t act_slv_w = act_slv_port_w_queue[0]; + task automatic mon_sbr_port_w (); + if (act_sbr_port_w_queue.size() != 0) begin + exp_sbr_rw_t act_sbr_w = act_sbr_port_w_queue[0]; - if (act_mst_port_aw_queue.size() != 0 && act_slv_port_aw_queue.size() != 0) begin + if (act_mgr_port_aw_queue.size() != 0 && act_sbr_port_aw_queue.size() != 0) begin // Retrieve the AW requests related to this W beat - exp_ax_t act_mst_aw = act_mst_port_aw_queue[0]; - exp_ax_t act_slv_aw = act_slv_port_aw_queue[0]; + exp_ax_t act_mgr_aw = act_mgr_port_aw_queue[0]; + exp_ax_t act_sbr_aw = act_sbr_port_aw_queue[0]; // Calculate the offsets - shortint unsigned mst_port_lower_byte = - axi_pkg::beat_lower_byte(act_mst_aw.axi_addr, act_mst_aw.axi_size, act_mst_aw.axi_len, act_mst_aw.axi_burst, MstPortStrbWidth, mst_port_w_cnt); - shortint unsigned mst_port_upper_byte = - axi_pkg::beat_upper_byte(act_mst_aw.axi_addr, act_mst_aw.axi_size, act_mst_aw.axi_len, act_mst_aw.axi_burst, MstPortStrbWidth, mst_port_w_cnt); - shortint unsigned slv_port_lower_byte = - axi_pkg::beat_lower_byte(act_slv_aw.axi_addr, act_slv_aw.axi_size, act_slv_aw.axi_len, act_slv_aw.axi_burst, SlvPortStrbWidth, slv_port_w_cnt); - shortint unsigned slv_port_upper_byte = - axi_pkg::beat_upper_byte(act_slv_aw.axi_addr, act_slv_aw.axi_size, act_slv_aw.axi_len, act_slv_aw.axi_burst, SlvPortStrbWidth, slv_port_w_cnt); + shortint unsigned mgr_port_lower_byte = + axi_pkg::beat_lower_byte(act_mgr_aw.axi_addr, act_mgr_aw.axi_size, act_mgr_aw.axi_len, act_mgr_aw.axi_burst, MgrPortStrbWidth, mgr_port_w_cnt); + shortint unsigned mgr_port_upper_byte = + axi_pkg::beat_upper_byte(act_mgr_aw.axi_addr, act_mgr_aw.axi_size, act_mgr_aw.axi_len, act_mgr_aw.axi_burst, MgrPortStrbWidth, mgr_port_w_cnt); + shortint unsigned sbr_port_lower_byte = + axi_pkg::beat_lower_byte(act_sbr_aw.axi_addr, act_sbr_aw.axi_size, act_sbr_aw.axi_len, act_sbr_aw.axi_burst, SbrPortStrbWidth, sbr_port_w_cnt); + shortint unsigned sbr_port_upper_byte = + axi_pkg::beat_upper_byte(act_sbr_aw.axi_addr, act_sbr_aw.axi_size, act_sbr_aw.axi_len, act_sbr_aw.axi_burst, SbrPortStrbWidth, sbr_port_w_cnt); shortint unsigned bytes_copied = 0; // Pointer inside the outcoming word - if (mst_port_w_pnt == '1) - mst_port_w_pnt = mst_port_lower_byte; + if (mgr_port_w_pnt == '1) + mgr_port_w_pnt = mgr_port_lower_byte; - mst_port_w.axi_last = mst_port_w_cnt == act_mst_aw.axi_len; - for (shortint unsigned b = slv_port_lower_byte; b <= slv_port_upper_byte; b++) begin - if (b + mst_port_w_pnt - slv_port_lower_byte == MstPortStrbWidth) + mgr_port_w.axi_last = mgr_port_w_cnt == act_mgr_aw.axi_len; + for (shortint unsigned b = sbr_port_lower_byte; b <= sbr_port_upper_byte; b++) begin + if (b + mgr_port_w_pnt - sbr_port_lower_byte == MgrPortStrbWidth) break; - mst_port_w.axi_data[8*(b + mst_port_w_pnt - slv_port_lower_byte) +: 8] = act_slv_w.axi_data[8*b +: 8]; - mst_port_w.axi_strb[b + mst_port_w_pnt - slv_port_lower_byte] = act_slv_w.axi_strb[b] ; + mgr_port_w.axi_data[8*(b + mgr_port_w_pnt - sbr_port_lower_byte) +: 8] = act_sbr_w.axi_data[8*b +: 8]; + mgr_port_w.axi_strb[b + mgr_port_w_pnt - sbr_port_lower_byte] = act_sbr_w.axi_strb[b] ; bytes_copied++; end // Increment the len counters - slv_port_w_cnt++ ; - mst_port_w_pnt += bytes_copied; + sbr_port_w_cnt++ ; + mgr_port_w_pnt += bytes_copied; - if (act_mst_aw.axi_burst == axi_pkg::BURST_FIXED // No upsizing - || mst_port_w_pnt == MstPortStrbWidth // Filled up an outcoming W beat - || act_slv_w.axi_last // Last beat of a W burst + if (act_mgr_aw.axi_burst == axi_pkg::BURST_FIXED // No upsizing + || mgr_port_w_pnt == MgrPortStrbWidth // Filled up an outcoming W beat + || act_sbr_w.axi_last // Last beat of a W burst ) begin // Don't care for the bits outside these accessed by this request - for (int unsigned b = 0; b < MstPortStrbWidth; b++) - if (!(mst_port_lower_byte <= b && b <= mst_port_upper_byte)) - mst_port_w.axi_data[8*b +: 8] = {8{1'b?}}; + for (int unsigned b = 0; b < MgrPortStrbWidth; b++) + if (!(mgr_port_lower_byte <= b && b <= mgr_port_upper_byte)) + mgr_port_w.axi_data[8*b +: 8] = {8{1'b?}}; - this.exp_mst_port_w_queue.push_back(mst_port_w); + this.exp_mgr_port_w_queue.push_back(mgr_port_w); incr_expected_tests(3) ; // Increment the len counter - mst_port_w_cnt++; + mgr_port_w_cnt++; // Reset W beat - mst_port_w = '0; - mst_port_w_pnt = '1; + mgr_port_w = '0; + mgr_port_w_pnt = '1; end // Pop the AW request from the queues - if (slv_port_w_cnt == act_slv_aw.axi_len + 1) begin - void'(act_slv_port_aw_queue.pop_front()); - slv_port_w_cnt = 0; + if (sbr_port_w_cnt == act_sbr_aw.axi_len + 1) begin + void'(act_sbr_port_aw_queue.pop_front()); + sbr_port_w_cnt = 0; end - if (mst_port_w_cnt == act_mst_aw.axi_len + 1) begin - void'(act_mst_port_aw_queue.pop_front()); - mst_port_w_cnt = 0; + if (mgr_port_w_cnt == act_mgr_aw.axi_len + 1) begin + void'(act_mgr_port_aw_queue.pop_front()); + mgr_port_w_cnt = 0; end // Pop the W request - void'(act_slv_port_w_queue.pop_front()); + void'(act_sbr_port_w_queue.pop_front()); end end - endtask : mon_slv_port_w + endtask : mon_sbr_port_w - task automatic mon_slv_port_ar (); - exp_ax_t exp_slv_ar; - exp_b_t exp_mst_r; + task automatic mon_sbr_port_ar (); + exp_ax_t exp_sbr_ar; + exp_b_t exp_mgr_r; - if (slv_port_axi.ar_valid && slv_port_axi.ar_ready) begin + if (sbr_port_axi.ar_valid && sbr_port_axi.ar_ready) begin // Non-modifiable transaction - if (!axi_pkg::modifiable(slv_port_axi.ar_cache)) begin + if (!axi_pkg::modifiable(sbr_port_axi.ar_cache)) begin // We expect that the transaction will not be modified - exp_slv_ar = '{ - axi_id : slv_port_axi.ar_id , - axi_addr : slv_port_axi.ar_addr , - axi_len : slv_port_axi.ar_len , - axi_burst: slv_port_axi.ar_burst, - axi_size : slv_port_axi.ar_size , - axi_cache: slv_port_axi.ar_cache + exp_sbr_ar = '{ + axi_id : sbr_port_axi.ar_id , + axi_addr : sbr_port_axi.ar_addr , + axi_len : sbr_port_axi.ar_len , + axi_burst: sbr_port_axi.ar_burst, + axi_size : sbr_port_axi.ar_size , + axi_cache: sbr_port_axi.ar_cache }; end // Modifiable transaction else begin - case (slv_port_axi.ar_burst) + case (sbr_port_axi.ar_burst) // Passthrough upsize axi_pkg::BURST_FIXED: begin - exp_slv_ar = '{ - axi_id : slv_port_axi.ar_id , - axi_addr : slv_port_axi.ar_addr , - axi_len : slv_port_axi.ar_len , - axi_burst: slv_port_axi.ar_burst, - axi_size : slv_port_axi.ar_size , - axi_cache: slv_port_axi.ar_cache + exp_sbr_ar = '{ + axi_id : sbr_port_axi.ar_id , + axi_addr : sbr_port_axi.ar_addr , + axi_len : sbr_port_axi.ar_len , + axi_burst: sbr_port_axi.ar_burst, + axi_size : sbr_port_axi.ar_size , + axi_cache: sbr_port_axi.ar_cache }; end // INCR upsize axi_pkg::BURST_INCR: begin - automatic axi_addr_t aligned_start = axi_pkg::aligned_addr(slv_port_axi.ar_addr, MstPortMaxSize) ; - automatic axi_addr_t aligned_end = axi_pkg::aligned_addr(axi_pkg::aligned_addr(slv_port_axi.ar_addr, slv_port_axi.ar_size) + (unsigned'(slv_port_axi.ar_len) << slv_port_axi.ar_size), MstPortMaxSize); - - exp_slv_ar = '{ - axi_id : slv_port_axi.ar_id , - axi_addr : slv_port_axi.ar_addr , - axi_len : (aligned_end - aligned_start) >> MstPortMaxSize , - axi_burst: slv_port_axi.ar_burst , - axi_size : slv_port_axi.ar_len == 0 ? slv_port_axi.ar_size : MstPortMaxSize, - axi_cache: slv_port_axi.ar_cache + automatic axi_addr_t aligned_start = axi_pkg::aligned_addr(sbr_port_axi.ar_addr, MgrPortMaxSize) ; + automatic axi_addr_t aligned_end = axi_pkg::aligned_addr(axi_pkg::aligned_addr(sbr_port_axi.ar_addr, sbr_port_axi.ar_size) + (unsigned'(sbr_port_axi.ar_len) << sbr_port_axi.ar_size), MgrPortMaxSize); + + exp_sbr_ar = '{ + axi_id : sbr_port_axi.ar_id , + axi_addr : sbr_port_axi.ar_addr , + axi_len : (aligned_end - aligned_start) >> MgrPortMaxSize , + axi_burst: sbr_port_axi.ar_burst , + axi_size : sbr_port_axi.ar_len == 0 ? sbr_port_axi.ar_size : MgrPortMaxSize, + axi_cache: sbr_port_axi.ar_cache }; end // WRAP upsize axi_pkg::BURST_WRAP: begin - exp_slv_ar = '0; + exp_sbr_ar = '0; $warning("WRAP bursts are not supported."); end endcase - this.exp_mst_port_ar_queue.push(slv_port_axi.ar_id, exp_slv_ar); + this.exp_mgr_port_ar_queue.push(sbr_port_axi.ar_id, exp_sbr_ar); incr_expected_tests(6) ; - $display("%0tns > Master: AR with ID: %b", - $time, slv_port_axi.ar_id); + $display("%0tns > Manager: AR with ID: %b", + $time, sbr_port_axi.ar_id); end end - endtask : mon_slv_port_ar + endtask : mon_sbr_port_ar - task automatic mon_mst_port_r (); - if (mst_port_axi.r_valid && mst_port_axi.r_ready) begin + task automatic mon_mgr_port_r (); + if (mgr_port_axi.r_valid && mgr_port_axi.r_ready) begin // Retrieve the AR requests related to this R beat - exp_ax_t act_mst_ar = act_mst_port_ar_queue.get(mst_port_axi.r_id); - exp_ax_t act_slv_ar = act_slv_port_ar_queue.get(mst_port_axi.r_id); - axi_id_t id = mst_port_axi.r_id ; + exp_ax_t act_mgr_ar = act_mgr_port_ar_queue.get(mgr_port_axi.r_id); + exp_ax_t act_sbr_ar = act_sbr_port_ar_queue.get(mgr_port_axi.r_id); + axi_id_t id = mgr_port_axi.r_id ; // Calculate the offsets inside the incoming word - shortint unsigned mst_port_lower_byte = - axi_pkg::beat_lower_byte(act_mst_ar.axi_addr, act_mst_ar.axi_size, act_mst_ar.axi_len, act_mst_ar.axi_burst, MstPortStrbWidth, mst_port_r_cnt[id]); - shortint unsigned mst_port_upper_byte = - axi_pkg::beat_upper_byte(act_mst_ar.axi_addr, act_mst_ar.axi_size, act_mst_ar.axi_len, act_mst_ar.axi_burst, MstPortStrbWidth, mst_port_r_cnt[id]); + shortint unsigned mgr_port_lower_byte = + axi_pkg::beat_lower_byte(act_mgr_ar.axi_addr, act_mgr_ar.axi_size, act_mgr_ar.axi_len, act_mgr_ar.axi_burst, MgrPortStrbWidth, mgr_port_r_cnt[id]); + shortint unsigned mgr_port_upper_byte = + axi_pkg::beat_upper_byte(act_mgr_ar.axi_addr, act_mgr_ar.axi_size, act_mgr_ar.axi_len, act_mgr_ar.axi_burst, MgrPortStrbWidth, mgr_port_r_cnt[id]); // Pointer inside the incoming word - shortint unsigned mst_port_data_pointer = mst_port_lower_byte; + shortint unsigned mgr_port_data_pointer = mgr_port_lower_byte; // Conversion ratio. How many R beats are generated from this incoming R beat. - int unsigned conversion_ratio = axi_pkg::modifiable(act_mst_ar.axi_cache) ? conv_ratio(act_mst_ar.axi_size, act_slv_ar.axi_size) : 1; + int unsigned conversion_ratio = axi_pkg::modifiable(act_mgr_ar.axi_cache) ? conv_ratio(act_mgr_ar.axi_size, act_sbr_ar.axi_size) : 1; // Several R beats generated from this incoming R beat for (int unsigned beat = 0; beat < conversion_ratio; beat++) begin - exp_slv_rw_t act_slv_r = '0; + exp_sbr_rw_t act_sbr_r = '0; // Calculate the offsets inside the outcoming word - shortint unsigned slv_port_lower_byte = - axi_pkg::beat_lower_byte(act_slv_ar.axi_addr, act_slv_ar.axi_size, act_slv_ar.axi_len, act_slv_ar.axi_burst, SlvPortStrbWidth, slv_port_r_cnt[id]); - shortint unsigned slv_port_upper_byte = - axi_pkg::beat_upper_byte(act_slv_ar.axi_addr, act_slv_ar.axi_size, act_slv_ar.axi_len, act_slv_ar.axi_burst, SlvPortStrbWidth, slv_port_r_cnt[id]); + shortint unsigned sbr_port_lower_byte = + axi_pkg::beat_lower_byte(act_sbr_ar.axi_addr, act_sbr_ar.axi_size, act_sbr_ar.axi_len, act_sbr_ar.axi_burst, SbrPortStrbWidth, sbr_port_r_cnt[id]); + shortint unsigned sbr_port_upper_byte = + axi_pkg::beat_upper_byte(act_sbr_ar.axi_addr, act_sbr_ar.axi_size, act_sbr_ar.axi_len, act_sbr_ar.axi_burst, SbrPortStrbWidth, sbr_port_r_cnt[id]); shortint unsigned bytes_copied = 0; - act_slv_r.axi_id = mst_port_axi.r_id ; - act_slv_r.axi_last = slv_port_r_cnt[id] == act_slv_ar.axi_len; - act_slv_r.axi_data = {SlvPortDataWidth{1'b?}} ; - act_slv_r.axi_strb = {SlvPortStrbWidth{1'b?}} ; - for (shortint unsigned b = mst_port_data_pointer; b <= mst_port_upper_byte; b++) begin - act_slv_r.axi_data[8*(b + slv_port_lower_byte - mst_port_data_pointer) +: 8] = mst_port_axi.r_data[8*b +: 8]; + act_sbr_r.axi_id = mgr_port_axi.r_id ; + act_sbr_r.axi_last = sbr_port_r_cnt[id] == act_sbr_ar.axi_len; + act_sbr_r.axi_data = {SbrPortDataWidth{1'b?}} ; + act_sbr_r.axi_strb = {SbrPortStrbWidth{1'b?}} ; + for (shortint unsigned b = mgr_port_data_pointer; b <= mgr_port_upper_byte; b++) begin + act_sbr_r.axi_data[8*(b + sbr_port_lower_byte - mgr_port_data_pointer) +: 8] = mgr_port_axi.r_data[8*b +: 8]; bytes_copied++; - if (b + slv_port_lower_byte - mst_port_data_pointer == slv_port_upper_byte) + if (b + sbr_port_lower_byte - mgr_port_data_pointer == sbr_port_upper_byte) break; end - this.exp_slv_port_r_queue.push(act_slv_r.axi_id, act_slv_r); + this.exp_sbr_port_r_queue.push(act_sbr_r.axi_id, act_sbr_r); incr_expected_tests(3) ; // Increment the len counters - slv_port_r_cnt[id]++ ; - mst_port_data_pointer += bytes_copied; + sbr_port_r_cnt[id]++ ; + mgr_port_data_pointer += bytes_copied; // Used the whole R beat - if (mst_port_data_pointer == MstPortStrbWidth) + if (mgr_port_data_pointer == MgrPortStrbWidth) break; // Finished the R beat - if (act_slv_r.axi_last) + if (act_sbr_r.axi_last) break; end // Increment the len counter - mst_port_r_cnt[id]++; + mgr_port_r_cnt[id]++; // Pop the AR request from the queues - if (mst_port_r_cnt[id] == act_mst_ar.axi_len + 1) begin - void'(act_mst_port_ar_queue.pop_id(act_mst_ar.axi_id)); - mst_port_r_cnt[id] = 0; + if (mgr_port_r_cnt[id] == act_mgr_ar.axi_len + 1) begin + void'(act_mgr_port_ar_queue.pop_id(act_mgr_ar.axi_id)); + mgr_port_r_cnt[id] = 0; end - if (slv_port_r_cnt[id] == act_slv_ar.axi_len + 1) begin - void'(act_slv_port_ar_queue.pop_id(act_slv_ar.axi_id)); - slv_port_r_cnt[id] = 0; + if (sbr_port_r_cnt[id] == act_sbr_ar.axi_len + 1) begin + void'(act_sbr_port_ar_queue.pop_id(act_sbr_ar.axi_id)); + sbr_port_r_cnt[id] = 0; end end - endtask: mon_mst_port_r + endtask: mon_mgr_port_r endclass : axi_dw_upsizer_monitor /*************** @@ -904,27 +904,27 @@ package tb_axi_dw_pkg ; class axi_dw_downsizer_monitor #( parameter int unsigned AddrWidth , - parameter int unsigned SlvPortDataWidth, - parameter int unsigned MstPortDataWidth, + parameter int unsigned SbrPortDataWidth, + parameter int unsigned MgrPortDataWidth, parameter int unsigned IdWidth , parameter int unsigned UserWidth , // Stimuli application and test time parameter time TimeTest ) extends axi_dw_monitor #( .AddrWidth (AddrWidth ), - .SlvPortDataWidth(SlvPortDataWidth), - .MstPortDataWidth(MstPortDataWidth), + .SbrPortDataWidth(SbrPortDataWidth), + .MgrPortDataWidth(MgrPortDataWidth), .IdWidth (IdWidth ), .UserWidth (UserWidth ), .TimeTest (TimeTest ) ); - local static shortint unsigned slv_port_r_cnt[axi_id_t]; - local static shortint unsigned mst_port_r_cnt[axi_id_t]; - local static exp_slv_rw_t slv_port_r[axi_id_t]; - local static shortint unsigned slv_port_r_pnt[axi_id_t]; - local static shortint unsigned slv_port_w_cnt; - local static shortint unsigned mst_port_w_cnt; + local static shortint unsigned sbr_port_r_cnt[axi_id_t]; + local static shortint unsigned mgr_port_r_cnt[axi_id_t]; + local static exp_sbr_rw_t sbr_port_r[axi_id_t]; + local static shortint unsigned sbr_port_r_pnt[axi_id_t]; + local static shortint unsigned sbr_port_w_cnt; + local static shortint unsigned mgr_port_w_cnt; /********************** * Helper functions * @@ -935,7 +935,7 @@ package tb_axi_dw_pkg ; * due to an unaligned memory address. */ function automatic len_t aligned_adjustment(axi_addr_t addr, axi_pkg::size_t size) ; - return (addr & size_mask(size) & ~size_mask(MstPortMaxSize))/axi_pkg::num_bytes(MstPortMaxSize); + return (addr & size_mask(size) & ~size_mask(MgrPortMaxSize))/axi_pkg::num_bytes(MgrPortMaxSize); endfunction: aligned_adjustment /***************** @@ -945,27 +945,27 @@ package tb_axi_dw_pkg ; function new ( virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AddrWidth ), - .AXI_DATA_WIDTH(SlvPortDataWidth), + .AXI_DATA_WIDTH(SbrPortDataWidth), .AXI_ID_WIDTH (IdWidth ), .AXI_USER_WIDTH(UserWidth ) - ) slv_port_vif, + ) sbr_port_vif, virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AddrWidth ), - .AXI_DATA_WIDTH(MstPortDataWidth), + .AXI_DATA_WIDTH(MgrPortDataWidth), .AXI_ID_WIDTH (IdWidth ), .AXI_USER_WIDTH(UserWidth ) - ) mst_port_vif + ) mgr_port_vif ); begin - super.new(slv_port_vif, mst_port_vif); + super.new(sbr_port_vif, mgr_port_vif); - slv_port_w_cnt = 0; - mst_port_w_cnt = 0; + sbr_port_w_cnt = 0; + mgr_port_w_cnt = 0; for (int unsigned id = 0; id < 2**IdWidth; id++) begin - slv_port_r_cnt[id] = '0; - mst_port_r_cnt[id] = '0; - slv_port_r[id] = '0; - slv_port_r_pnt[id] = '1; + sbr_port_r_cnt[id] = '0; + mgr_port_r_cnt[id] = '0; + sbr_port_r[id] = '0; + sbr_port_r_pnt[id] = '1; end end endfunction @@ -974,41 +974,41 @@ package tb_axi_dw_pkg ; * Monitors * **************/ - task automatic mon_slv_port_aw (); + task automatic mon_sbr_port_aw (); exp_ax_t exp_aw; - if (slv_port_axi.aw_valid && slv_port_axi.aw_ready) begin - case (slv_port_axi.aw_burst) + if (sbr_port_axi.aw_valid && sbr_port_axi.aw_ready) begin + case (sbr_port_axi.aw_burst) axi_pkg::BURST_INCR: begin // Transaction unchanged - if (conv_ratio(slv_port_axi.aw_size, MstPortMaxSize) == 1) begin + if (conv_ratio(sbr_port_axi.aw_size, MgrPortMaxSize) == 1) begin exp_aw = '{ - axi_id : slv_port_axi.aw_id , - axi_addr : slv_port_axi.aw_addr , - axi_len : slv_port_axi.aw_len , - axi_burst: slv_port_axi.aw_burst, - axi_size : slv_port_axi.aw_size , - axi_cache: slv_port_axi.aw_cache + axi_id : sbr_port_axi.aw_id , + axi_addr : sbr_port_axi.aw_addr , + axi_len : sbr_port_axi.aw_len , + axi_burst: sbr_port_axi.aw_burst, + axi_size : sbr_port_axi.aw_size , + axi_cache: sbr_port_axi.aw_cache }; - this.exp_mst_port_aw_queue.push(slv_port_axi.aw_id, exp_aw); + this.exp_mgr_port_aw_queue.push(sbr_port_axi.aw_id, exp_aw); incr_expected_tests(6) ; end // INCR downsize else begin - automatic int unsigned num_beats = (slv_port_axi.aw_len + 1) * conv_ratio(slv_port_axi.aw_size, MstPortMaxSize) - aligned_adjustment(slv_port_axi.aw_addr, slv_port_axi.aw_size); + automatic int unsigned num_beats = (sbr_port_axi.aw_len + 1) * conv_ratio(sbr_port_axi.aw_size, MgrPortMaxSize) - aligned_adjustment(sbr_port_axi.aw_addr, sbr_port_axi.aw_size); // One burst if (num_beats <= 256) begin exp_aw = '{ - axi_id : slv_port_axi.aw_id , - axi_addr : slv_port_axi.aw_addr , + axi_id : sbr_port_axi.aw_id , + axi_addr : sbr_port_axi.aw_addr , axi_len : num_beats - 1 , - axi_burst: slv_port_axi.aw_burst, - axi_size : MstPortMaxSize , - axi_cache: slv_port_axi.aw_cache + axi_burst: sbr_port_axi.aw_burst, + axi_size : MgrPortMaxSize , + axi_cache: sbr_port_axi.aw_cache }; - this.exp_mst_port_aw_queue.push(slv_port_axi.aw_id, exp_aw); + this.exp_mgr_port_aw_queue.push(sbr_port_axi.aw_id, exp_aw); incr_expected_tests(6) ; end // Need to split the incoming burst into several INCR bursts @@ -1017,36 +1017,36 @@ package tb_axi_dw_pkg ; automatic len_t burst_len ; // First burst is a "partial" burst - burst_len = 255 - aligned_adjustment(slv_port_axi.aw_addr, slv_port_axi.aw_size); + burst_len = 255 - aligned_adjustment(sbr_port_axi.aw_addr, sbr_port_axi.aw_size); exp_aw = '{ - axi_id : slv_port_axi.aw_id , - axi_addr : slv_port_axi.aw_addr , + axi_id : sbr_port_axi.aw_id , + axi_addr : sbr_port_axi.aw_addr , axi_len : burst_len , - axi_burst: slv_port_axi.aw_burst, - axi_size : MstPortMaxSize , - axi_cache: slv_port_axi.aw_cache + axi_burst: sbr_port_axi.aw_burst, + axi_size : MgrPortMaxSize , + axi_cache: sbr_port_axi.aw_cache } ; - this.exp_mst_port_aw_queue.push(slv_port_axi.aw_id, exp_aw); + this.exp_mgr_port_aw_queue.push(sbr_port_axi.aw_id, exp_aw); incr_expected_tests(6) ; // Push the other bursts in a loop num_beats = num_beats - burst_len - 1 ; - burst_addr = axi_pkg::beat_addr(axi_pkg::aligned_addr(slv_port_axi.aw_addr, MstPortMaxSize), MstPortMaxSize, burst_len, axi_pkg::BURST_INCR, burst_len+1); + burst_addr = axi_pkg::beat_addr(axi_pkg::aligned_addr(sbr_port_axi.aw_addr, MgrPortMaxSize), MgrPortMaxSize, burst_len, axi_pkg::BURST_INCR, burst_len+1); while (num_beats != 0) begin burst_len = num_beats >= 256 ? 255 : num_beats - 1; exp_aw = '{ - axi_id : slv_port_axi.aw_id , + axi_id : sbr_port_axi.aw_id , axi_addr : burst_addr , axi_len : burst_len , - axi_burst: slv_port_axi.aw_burst, - axi_size : MstPortMaxSize , - axi_cache: slv_port_axi.aw_cache + axi_burst: sbr_port_axi.aw_burst, + axi_size : MgrPortMaxSize , + axi_cache: sbr_port_axi.aw_cache } ; - this.exp_mst_port_aw_queue.push(slv_port_axi.aw_id, exp_aw); + this.exp_mgr_port_aw_queue.push(sbr_port_axi.aw_id, exp_aw); incr_expected_tests(6) ; num_beats = num_beats - burst_len - 1 ; - burst_addr = axi_pkg::beat_addr(burst_addr, MstPortMaxSize, burst_len, axi_pkg::BURST_INCR, burst_len+1); + burst_addr = axi_pkg::beat_addr(burst_addr, MgrPortMaxSize, burst_len, axi_pkg::BURST_INCR, burst_len+1); end; end end @@ -1054,33 +1054,33 @@ package tb_axi_dw_pkg ; // Passthrough downsize axi_pkg::BURST_FIXED: begin // Transaction unchanged - if (conv_ratio(slv_port_axi.aw_size, MstPortMaxSize) == 1) begin + if (conv_ratio(sbr_port_axi.aw_size, MgrPortMaxSize) == 1) begin exp_aw = '{ - axi_id : slv_port_axi.aw_id , - axi_addr : slv_port_axi.aw_addr , - axi_len : slv_port_axi.aw_len , - axi_burst: slv_port_axi.aw_burst, - axi_size : slv_port_axi.aw_size , - axi_cache: slv_port_axi.aw_cache + axi_id : sbr_port_axi.aw_id , + axi_addr : sbr_port_axi.aw_addr , + axi_len : sbr_port_axi.aw_len , + axi_burst: sbr_port_axi.aw_burst, + axi_size : sbr_port_axi.aw_size , + axi_cache: sbr_port_axi.aw_cache }; - this.exp_mst_port_aw_queue.push(slv_port_axi.aw_id, exp_aw); + this.exp_mgr_port_aw_queue.push(sbr_port_axi.aw_id, exp_aw); incr_expected_tests(6) ; end - // Split into master_axi.aw_len + 1 INCR bursts + // Split into manager_axi.aw_len + 1 INCR bursts else begin - for (int unsigned j = 0; j <= slv_port_axi.aw_len; j++) begin - exp_aw.axi_id = slv_port_axi.aw_id ; - exp_aw.axi_addr = slv_port_axi.aw_addr ; + for (int unsigned j = 0; j <= sbr_port_axi.aw_len; j++) begin + exp_aw.axi_id = sbr_port_axi.aw_id ; + exp_aw.axi_addr = sbr_port_axi.aw_addr ; exp_aw.axi_burst = axi_pkg::BURST_INCR ; - exp_aw.axi_size = MstPortMaxSize ; - exp_aw.axi_cache = slv_port_axi.aw_cache; - if (conv_ratio(slv_port_axi.aw_size, MstPortMaxSize) >= aligned_adjustment(slv_port_axi.aw_addr, slv_port_axi.aw_size) + 1) - exp_aw.axi_len = conv_ratio(slv_port_axi.aw_size, MstPortMaxSize) - aligned_adjustment(slv_port_axi.aw_addr, slv_port_axi.aw_size) - 1; + exp_aw.axi_size = MgrPortMaxSize ; + exp_aw.axi_cache = sbr_port_axi.aw_cache; + if (conv_ratio(sbr_port_axi.aw_size, MgrPortMaxSize) >= aligned_adjustment(sbr_port_axi.aw_addr, sbr_port_axi.aw_size) + 1) + exp_aw.axi_len = conv_ratio(sbr_port_axi.aw_size, MgrPortMaxSize) - aligned_adjustment(sbr_port_axi.aw_addr, sbr_port_axi.aw_size) - 1; else exp_aw.axi_len = 0; - this.exp_mst_port_aw_queue.push(slv_port_axi.aw_id, exp_aw); + this.exp_mgr_port_aw_queue.push(sbr_port_axi.aw_id, exp_aw); incr_expected_tests(6) ; end end @@ -1092,133 +1092,133 @@ package tb_axi_dw_pkg ; end endcase - $display("%0tns > Master: AW with ID: %b", - $time, slv_port_axi.aw_id); + $display("%0tns > Manager: AW with ID: %b", + $time, sbr_port_axi.aw_id); // Populate the expected B queue - this.exp_slv_port_b_queue.push(slv_port_axi.aw_id, '{ - axi_id : slv_port_axi.aw_id, + this.exp_sbr_port_b_queue.push(sbr_port_axi.aw_id, '{ + axi_id : sbr_port_axi.aw_id, axi_last: 1'b1 }) ; incr_expected_tests(1) ; $display(" Expect B response."); end - endtask : mon_slv_port_aw + endtask : mon_sbr_port_aw - task automatic mon_slv_port_w (); - if (act_slv_port_w_queue.size() != 0) begin - exp_slv_rw_t act_slv_w = act_slv_port_w_queue[0]; + task automatic mon_sbr_port_w (); + if (act_sbr_port_w_queue.size() != 0) begin + exp_sbr_rw_t act_sbr_w = act_sbr_port_w_queue[0]; - if (act_mst_port_aw_queue.size() != 0 && act_slv_port_aw_queue.size() != 0) begin + if (act_mgr_port_aw_queue.size() != 0 && act_sbr_port_aw_queue.size() != 0) begin // Retrieve the AW requests related to this W beat - exp_ax_t act_mst_aw = act_mst_port_aw_queue[0]; - exp_ax_t act_slv_aw = act_slv_port_aw_queue[0]; + exp_ax_t act_mgr_aw = act_mgr_port_aw_queue[0]; + exp_ax_t act_sbr_aw = act_sbr_port_aw_queue[0]; // Address of the current beat - axi_addr_t slv_aw_addr = axi_pkg::beat_addr(act_slv_aw.axi_addr, act_slv_aw.axi_size, act_slv_aw.axi_len, act_slv_aw.axi_burst, slv_port_w_cnt); + axi_addr_t sbr_aw_addr = axi_pkg::beat_addr(act_sbr_aw.axi_addr, act_sbr_aw.axi_size, act_sbr_aw.axi_len, act_sbr_aw.axi_burst, sbr_port_w_cnt); // Calculate the offsets inside the incoming word - shortint unsigned slv_port_lower_byte = - axi_pkg::beat_lower_byte(act_slv_aw.axi_addr, act_slv_aw.axi_size, act_slv_aw.axi_len, act_slv_aw.axi_burst, SlvPortStrbWidth, slv_port_w_cnt); + shortint unsigned sbr_port_lower_byte = + axi_pkg::beat_lower_byte(act_sbr_aw.axi_addr, act_sbr_aw.axi_size, act_sbr_aw.axi_len, act_sbr_aw.axi_burst, SbrPortStrbWidth, sbr_port_w_cnt); // Pointer inside the incoming word - shortint unsigned slv_port_data_pointer = slv_port_lower_byte; + shortint unsigned sbr_port_data_pointer = sbr_port_lower_byte; // Several W beats generated from this incoming W beat - int unsigned beat_cnt = conv_ratio(act_slv_aw.axi_size, MstPortMaxSize) - aligned_adjustment(slv_aw_addr, act_slv_aw.axi_size); + int unsigned beat_cnt = conv_ratio(act_sbr_aw.axi_size, MgrPortMaxSize) - aligned_adjustment(sbr_aw_addr, act_sbr_aw.axi_size); for (int unsigned beat = 0; beat < beat_cnt; beat++) begin - exp_mst_rw_t act_mst_w = '0; + exp_mgr_rw_t act_mgr_w = '0; // Calculate the offsets inside the outcoming word - shortint unsigned mst_port_lower_byte = - axi_pkg::beat_lower_byte(act_mst_aw.axi_addr, act_mst_aw.axi_size, act_mst_aw.axi_len, act_mst_aw.axi_burst, MstPortStrbWidth, mst_port_w_cnt); - shortint unsigned mst_port_upper_byte = - axi_pkg::beat_upper_byte(act_mst_aw.axi_addr, act_mst_aw.axi_size, act_mst_aw.axi_len, act_mst_aw.axi_burst, MstPortStrbWidth, mst_port_w_cnt); + shortint unsigned mgr_port_lower_byte = + axi_pkg::beat_lower_byte(act_mgr_aw.axi_addr, act_mgr_aw.axi_size, act_mgr_aw.axi_len, act_mgr_aw.axi_burst, MgrPortStrbWidth, mgr_port_w_cnt); + shortint unsigned mgr_port_upper_byte = + axi_pkg::beat_upper_byte(act_mgr_aw.axi_addr, act_mgr_aw.axi_size, act_mgr_aw.axi_len, act_mgr_aw.axi_burst, MgrPortStrbWidth, mgr_port_w_cnt); shortint unsigned bytes_copied = 0; - act_mst_w.axi_id = act_mst_aw.axi_id ; - act_mst_w.axi_last = mst_port_w_cnt == act_mst_aw.axi_len; - act_mst_w.axi_data = '0 ; - for (shortint unsigned b = slv_port_data_pointer; b < SlvPortStrbWidth; b++) begin - if (b + mst_port_lower_byte - slv_port_data_pointer == MstPortStrbWidth) + act_mgr_w.axi_id = act_mgr_aw.axi_id ; + act_mgr_w.axi_last = mgr_port_w_cnt == act_mgr_aw.axi_len; + act_mgr_w.axi_data = '0 ; + for (shortint unsigned b = sbr_port_data_pointer; b < SbrPortStrbWidth; b++) begin + if (b + mgr_port_lower_byte - sbr_port_data_pointer == MgrPortStrbWidth) break; - act_mst_w.axi_data[8*(b + mst_port_lower_byte - slv_port_data_pointer) +: 8] = act_slv_w.axi_data[8*b +: 8]; - act_mst_w.axi_strb[b + mst_port_lower_byte - slv_port_data_pointer] = act_slv_w.axi_strb[b] ; + act_mgr_w.axi_data[8*(b + mgr_port_lower_byte - sbr_port_data_pointer) +: 8] = act_sbr_w.axi_data[8*b +: 8]; + act_mgr_w.axi_strb[b + mgr_port_lower_byte - sbr_port_data_pointer] = act_sbr_w.axi_strb[b] ; bytes_copied++; end // Don't care for the bits outside these accessed by this request - for (int unsigned b = 0; b < MstPortStrbWidth; b++) - if (!(mst_port_lower_byte <= b && b <= mst_port_upper_byte)) - act_mst_w.axi_data[8*b +: 8] = {8{1'b?}}; + for (int unsigned b = 0; b < MgrPortStrbWidth; b++) + if (!(mgr_port_lower_byte <= b && b <= mgr_port_upper_byte)) + act_mgr_w.axi_data[8*b +: 8] = {8{1'b?}}; - this.exp_mst_port_w_queue.push_back(act_mst_w); + this.exp_mgr_port_w_queue.push_back(act_mgr_w); incr_expected_tests(3) ; // Increment the len counters - mst_port_w_cnt++ ; - slv_port_data_pointer += bytes_copied; + mgr_port_w_cnt++ ; + sbr_port_data_pointer += bytes_copied; // Used the whole W beat - if (slv_port_data_pointer == SlvPortStrbWidth) + if (sbr_port_data_pointer == SbrPortStrbWidth) break; end // Increment the len counter - slv_port_w_cnt++; + sbr_port_w_cnt++; // Pop the AW request from the queues - if (slv_port_w_cnt == act_slv_aw.axi_len + 1) begin - void'(act_slv_port_aw_queue.pop_front()); - slv_port_w_cnt = 0; + if (sbr_port_w_cnt == act_sbr_aw.axi_len + 1) begin + void'(act_sbr_port_aw_queue.pop_front()); + sbr_port_w_cnt = 0; end - if (mst_port_w_cnt == act_mst_aw.axi_len + 1) begin - void'(act_mst_port_aw_queue.pop_front()); - mst_port_w_cnt = 0; + if (mgr_port_w_cnt == act_mgr_aw.axi_len + 1) begin + void'(act_mgr_port_aw_queue.pop_front()); + mgr_port_w_cnt = 0; end // Pop the W request - void'(act_slv_port_w_queue.pop_front()); + void'(act_sbr_port_w_queue.pop_front()); end end - endtask: mon_slv_port_w + endtask: mon_sbr_port_w - task automatic mon_slv_port_ar (); - exp_ax_t exp_slv_ar; - exp_b_t exp_mst_r; + task automatic mon_sbr_port_ar (); + exp_ax_t exp_sbr_ar; + exp_b_t exp_mgr_r; - if (slv_port_axi.ar_valid && slv_port_axi.ar_ready) begin - case (slv_port_axi.ar_burst) + if (sbr_port_axi.ar_valid && sbr_port_axi.ar_ready) begin + case (sbr_port_axi.ar_burst) axi_pkg::BURST_INCR: begin // Transaction unchanged - if (conv_ratio(slv_port_axi.ar_size, MstPortMaxSize) == 1) begin - exp_slv_ar = '{ - axi_id : slv_port_axi.ar_id , - axi_addr : slv_port_axi.ar_addr , - axi_len : slv_port_axi.ar_len , - axi_burst: slv_port_axi.ar_burst, - axi_size : slv_port_axi.ar_size , - axi_cache: slv_port_axi.ar_cache + if (conv_ratio(sbr_port_axi.ar_size, MgrPortMaxSize) == 1) begin + exp_sbr_ar = '{ + axi_id : sbr_port_axi.ar_id , + axi_addr : sbr_port_axi.ar_addr , + axi_len : sbr_port_axi.ar_len , + axi_burst: sbr_port_axi.ar_burst, + axi_size : sbr_port_axi.ar_size , + axi_cache: sbr_port_axi.ar_cache }; - this.exp_mst_port_ar_queue.push(slv_port_axi.ar_id, exp_slv_ar); + this.exp_mgr_port_ar_queue.push(sbr_port_axi.ar_id, exp_sbr_ar); incr_expected_tests(6) ; end // INCR downsize else begin - automatic int unsigned num_beats = (slv_port_axi.ar_len + 1) * conv_ratio(slv_port_axi.ar_size, MstPortMaxSize) - aligned_adjustment(slv_port_axi.ar_addr, slv_port_axi.ar_size); + automatic int unsigned num_beats = (sbr_port_axi.ar_len + 1) * conv_ratio(sbr_port_axi.ar_size, MgrPortMaxSize) - aligned_adjustment(sbr_port_axi.ar_addr, sbr_port_axi.ar_size); // One burst if (num_beats <= 256) begin - exp_slv_ar = '{ - axi_id : slv_port_axi.ar_id , - axi_addr : slv_port_axi.ar_addr , + exp_sbr_ar = '{ + axi_id : sbr_port_axi.ar_id , + axi_addr : sbr_port_axi.ar_addr , axi_len : num_beats - 1 , - axi_burst: slv_port_axi.ar_burst, - axi_size : MstPortMaxSize , - axi_cache: slv_port_axi.ar_cache + axi_burst: sbr_port_axi.ar_burst, + axi_size : MgrPortMaxSize , + axi_cache: sbr_port_axi.ar_cache }; - this.exp_mst_port_ar_queue.push(slv_port_axi.ar_id, exp_slv_ar); + this.exp_mgr_port_ar_queue.push(sbr_port_axi.ar_id, exp_sbr_ar); incr_expected_tests(6) ; end // Need to split the incoming burst into several INCR bursts @@ -1227,36 +1227,36 @@ package tb_axi_dw_pkg ; automatic len_t burst_len ; // First burst is a "partial" burst - burst_len = 255 - aligned_adjustment(slv_port_axi.ar_addr, slv_port_axi.ar_size); - exp_slv_ar = '{ - axi_id : slv_port_axi.ar_id , - axi_addr : slv_port_axi.ar_addr , + burst_len = 255 - aligned_adjustment(sbr_port_axi.ar_addr, sbr_port_axi.ar_size); + exp_sbr_ar = '{ + axi_id : sbr_port_axi.ar_id , + axi_addr : sbr_port_axi.ar_addr , axi_len : burst_len , - axi_burst: slv_port_axi.ar_burst, - axi_size : MstPortMaxSize , - axi_cache: slv_port_axi.ar_cache + axi_burst: sbr_port_axi.ar_burst, + axi_size : MgrPortMaxSize , + axi_cache: sbr_port_axi.ar_cache } ; - this.exp_mst_port_ar_queue.push(slv_port_axi.ar_id, exp_slv_ar); + this.exp_mgr_port_ar_queue.push(sbr_port_axi.ar_id, exp_sbr_ar); incr_expected_tests(6) ; // Push the other bursts in a loop num_beats = num_beats - burst_len - 1 ; - burst_addr = axi_pkg::beat_addr(axi_pkg::aligned_addr(slv_port_axi.ar_addr, MstPortMaxSize), MstPortMaxSize, burst_len, axi_pkg::BURST_INCR, burst_len+1); + burst_addr = axi_pkg::beat_addr(axi_pkg::aligned_addr(sbr_port_axi.ar_addr, MgrPortMaxSize), MgrPortMaxSize, burst_len, axi_pkg::BURST_INCR, burst_len+1); while (num_beats != 0) begin burst_len = num_beats >= 256 ? 255 : num_beats - 1; - exp_slv_ar = '{ - axi_id : slv_port_axi.ar_id , + exp_sbr_ar = '{ + axi_id : sbr_port_axi.ar_id , axi_addr : burst_addr , axi_len : burst_len , - axi_burst: slv_port_axi.ar_burst, - axi_size : MstPortMaxSize , - axi_cache: slv_port_axi.ar_cache + axi_burst: sbr_port_axi.ar_burst, + axi_size : MgrPortMaxSize , + axi_cache: sbr_port_axi.ar_cache } ; - this.exp_mst_port_ar_queue.push(slv_port_axi.ar_id, exp_slv_ar); + this.exp_mgr_port_ar_queue.push(sbr_port_axi.ar_id, exp_sbr_ar); incr_expected_tests(6) ; num_beats = num_beats - burst_len - 1 ; - burst_addr = axi_pkg::beat_addr(burst_addr, MstPortMaxSize, burst_len, axi_pkg::BURST_INCR, burst_len+1); + burst_addr = axi_pkg::beat_addr(burst_addr, MgrPortMaxSize, burst_len, axi_pkg::BURST_INCR, burst_len+1); end; end end @@ -1264,116 +1264,116 @@ package tb_axi_dw_pkg ; // Passthrough downsize axi_pkg::BURST_FIXED: begin // Transaction unchanged - if (conv_ratio(slv_port_axi.ar_size, MstPortMaxSize) == 1) begin - exp_slv_ar = '{ - axi_id : slv_port_axi.ar_id , - axi_addr : slv_port_axi.ar_addr , - axi_len : slv_port_axi.ar_len , - axi_burst: slv_port_axi.ar_burst, - axi_size : slv_port_axi.ar_size , - axi_cache: slv_port_axi.ar_cache + if (conv_ratio(sbr_port_axi.ar_size, MgrPortMaxSize) == 1) begin + exp_sbr_ar = '{ + axi_id : sbr_port_axi.ar_id , + axi_addr : sbr_port_axi.ar_addr , + axi_len : sbr_port_axi.ar_len , + axi_burst: sbr_port_axi.ar_burst, + axi_size : sbr_port_axi.ar_size , + axi_cache: sbr_port_axi.ar_cache }; - this.exp_mst_port_ar_queue.push(slv_port_axi.ar_id, exp_slv_ar); + this.exp_mgr_port_ar_queue.push(sbr_port_axi.ar_id, exp_sbr_ar); incr_expected_tests(6) ; end - // Split into master_axi.ar_len + 1 INCR bursts + // Split into manager_axi.ar_len + 1 INCR bursts else begin - for (int unsigned j = 0; j <= slv_port_axi.ar_len; j++) begin - exp_slv_ar.axi_id = slv_port_axi.ar_id ; - exp_slv_ar.axi_addr = slv_port_axi.ar_addr ; - exp_slv_ar.axi_burst = axi_pkg::BURST_INCR ; - exp_slv_ar.axi_size = MstPortMaxSize ; - exp_slv_ar.axi_cache = slv_port_axi.ar_cache; - if (conv_ratio(slv_port_axi.ar_size, MstPortMaxSize) >= aligned_adjustment(slv_port_axi.ar_addr, slv_port_axi.ar_size) + 1) - exp_slv_ar.axi_len = conv_ratio(slv_port_axi.ar_size, MstPortMaxSize) - aligned_adjustment(slv_port_axi.ar_addr, slv_port_axi.ar_size) - 1; + for (int unsigned j = 0; j <= sbr_port_axi.ar_len; j++) begin + exp_sbr_ar.axi_id = sbr_port_axi.ar_id ; + exp_sbr_ar.axi_addr = sbr_port_axi.ar_addr ; + exp_sbr_ar.axi_burst = axi_pkg::BURST_INCR ; + exp_sbr_ar.axi_size = MgrPortMaxSize ; + exp_sbr_ar.axi_cache = sbr_port_axi.ar_cache; + if (conv_ratio(sbr_port_axi.ar_size, MgrPortMaxSize) >= aligned_adjustment(sbr_port_axi.ar_addr, sbr_port_axi.ar_size) + 1) + exp_sbr_ar.axi_len = conv_ratio(sbr_port_axi.ar_size, MgrPortMaxSize) - aligned_adjustment(sbr_port_axi.ar_addr, sbr_port_axi.ar_size) - 1; else - exp_slv_ar.axi_len = 0; + exp_sbr_ar.axi_len = 0; - this.exp_mst_port_ar_queue.push(slv_port_axi.ar_id, exp_slv_ar); + this.exp_mgr_port_ar_queue.push(sbr_port_axi.ar_id, exp_sbr_ar); incr_expected_tests(6) ; end end end // WRAP downsize axi_pkg::BURST_WRAP: begin - exp_slv_ar = '0; + exp_sbr_ar = '0; $warning("WRAP bursts are not supported."); end endcase - $display("%0tns > Master: AR with ID: %b", - $time, slv_port_axi.ar_id); + $display("%0tns > Manager: AR with ID: %b", + $time, sbr_port_axi.ar_id); end - endtask : mon_slv_port_ar + endtask : mon_sbr_port_ar - virtual task automatic mon_mst_port_r(); - if (mst_port_axi.r_valid && mst_port_axi.r_ready) begin + virtual task automatic mon_mgr_port_r(); + if (mgr_port_axi.r_valid && mgr_port_axi.r_ready) begin // Retrieve the AR requests related to this R beat - exp_ax_t act_mst_ar = act_mst_port_ar_queue.get(mst_port_axi.r_id); - exp_ax_t act_slv_ar = act_slv_port_ar_queue.get(mst_port_axi.r_id); - axi_id_t id = mst_port_axi.r_id ; + exp_ax_t act_mgr_ar = act_mgr_port_ar_queue.get(mgr_port_axi.r_id); + exp_ax_t act_sbr_ar = act_sbr_port_ar_queue.get(mgr_port_axi.r_id); + axi_id_t id = mgr_port_axi.r_id ; // Calculate the offsets - shortint unsigned mst_port_lower_byte = - axi_pkg::beat_lower_byte(act_mst_ar.axi_addr, act_mst_ar.axi_size, act_mst_ar.axi_len, act_mst_ar.axi_burst, MstPortStrbWidth, mst_port_r_cnt[id]); - shortint unsigned mst_port_upper_byte = - axi_pkg::beat_upper_byte(act_mst_ar.axi_addr, act_mst_ar.axi_size, act_mst_ar.axi_len, act_mst_ar.axi_burst, MstPortStrbWidth, mst_port_r_cnt[id]); - shortint unsigned slv_port_lower_byte = - axi_pkg::beat_lower_byte(act_slv_ar.axi_addr, act_slv_ar.axi_size, act_slv_ar.axi_len, act_slv_ar.axi_burst, SlvPortStrbWidth, slv_port_r_cnt[id]); - shortint unsigned slv_port_upper_byte = - axi_pkg::beat_upper_byte(act_slv_ar.axi_addr, act_slv_ar.axi_size, act_slv_ar.axi_len, act_slv_ar.axi_burst, SlvPortStrbWidth, slv_port_r_cnt[id]); + shortint unsigned mgr_port_lower_byte = + axi_pkg::beat_lower_byte(act_mgr_ar.axi_addr, act_mgr_ar.axi_size, act_mgr_ar.axi_len, act_mgr_ar.axi_burst, MgrPortStrbWidth, mgr_port_r_cnt[id]); + shortint unsigned mgr_port_upper_byte = + axi_pkg::beat_upper_byte(act_mgr_ar.axi_addr, act_mgr_ar.axi_size, act_mgr_ar.axi_len, act_mgr_ar.axi_burst, MgrPortStrbWidth, mgr_port_r_cnt[id]); + shortint unsigned sbr_port_lower_byte = + axi_pkg::beat_lower_byte(act_sbr_ar.axi_addr, act_sbr_ar.axi_size, act_sbr_ar.axi_len, act_sbr_ar.axi_burst, SbrPortStrbWidth, sbr_port_r_cnt[id]); + shortint unsigned sbr_port_upper_byte = + axi_pkg::beat_upper_byte(act_sbr_ar.axi_addr, act_sbr_ar.axi_size, act_sbr_ar.axi_len, act_sbr_ar.axi_burst, SbrPortStrbWidth, sbr_port_r_cnt[id]); // Pointer inside the outcoming word shortint unsigned bytes_copied = 0; - if (slv_port_r_pnt[id] == '1) - slv_port_r_pnt[id] = slv_port_lower_byte; + if (sbr_port_r_pnt[id] == '1) + sbr_port_r_pnt[id] = sbr_port_lower_byte; - slv_port_r[id].axi_id = id ; - slv_port_r[id].axi_last = slv_port_r_cnt[id] == act_slv_ar.axi_len; - for (shortint unsigned b = mst_port_lower_byte; b <= mst_port_upper_byte; b++) begin - if (b + slv_port_r_pnt[id] - mst_port_lower_byte == SlvPortStrbWidth) + sbr_port_r[id].axi_id = id ; + sbr_port_r[id].axi_last = sbr_port_r_cnt[id] == act_sbr_ar.axi_len; + for (shortint unsigned b = mgr_port_lower_byte; b <= mgr_port_upper_byte; b++) begin + if (b + sbr_port_r_pnt[id] - mgr_port_lower_byte == SbrPortStrbWidth) break; - slv_port_r[id].axi_data[8*(b + slv_port_r_pnt[id] - mst_port_lower_byte) +: 8] = mst_port_axi.r_data[8*b +: 8]; + sbr_port_r[id].axi_data[8*(b + sbr_port_r_pnt[id] - mgr_port_lower_byte) +: 8] = mgr_port_axi.r_data[8*b +: 8]; bytes_copied++; end // Increment the len counters - mst_port_r_cnt[id]++ ; - slv_port_r_pnt[id] += bytes_copied; + mgr_port_r_cnt[id]++ ; + sbr_port_r_pnt[id] += bytes_copied; - if (slv_port_r_pnt[id] == slv_port_upper_byte + 1 // Used all bits from the incoming R beat - || slv_port_r_pnt[id] == SlvPortStrbWidth // Filled up an outcoming R beat - || conv_ratio(act_slv_ar.axi_size, act_mst_ar.axi_size) == 1 // Not downsizing - || mst_port_axi.r_last // Last beat of an R burst + if (sbr_port_r_pnt[id] == sbr_port_upper_byte + 1 // Used all bits from the incoming R beat + || sbr_port_r_pnt[id] == SbrPortStrbWidth // Filled up an outcoming R beat + || conv_ratio(act_sbr_ar.axi_size, act_mgr_ar.axi_size) == 1 // Not downsizing + || mgr_port_axi.r_last // Last beat of an R burst ) begin // Don't care for the bits outside these accessed by this request - for (int unsigned b = 0; b < SlvPortStrbWidth; b++) - if (!(slv_port_lower_byte <= b && b <= slv_port_upper_byte)) - slv_port_r[id].axi_data[8*b +: 8] = {8{1'b?}}; + for (int unsigned b = 0; b < SbrPortStrbWidth; b++) + if (!(sbr_port_lower_byte <= b && b <= sbr_port_upper_byte)) + sbr_port_r[id].axi_data[8*b +: 8] = {8{1'b?}}; - this.exp_slv_port_r_queue.push(id, slv_port_r[id]); + this.exp_sbr_port_r_queue.push(id, sbr_port_r[id]); incr_expected_tests(3) ; // Increment the len counter - slv_port_r_cnt[id]++; + sbr_port_r_cnt[id]++; // Reset R beat - slv_port_r[id] = '0; - slv_port_r_pnt[id] = '1; + sbr_port_r[id] = '0; + sbr_port_r_pnt[id] = '1; end // Pop the AW request from the queues - if (slv_port_r_cnt[id] == act_slv_ar.axi_len + 1) begin - void'(act_slv_port_ar_queue.pop_id(id)); - slv_port_r_cnt[id] = 0; + if (sbr_port_r_cnt[id] == act_sbr_ar.axi_len + 1) begin + void'(act_sbr_port_ar_queue.pop_id(id)); + sbr_port_r_cnt[id] = 0; end - if (mst_port_r_cnt[id] == act_mst_ar.axi_len + 1) begin - void'(act_mst_port_ar_queue.pop_id(id)); - mst_port_r_cnt[id] = 0; + if (mgr_port_r_cnt[id] == act_mgr_ar.axi_len + 1) begin + void'(act_mgr_port_ar_queue.pop_id(id)); + mgr_port_r_cnt[id] = 0; end end - endtask : mon_mst_port_r + endtask : mon_mgr_port_r endclass : axi_dw_downsizer_monitor endpackage: tb_axi_dw_pkg diff --git a/test/tb_axi_dw_upsizer.do b/test/tb_axi_dw_upsizer.do index 3090ee96d..39426e59a 100644 --- a/test/tb_axi_dw_upsizer.do +++ b/test/tb_axi_dw_upsizer.do @@ -1,4 +1,4 @@ add wave -position insertpoint \ - sim:/tb_axi_dw_upsizer/i_dw_converter/i_axi_dw_converter/gen_dw_upsize/i_axi_dw_upsizer/SlvPortDataWidth \ - sim:/tb_axi_dw_upsizer/i_dw_converter/i_axi_dw_converter/gen_dw_upsize/i_axi_dw_upsizer/MstPortDataWidth \ + sim:/tb_axi_dw_upsizer/i_dw_converter/i_axi_dw_converter/gen_dw_upsize/i_axi_dw_upsizer/SbrPortDataWidth \ + sim:/tb_axi_dw_upsizer/i_dw_converter/i_axi_dw_converter/gen_dw_upsize/i_axi_dw_upsizer/MgrPortDataWidth \ sim:/tb_axi_dw_upsizer/i_dw_converter/i_axi_dw_converter/gen_dw_upsize/i_axi_dw_upsizer/* diff --git a/test/tb_axi_dw_upsizer.sv b/test/tb_axi_dw_upsizer.sv index e42e9bef1..f423cda78 100644 --- a/test/tb_axi_dw_upsizer.sv +++ b/test/tb_axi_dw_upsizer.sv @@ -18,8 +18,8 @@ module tb_axi_dw_upsizer #( // AXI Parameters parameter int unsigned TbAddrWidth = 64 , parameter int unsigned TbIdWidth = 4 , - parameter int unsigned TbSlvPortDataWidth = 32 , - parameter int unsigned TbMstPortDataWidth = 64 , + parameter int unsigned TbSbrPortDataWidth = 32 , + parameter int unsigned TbMgrPortDataWidth = 64 , parameter int unsigned TbUserWidth = 8 , // TB Parameters parameter time TbCyclTime = 10ns, @@ -47,29 +47,29 @@ module tb_axi_dw_upsizer #( * AXI * *********/ - // Master port + // Manager port AXI_BUS_DV #( .AXI_ADDR_WIDTH(TbAddrWidth ), - .AXI_DATA_WIDTH(TbSlvPortDataWidth), + .AXI_DATA_WIDTH(TbSbrPortDataWidth), .AXI_ID_WIDTH (TbIdWidth ), .AXI_USER_WIDTH(TbUserWidth ) - ) master_dv ( + ) manager_dv ( .clk_i(clk) ); AXI_BUS #( .AXI_ADDR_WIDTH(TbAddrWidth ), - .AXI_DATA_WIDTH(TbSlvPortDataWidth), + .AXI_DATA_WIDTH(TbSbrPortDataWidth), .AXI_ID_WIDTH (TbIdWidth ), .AXI_USER_WIDTH(TbUserWidth ) - ) master (); + ) manager (); - `AXI_ASSIGN(master, master_dv) + `AXI_ASSIGN(manager, manager_dv) - axi_test::axi_rand_master #( + axi_test::axi_rand_manager #( .AW (TbAddrWidth ), - .DW (TbSlvPortDataWidth), + .DW (TbSbrPortDataWidth), .IW (TbIdWidth ), .UW (TbUserWidth ), .TA (TbApplTime ), @@ -77,36 +77,36 @@ module tb_axi_dw_upsizer #( .MAX_READ_TXNS (8 ), .MAX_WRITE_TXNS(8 ), .AXI_ATOPS (1'b1 ) - ) master_drv = new (master_dv); + ) manager_drv = new (manager_dv); - // Slave port + // Subordinate port AXI_BUS_DV #( .AXI_ADDR_WIDTH(TbAddrWidth ), - .AXI_DATA_WIDTH(TbMstPortDataWidth), + .AXI_DATA_WIDTH(TbMgrPortDataWidth), .AXI_ID_WIDTH (TbIdWidth ), .AXI_USER_WIDTH(TbUserWidth ) - ) slave_dv ( + ) subordinate_dv ( .clk_i(clk) ); AXI_BUS #( .AXI_ADDR_WIDTH(TbAddrWidth ), - .AXI_DATA_WIDTH(TbMstPortDataWidth), + .AXI_DATA_WIDTH(TbMgrPortDataWidth), .AXI_ID_WIDTH (TbIdWidth ), .AXI_USER_WIDTH(TbUserWidth ) - ) slave (); + ) subordinate (); - axi_test::axi_rand_slave #( + axi_test::axi_rand_subordinate #( .AW(TbAddrWidth ), - .DW(TbMstPortDataWidth), + .DW(TbMgrPortDataWidth), .IW(TbIdWidth ), .UW(TbUserWidth ), .TA(TbApplTime ), .TT(TbTestTime ) - ) slave_drv = new (slave_dv); + ) subordinate_drv = new (subordinate_dv); - `AXI_ASSIGN(slave_dv, slave) + `AXI_ASSIGN(subordinate_dv, subordinate) /********* * DUT * @@ -116,14 +116,14 @@ module tb_axi_dw_upsizer #( .AXI_MAX_READS (4 ), .AXI_ADDR_WIDTH (TbAddrWidth ), .AXI_ID_WIDTH (TbIdWidth ), - .AXI_SLV_PORT_DATA_WIDTH(TbSlvPortDataWidth), - .AXI_MST_PORT_DATA_WIDTH(TbMstPortDataWidth), + .AXI_SBR_PORT_DATA_WIDTH(TbSbrPortDataWidth), + .AXI_MGR_PORT_DATA_WIDTH(TbMgrPortDataWidth), .AXI_USER_WIDTH (TbUserWidth ) ) i_dw_converter ( .clk_i (clk ), .rst_ni(rst_n ), - .slv (master), - .mst (slave ) + .sbr (manager), + .mgr (subordinate ) ); /************* @@ -134,17 +134,17 @@ module tb_axi_dw_upsizer #( eos = 1'b0; // Configuration - slave_drv.reset() ; - master_drv.reset() ; - master_drv.add_memory_region({TbAddrWidth{1'b0}}, {TbAddrWidth{1'b1}}, axi_pkg::WTHRU_NOALLOCATE); + subordinate_drv.reset() ; + manager_drv.reset() ; + manager_drv.add_memory_region({TbAddrWidth{1'b0}}, {TbAddrWidth{1'b1}}, axi_pkg::WTHRU_NOALLOCATE); // Wait for the reset before sending requests @(posedge rst_n); fork // Act as a sink - slave_drv.run() ; - master_drv.run(200, 200); + subordinate_drv.run() ; + manager_drv.run(200, 200); join_any // Done @@ -159,12 +159,12 @@ module tb_axi_dw_upsizer #( initial begin : proc_monitor static tb_axi_dw_pkg::axi_dw_upsizer_monitor #( .AddrWidth (TbAddrWidth ), - .MstPortDataWidth(TbMstPortDataWidth), - .SlvPortDataWidth(TbSlvPortDataWidth), + .MgrPortDataWidth(TbMgrPortDataWidth), + .SbrPortDataWidth(TbSbrPortDataWidth), .IdWidth (TbIdWidth ), .UserWidth (TbUserWidth ), .TimeTest (TbTestTime ) - ) monitor = new (master_dv, slave_dv); + ) monitor = new (manager_dv, subordinate_dv); fork monitor.run(); forever begin diff --git a/test/tb_axi_fifo.sv b/test/tb_axi_fifo.sv index 8a4170fb9..031f7bca9 100644 --- a/test/tb_axi_fifo.sv +++ b/test/tb_axi_fifo.sv @@ -17,10 +17,10 @@ module tb_axi_fifo #( parameter int unsigned Depth = 16, parameter int unsigned FallThrough = 0, - parameter int unsigned NumWrites = 200, // How many writes per master - parameter int unsigned NumReads = 200 // How many reads per master + parameter int unsigned NumWrites = 200, // How many writes per manager + parameter int unsigned NumReads = 200 // How many reads per manager ); - // Random Master Atomics + // Random Manager Atomics localparam int unsigned MaxAW = 30; localparam int unsigned MaxAR = 30; localparam bit EnAtop = 1'b1; @@ -36,7 +36,7 @@ module tb_axi_fifo #( // Sim print config, how many transactions localparam int unsigned PrintTnx = 100; - typedef axi_test::axi_rand_master#( + typedef axi_test::axi_rand_manager#( // AXI interface parameters .AW (AddrWidth), .DW (DataWidth), @@ -49,8 +49,8 @@ module tb_axi_fifo #( .MAX_READ_TXNS (MaxAR), .MAX_WRITE_TXNS(MaxAW), .AXI_ATOPS (EnAtop) - ) axi_rand_master_t; - typedef axi_test::axi_rand_slave#( + ) axi_rand_manager_t; + typedef axi_test::axi_rand_subordinate#( // AXI interface parameters .AW(AddrWidth), .DW(DataWidth), @@ -59,7 +59,7 @@ module tb_axi_fifo #( // Stimuli application and test time .TA(ApplTime), .TT(TestTime) - ) axi_rand_slave_t; + ) axi_rand_subordinate_t; // ------------- // DUT signals @@ -75,17 +75,17 @@ module tb_axi_fifo #( .AXI_ID_WIDTH (IdWidth), .AXI_USER_WIDTH(UserWidth) ) - master (), slave (); + manager (), subordinate (); AXI_BUS_DV #( .AXI_ADDR_WIDTH(AddrWidth), .AXI_DATA_WIDTH(DataWidth), .AXI_ID_WIDTH (IdWidth), .AXI_USER_WIDTH(UserWidth) ) - master_dv (clk), slave_dv (clk); + manager_dv (clk), subordinate_dv (clk); - `AXI_ASSIGN(master, master_dv) - `AXI_ASSIGN(slave_dv, slave) + `AXI_ASSIGN(manager, manager_dv) + `AXI_ASSIGN(subordinate_dv, subordinate) //----------------------------------- // Clock generator @@ -112,29 +112,29 @@ module tb_axi_fifo #( .clk_i (clk), // clock .rst_ni(rst_n), // asynchronous reset active low .test_i(1'b0), - .slv (master), // slave port - .mst (slave) // master port + .sbr (manager), // subordinate port + .mgr (subordinate) // manager port ); - initial begin : proc_axi_master - automatic axi_rand_master_t axi_rand_master = new(master_dv); + initial begin : proc_axi_manager + automatic axi_rand_manager_t axi_rand_manager = new(manager_dv); end_of_sim <= 1'b0; - axi_rand_master.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE); - axi_rand_master.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE); - axi_rand_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); - axi_rand_master.reset(); + axi_rand_manager.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_manager.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE); + axi_rand_manager.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); + axi_rand_manager.reset(); @(posedge rst_n); - axi_rand_master.run(NumReads, NumWrites); + axi_rand_manager.run(NumReads, NumWrites); end_of_sim <= 1'b1; repeat (10000) @(posedge clk); $stop(); end - initial begin : proc_axi_slave - automatic axi_rand_slave_t axi_rand_slave = new(slave_dv); - axi_rand_slave.reset(); + initial begin : proc_axi_subordinate + automatic axi_rand_subordinate_t axi_rand_subordinate = new(subordinate_dv); + axi_rand_subordinate.reset(); @(posedge rst_n); - axi_rand_slave.run(); + axi_rand_subordinate.run(); end initial begin : proc_sim_progress @@ -148,10 +148,10 @@ module tb_axi_fifo #( forever begin @(posedge clk); #TestTime; - if (master.aw_valid && master.aw_ready) begin + if (manager.aw_valid && manager.aw_ready) begin aw++; end - if (master.ar_valid && master.ar_ready) begin + if (manager.ar_valid && manager.ar_ready) begin ar++; end @@ -180,19 +180,19 @@ module tb_axi_fifo #( default disable iff (!rst_n); aw_unstable : - assert property (@(posedge clk) (slave.aw_valid && !slave.aw_ready) |=> $stable(slave.aw_addr)) + assert property (@(posedge clk) (subordinate.aw_valid && !subordinate.aw_ready) |=> $stable(subordinate.aw_addr)) else $fatal(1, "AW is unstable."); w_unstable : - assert property (@(posedge clk) (slave.w_valid && !slave.w_ready) |=> $stable(slave.w_data)) + assert property (@(posedge clk) (subordinate.w_valid && !subordinate.w_ready) |=> $stable(subordinate.w_data)) else $fatal(1, "W is unstable."); b_unstable : - assert property (@(posedge clk) (master.b_valid && !master.b_ready) |=> $stable(master.b_resp)) + assert property (@(posedge clk) (manager.b_valid && !manager.b_ready) |=> $stable(manager.b_resp)) else $fatal(1, "B is unstable."); ar_unstable : - assert property (@(posedge clk) (slave.ar_valid && !slave.ar_ready) |=> $stable(slave.ar_addr)) + assert property (@(posedge clk) (subordinate.ar_valid && !subordinate.ar_ready) |=> $stable(subordinate.ar_addr)) else $fatal(1, "AR is unstable."); r_unstable : - assert property (@(posedge clk) (master.r_valid && !master.r_ready) |=> $stable(master.r_data)) + assert property (@(posedge clk) (manager.r_valid && !manager.r_ready) |=> $stable(manager.r_data)) else $fatal(1, "R is unstable."); diff --git a/test/tb_axi_fifo.wave.do b/test/tb_axi_fifo.wave.do index bdf1d9e20..d5155c412 100644 --- a/test/tb_axi_fifo.wave.do +++ b/test/tb_axi_fifo.wave.do @@ -2,98 +2,98 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -label Clock /tb_axi_fifo/i_dut/clk_i add wave -noupdate -label Reset /tb_axi_fifo/i_dut/rst_ni -add wave -noupdate -divider {Slave Ports} -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_id -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_addr -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_len -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_size -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_burst -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_lock -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_cache -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_prot -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_qos -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_region -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_atop -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_user -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_valid -add wave -noupdate -expand -group {Master AW} /tb_axi_fifo/master/aw_ready -add wave -noupdate -group {Master W} /tb_axi_fifo/master/w_data -add wave -noupdate -group {Master W} /tb_axi_fifo/master/w_strb -add wave -noupdate -group {Master W} /tb_axi_fifo/master/w_last -add wave -noupdate -group {Master W} /tb_axi_fifo/master/w_user -add wave -noupdate -group {Master W} /tb_axi_fifo/master/w_valid -add wave -noupdate -group {Master W} /tb_axi_fifo/master/w_ready -add wave -noupdate -group {Master B} /tb_axi_fifo/master/b_id -add wave -noupdate -group {Master B} /tb_axi_fifo/master/b_resp -add wave -noupdate -group {Master B} /tb_axi_fifo/master/b_user -add wave -noupdate -group {Master B} /tb_axi_fifo/master/b_valid -add wave -noupdate -group {Master B} /tb_axi_fifo/master/b_ready -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_id -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_addr -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_len -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_size -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_burst -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_lock -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_cache -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_prot -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_qos -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_region -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_user -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_valid -add wave -noupdate -expand -group {Master AR} /tb_axi_fifo/master/ar_ready -add wave -noupdate -group {Master R} /tb_axi_fifo/master/r_id -add wave -noupdate -group {Master R} /tb_axi_fifo/master/r_data -add wave -noupdate -group {Master R} /tb_axi_fifo/master/r_resp -add wave -noupdate -group {Master R} /tb_axi_fifo/master/r_last -add wave -noupdate -group {Master R} /tb_axi_fifo/master/r_user -add wave -noupdate -group {Master R} /tb_axi_fifo/master/r_valid -add wave -noupdate -group {Master R} /tb_axi_fifo/master/r_ready -add wave -noupdate -divider {Master Ports} -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_id -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_addr -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_len -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_size -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_burst -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_lock -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_cache -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_prot -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_qos -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_region -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_atop -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_user -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_valid -add wave -noupdate -expand -group {Slave AW} /tb_axi_fifo/slave/aw_ready -add wave -noupdate -group {Slave W} /tb_axi_fifo/slave/w_data -add wave -noupdate -group {Slave W} /tb_axi_fifo/slave/w_strb -add wave -noupdate -group {Slave W} /tb_axi_fifo/slave/w_last -add wave -noupdate -group {Slave W} /tb_axi_fifo/slave/w_user -add wave -noupdate -group {Slave W} /tb_axi_fifo/slave/w_valid -add wave -noupdate -group {Slave W} /tb_axi_fifo/slave/w_ready -add wave -noupdate -group {Slave B} /tb_axi_fifo/slave/b_id -add wave -noupdate -group {Slave B} /tb_axi_fifo/slave/b_resp -add wave -noupdate -group {Slave B} /tb_axi_fifo/slave/b_user -add wave -noupdate -group {Slave B} /tb_axi_fifo/slave/b_valid -add wave -noupdate -group {Slave B} /tb_axi_fifo/slave/b_ready -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_id -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_addr -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_len -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_size -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_burst -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_lock -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_cache -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_prot -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_qos -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_region -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_user -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_valid -add wave -noupdate -expand -group {Slave AR} /tb_axi_fifo/slave/ar_ready -add wave -noupdate -group {Slave R} /tb_axi_fifo/slave/r_id -add wave -noupdate -group {Slave R} /tb_axi_fifo/slave/r_data -add wave -noupdate -group {Slave R} /tb_axi_fifo/slave/r_resp -add wave -noupdate -group {Slave R} /tb_axi_fifo/slave/r_last -add wave -noupdate -group {Slave R} /tb_axi_fifo/slave/r_user -add wave -noupdate -group {Slave R} /tb_axi_fifo/slave/r_valid -add wave -noupdate -group {Slave R} /tb_axi_fifo/slave/r_ready +add wave -noupdate -divider {Subordinate Ports} +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_id +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_addr +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_len +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_size +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_burst +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_lock +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_cache +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_prot +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_qos +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_region +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_atop +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_user +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_valid +add wave -noupdate -expand -group {Manager AW} /tb_axi_fifo/manager/aw_ready +add wave -noupdate -group {Manager W} /tb_axi_fifo/manager/w_data +add wave -noupdate -group {Manager W} /tb_axi_fifo/manager/w_strb +add wave -noupdate -group {Manager W} /tb_axi_fifo/manager/w_last +add wave -noupdate -group {Manager W} /tb_axi_fifo/manager/w_user +add wave -noupdate -group {Manager W} /tb_axi_fifo/manager/w_valid +add wave -noupdate -group {Manager W} /tb_axi_fifo/manager/w_ready +add wave -noupdate -group {Manager B} /tb_axi_fifo/manager/b_id +add wave -noupdate -group {Manager B} /tb_axi_fifo/manager/b_resp +add wave -noupdate -group {Manager B} /tb_axi_fifo/manager/b_user +add wave -noupdate -group {Manager B} /tb_axi_fifo/manager/b_valid +add wave -noupdate -group {Manager B} /tb_axi_fifo/manager/b_ready +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_id +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_addr +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_len +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_size +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_burst +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_lock +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_cache +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_prot +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_qos +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_region +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_user +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_valid +add wave -noupdate -expand -group {Manager AR} /tb_axi_fifo/manager/ar_ready +add wave -noupdate -group {Manager R} /tb_axi_fifo/manager/r_id +add wave -noupdate -group {Manager R} /tb_axi_fifo/manager/r_data +add wave -noupdate -group {Manager R} /tb_axi_fifo/manager/r_resp +add wave -noupdate -group {Manager R} /tb_axi_fifo/manager/r_last +add wave -noupdate -group {Manager R} /tb_axi_fifo/manager/r_user +add wave -noupdate -group {Manager R} /tb_axi_fifo/manager/r_valid +add wave -noupdate -group {Manager R} /tb_axi_fifo/manager/r_ready +add wave -noupdate -divider {Manager Ports} +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_id +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_addr +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_len +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_size +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_burst +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_lock +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_cache +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_prot +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_qos +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_region +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_atop +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_user +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_valid +add wave -noupdate -expand -group {Subordinate AW} /tb_axi_fifo/subordinate/aw_ready +add wave -noupdate -group {Subordinate W} /tb_axi_fifo/subordinate/w_data +add wave -noupdate -group {Subordinate W} /tb_axi_fifo/subordinate/w_strb +add wave -noupdate -group {Subordinate W} /tb_axi_fifo/subordinate/w_last +add wave -noupdate -group {Subordinate W} /tb_axi_fifo/subordinate/w_user +add wave -noupdate -group {Subordinate W} /tb_axi_fifo/subordinate/w_valid +add wave -noupdate -group {Subordinate W} /tb_axi_fifo/subordinate/w_ready +add wave -noupdate -group {Subordinate B} /tb_axi_fifo/subordinate/b_id +add wave -noupdate -group {Subordinate B} /tb_axi_fifo/subordinate/b_resp +add wave -noupdate -group {Subordinate B} /tb_axi_fifo/subordinate/b_user +add wave -noupdate -group {Subordinate B} /tb_axi_fifo/subordinate/b_valid +add wave -noupdate -group {Subordinate B} /tb_axi_fifo/subordinate/b_ready +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_id +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_addr +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_len +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_size +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_burst +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_lock +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_cache +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_prot +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_qos +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_region +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_user +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_valid +add wave -noupdate -expand -group {Subordinate AR} /tb_axi_fifo/subordinate/ar_ready +add wave -noupdate -group {Subordinate R} /tb_axi_fifo/subordinate/r_id +add wave -noupdate -group {Subordinate R} /tb_axi_fifo/subordinate/r_data +add wave -noupdate -group {Subordinate R} /tb_axi_fifo/subordinate/r_resp +add wave -noupdate -group {Subordinate R} /tb_axi_fifo/subordinate/r_last +add wave -noupdate -group {Subordinate R} /tb_axi_fifo/subordinate/r_user +add wave -noupdate -group {Subordinate R} /tb_axi_fifo/subordinate/r_valid +add wave -noupdate -group {Subordinate R} /tb_axi_fifo/subordinate/r_ready add wave -noupdate -divider Custom add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/clk_i add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/rst_ni @@ -151,36 +151,36 @@ add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/data_o add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/pop_i add wave -noupdate -divider {DUT Ports} -add wave -noupdate -expand -group {DUT slv AW} /tb_axi_fifo/i_dut/i_axi_fifo/slv_req_i.aw_valid -add wave -noupdate -expand -group {DUT slv AW} /tb_axi_fifo/i_dut/i_axi_fifo/slv_resp_o.aw_ready -add wave -noupdate -expand -group {DUT slv AW} /tb_axi_fifo/i_dut/i_axi_fifo/slv_req_i.aw -add wave -noupdate -expand -group {DUT slv W} /tb_axi_fifo/i_dut/i_axi_fifo/slv_req_i.w -add wave -noupdate -expand -group {DUT slv W} /tb_axi_fifo/i_dut/i_axi_fifo/slv_req_i.w_valid -add wave -noupdate -expand -group {DUT slv W} /tb_axi_fifo/i_dut/i_axi_fifo/slv_resp_o.w_ready -add wave -noupdate -expand -group {DUT slv B} /tb_axi_fifo/i_dut/i_axi_fifo/slv_resp_o.b_valid -add wave -noupdate -expand -group {DUT slv B} /tb_axi_fifo/i_dut/i_axi_fifo/slv_req_i.b_ready -add wave -noupdate -expand -group {DUT slv B} /tb_axi_fifo/i_dut/i_axi_fifo/slv_resp_o.b -add wave -noupdate -expand -group {DUT slv AR} /tb_axi_fifo/i_dut/i_axi_fifo/slv_req_i.ar_valid -add wave -noupdate -expand -group {DUT slv AR} /tb_axi_fifo/i_dut/i_axi_fifo/slv_resp_o.ar_ready -add wave -noupdate -expand -group {DUT slv AR} /tb_axi_fifo/i_dut/i_axi_fifo/slv_req_i.ar -add wave -noupdate -expand -group {DUT slv R} /tb_axi_fifo/i_dut/i_axi_fifo/slv_resp_o.r_valid -add wave -noupdate -expand -group {DUT slv R} /tb_axi_fifo/i_dut/i_axi_fifo/slv_req_i.r_ready -add wave -noupdate -expand -group {DUT slv R} /tb_axi_fifo/i_dut/i_axi_fifo/slv_resp_o.r -add wave -noupdate -expand -group {DUT mst AW} /tb_axi_fifo/i_dut/i_axi_fifo/mst_req_o.aw_valid -add wave -noupdate -expand -group {DUT mst AW} /tb_axi_fifo/i_dut/i_axi_fifo/mst_resp_i.aw_ready -add wave -noupdate -expand -group {DUT mst AW} /tb_axi_fifo/i_dut/i_axi_fifo/mst_req_o.aw -add wave -noupdate -expand -group {DUT mst W} /tb_axi_fifo/i_dut/i_axi_fifo/mst_req_o.w -add wave -noupdate -expand -group {DUT mst W} /tb_axi_fifo/i_dut/i_axi_fifo/mst_req_o.w_valid -add wave -noupdate -expand -group {DUT mst W} /tb_axi_fifo/i_dut/i_axi_fifo/mst_resp_i.w_ready -add wave -noupdate -expand -group {DUT mst B} /tb_axi_fifo/i_dut/i_axi_fifo/mst_resp_i.b_valid -add wave -noupdate -expand -group {DUT mst B} /tb_axi_fifo/i_dut/i_axi_fifo/mst_req_o.b_ready -add wave -noupdate -expand -group {DUT mst B} /tb_axi_fifo/i_dut/i_axi_fifo/mst_resp_i.b -add wave -noupdate -expand -group {DUT mst AR} /tb_axi_fifo/i_dut/i_axi_fifo/mst_req_o.ar_valid -add wave -noupdate -expand -group {DUT mst AR} /tb_axi_fifo/i_dut/i_axi_fifo/mst_resp_i.ar_ready -add wave -noupdate -expand -group {DUT mst AR} /tb_axi_fifo/i_dut/i_axi_fifo/mst_req_o.ar -add wave -noupdate -expand -group {DUT mst R} /tb_axi_fifo/i_dut/i_axi_fifo/mst_resp_i.r_valid -add wave -noupdate -expand -group {DUT mst R} /tb_axi_fifo/i_dut/i_axi_fifo/mst_req_o.r_ready -add wave -noupdate -expand -group {DUT mst R} /tb_axi_fifo/i_dut/i_axi_fifo/mst_resp_i.r +add wave -noupdate -expand -group {DUT sbr AW} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.aw_valid +add wave -noupdate -expand -group {DUT sbr AW} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.aw_ready +add wave -noupdate -expand -group {DUT sbr AW} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.aw +add wave -noupdate -expand -group {DUT sbr W} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.w +add wave -noupdate -expand -group {DUT sbr W} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.w_valid +add wave -noupdate -expand -group {DUT sbr W} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.w_ready +add wave -noupdate -expand -group {DUT sbr B} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.b_valid +add wave -noupdate -expand -group {DUT sbr B} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.b_ready +add wave -noupdate -expand -group {DUT sbr B} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.b +add wave -noupdate -expand -group {DUT sbr AR} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.ar_valid +add wave -noupdate -expand -group {DUT sbr AR} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.ar_ready +add wave -noupdate -expand -group {DUT sbr AR} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.ar +add wave -noupdate -expand -group {DUT sbr R} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.r_valid +add wave -noupdate -expand -group {DUT sbr R} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.r_ready +add wave -noupdate -expand -group {DUT sbr R} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.r +add wave -noupdate -expand -group {DUT mgr AW} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.aw_valid +add wave -noupdate -expand -group {DUT mgr AW} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.aw_ready +add wave -noupdate -expand -group {DUT mgr AW} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.aw +add wave -noupdate -expand -group {DUT mgr W} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.w +add wave -noupdate -expand -group {DUT mgr W} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.w_valid +add wave -noupdate -expand -group {DUT mgr W} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.w_ready +add wave -noupdate -expand -group {DUT mgr B} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.b_valid +add wave -noupdate -expand -group {DUT mgr B} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.b_ready +add wave -noupdate -expand -group {DUT mgr B} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.b +add wave -noupdate -expand -group {DUT mgr AR} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.ar_valid +add wave -noupdate -expand -group {DUT mgr AR} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.ar_ready +add wave -noupdate -expand -group {DUT mgr AR} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.ar +add wave -noupdate -expand -group {DUT mgr R} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.r_valid +add wave -noupdate -expand -group {DUT mgr R} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.r_ready +add wave -noupdate -expand -group {DUT mgr R} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.r TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {70 ns} 0} quietly wave cursor active 1 diff --git a/test/tb_axi_isolate.sv b/test/tb_axi_isolate.sv index 959225392..a1dc6c2a5 100644 --- a/test/tb_axi_isolate.sv +++ b/test/tb_axi_isolate.sv @@ -16,12 +16,12 @@ `include "axi/assign.svh" module tb_axi_isolate #( - parameter int unsigned NumWrites = 50000, // How many writes per master - parameter int unsigned NumReads = 30000 // How many reads per master + parameter int unsigned NumWrites = 50000, // How many writes per manager + parameter int unsigned NumReads = 30000 // How many reads per manager ); - // Random master no Transactions + // Random manager no Transactions localparam int unsigned NumPendingDut = 16; - // Random Master Atomics + // Random Manager Atomics localparam int unsigned MaxAW = 32'd30; localparam int unsigned MaxAR = 32'd30; localparam bit EnAtop = 1'b1; @@ -38,7 +38,7 @@ module tb_axi_isolate #( localparam int unsigned PrintTnx = 1000; - typedef axi_test::axi_rand_master #( + typedef axi_test::axi_rand_manager #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), @@ -51,8 +51,8 @@ module tb_axi_isolate #( .MAX_READ_TXNS ( MaxAR ), .MAX_WRITE_TXNS ( MaxAW ), .AXI_ATOPS ( EnAtop ) - ) axi_rand_master_t; - typedef axi_test::axi_rand_slave #( + ) axi_rand_manager_t; + typedef axi_test::axi_rand_subordinate #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), @@ -61,7 +61,7 @@ module tb_axi_isolate #( // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) axi_rand_slave_t; + ) axi_rand_subordinate_t; // ------------- // DUT signals @@ -78,28 +78,28 @@ module tb_axi_isolate #( .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidth ), .AXI_USER_WIDTH ( UserWidth ) - ) master (); + ) manager (); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidth ), .AXI_USER_WIDTH ( UserWidth ) - ) master_dv (clk); + ) manager_dv (clk); AXI_BUS #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidth ), .AXI_USER_WIDTH ( UserWidth ) - ) slave (); + ) subordinate (); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidth ), .AXI_USER_WIDTH ( UserWidth ) - ) slave_dv (clk); + ) subordinate_dv (clk); - `AXI_ASSIGN ( master, master_dv ) - `AXI_ASSIGN ( slave_dv, slave ) + `AXI_ASSIGN ( manager, manager_dv ) + `AXI_ASSIGN ( subordinate_dv, subordinate ) //----------------------------------- // Clock generator @@ -124,31 +124,31 @@ module tb_axi_isolate #( ) i_dut ( .clk_i ( clk ), // clock .rst_ni ( rst_n ), // asynchronous reset active low - .slv ( master ), // slave port - .mst ( slave ), // master port - .isolate_i ( isolate ), // isolate master port from slave port - .isolated_o ( isolated ) // master port is isolated from slave port + .sbr ( manager ), // subordinate port + .mgr ( subordinate ), // manager port + .isolate_i ( isolate ), // isolate manager port from subordinate port + .isolated_o ( isolated ) // manager port is isolated from subordinate port ); - initial begin : proc_axi_master - automatic axi_rand_master_t axi_rand_master = new(master_dv); + initial begin : proc_axi_manager + automatic axi_rand_manager_t axi_rand_manager = new(manager_dv); end_of_sim <= 1'b0; - axi_rand_master.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE); - axi_rand_master.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE); - axi_rand_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); - axi_rand_master.reset(); + axi_rand_manager.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_manager.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE); + axi_rand_manager.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); + axi_rand_manager.reset(); @(posedge rst_n); - axi_rand_master.run(NumReads, NumWrites); + axi_rand_manager.run(NumReads, NumWrites); end_of_sim <= 1'b1; repeat (10000) @(posedge clk); $stop(); end - initial begin : proc_axi_slave - automatic axi_rand_slave_t axi_rand_slave = new(slave_dv); - axi_rand_slave.reset(); + initial begin : proc_axi_subordinate + automatic axi_rand_subordinate_t axi_rand_subordinate = new(subordinate_dv); + axi_rand_subordinate.reset(); @(posedge rst_n); - axi_rand_slave.run(); + axi_rand_subordinate.run(); end initial begin : proc_sim_ctl @@ -171,10 +171,10 @@ module tb_axi_isolate #( forever begin @(posedge clk); #TestTime; - if (master.aw_valid && master.aw_ready) begin + if (manager.aw_valid && manager.aw_ready) begin aw++; end - if (master.ar_valid && master.ar_ready) begin + if (manager.ar_valid && manager.ar_ready) begin ar++; end @@ -204,19 +204,19 @@ module tb_axi_isolate #( default disable iff (!rst_n); aw_unstable: assert property (@(posedge clk) - (slave.aw_valid && !slave.aw_ready) |=> $stable(slave.aw_addr)) else + (subordinate.aw_valid && !subordinate.aw_ready) |=> $stable(subordinate.aw_addr)) else $fatal(1, "AW is unstable."); w_unstable: assert property (@(posedge clk) - (slave.w_valid && !slave.w_ready) |=> $stable(slave.w_data)) else + (subordinate.w_valid && !subordinate.w_ready) |=> $stable(subordinate.w_data)) else $fatal(1, "W is unstable."); b_unstable: assert property (@(posedge clk) - (master.b_valid && !master.b_ready) |=> $stable(master.b_resp)) else + (manager.b_valid && !manager.b_ready) |=> $stable(manager.b_resp)) else $fatal(1, "B is unstable."); ar_unstable: assert property (@(posedge clk) - (slave.ar_valid && !slave.ar_ready) |=> $stable(slave.ar_addr)) else + (subordinate.ar_valid && !subordinate.ar_ready) |=> $stable(subordinate.ar_addr)) else $fatal(1, "AR is unstable."); r_unstable: assert property (@(posedge clk) - (master.r_valid && !master.r_ready) |=> $stable(master.r_data)) else + (manager.r_valid && !manager.r_ready) |=> $stable(manager.r_data)) else $fatal(1, "R is unstable."); diff --git a/test/tb_axi_isolate.wave.do b/test/tb_axi_isolate.wave.do index 1ddc75898..d21ef80e5 100644 --- a/test/tb_axi_isolate.wave.do +++ b/test/tb_axi_isolate.wave.do @@ -3,98 +3,98 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -label Clock /tb_axi_isolate/i_dut/clk_i add wave -noupdate -label Reset /tb_axi_isolate/i_dut/rst_ni -add wave -noupdate -divider {Slave Ports} -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_id -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_addr -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_len -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_size -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_burst -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_lock -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_cache -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_prot -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_qos -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_region -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_atop -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_user -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_valid -add wave -noupdate -group {Master AW} /tb_axi_isolate/master/aw_ready -add wave -noupdate -group {Master W} /tb_axi_isolate/master/w_data -add wave -noupdate -group {Master W} /tb_axi_isolate/master/w_strb -add wave -noupdate -group {Master W} /tb_axi_isolate/master/w_last -add wave -noupdate -group {Master W} /tb_axi_isolate/master/w_user -add wave -noupdate -group {Master W} /tb_axi_isolate/master/w_valid -add wave -noupdate -group {Master W} /tb_axi_isolate/master/w_ready -add wave -noupdate -group {Master B} /tb_axi_isolate/master/b_id -add wave -noupdate -group {Master B} /tb_axi_isolate/master/b_resp -add wave -noupdate -group {Master B} /tb_axi_isolate/master/b_user -add wave -noupdate -group {Master B} /tb_axi_isolate/master/b_valid -add wave -noupdate -group {Master B} /tb_axi_isolate/master/b_ready -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_id -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_addr -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_len -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_size -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_burst -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_lock -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_cache -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_prot -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_qos -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_region -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_user -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_valid -add wave -noupdate -group {Master AR} /tb_axi_isolate/master/ar_ready -add wave -noupdate -group {Master R} /tb_axi_isolate/master/r_id -add wave -noupdate -group {Master R} /tb_axi_isolate/master/r_data -add wave -noupdate -group {Master R} /tb_axi_isolate/master/r_resp -add wave -noupdate -group {Master R} /tb_axi_isolate/master/r_last -add wave -noupdate -group {Master R} /tb_axi_isolate/master/r_user -add wave -noupdate -group {Master R} /tb_axi_isolate/master/r_valid -add wave -noupdate -group {Master R} /tb_axi_isolate/master/r_ready -add wave -noupdate -divider {Master Ports} -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_id -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_addr -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_len -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_size -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_burst -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_lock -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_cache -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_prot -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_qos -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_region -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_atop -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_user -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_valid -add wave -noupdate -group {Slave AW} /tb_axi_isolate/slave/aw_ready -add wave -noupdate -group {Slave W} /tb_axi_isolate/slave/w_data -add wave -noupdate -group {Slave W} /tb_axi_isolate/slave/w_strb -add wave -noupdate -group {Slave W} /tb_axi_isolate/slave/w_last -add wave -noupdate -group {Slave W} /tb_axi_isolate/slave/w_user -add wave -noupdate -group {Slave W} /tb_axi_isolate/slave/w_valid -add wave -noupdate -group {Slave W} /tb_axi_isolate/slave/w_ready -add wave -noupdate -group {Slave B} /tb_axi_isolate/slave/b_id -add wave -noupdate -group {Slave B} /tb_axi_isolate/slave/b_resp -add wave -noupdate -group {Slave B} /tb_axi_isolate/slave/b_user -add wave -noupdate -group {Slave B} /tb_axi_isolate/slave/b_valid -add wave -noupdate -group {Slave B} /tb_axi_isolate/slave/b_ready -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_id -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_addr -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_len -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_size -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_burst -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_lock -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_cache -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_prot -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_qos -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_region -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_user -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_valid -add wave -noupdate -group {Slave AR} /tb_axi_isolate/slave/ar_ready -add wave -noupdate -group {Slave R} /tb_axi_isolate/slave/r_id -add wave -noupdate -group {Slave R} /tb_axi_isolate/slave/r_data -add wave -noupdate -group {Slave R} /tb_axi_isolate/slave/r_resp -add wave -noupdate -group {Slave R} /tb_axi_isolate/slave/r_last -add wave -noupdate -group {Slave R} /tb_axi_isolate/slave/r_user -add wave -noupdate -group {Slave R} /tb_axi_isolate/slave/r_valid -add wave -noupdate -group {Slave R} /tb_axi_isolate/slave/r_ready +add wave -noupdate -divider {Subordinate Ports} +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_id +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_addr +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_len +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_size +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_burst +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_lock +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_cache +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_prot +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_qos +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_region +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_atop +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_user +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_valid +add wave -noupdate -group {Manager AW} /tb_axi_isolate/manager/aw_ready +add wave -noupdate -group {Manager W} /tb_axi_isolate/manager/w_data +add wave -noupdate -group {Manager W} /tb_axi_isolate/manager/w_strb +add wave -noupdate -group {Manager W} /tb_axi_isolate/manager/w_last +add wave -noupdate -group {Manager W} /tb_axi_isolate/manager/w_user +add wave -noupdate -group {Manager W} /tb_axi_isolate/manager/w_valid +add wave -noupdate -group {Manager W} /tb_axi_isolate/manager/w_ready +add wave -noupdate -group {Manager B} /tb_axi_isolate/manager/b_id +add wave -noupdate -group {Manager B} /tb_axi_isolate/manager/b_resp +add wave -noupdate -group {Manager B} /tb_axi_isolate/manager/b_user +add wave -noupdate -group {Manager B} /tb_axi_isolate/manager/b_valid +add wave -noupdate -group {Manager B} /tb_axi_isolate/manager/b_ready +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_id +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_addr +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_len +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_size +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_burst +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_lock +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_cache +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_prot +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_qos +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_region +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_user +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_valid +add wave -noupdate -group {Manager AR} /tb_axi_isolate/manager/ar_ready +add wave -noupdate -group {Manager R} /tb_axi_isolate/manager/r_id +add wave -noupdate -group {Manager R} /tb_axi_isolate/manager/r_data +add wave -noupdate -group {Manager R} /tb_axi_isolate/manager/r_resp +add wave -noupdate -group {Manager R} /tb_axi_isolate/manager/r_last +add wave -noupdate -group {Manager R} /tb_axi_isolate/manager/r_user +add wave -noupdate -group {Manager R} /tb_axi_isolate/manager/r_valid +add wave -noupdate -group {Manager R} /tb_axi_isolate/manager/r_ready +add wave -noupdate -divider {Manager Ports} +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_id +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_addr +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_len +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_size +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_burst +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_lock +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_cache +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_prot +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_qos +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_region +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_atop +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_user +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_valid +add wave -noupdate -group {Subordinate AW} /tb_axi_isolate/subordinate/aw_ready +add wave -noupdate -group {Subordinate W} /tb_axi_isolate/subordinate/w_data +add wave -noupdate -group {Subordinate W} /tb_axi_isolate/subordinate/w_strb +add wave -noupdate -group {Subordinate W} /tb_axi_isolate/subordinate/w_last +add wave -noupdate -group {Subordinate W} /tb_axi_isolate/subordinate/w_user +add wave -noupdate -group {Subordinate W} /tb_axi_isolate/subordinate/w_valid +add wave -noupdate -group {Subordinate W} /tb_axi_isolate/subordinate/w_ready +add wave -noupdate -group {Subordinate B} /tb_axi_isolate/subordinate/b_id +add wave -noupdate -group {Subordinate B} /tb_axi_isolate/subordinate/b_resp +add wave -noupdate -group {Subordinate B} /tb_axi_isolate/subordinate/b_user +add wave -noupdate -group {Subordinate B} /tb_axi_isolate/subordinate/b_valid +add wave -noupdate -group {Subordinate B} /tb_axi_isolate/subordinate/b_ready +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_id +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_addr +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_len +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_size +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_burst +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_lock +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_cache +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_prot +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_qos +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_region +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_user +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_valid +add wave -noupdate -group {Subordinate AR} /tb_axi_isolate/subordinate/ar_ready +add wave -noupdate -group {Subordinate R} /tb_axi_isolate/subordinate/r_id +add wave -noupdate -group {Subordinate R} /tb_axi_isolate/subordinate/r_data +add wave -noupdate -group {Subordinate R} /tb_axi_isolate/subordinate/r_resp +add wave -noupdate -group {Subordinate R} /tb_axi_isolate/subordinate/r_last +add wave -noupdate -group {Subordinate R} /tb_axi_isolate/subordinate/r_user +add wave -noupdate -group {Subordinate R} /tb_axi_isolate/subordinate/r_valid +add wave -noupdate -group {Subordinate R} /tb_axi_isolate/subordinate/r_ready add wave -noupdate -divider Custom add wave -noupdate -label isolate_i /tb_axi_isolate/i_dut/isolate_i add wave -noupdate -label isolated_o /tb_axi_isolate/i_dut/isolated_o diff --git a/test/tb_axi_iw_converter.sv b/test/tb_axi_iw_converter.sv index 14ca66abd..286b2f2ac 100644 --- a/test/tb_axi_iw_converter.sv +++ b/test/tb_axi_iw_converter.sv @@ -39,13 +39,13 @@ endclass module tb_axi_iw_converter #( // DUT Parameters - parameter int unsigned TbSlvPortIdWidth = 32'd0, - parameter int unsigned TbMstPortIdWidth = 32'd0, - parameter int unsigned TbSlvPortMaxUniqIds = 32'd0, - parameter int unsigned TbSlvPortMaxTxnsPerId = 32'd0, - parameter int unsigned TbSlvPortMaxTxns = 32'd0, - parameter int unsigned TbMstPortMaxUniqIds = 32'd0, - parameter int unsigned TbMstPortMaxTxnsPerId = 32'd0, + parameter int unsigned TbSbrPortIdWidth = 32'd0, + parameter int unsigned TbMgrPortIdWidth = 32'd0, + parameter int unsigned TbSbrPortMaxUniqIds = 32'd0, + parameter int unsigned TbSbrPortMaxTxnsPerId = 32'd0, + parameter int unsigned TbSbrPortMaxTxns = 32'd0, + parameter int unsigned TbMgrPortMaxUniqIds = 32'd0, + parameter int unsigned TbMgrPortMaxTxnsPerId = 32'd0, parameter int unsigned TbAddrWidth = 32'd32, parameter int unsigned TbDataWidth = 32'd32, parameter int unsigned TbUserWidth = 32'd4, @@ -63,11 +63,11 @@ module tb_axi_iw_converter #( localparam time TestTime = 8ns; // Driver definitions - typedef axi_test::axi_rand_master #( + typedef axi_test::axi_rand_manager #( // AXI interface parameters .AW ( TbAddrWidth ), .DW ( TbDataWidth ), - .IW ( TbSlvPortIdWidth ), + .IW ( TbSbrPortIdWidth ), .UW ( TbUserWidth ), // Stimuli application and test time .TA ( ApplTime ), @@ -77,17 +77,17 @@ module tb_axi_iw_converter #( .MAX_WRITE_TXNS ( 20 ), .AXI_EXCLS ( TbEnExcl ), .AXI_ATOPS ( TbEnAtop ) - ) rand_axi_master_t; - typedef axi_test::axi_rand_slave #( + ) rand_axi_manager_t; + typedef axi_test::axi_rand_subordinate #( // AXI interface parameters .AW ( TbAddrWidth ), .DW ( TbDataWidth ), - .IW ( TbMstPortIdWidth ), + .IW ( TbMgrPortIdWidth ), .UW ( TbUserWidth ), // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) rand_axi_slave_t; + ) rand_axi_subordinate_t; // TB signals logic clk, rst_n, sim_done; @@ -106,14 +106,14 @@ module tb_axi_iw_converter #( AXI_BUS_DV #( .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), - .AXI_ID_WIDTH ( TbSlvPortIdWidth ), + .AXI_ID_WIDTH ( TbSbrPortIdWidth ), .AXI_USER_WIDTH ( TbUserWidth ) ) axi_upstream_dv (clk); AXI_BUS #( .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), - .AXI_ID_WIDTH ( TbSlvPortIdWidth ), + .AXI_ID_WIDTH ( TbSbrPortIdWidth ), .AXI_USER_WIDTH ( TbUserWidth ) ) axi_upstream(); @@ -122,36 +122,36 @@ module tb_axi_iw_converter #( AXI_BUS_DV #( .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), - .AXI_ID_WIDTH ( TbMstPortIdWidth ), + .AXI_ID_WIDTH ( TbMgrPortIdWidth ), .AXI_USER_WIDTH ( TbUserWidth ) ) axi_downstream_dv (clk); AXI_BUS #( .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), - .AXI_ID_WIDTH ( TbMstPortIdWidth ), + .AXI_ID_WIDTH ( TbMgrPortIdWidth ), .AXI_USER_WIDTH ( TbUserWidth ) ) axi_downstream(); `AXI_ASSIGN(axi_downstream_dv, axi_downstream); - initial begin : proc_rand_master - automatic rand_axi_master_t axi_master = new(axi_upstream_dv); + initial begin : proc_rand_manager + automatic rand_axi_manager_t axi_manager = new(axi_upstream_dv); sim_done = 1'b0; @(posedge rst_n); - axi_master.reset(); - axi_master.add_memory_region('0, '1, axi_pkg::DEVICE_NONBUFFERABLE); + axi_manager.reset(); + axi_manager.add_memory_region('0, '1, axi_pkg::DEVICE_NONBUFFERABLE); repeat (5) @(posedge clk); - axi_master.run(TbNumReadTxns, TbNumWriteTxns); + axi_manager.run(TbNumReadTxns, TbNumWriteTxns); sim_done = 1'b1; end - initial begin : proc_rand_slave - automatic rand_axi_slave_t axi_slave = new(axi_downstream_dv); + initial begin : proc_rand_subordinate + automatic rand_axi_subordinate_t axi_subordinate = new(axi_downstream_dv); @(posedge rst_n); - axi_slave.reset(); - axi_slave.run(); + axi_subordinate.reset(); + axi_subordinate.run(); end initial begin : proc_sim_stop @@ -162,28 +162,28 @@ module tb_axi_iw_converter #( end axi_iw_converter_intf #( - .AXI_SLV_PORT_ID_WIDTH ( TbSlvPortIdWidth ), - .AXI_MST_PORT_ID_WIDTH ( TbMstPortIdWidth ), - .AXI_SLV_PORT_MAX_UNIQ_IDS ( TbSlvPortMaxUniqIds ), - .AXI_SLV_PORT_MAX_TXNS_PER_ID ( TbSlvPortMaxTxnsPerId ), - .AXI_SLV_PORT_MAX_TXNS ( TbSlvPortMaxTxns ), - .AXI_MST_PORT_MAX_UNIQ_IDS ( TbMstPortMaxUniqIds ), - .AXI_MST_PORT_MAX_TXNS_PER_ID ( TbMstPortMaxTxnsPerId ), + .AXI_SBR_PORT_ID_WIDTH ( TbSbrPortIdWidth ), + .AXI_MGR_PORT_ID_WIDTH ( TbMgrPortIdWidth ), + .AXI_SBR_PORT_MAX_UNIQ_IDS ( TbSbrPortMaxUniqIds ), + .AXI_SBR_PORT_MAX_TXNS_PER_ID ( TbSbrPortMaxTxnsPerId ), + .AXI_SBR_PORT_MAX_TXNS ( TbSbrPortMaxTxns ), + .AXI_MGR_PORT_MAX_UNIQ_IDS ( TbMgrPortMaxUniqIds ), + .AXI_MGR_PORT_MAX_TXNS_PER_ID ( TbMgrPortMaxTxnsPerId ), .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), .AXI_USER_WIDTH ( TbUserWidth ) ) i_dut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .slv ( axi_upstream ), - .mst ( axi_downstream ) + .sbr ( axi_upstream ), + .mgr ( axi_downstream ) ); - typedef rand_axi_master_t::addr_t addr_t; - typedef rand_axi_master_t::data_t data_t; - typedef rand_axi_master_t::id_t id_t; - typedef logic[rand_axi_master_t::DW/8-1:0] strb_t; - typedef rand_axi_master_t::user_t user_t; + typedef rand_axi_manager_t::addr_t addr_t; + typedef rand_axi_manager_t::data_t data_t; + typedef rand_axi_manager_t::id_t id_t; + typedef logic[rand_axi_manager_t::DW/8-1:0] strb_t; + typedef rand_axi_manager_t::user_t user_t; `AXI_TYPEDEF_AW_CHAN_T(aw_beat_t, addr_t, id_t, user_t) `AXI_TYPEDEF_W_CHAN_T(w_beat_t, data_t, strb_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_beat_t, addr_t, id_t, user_t) diff --git a/test/tb_axi_lite_mailbox.sv b/test/tb_axi_lite_mailbox.sv index 1cf9cc3ff..847edab0c 100644 --- a/test/tb_axi_lite_mailbox.sv +++ b/test/tb_axi_lite_mailbox.sv @@ -26,7 +26,7 @@ // flushing the FIFOs and reading the `ERROR` register. // - Port 0 makes an unmapped read and write access, and some targeted accesses to get the branch // coverage to 96.25%, the not taken branches have to do with the stalling -// capabilities of the slave, when the response path is not ready. +// capabilities of the subordinate, when the response path is not ready. // Each of these tests has the respective AXI Lite transaction asserted in the expected output. // Simulation end tells the number of failed assertions. @@ -61,7 +61,7 @@ module tb_axi_lite_mailbox; CTRL = addr_t'(9 * DataWidth/8) } reg_addr_e; - typedef axi_test::axi_lite_rand_master #( + typedef axi_test::axi_lite_rand_manager #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), @@ -72,7 +72,7 @@ module tb_axi_lite_mailbox; .MAX_ADDR ( 32'h0001_3000 ), .MAX_READ_TXNS ( 10 ), .MAX_WRITE_TXNS ( 10 ) - ) rand_lite_master_t; + ) rand_lite_manager_t; // ------------- // DUT signals @@ -92,81 +92,81 @@ module tb_axi_lite_mailbox; AXI_LITE #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) master [1:0] (); + ) manager [1:0] (); AXI_LITE_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) master_dv [1:0] (clk); - for (genvar i = 0; i < 2; i++) begin : gen_conn_dv_masters - `AXI_LITE_ASSIGN(master[i], master_dv[i]) + ) manager_dv [1:0] (clk); + for (genvar i = 0; i < 2; i++) begin : gen_conn_dv_managers + `AXI_LITE_ASSIGN(manager[i], manager_dv[i]) end - // Masters control simulation run time - initial begin : proc_master_0 - automatic rand_lite_master_t lite_axi_master = new ( master_dv[0], "MST_0"); + // Managers control simulation run time + initial begin : proc_manager_0 + automatic rand_lite_manager_t lite_axi_manager = new ( manager_dv[0], "MGR_0"); automatic data_t data = '0; automatic axi_pkg::resp_t resp = axi_pkg::RESP_SLVERR; // automatic int unsigned test_failed[0] = 0; automatic int unsigned loop = 0; end_of_sim[0] <= 1'b0; - lite_axi_master.reset(); + lite_axi_manager.reset(); @(posedge rst_n); // ------------------------------- // Read all registers anf compare their results // ------------------------------- $info("Initial test by reading each register"); - $display("%0t MST_0> Read register MBOXW ", $time()); - lite_axi_master.read(MBOXW, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register MBOXW ", $time()); + lite_axi_manager.read(MBOXW, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(32'hFEEDC0DE)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register MBOXR, this generates an error ", $time()); - lite_axi_master.read(MBOXR, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register MBOXR, this generates an error ", $time()); + lite_axi_manager.read(MBOXR, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(32'hFEEDDEAD)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_SLVERR) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register STATUS", $time()); - lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register STATUS", $time()); + lite_axi_manager.read(STATUS, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(1)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register ERROR ", $time()); - lite_axi_master.read(ERROR, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register ERROR ", $time()); + lite_axi_manager.read(ERROR, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(1)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register WIRQT ", $time()); - lite_axi_master.read(WIRQT, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register WIRQT ", $time()); + lite_axi_manager.read(WIRQT, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(0)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register RIRQT ", $time()); - lite_axi_master.read(RIRQT, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register RIRQT ", $time()); + lite_axi_manager.read(RIRQT, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(0)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register IRQS ", $time()); - lite_axi_master.read(IRQS, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register IRQS ", $time()); + lite_axi_manager.read(IRQS, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(3'b100)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Acknowledge Error by writing to IRQS", $time()); - lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), 64'h4, 8'hFF, resp); + $display("%0t MGR_0> Acknowledge Error by writing to IRQS", $time()); + lite_axi_manager.write(IRQS, axi_pkg::prot_t'('0), 64'h4, 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register IRQEN ", $time()); - lite_axi_master.read(IRQEN, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register IRQEN ", $time()); + lite_axi_manager.read(IRQEN, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(0)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register IRQP ", $time()); - lite_axi_master.read(IRQP, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register IRQP ", $time()); + lite_axi_manager.read(IRQP, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(0)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register CTRL ", $time()); - lite_axi_master.read(CTRL, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register CTRL ", $time()); + lite_axi_manager.read(CTRL, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(0)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end @@ -175,122 +175,122 @@ module tb_axi_lite_mailbox; // ------------------------------- repeat (50) @(posedge clk); $info("Test error interrupt"); - $display("%0t MST_0> Enable Error interrupt ", $time()); - lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp); + $display("%0t MGR_0> Enable Error interrupt ", $time()); + lite_axi_manager.write(IRQEN, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register MBOXR, this generates an error ", $time()); - lite_axi_master.read(MBOXR, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register MBOXR, this generates an error ", $time()); + lite_axi_manager.read(MBOXR, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(32'hFEEDDEAD)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_SLVERR) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read register ERROR ", $time()); - lite_axi_master.read(ERROR, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read register ERROR ", $time()); + lite_axi_manager.read(ERROR, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(1)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Acknowledge Error by writing to IRQS", $time()); - lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp); + $display("%0t MGR_0> Acknowledge Error by writing to IRQS", $time()); + lite_axi_manager.write(IRQS, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Disable interrupt", $time()); - lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp); + $display("%0t MGR_0> Disable interrupt", $time()); + lite_axi_manager.write(IRQEN, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end // ------------------------------- // Send data to the other port, and enable interrupt for recieving // ------------------------------- repeat (50) @(posedge clk); - $info("Test sending data from one to the other slave interface"); - $display("%0t MST_0> Set write threshold to 100, truncates to depth ", $time()); - lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), 64'd100, 8'hFF, resp); + $info("Test sending data from one to the other subordinate interface"); + $display("%0t MGR_0> Set write threshold to 100, truncates to depth ", $time()); + lite_axi_manager.write(WIRQT, axi_pkg::prot_t'('0), 64'd100, 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read out write threshold ", $time()); - lite_axi_master.read(WIRQT, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read out write threshold ", $time()); + lite_axi_manager.read(WIRQT, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(MailboxDepth - 1)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Set write threshold to 0", $time()); - lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), 64'd0, 8'hFF, resp); + $display("%0t MGR_0> Set write threshold to 0", $time()); + lite_axi_manager.write(WIRQT, axi_pkg::prot_t'('0), 64'd0, 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Set Read threshold to 100, truncates to depth ", $time()); - lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), 64'd100, 8'hFF, resp); + $display("%0t MGR_0> Set Read threshold to 100, truncates to depth ", $time()); + lite_axi_manager.write(RIRQT, axi_pkg::prot_t'('0), 64'd100, 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Read out read threshold ", $time()); - lite_axi_master.read(RIRQT, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> Read out read threshold ", $time()); + lite_axi_manager.read(RIRQT, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(MailboxDepth - 1)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Set Read threshold to 64'd2 ", $time()); - lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), 64'd2, 8'hFF, resp); + $display("%0t MGR_0> Set Read threshold to 64'd2 ", $time()); + lite_axi_manager.write(RIRQT, axi_pkg::prot_t'('0), 64'd2, 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Enable Read threshold interrupt ", $time()); - lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), 64'h2, 8'hFF, resp); + $display("%0t MGR_0> Enable Read threshold interrupt ", $time()); + lite_axi_manager.write(IRQEN, axi_pkg::prot_t'('0), 64'h2, 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Send to slave 1 data ", $time()); - lite_axi_master.write(MBOXW, axi_pkg::prot_t'('0), data_t'(32'hFEEDFEED), 8'hFF, resp); + $display("%0t MGR_0> Send to subordinate 1 data ", $time()); + lite_axi_manager.write(MBOXW, axi_pkg::prot_t'('0), data_t'(32'hFEEDFEED), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end // wait for interrupt wait (irq[0]); - $display("%0t MST_0> interrupt recieved, test that it is the expected one ", $time()); - lite_axi_master.read(IRQP, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_0> interrupt recieved, test that it is the expected one ", $time()); + lite_axi_manager.read(IRQP, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(3'b010)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(STATUS, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(4'b1000)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> empty data from port ", $time()); + $display("%0t MGR_0> empty data from port ", $time()); while (!data[0]) begin - lite_axi_master.read(MBOXR, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(MBOXR, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(loop)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end loop ++; - lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(STATUS, axi_pkg::prot_t'('0), data, resp); end - $display("%0t MST_0> FIFO is now empty, clear interrupt and disable it ", $time()); - lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(3'b111), 8'hFF, resp); - lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp); - lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp); + $display("%0t MGR_0> FIFO is now empty, clear interrupt and disable it ", $time()); + lite_axi_manager.write(IRQS, axi_pkg::prot_t'('0), data_t'(3'b111), 8'hFF, resp); + lite_axi_manager.write(IRQEN, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp); + lite_axi_manager.write(RIRQT, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp); // ------------------------------- // Test Flush // ------------------------------- repeat (50) @(posedge clk); - $info("%0t MST_0> Test Flush all FIFOs ", $time()); - lite_axi_master.write(CTRL, axi_pkg::prot_t'('0), data_t'('1), 8'h00, resp); + $info("%0t MGR_0> Test Flush all FIFOs ", $time()); + lite_axi_manager.write(CTRL, axi_pkg::prot_t'('0), data_t'('1), 8'h00, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(CTRL, axi_pkg::prot_t'('0), data_t'('1), 8'hFF, resp); + lite_axi_manager.write(CTRL, axi_pkg::prot_t'('0), data_t'('1), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end // ------------------------------- // Fill the write FIFO, until write error interrupt, then flush and clear interrupt // ------------------------------- repeat (50) @(posedge clk); - $info("%0t MST_0> Test Write error interrupt ", $time()); - lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp); + $info("%0t MGR_0> Test Write error interrupt ", $time()); + lite_axi_manager.write(IRQEN, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp); loop = 0; while (!irq[0]) begin - lite_axi_master.write(MBOXW, axi_pkg::prot_t'('0), data_t'(loop), 8'hFF, resp); + lite_axi_manager.write(MBOXW, axi_pkg::prot_t'('0), data_t'(loop), 8'hFF, resp); end - lite_axi_master.read(IRQP, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(IRQP, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(3'b100)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.read(ERROR, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(ERROR, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(2'b10)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(CTRL, axi_pkg::prot_t'('0), data_t'(2'b01), 8'h01, resp); + lite_axi_manager.write(CTRL, axi_pkg::prot_t'('0), data_t'(2'b01), 8'h01, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(3'b111), 8'h01, resp); + lite_axi_manager.write(IRQS, axi_pkg::prot_t'('0), data_t'(3'b111), 8'h01, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(STATUS, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(4'b0001)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end @@ -298,109 +298,109 @@ module tb_axi_lite_mailbox; // Make an unmapped read and write access // ------------------------------- repeat (50) @(posedge clk); - $info("%0t MST_0> Make an unmapped access read and write ", $time()); - lite_axi_master.read(addr_t'(16'hDEAD), axi_pkg::prot_t'('0), data, resp); + $info("%0t MGR_0> Make an unmapped access read and write ", $time()); + lite_axi_manager.read(addr_t'(16'hDEAD), axi_pkg::prot_t'('0), data, resp); assert (resp == axi_pkg::RESP_SLVERR) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(addr_t'(16'hDEAD), axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'hFF, resp); + lite_axi_manager.write(addr_t'(16'hDEAD), axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'hFF, resp); assert (resp == axi_pkg::RESP_SLVERR) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(ERROR, axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'hFF, resp); + lite_axi_manager.write(ERROR, axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'hFF, resp); assert (resp == axi_pkg::RESP_SLVERR) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'h00, resp); + lite_axi_manager.write(IRQEN, axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'h00, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'h00, resp); + lite_axi_manager.write(IRQS, axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'h00, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'h00, resp); + lite_axi_manager.write(WIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'h00, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'hFF, resp); + lite_axi_manager.write(WIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), data_t'('0), 8'hFF, resp); + lite_axi_manager.write(WIRQT, axi_pkg::prot_t'('0), data_t'('0), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'h00, resp); + lite_axi_manager.write(RIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'h00, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'hFF, resp); + lite_axi_manager.write(RIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), data_t'('0), 8'hFF, resp); + lite_axi_manager.write(WIRQT, axi_pkg::prot_t'('0), data_t'('0), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end end_of_sim[0] <= 1'b1; end - initial begin : proc_master_1 - automatic rand_lite_master_t lite_axi_master = new ( master_dv[1], "MST_1"); + initial begin : proc_manager_1 + automatic rand_lite_manager_t lite_axi_manager = new ( manager_dv[1], "MGR_1"); //automatic int unsigned test_failed = 0; automatic data_t data = '0; automatic axi_pkg::resp_t resp = axi_pkg::RESP_SLVERR; automatic int unsigned loop = 0; end_of_sim[1] <= 1'b0; - lite_axi_master.reset(); + lite_axi_manager.reset(); @(posedge rst_n); // ------------------------------- // Test Flush seperately // ------------------------------- - $display("%0t MST_1> Flush Read MBOX ", $time()); - lite_axi_master.write(CTRL, axi_pkg::prot_t'('0), data_t'(2'b10), 8'hFF, resp); + $display("%0t MGR_1> Flush Read MBOX ", $time()); + lite_axi_manager.write(CTRL, axi_pkg::prot_t'('0), data_t'(2'b10), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - $display("%0t MST_1> Flush Write MBOX ", $time()); - lite_axi_master.write(CTRL, axi_pkg::prot_t'('0), data_t'(2'b01), 8'hFF, resp); + $display("%0t MGR_1> Flush Write MBOX ", $time()); + lite_axi_manager.write(CTRL, axi_pkg::prot_t'('0), data_t'(2'b01), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end // ------------------------------- // Set read and write thresholds, wait for reflect some data // ------------------------------- - $display("%0t MST_1> Set Read threshold to 64'd0 ", $time()); - lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp); + $display("%0t MGR_1> Set Read threshold to 64'd0 ", $time()); + lite_axi_manager.write(RIRQT, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - $display("%0t MST_1> Enable Read threshold interrupt ", $time()); - lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(2), 8'hFF, resp); + $display("%0t MGR_1> Enable Read threshold interrupt ", $time()); + lite_axi_manager.write(IRQEN, axi_pkg::prot_t'('0), data_t'(2), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - $display("%0t MST_1> Wait for Read threshold interrupt ", $time()); + $display("%0t MGR_1> Wait for Read threshold interrupt ", $time()); wait (irq[1]); - $display("%0t MST_1> Interrupt Recieved, read pending register and Acknowledge irq ", $time()); - lite_axi_master.read(IRQP, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_1> Interrupt Recieved, read pending register and Acknowledge irq ", $time()); + lite_axi_manager.read(IRQP, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(2)) else begin test_failed[1]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - lite_axi_master.read(IRQS, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(IRQS, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(2)) else begin test_failed[1]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - lite_axi_master.read(MBOXR, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(MBOXR, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(32'hFEEDFEED)) else begin test_failed[1]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(2), 8'h1, resp); + lite_axi_manager.write(IRQS, axi_pkg::prot_t'('0), data_t'(2), 8'h1, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - $display("%0t MST_1> Enable write threshold interrupt ", $time()); - lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), 32'h8, 8'h1, resp); + $display("%0t MGR_1> Enable write threshold interrupt ", $time()); + lite_axi_manager.write(WIRQT, axi_pkg::prot_t'('0), 32'h8, 8'h1, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(1), 8'hFF, resp); + lite_axi_manager.write(IRQEN, axi_pkg::prot_t'('0), data_t'(1), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - $display("%0t MST_1> Write back looping answer ", $time()); + $display("%0t MGR_1> Write back looping answer ", $time()); while (!irq[1]) begin - lite_axi_master.write(MBOXW, axi_pkg::prot_t'('0), data_t'(loop), 8'hFF, resp); + lite_axi_manager.write(MBOXW, axi_pkg::prot_t'('0), data_t'(loop), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end loop++; end - $display("%0t MST_1> Stop looping answer and clear interrupt", $time()); - lite_axi_master.read(IRQP, axi_pkg::prot_t'('0), data, resp); + $display("%0t MGR_1> Stop looping answer and clear interrupt", $time()); + lite_axi_manager.read(IRQP, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(1)) else begin test_failed[1]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - lite_axi_master.read(IRQS, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(IRQS, axi_pkg::prot_t'('0), data, resp); assert (data == data_t'(1)) else begin test_failed[1]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end // clear the interrupt, if the Write FIFO is status reg is below threshold - lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(STATUS, axi_pkg::prot_t'('0), data, resp); while (data[3]) begin repeat (10) @(posedge clk); - lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(STATUS, axi_pkg::prot_t'('0), data, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end end - lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(2), 8'h1, resp); + lite_axi_manager.write(IRQS, axi_pkg::prot_t'('0), data_t'(2), 8'h1, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end - lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(0), 8'h1, resp); + lite_axi_manager.write(IRQEN, axi_pkg::prot_t'('0), data_t'(0), 8'h1, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end end_of_sim[1] <= 1'b1; @@ -409,26 +409,26 @@ module tb_axi_lite_mailbox; initial begin : proc_monitor_irq_0 forever begin @(posedge irq[0]); - $info("Recieved interrupt from slave port 0"); + $info("Recieved interrupt from subordinate port 0"); end end initial begin : proc_monitor_irq_1 forever begin @(posedge irq[1]); - $info("Recieved interrupt from slave port 1"); + $info("Recieved interrupt from subordinate port 1"); end end initial begin : proc_stop_sim wait (&end_of_sim); repeat (50) @(posedge clk); - $display("Slave port 0 failed tests: %0d", test_failed[0]); - $display("Slave port 1 failed tests: %0d", test_failed[1]); + $display("Subordinate port 0 failed tests: %0d", test_failed[0]); + $display("Subordinate port 1 failed tests: %0d", test_failed[1]); if (test_failed[0] > 0 || test_failed[1] > 0) begin $fatal(1, "Simulation stopped as assertion errors have been encountered, Failure!!!"); end else begin - $info("Simulation stopped as all Masters transferred their data, Success.",); + $info("Simulation stopped as all Managers transferred their data, Success.",); end $stop(); end @@ -457,7 +457,7 @@ module tb_axi_lite_mailbox; .clk_i ( clk ), .rst_ni ( rst_n ), .test_i ( 1'b0 ), - .slv ( master ), + .sbr ( manager ), .irq_o ( irq ), .base_addr_i ( '0 ) // set base address to '0 ); diff --git a/test/tb_axi_lite_mailbox.wave.do b/test/tb_axi_lite_mailbox.wave.do index c272b4fa2..63dc996dc 100644 --- a/test/tb_axi_lite_mailbox.wave.do +++ b/test/tb_axi_lite_mailbox.wave.do @@ -5,8 +5,8 @@ add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/clk_i add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/rst_ni add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/test_i add wave -noupdate -divider Ports -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/slv_reqs_i -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/slv_resps_o +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/sbr_reqs_i +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/sbr_resps_o add wave -noupdate -divider IRQ add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/irq_o add wave -noupdate -divider {Mailbox FIFO status} @@ -20,29 +20,29 @@ add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/mbox_w_ add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/mbox_r_data add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/mbox_usage add wave -noupdate -divider {Port 0 internal} -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/w_reg_idx -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/r_reg_idx -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/status_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/error_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/wirqt_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/rirqt_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/irqs_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/irqen_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/irqp_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/ctrl_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_0/update_regs +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/w_reg_idx +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/r_reg_idx +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/status_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/error_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/wirqt_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/rirqt_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/irqs_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/irqen_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/irqp_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/ctrl_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_0/update_regs add wave -noupdate -divider {Port 1 internal} -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/w_reg_idx -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/r_reg_idx -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/status_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/error_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/wirqt_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/rirqt_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/irqs_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/irqen_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/irqp_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/ctrl_q -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_slv_port_1/update_regs +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/w_reg_idx +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/r_reg_idx +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/status_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/error_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/wirqt_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/rirqt_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/irqs_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/irqen_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/irqp_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/ctrl_q +add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/i_sbr_port_1/update_regs TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {2613 ns} 0} quietly wave cursor active 1 diff --git a/test/tb_axi_lite_regs.sv b/test/tb_axi_lite_regs.sv index 32676aa0b..5f558ba65 100644 --- a/test/tb_axi_lite_regs.sv +++ b/test/tb_axi_lite_regs.sv @@ -26,9 +26,9 @@ module tb_axi_lite_regs #( parameter bit TbPrivProtOnly = 1'b0, /// Define the parameter `SecuProtOnly` of the DUT. parameter bit TbSecuProtOnly = 1'b0, - /// Number of random writes generated by the testbench AXI4-Lite random master. + /// Number of random writes generated by the testbench AXI4-Lite random manager. parameter int unsigned TbNumWrites = 32'd1000, - /// Number of random reads generated by the testbench AXI4-Lite random master. + /// Number of random reads generated by the testbench AXI4-Lite random manager. parameter int unsigned TbNumReads = 32'd1500 ); // AXI configuration @@ -51,7 +51,7 @@ module tb_axi_lite_regs #( localparam byte_t [TbRegNumBytes-1:0] RegRstVal = '0; - typedef axi_test::axi_lite_rand_master #( + typedef axi_test::axi_lite_rand_manager #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), @@ -62,7 +62,7 @@ module tb_axi_lite_regs #( .MAX_ADDR ( EndAddr ), .MAX_READ_TXNS ( 10 ), .MAX_WRITE_TXNS ( 10 ) - ) rand_lite_master_t; + ) rand_lite_manager_t; // ------------- // DUT signals @@ -81,28 +81,28 @@ module tb_axi_lite_regs #( AXI_LITE #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) master (); + ) manager (); AXI_LITE_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) master_dv (clk); - `AXI_LITE_ASSIGN(master, master_dv) + ) manager_dv (clk); + `AXI_LITE_ASSIGN(manager, manager_dv) // ------------------------------- - // AXI Rand Masters and Slaves + // AXI Rand Managers and Subordinates // ------------------------------- - // Masters control simulation run time + // Managers control simulation run time initial begin : proc_generate_axi_traffic - automatic rand_lite_master_t lite_axi_master = new ( master_dv, "Lite Master"); + automatic rand_lite_manager_t lite_axi_manager = new ( manager_dv, "Lite Manager"); automatic axi_data_t data = '0; automatic axi_pkg::resp_t resp = '0; end_of_sim <= 1'b0; - lite_axi_master.reset(); + lite_axi_manager.reset(); @(posedge rst_n); repeat (5) @(posedge clk); // Test known register. // Write to it. - lite_axi_master.write(axi_addr_t'(32'h0000_0000), axi_pkg::prot_t'('0), + lite_axi_manager.write(axi_addr_t'(32'h0000_0000), axi_pkg::prot_t'('0), axi_data_t'(64'hDEADBEEFDEADBEEF), axi_strb_t'(8'hFF), resp); if (TbPrivProtOnly || TbSecuProtOnly) begin assert (resp == axi_pkg::RESP_SLVERR) else @@ -112,7 +112,7 @@ module tb_axi_lite_regs #( $fatal(1, "Access should be granted"); end // Read from it. - lite_axi_master.read(axi_addr_t'(32'h0000_0000), axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.read(axi_addr_t'(32'h0000_0000), axi_pkg::prot_t'('0), data, resp); if (TbPrivProtOnly || TbSecuProtOnly) begin // Expect error response assert (resp == axi_pkg::RESP_SLVERR) else @@ -126,7 +126,7 @@ module tb_axi_lite_regs #( end // Let random stimuli application checking is separate. - lite_axi_master.run(TbNumReads, TbNumWrites); + lite_axi_manager.run(TbNumReads, TbNumWrites); end_of_sim <= 1'b1; end @@ -168,8 +168,8 @@ module tb_axi_lite_regs #( #(TestTime); // Push the expected data back. - if (master.ar_valid && master.ar_ready) begin - automatic int unsigned ar_idx = ((master.ar_addr - StartAddr) + if (manager.ar_valid && manager.ar_ready) begin + automatic int unsigned ar_idx = ((manager.ar_addr - StartAddr) >> $clog2(StrbWidth) << $clog2(StrbWidth)); automatic axi_data_t r_data = axi_data_t'(0); automatic axi_pkg::resp_t r_resp = axi_pkg::RESP_SLVERR; @@ -182,10 +182,10 @@ module tb_axi_lite_regs #( end end // check the right protection access - if (TbPrivProtOnly && !master.ar_prot[0]) begin + if (TbPrivProtOnly && !manager.ar_prot[0]) begin r_resp = axi_pkg::RESP_SLVERR; end - if (TbSecuProtOnly && !master.ar_prot[1]) begin + if (TbSecuProtOnly && !manager.ar_prot[1]) begin r_resp = axi_pkg::RESP_SLVERR; end exp_resp.push_back(r_resp); @@ -193,21 +193,21 @@ module tb_axi_lite_regs #( end // compare data if there is a value expected - if (master.r_valid && master.r_ready) begin + if (manager.r_valid && manager.r_ready) begin automatic axi_data_t r_data = exp_rdata.pop_front(); - if (master.r_resp == axi_pkg::RESP_OKAY) begin + if (manager.r_resp == axi_pkg::RESP_OKAY) begin for (int unsigned i = 0; i < StrbWidth; i++) begin automatic byte_t exp_byte = r_data[8*i+:8]; if (exp_byte !== 8'hxx) begin - assert (master.r_data[8*i+:8] == exp_byte) else - $error("Unexpected read data: exp: %0h observed: %0h", r_data, master.r_data); - assert (master.r_resp == axi_pkg::RESP_OKAY); + assert (manager.r_data[8*i+:8] == exp_byte) else + $error("Unexpected read data: exp: %0h observed: %0h", r_data, manager.r_data); + assert (manager.r_resp == axi_pkg::RESP_OKAY); end end - end else if (master.r_resp == axi_pkg::RESP_SLVERR) begin - assert (master.r_data == axi_data_t'(32'hBA5E1E55)); + end else if (manager.r_resp == axi_pkg::RESP_SLVERR) begin + assert (manager.r_data == axi_data_t'(32'hBA5E1E55)); end else begin - $error("Slave responded with false response: %0h", master.r_resp); + $error("Subordinate responded with false response: %0h", manager.r_resp); end end end @@ -221,17 +221,17 @@ module tb_axi_lite_regs #( forever begin #TestTime; // AW and W is launched, setup the test tasks - if (master.aw_valid && master.aw_ready && master.w_valid && master.w_ready) begin - automatic int unsigned aw_idx = ((master.aw_addr - StartAddr) + if (manager.aw_valid && manager.aw_ready && manager.w_valid && manager.w_ready) begin + automatic int unsigned aw_idx = ((manager.aw_addr - StartAddr) >> $clog2(StrbWidth) << $clog2(StrbWidth)); automatic axi_pkg::resp_t exp_b_resp = (aw_idx < TbRegNumBytes) ? axi_pkg::RESP_OKAY : axi_pkg::RESP_SLVERR; automatic bit all_ro = 1'b1; // check for errors from wrong access protection - if (TbPrivProtOnly && !master.aw_prot[0]) begin + if (TbPrivProtOnly && !manager.aw_prot[0]) begin exp_b_resp = axi_pkg::RESP_SLVERR; end - if (TbSecuProtOnly && !master.aw_prot[1]) begin + if (TbSecuProtOnly && !manager.aw_prot[1]) begin exp_b_resp = axi_pkg::RESP_SLVERR; end // Check if all accesses bytes are read only @@ -249,14 +249,14 @@ module tb_axi_lite_regs #( // go through every byte for (int unsigned i = 0; i < StrbWidth; i++) begin if ((aw_idx+i) < TbRegNumBytes) begin - if (master.w_strb[i]) begin + if (manager.w_strb[i]) begin automatic int unsigned j = aw_idx + i; - automatic byte_t exp_byte = master.w_data[8*i+:8]; + automatic byte_t exp_byte = manager.w_data[8*i+:8]; fork check_q(j, exp_byte); join_none end - assert (master.w_strb[i] == wr_active[aw_idx+i]); + assert (manager.w_strb[i] == wr_active[aw_idx+i]); end end end @@ -271,11 +271,11 @@ module tb_axi_lite_regs #( @(posedge rst_n); forever begin #TestTime; - if (master.b_valid && master.b_ready) begin + if (manager.b_valid && manager.b_ready) begin if (b_resp_queue.size()) begin exp_b_resp = b_resp_queue.pop_front(); - assert (exp_b_resp == master.b_resp) else - $error("Unexpected B response: EXP: %b ACT: %b", exp_b_resp, master.b_resp); + assert (exp_b_resp == manager.b_resp) else + $error("Unexpected B response: EXP: %b ACT: %b", exp_b_resp, manager.b_resp); end else begin $error("B response even no AW was sent."); end @@ -324,7 +324,7 @@ module tb_axi_lite_regs #( initial begin : proc_stop_sim wait (end_of_sim); repeat (1000) @(posedge clk); - $display("Simulation stopped as Master transferred its data."); + $display("Simulation stopped as Manager transferred its data."); $stop(); end @@ -353,7 +353,7 @@ module tb_axi_lite_regs #( ) i_axi_lite_regs ( .clk_i ( clk ), .rst_ni ( rst_n ), - .slv ( master ), + .sbr ( manager ), .wr_active_o ( wr_active ), .rd_active_o ( rd_active ), .reg_d_i ( reg_d ), diff --git a/test/tb_axi_lite_to_apb.sv b/test/tb_axi_lite_to_apb.sv index 87ef07aa7..e39c0f530 100644 --- a/test/tb_axi_lite_to_apb.sv +++ b/test/tb_axi_lite_to_apb.sv @@ -24,11 +24,11 @@ module tb_axi_lite_to_apb #( parameter bit TbPipelineResponse = 1'b0 ); // Dut parameters - localparam int unsigned NumApbSlaves = 8; // How many APB Slaves there are + localparam int unsigned NumApbSlaves = 8; // How many APB Slaves there are localparam int unsigned NumAddrRules = 9; // How many address rules for the APB slaves - // Random master no Transactions - localparam int unsigned NumWrites = 10000; // How many rand writes of the master - localparam int unsigned NumReads = 20000; // How many rand reads of the master + // Random manager no Transactions + localparam int unsigned NumWrites = 10000; // How many rand writes of the manager + localparam int unsigned NumReads = 20000; // How many rand reads of the manager // timing parameters localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -83,7 +83,7 @@ module tb_axi_lite_to_apb #( '{idx: 32'd0, start_addr: 32'h0000_0000, end_addr: 32'h0000_3000} }; - typedef axi_test::axi_lite_rand_master #( + typedef axi_test::axi_lite_rand_manager #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), @@ -102,7 +102,7 @@ module tb_axi_lite_to_apb #( .W_MAX_WAIT_CYCLES ( 5 ), .RESP_MIN_WAIT_CYCLES ( 0 ), .RESP_MAX_WAIT_CYCLES ( 20 ) - ) axi_lite_rand_master_t; + ) axi_lite_rand_manager_t; // ------------- // DUT signals @@ -112,7 +112,7 @@ module tb_axi_lite_to_apb #( logic rst_n; logic end_of_sim; - // master structs + // manager structs axi_lite_req_t axi_req; axi_lite_rsp_t axi_rsp; @@ -126,25 +126,25 @@ module tb_axi_lite_to_apb #( AXI_LITE #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) master (); + ) manager (); AXI_LITE_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) master_dv (clk); - `AXI_LITE_ASSIGN(master, master_dv) - `AXI_LITE_ASSIGN_TO_REQ(axi_req, master) - `AXI_LITE_ASSIGN_FROM_RSP(master, axi_rsp) + ) manager_dv (clk); + `AXI_LITE_ASSIGN(manager, manager_dv) + `AXI_LITE_ASSIGN_TO_REQ(axi_req, manager) + `AXI_LITE_ASSIGN_FROM_RSP(manager, axi_rsp) // ------------------------------- - // AXI Rand Masters + // AXI Rand Managers // ------------------------------- - // Master controls simulation run time - initial begin : proc_axi_master - static axi_lite_rand_master_t axi_lite_rand_master = new ( master_dv , "axi_lite_mst"); + // Manager controls simulation run time + initial begin : proc_axi_manager + static axi_lite_rand_manager_t axi_lite_rand_manager = new ( manager_dv , "axi_lite_mgr"); end_of_sim <= 1'b0; - axi_lite_rand_master.reset(); + axi_lite_rand_manager.reset(); @(posedge rst_n); - axi_lite_rand_master.run(NumReads, NumWrites); + axi_lite_rand_manager.run(NumReads, NumWrites); end_of_sim <= 1'b1; end diff --git a/test/tb_axi_lite_to_axi.sv b/test/tb_axi_lite_to_axi.sv index 50a9b81fc..d628c8b57 100644 --- a/test/tb_axi_lite_to_axi.sv +++ b/test/tb_axi_lite_to_axi.sv @@ -60,8 +60,8 @@ module tb_axi_lite_to_axi; .AXI_DATA_WIDTH (TB_DW) ) i_dut ( .in ( axi_lite ), - .slv_aw_cache_i ('0), - .slv_ar_cache_i ('0), + .sbr_aw_cache_i ('0), + .sbr_ar_cache_i ('0), .out ( axi ) ); @@ -84,7 +84,7 @@ module tb_axi_lite_to_axi; initial begin automatic axi_pkg::resp_t resp; - axi_lite_drv.reset_master(); + axi_lite_drv.reset_manager(); @(posedge clk); axi_lite_drv.send_aw('hdeadbeef, axi_pkg::prot_t'('0)); axi_lite_drv.send_w('hdeadbeef, '1); @@ -98,7 +98,7 @@ module tb_axi_lite_to_axi; automatic axi_test::axi_ax_beat #(.AW(TB_AW), .IW(TB_IW), .UW(TB_UW)) ax_beat; automatic axi_test::axi_w_beat #(.DW(TB_DW), .UW(TB_UW)) w_beat; automatic axi_test::axi_b_beat #(.IW(TB_IW), .UW(TB_UW)) b_beat = new; - axi_drv.reset_slave(); + axi_drv.reset_subordinate(); @(posedge clk); axi_drv.recv_aw(ax_beat); $info("AXI AW: addr %h", ax_beat.ax_addr); diff --git a/test/tb_axi_lite_xbar.sv b/test/tb_axi_lite_xbar.sv index 13a2d6390..4c860df35 100644 --- a/test/tb_axi_lite_xbar.sv +++ b/test/tb_axi_lite_xbar.sv @@ -14,8 +14,8 @@ // - Andreas Kurth // Directed Random Verification Testbench for `axi_lite_xbar`: The crossbar is instantiated with -// a number of random axi master and slave modules. Each random master executes a fixed number of -// writes and reads over the whole addess map. All masters simultaneously issue transactions +// a number of random axi manager and subordinate modules. Each random manager executes a fixed number of +// writes and reads over the whole addess map. All managers simultaneously issue transactions // through the crossbar, thereby fully saturating all its bandwidth. `include "axi/typedef.svh" @@ -23,11 +23,11 @@ module tb_axi_lite_xbar; // Dut parameters - localparam int unsigned NumMasters = 32'd6; // How many Masters there are - localparam int unsigned NumSlaves = 32'd8; // How many Slaves there are - // Random master no Transactions - localparam int unsigned NumWrites = 32'd10000; // How many writes per master - localparam int unsigned NumReads = 32'd10000; // How many reads per master + localparam int unsigned NumManagers = 32'd6; // How many Managers there are + localparam int unsigned NumSubordinates = 32'd8; // How many Subordinates there are + // Random manager no Transactions + localparam int unsigned NumWrites = 32'd10000; // How many writes per manager + localparam int unsigned NumReads = 32'd10000; // How many reads per manager // timing parameters localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -38,10 +38,10 @@ module tb_axi_lite_xbar; localparam int unsigned StrbWidth = DataWidth / 32'd8; // in the bench can change this variables which are set here freely localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ - NumSlvPorts: NumMasters, - NumMstPorts: NumSlaves, - MaxMstTrans: 32'd10, - MaxSlvTrans: 32'd6, + NumSbrPorts: NumManagers, + NumMgrPorts: NumSubordinates, + MaxMgrTrans: 32'd10, + MaxSbrTrans: 32'd6, FallThrough: 1'b0, LatencyMode: axi_pkg::CUT_ALL_AX, AddrWidth: AddrWidth, @@ -65,7 +65,7 @@ module tb_axi_lite_xbar; '{idx: 32'd0, start_addr: 32'h0000_0000, end_addr: 32'h0000_3000} }; - typedef axi_test::axi_lite_rand_master #( + typedef axi_test::axi_lite_rand_manager #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), @@ -76,15 +76,15 @@ module tb_axi_lite_xbar; .MAX_ADDR ( 32'h0001_3000 ), .MAX_READ_TXNS ( 10 ), .MAX_WRITE_TXNS ( 10 ) - ) rand_lite_master_t; - typedef axi_test::axi_lite_rand_slave #( + ) rand_lite_manager_t; + typedef axi_test::axi_lite_rand_subordinate #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) rand_lite_slave_t; + ) rand_lite_subordinate_t; // ------------- // DUT signals @@ -92,7 +92,7 @@ module tb_axi_lite_xbar; logic clk; // DUT signals logic rst_n; - logic [NumMasters-1:0] end_of_sim; + logic [NumManagers-1:0] end_of_sim; // ------------------------------- // AXI Interfaces @@ -100,58 +100,58 @@ module tb_axi_lite_xbar; AXI_LITE #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) master [NumMasters-1:0] (); + ) manager [NumManagers-1:0] (); AXI_LITE_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) master_dv [NumMasters-1:0] (clk); - for (genvar i = 0; i < NumMasters; i++) begin : gen_conn_dv_masters - `AXI_LITE_ASSIGN(master[i], master_dv[i]) + ) manager_dv [NumManagers-1:0] (clk); + for (genvar i = 0; i < NumManagers; i++) begin : gen_conn_dv_managers + `AXI_LITE_ASSIGN(manager[i], manager_dv[i]) end AXI_LITE #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) slave [NumSlaves-1:0] (); + ) subordinate [NumSubordinates-1:0] (); AXI_LITE_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) slave_dv [NumSlaves-1:0](clk); - for (genvar i = 0; i < NumSlaves; i++) begin : gen_conn_dv_slaves - `AXI_LITE_ASSIGN(slave_dv[i], slave[i]) + ) subordinate_dv [NumSubordinates-1:0](clk); + for (genvar i = 0; i < NumSubordinates; i++) begin : gen_conn_dv_subordinates + `AXI_LITE_ASSIGN(subordinate_dv[i], subordinate[i]) end // ------------------------------- - // AXI Rand Masters and Slaves + // AXI Rand Managers and Subordinates // ------------------------------- - // Masters control simulation run time - for (genvar i = 0; i < NumMasters; i++) begin : gen_rand_master + // Managers control simulation run time + for (genvar i = 0; i < NumManagers; i++) begin : gen_rand_manager initial begin : proc_generate_traffic - automatic rand_lite_master_t lite_axi_master = new ( master_dv[i], $sformatf("MST_%0d", i)); + automatic rand_lite_manager_t lite_axi_manager = new ( manager_dv[i], $sformatf("MGR_%0d", i)); automatic data_t data = '0; automatic axi_pkg::resp_t resp = '0; end_of_sim[i] <= 1'b0; - lite_axi_master.reset(); + lite_axi_manager.reset(); @(posedge rst_n); - lite_axi_master.write(32'h0000_1100, axi_pkg::prot_t'('0), 64'hDEADBEEFDEADBEEF, 8'hFF, resp); - lite_axi_master.read(32'h0000_e100, axi_pkg::prot_t'('0), data, resp); - lite_axi_master.run(NumReads, NumWrites); + lite_axi_manager.write(32'h0000_1100, axi_pkg::prot_t'('0), 64'hDEADBEEFDEADBEEF, 8'hFF, resp); + lite_axi_manager.read(32'h0000_e100, axi_pkg::prot_t'('0), data, resp); + lite_axi_manager.run(NumReads, NumWrites); end_of_sim[i] <= 1'b1; end end - for (genvar i = 0; i < NumSlaves; i++) begin : gen_rand_slave + for (genvar i = 0; i < NumSubordinates; i++) begin : gen_rand_subordinate initial begin : proc_recieve_traffic - automatic rand_lite_slave_t lite_axi_slave = new( slave_dv[i] , $sformatf("SLV_%0d", i)); - lite_axi_slave.reset(); + automatic rand_lite_subordinate_t lite_axi_subordinate = new( subordinate_dv[i] , $sformatf("SBR_%0d", i)); + lite_axi_subordinate.reset(); @(posedge rst_n); - lite_axi_slave.run(); + lite_axi_subordinate.run(); end end initial begin : proc_stop_sim wait (&end_of_sim); repeat (1000) @(posedge clk); - $display("Simulation stopped as all Masters transferred their data, Success.",); + $display("Simulation stopped as all Managers transferred their data, Success.",); $stop(); end @@ -176,10 +176,10 @@ module tb_axi_lite_xbar; .clk_i ( clk ), .rst_ni ( rst_n ), .test_i ( 1'b0 ), - .slv_ports ( master ), - .mst_ports ( slave ), + .sbr_ports ( manager ), + .mgr_ports ( subordinate ), .addr_map_i ( AddrMap ), - .en_default_mst_port_i ( '0 ), - .default_mst_port_i ( '0 ) + .en_default_mgr_port_i ( '0 ), + .default_mgr_port_i ( '0 ) ); endmodule diff --git a/test/tb_axi_lite_xbar.wave.do b/test/tb_axi_lite_xbar.wave.do index 604e70c80..8767ae521 100644 --- a/test/tb_axi_lite_xbar.wave.do +++ b/test/tb_axi_lite_xbar.wave.do @@ -4,16 +4,16 @@ quietly WaveActivateNextPane {} 0 add wave -noupdate -label Clock /tb_axi_lite_xbar/i_xbar_dut/clk_i add wave -noupdate -label Reset /tb_axi_lite_xbar/i_xbar_dut/rst_ni add wave -noupdate -label {Test Mode} /tb_axi_lite_xbar/i_xbar_dut/test_i -add wave -noupdate -divider {Slave Ports} -add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/slv_ports_req_i -add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/slv_ports_resp_o -add wave -noupdate -divider {Master Ports} -add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/mst_ports_req_o -add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/mst_ports_resp_i +add wave -noupdate -divider {Subordinate Ports} +add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/sbr_ports_req_i +add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/sbr_ports_resp_o +add wave -noupdate -divider {Manager Ports} +add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/mgr_ports_req_o +add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/mgr_ports_resp_i add wave -noupdate -divider {Address Mapping} add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/addr_map_i -add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/en_default_mst_port_i -add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/default_mst_port_i +add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/en_default_mgr_port_i +add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/default_mgr_port_i add wave -noupdate -divider Custom TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {148 ns} 0} diff --git a/test/tb_axi_modify_address.sv b/test/tb_axi_modify_address.sv index 3fab7ff42..7d5f06012 100644 --- a/test/tb_axi_modify_address.sv +++ b/test/tb_axi_modify_address.sv @@ -17,8 +17,8 @@ /// Testbench for `axi_modify_address` module tb_axi_modify_address #( // DUT Parameters - parameter int unsigned AXI_SLV_PORT_ADDR_WIDTH = 32, - parameter int unsigned AXI_MST_PORT_ADDR_WIDTH = 48, + parameter int unsigned AXI_SBR_PORT_ADDR_WIDTH = 32, + parameter int unsigned AXI_MGR_PORT_ADDR_WIDTH = 48, parameter int unsigned AXI_DATA_WIDTH = 64, parameter int unsigned AXI_ID_WIDTH = 3, parameter int unsigned AXI_USER_WIDTH = 2, @@ -49,7 +49,7 @@ module tb_axi_modify_address #( // AXI Interfaces AXI_BUS_DV #( - .AXI_ADDR_WIDTH (AXI_SLV_PORT_ADDR_WIDTH), + .AXI_ADDR_WIDTH (AXI_SBR_PORT_ADDR_WIDTH), .AXI_DATA_WIDTH (AXI_DATA_WIDTH), .AXI_ID_WIDTH (AXI_ID_WIDTH), .AXI_USER_WIDTH (AXI_USER_WIDTH) @@ -57,14 +57,14 @@ module tb_axi_modify_address #( .clk_i (clk) ); AXI_BUS #( - .AXI_ADDR_WIDTH (AXI_SLV_PORT_ADDR_WIDTH), + .AXI_ADDR_WIDTH (AXI_SBR_PORT_ADDR_WIDTH), .AXI_DATA_WIDTH (AXI_DATA_WIDTH), .AXI_ID_WIDTH (AXI_ID_WIDTH), .AXI_USER_WIDTH (AXI_USER_WIDTH) ) upstream (); `AXI_ASSIGN(upstream, upstream_dv) AXI_BUS_DV #( - .AXI_ADDR_WIDTH (AXI_MST_PORT_ADDR_WIDTH), + .AXI_ADDR_WIDTH (AXI_MGR_PORT_ADDR_WIDTH), .AXI_DATA_WIDTH (AXI_DATA_WIDTH), .AXI_ID_WIDTH (AXI_ID_WIDTH), .AXI_USER_WIDTH (AXI_USER_WIDTH) @@ -72,7 +72,7 @@ module tb_axi_modify_address #( .clk_i (clk) ); AXI_BUS #( - .AXI_ADDR_WIDTH (AXI_MST_PORT_ADDR_WIDTH), + .AXI_ADDR_WIDTH (AXI_MGR_PORT_ADDR_WIDTH), .AXI_DATA_WIDTH (AXI_DATA_WIDTH), .AXI_ID_WIDTH (AXI_ID_WIDTH), .AXI_USER_WIDTH (AXI_USER_WIDTH) @@ -80,10 +80,10 @@ module tb_axi_modify_address #( `AXI_ASSIGN(downstream_dv, downstream) // Types - typedef logic [AXI_MST_PORT_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_MGR_PORT_ADDR_WIDTH-1:0] addr_t; typedef logic [AXI_DATA_WIDTH-1:0] data_t; typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_MST_PORT_ADDR_WIDTH-13:0] page_t; + typedef logic [AXI_MGR_PORT_ADDR_WIDTH-13:0] page_t; typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; typedef logic [AXI_USER_WIDTH-1:0] user_t; `AXI_TYPEDEF_AW_CHAN_T(aw_t, addr_t, id_t, user_t) @@ -93,24 +93,24 @@ module tb_axi_modify_address #( `AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, user_t) // DUT - addr_t mst_aw_addr, - mst_ar_addr; + addr_t mgr_aw_addr, + mgr_ar_addr; axi_modify_address_intf #( - .AXI_SLV_PORT_ADDR_WIDTH (AXI_SLV_PORT_ADDR_WIDTH), - .AXI_MST_PORT_ADDR_WIDTH (AXI_MST_PORT_ADDR_WIDTH), + .AXI_SBR_PORT_ADDR_WIDTH (AXI_SBR_PORT_ADDR_WIDTH), + .AXI_MGR_PORT_ADDR_WIDTH (AXI_MGR_PORT_ADDR_WIDTH), .AXI_DATA_WIDTH (AXI_DATA_WIDTH), .AXI_ID_WIDTH (AXI_ID_WIDTH), .AXI_USER_WIDTH (AXI_USER_WIDTH) ) i_dut ( - .slv (upstream), - .mst_aw_addr_i (mst_aw_addr), - .mst_ar_addr_i (mst_ar_addr), - .mst (downstream) + .sbr (upstream), + .mgr_aw_addr_i (mgr_aw_addr), + .mgr_ar_addr_i (mgr_ar_addr), + .mgr (downstream) ); - // Test harness master - typedef axi_test::axi_rand_master #( - .AW (AXI_SLV_PORT_ADDR_WIDTH), + // Test harness manager + typedef axi_test::axi_rand_manager #( + .AW (AXI_SBR_PORT_ADDR_WIDTH), .DW (AXI_DATA_WIDTH), .IW (AXI_ID_WIDTH), .UW (AXI_USER_WIDTH), @@ -125,18 +125,18 @@ module tb_axi_modify_address #( .RESP_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES), .RESP_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES), .AXI_MAX_BURST_LEN (16) - ) axi_master_t; - axi_master_t axi_master = new(upstream_dv); + ) axi_manager_t; + axi_manager_t axi_manager = new(upstream_dv); initial begin wait (rst_n); - axi_master.run(N_RD_TXNS, N_WR_TXNS); + axi_manager.run(N_RD_TXNS, N_WR_TXNS); #(10*TCLK); $finish(); end - // Test harness slave - typedef axi_test::axi_rand_slave #( - .AW (AXI_MST_PORT_ADDR_WIDTH), + // Test harness subordinate + typedef axi_test::axi_rand_subordinate #( + .AW (AXI_MGR_PORT_ADDR_WIDTH), .DW (AXI_DATA_WIDTH), .IW (AXI_ID_WIDTH), .UW (AXI_USER_WIDTH), @@ -148,36 +148,36 @@ module tb_axi_modify_address #( .R_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES), .RESP_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES), .RESP_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES) - ) axi_slave_t; - axi_slave_t axi_slave = new(downstream_dv); + ) axi_subordinate_t; + axi_subordinate_t axi_subordinate = new(downstream_dv); initial begin wait (rst_n); - axi_slave.run(); + axi_subordinate.run(); end // Assign offset within page from upstream. - assign mst_aw_addr[11:0] = upstream.aw_addr[11:0]; - assign mst_ar_addr[11:0] = upstream.ar_addr[11:0]; + assign mgr_aw_addr[11:0] = upstream.aw_addr[11:0]; + assign mgr_ar_addr[11:0] = upstream.ar_addr[11:0]; // Randomize page number. - page_t mst_aw_page, - mst_ar_page; - assign mst_aw_addr[AXI_MST_PORT_ADDR_WIDTH-1:12] = mst_aw_page; - assign mst_ar_addr[AXI_MST_PORT_ADDR_WIDTH-1:12] = mst_ar_page; + page_t mgr_aw_page, + mgr_ar_page; + assign mgr_aw_addr[AXI_MGR_PORT_ADDR_WIDTH-1:12] = mgr_aw_page; + assign mgr_ar_addr[AXI_MGR_PORT_ADDR_WIDTH-1:12] = mgr_ar_page; initial begin logic rand_success; - mst_aw_page = '0; - mst_ar_page = '0; + mgr_aw_page = '0; + mgr_ar_page = '0; wait (rst_n); forever begin @(posedge clk); #TA; if (!(upstream.aw_valid && !upstream.aw_ready)) begin - rand_success = std::randomize(mst_aw_page); + rand_success = std::randomize(mgr_aw_page); assert(rand_success); end if (!(upstream.ar_valid && !upstream.ar_ready)) begin - rand_success = std::randomize(mst_ar_page); + rand_success = std::randomize(mgr_ar_page); assert(rand_success); end end @@ -193,9 +193,9 @@ module tb_axi_modify_address #( // Compute expected responses. always_comb begin `AXI_SET_TO_AW(aw_exp, upstream) - aw_exp.addr = mst_aw_addr; + aw_exp.addr = mgr_aw_addr; `AXI_SET_TO_AR(ar_exp, upstream) - ar_exp.addr = mst_ar_addr; + ar_exp.addr = mgr_ar_addr; end `AXI_ASSIGN_TO_W(w_exp, upstream) `AXI_ASSIGN_TO_B(b_exp, downstream) diff --git a/test/tb_axi_serializer.sv b/test/tb_axi_serializer.sv index aa027ef41..0b3cd6b38 100644 --- a/test/tb_axi_serializer.sv +++ b/test/tb_axi_serializer.sv @@ -16,12 +16,12 @@ `include "axi/assign.svh" module tb_axi_serializer #( - parameter int unsigned NumWrites = 5000, // How many writes per master - parameter int unsigned NumReads = 3000 // How many reads per master + parameter int unsigned NumWrites = 5000, // How many writes per manager + parameter int unsigned NumReads = 3000 // How many reads per manager ); - // Random master no Transactions + // Random manager no Transactions localparam int unsigned NumPendingDut = 4; - // Random Master Atomics + // Random Manager Atomics localparam int unsigned MaxAW = 32'd30; localparam int unsigned MaxAR = 32'd30; localparam bit EnAtop = 1'b1; @@ -37,7 +37,7 @@ module tb_axi_serializer #( // Sim print config, how many transactions localparam int unsigned PrintTxn = 500; - typedef axi_test::axi_rand_master #( + typedef axi_test::axi_rand_manager #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), @@ -50,8 +50,8 @@ module tb_axi_serializer #( .MAX_READ_TXNS ( MaxAR ), .MAX_WRITE_TXNS ( MaxAW ), .AXI_ATOPS ( EnAtop ) - ) axi_rand_master_t; - typedef axi_test::axi_rand_slave #( + ) axi_rand_manager_t; + typedef axi_test::axi_rand_subordinate #( // AXI interface parameters .AW ( AddrWidth ), .DW ( DataWidth ), @@ -60,7 +60,7 @@ module tb_axi_serializer #( // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) axi_rand_slave_t; + ) axi_rand_subordinate_t; // ------------- // DUT signals @@ -75,28 +75,28 @@ module tb_axi_serializer #( .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidth ), .AXI_USER_WIDTH ( UserWidth ) - ) master (); + ) manager (); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidth ), .AXI_USER_WIDTH ( UserWidth ) - ) master_dv (clk); + ) manager_dv (clk); AXI_BUS #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidth ), .AXI_USER_WIDTH ( UserWidth ) - ) slave (); + ) subordinate (); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidth ), .AXI_USER_WIDTH ( UserWidth ) - ) slave_dv (clk); + ) subordinate_dv (clk); - `AXI_ASSIGN(master, master_dv) - `AXI_ASSIGN(slave_dv, slave) + `AXI_ASSIGN(manager, manager_dv) + `AXI_ASSIGN(subordinate_dv, subordinate) //----------------------------------- // Clock generator @@ -122,29 +122,29 @@ module tb_axi_serializer #( ) i_dut ( .clk_i ( clk ), // clock .rst_ni ( rst_n ), // asynchronous reset active low - .slv ( master ), // slave port - .mst ( slave ) // master port + .sbr ( manager ), // subordinate port + .mgr ( subordinate ) // manager port ); - initial begin : proc_axi_master - automatic axi_rand_master_t axi_rand_master = new(master_dv); + initial begin : proc_axi_manager + automatic axi_rand_manager_t axi_rand_manager = new(manager_dv); end_of_sim <= 1'b0; - axi_rand_master.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE); - axi_rand_master.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE); - axi_rand_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); - axi_rand_master.reset(); + axi_rand_manager.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_manager.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE); + axi_rand_manager.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); + axi_rand_manager.reset(); @(posedge rst_n); - axi_rand_master.run(NumReads, NumWrites); + axi_rand_manager.run(NumReads, NumWrites); end_of_sim <= 1'b1; repeat (100) @(posedge clk); $stop(); end - initial begin : proc_axi_slave - automatic axi_rand_slave_t axi_rand_slave = new(slave_dv); - axi_rand_slave.reset(); + initial begin : proc_axi_subordinate + automatic axi_rand_subordinate_t axi_rand_subordinate = new(subordinate_dv); + axi_rand_subordinate.reset(); @(posedge rst_n); - axi_rand_slave.run(); + axi_rand_subordinate.run(); end // Checker @@ -182,36 +182,36 @@ module tb_axi_serializer #( @(posedge clk); #TestTime; // All FIFOs get populated if there is something to put in - if (master.aw_valid && master.aw_ready) begin - `AXI_SET_TO_AW(aw_exp, master) + if (manager.aw_valid && manager.aw_ready) begin + `AXI_SET_TO_AW(aw_exp, manager) aw_exp.id = '0; - id_exp = master.aw_id; + id_exp = manager.aw_id; aw_chan.push_back(aw_exp); aw_queue.push_back(id_exp); - if (master.aw_atop[axi_pkg::ATOP_R_RESP]) begin + if (manager.aw_atop[axi_pkg::ATOP_R_RESP]) begin ar_queue.push_back(id_exp); end end - if (master.w_valid && master.w_ready) begin - `AXI_SET_TO_W(w_exp, master) + if (manager.w_valid && manager.w_ready) begin + `AXI_SET_TO_W(w_exp, manager) w_chan.push_back(w_exp); end - if (slave.b_valid && slave.b_ready) begin + if (subordinate.b_valid && subordinate.b_ready) begin id_exp = aw_queue.pop_front(); - `AXI_SET_TO_B(b_exp, slave) + `AXI_SET_TO_B(b_exp, subordinate) b_exp.id = id_exp; b_chan.push_back(b_exp); end - if (master.ar_valid && master.ar_ready) begin - `AXI_SET_TO_AR(ar_exp, master) + if (manager.ar_valid && manager.ar_ready) begin + `AXI_SET_TO_AR(ar_exp, manager) ar_exp.id = '0; - id_exp = master.ar_id; + id_exp = manager.ar_id; ar_chan.push_back(ar_exp); ar_queue.push_back(id_exp); end - if (slave.r_valid && slave.r_ready) begin - `AXI_SET_TO_R(r_exp, slave) - if (slave.r_last) begin + if (subordinate.r_valid && subordinate.r_ready) begin + `AXI_SET_TO_R(r_exp, subordinate) + if (subordinate.r_last) begin id_exp = ar_queue.pop_front(); end else begin id_exp = ar_queue[0]; @@ -220,29 +220,29 @@ module tb_axi_serializer #( r_chan.push_back(r_exp); end // Check that all channels match the expected response - if (slave.aw_valid && slave.aw_ready) begin + if (subordinate.aw_valid && subordinate.aw_ready) begin aw_exp = aw_chan.pop_front(); - `AXI_SET_TO_AW(aw_act, slave) + `AXI_SET_TO_AW(aw_act, subordinate) assert(aw_act == aw_exp) else $error("AW Measured: %h Expected: %h", aw_act, aw_exp); end - if (slave.w_valid && slave.w_ready) begin + if (subordinate.w_valid && subordinate.w_ready) begin w_exp = w_chan.pop_front(); - `AXI_SET_TO_W(w_act, slave) + `AXI_SET_TO_W(w_act, subordinate) assert(w_act == w_exp) else $error("W Measured: %h Expected: %h", w_act, w_exp); end - if (master.b_valid && master.b_ready) begin + if (manager.b_valid && manager.b_ready) begin b_exp = b_chan.pop_front(); - `AXI_SET_TO_B(b_act, master) + `AXI_SET_TO_B(b_act, manager) assert(b_act == b_exp) else $error("B Measured: %h Expected: %h", b_act, b_exp); end - if (slave.ar_valid && slave.ar_ready) begin + if (subordinate.ar_valid && subordinate.ar_ready) begin ar_exp = ar_chan.pop_front(); - `AXI_SET_TO_AR(ar_act, slave) + `AXI_SET_TO_AR(ar_act, subordinate) assert(ar_act == ar_exp) else $error("AR Measured: %h Expected: %h", ar_act, ar_exp); end - if (master.r_valid && master.r_ready) begin + if (manager.r_valid && manager.r_ready) begin r_exp = r_chan.pop_front(); - `AXI_SET_TO_R(r_act, master) + `AXI_SET_TO_R(r_act, manager) assert(r_act == r_exp) else $error("R Measured: %h Expected: %h", r_act, r_exp); end end @@ -259,10 +259,10 @@ module tb_axi_serializer #( forever begin @(posedge clk); #TestTime; - if (master.aw_valid && master.aw_ready) begin + if (manager.aw_valid && manager.aw_ready) begin aw++; end - if (master.ar_valid && master.ar_ready) begin + if (manager.ar_valid && manager.ar_ready) begin ar++; end diff --git a/test/tb_axi_serializer.wave.do b/test/tb_axi_serializer.wave.do index b89af5c98..4658a5ed5 100644 --- a/test/tb_axi_serializer.wave.do +++ b/test/tb_axi_serializer.wave.do @@ -2,10 +2,10 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/clk_i add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/rst_ni -add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/slv_req_i -add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/slv_resp_o -add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/mst_req_o -add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/mst_resp_i +add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/sbr_req_i +add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/sbr_resp_o +add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/mgr_req_o +add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/mgr_resp_i add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/rd_fifo_full add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/rd_fifo_empty add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/rd_fifo_push diff --git a/test/tb_axi_sim_mem.sv b/test/tb_axi_sim_mem.sv index d6a899fc1..e1a54c98f 100644 --- a/test/tb_axi_sim_mem.sv +++ b/test/tb_axi_sim_mem.sv @@ -71,7 +71,7 @@ module tb_axi_sim_mem #( ) i_sim_mem ( .clk_i (clk), .rst_ni (rst_n), - .axi_slv (axi) + .axi_sbr (axi) ); // Simply read and write a random memory region. @@ -82,7 +82,7 @@ module tb_axi_sim_mem #( automatic drv_t::w_beat_t w_beat = new; automatic drv_t::b_beat_t b_beat; automatic drv_t::r_beat_t r_beat; - drv.reset_master(); + drv.reset_manager(); wait (rst_n); // AW `ifdef XSIM diff --git a/test/tb_axi_slave_compare.sv b/test/tb_axi_subordinate_compare.sv similarity index 95% rename from test/tb_axi_slave_compare.sv rename to test/tb_axi_subordinate_compare.sv index 1b8a37d40..46a20baaf 100644 --- a/test/tb_axi_slave_compare.sv +++ b/test/tb_axi_subordinate_compare.sv @@ -7,8 +7,8 @@ `include "axi/assign.svh" `include "axi/typedef.svh" -/// Testbench for `axi_slave_compare` -module tb_axi_slave_compare #( +/// Testbench for `axi_subordinate_compare` +module tb_axi_subordinate_compare #( // TB Parameters parameter time TbTclk = 10ns, // Module Parameters @@ -67,7 +67,7 @@ module tb_axi_slave_compare #( `AXI_ASSIGN_TO_REQ(axi_req, axi) `AXI_ASSIGN_FROM_RSP(axi, axi_rsp) - axi_slave_compare #( + axi_subordinate_compare #( .IdWidth ( TbIdWidth ), .FifoDepth ( 32'd16 ), .axi_aw_chan_t ( axi_aw_chan_t ), @@ -81,8 +81,8 @@ module tb_axi_slave_compare #( .clk_i ( clk ), .rst_ni ( rst_n ), .testmode_i ( 1'b0 ), - .axi_mst_req_i ( axi_req ), - .axi_mst_rsp_o ( axi_rsp ), + .axi_mgr_req_i ( axi_req ), + .axi_mgr_rsp_o ( axi_rsp ), .axi_ref_req_o ( axi_req_a_out ), .axi_ref_rsp_i ( axi_rsp_a_out ), .axi_test_req_o ( axi_req_b_out ), @@ -138,10 +138,10 @@ module tb_axi_slave_compare #( ) i_axi_multicut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .slv_req_i ( axi_req_b_out ), - .slv_rsp_o ( axi_rsp_b_out ), - .mst_req_o ( axi_req_b_dly ), - .mst_rsp_i ( axi_rsp_b_dly ) + .sbr_req_i ( axi_req_b_out ), + .sbr_rsp_o ( axi_rsp_b_out ), + .mgr_req_o ( axi_req_b_dly ), + .mgr_rsp_i ( axi_rsp_b_dly ) ); axi_sim_mem #( @@ -183,7 +183,7 @@ module tb_axi_slave_compare #( automatic drv_t::w_beat_t w_beat = new; automatic drv_t::b_beat_t b_beat; automatic drv_t::r_beat_t r_beat; - drv.reset_master(); + drv.reset_manager(); wait (rst_n); // AW `ifdef XSIM diff --git a/test/tb_axi_to_axi_lite.sv b/test/tb_axi_to_axi_lite.sv index e854cb106..69646e7c5 100644 --- a/test/tb_axi_to_axi_lite.sv +++ b/test/tb_axi_to_axi_lite.sv @@ -75,11 +75,11 @@ module tb_axi_to_axi_lite; .clk_i ( clk ), .rst_ni ( rst ), .testmode_i ( 1'b0 ), - .slv ( axi ), - .mst ( axi_lite ) + .sbr ( axi ), + .mgr ( axi_lite ) ); - typedef axi_test::axi_rand_master #( + typedef axi_test::axi_rand_manager #( // AXI interface parameters .AW ( AW ), .DW ( DW ), @@ -92,11 +92,11 @@ module tb_axi_to_axi_lite; .MAX_READ_TXNS ( MAX_READ_TXNS ), .MAX_WRITE_TXNS ( MAX_WRITE_TXNS ), .AXI_ATOPS ( AXI_ATOPS ) - ) axi_rand_master_t; - typedef axi_test::axi_lite_rand_slave #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)) axi_lite_rand_slv_t; + ) axi_rand_manager_t; + typedef axi_test::axi_lite_rand_subordinate #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)) axi_lite_rand_sbr_t; - axi_lite_rand_slv_t axi_lite_drv = new(axi_lite_dv, "axi_lite_rand_slave"); - axi_rand_master_t axi_drv = new(axi_dv); + axi_lite_rand_sbr_t axi_lite_drv = new(axi_lite_dv, "axi_lite_rand_subordinate"); + axi_rand_manager_t axi_drv = new(axi_dv); initial begin #tCK; diff --git a/test/tb_axi_to_mem_banked.sv b/test/tb_axi_to_mem_banked.sv index d6414c682..f00bcad7f 100644 --- a/test/tb_axi_to_mem_banked.sv +++ b/test/tb_axi_to_mem_banked.sv @@ -48,7 +48,7 @@ module tb_axi_to_mem_banked #( typedef logic [AddrWidth-1:0] axi_addr_t; // AXI test defines - typedef axi_test::axi_rand_master #( + typedef axi_test::axi_rand_manager #( // AXI interface parameters .AW ( AddrWidth ), .DW ( TbDataWidth ), @@ -75,7 +75,7 @@ module tb_axi_to_mem_banked #( .AXI_BURST_FIXED ( 1'b0 ), .AXI_BURST_INCR ( 1'b1 ), .AXI_BURST_WRAP ( 1'b0 ) - ) axi_rand_master_t; + ) axi_rand_manager_t; // memory defines localparam int unsigned MemAddrWidth = $clog2(TbNumWords); @@ -125,16 +125,16 @@ module tb_axi_to_mem_banked #( `AXI_ASSIGN(mem_axi, mem_axi_dv) // stimuli generation - initial begin : proc_axi_master - static axi_rand_master_t axi_rand_master = new ( mem_axi_dv ); + initial begin : proc_axi_manager + static axi_rand_manager_t axi_rand_manager = new ( mem_axi_dv ); end_of_sim <= 1'b0; - axi_rand_master.add_memory_region(StartAddr, EndAddr, axi_pkg::DEVICE_NONBUFFERABLE); - axi_rand_master.reset(); + axi_rand_manager.add_memory_region(StartAddr, EndAddr, axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_manager.reset(); @(posedge rst_n); @(posedge clk); @(posedge clk); - axi_rand_master.run(TbNumReads, TbNumWrites); + axi_rand_manager.run(TbNumReads, TbNumWrites); end_of_sim <= 1'b1; end @@ -200,7 +200,7 @@ module tb_axi_to_mem_banked #( .rst_ni ( rst_n ), .test_i ( 1'b0 ), .axi_to_mem_busy_o ( dut_busy ), - .slv ( mem_axi ), + .sbr ( mem_axi ), .mem_req_o ( mem_req ), .mem_gnt_i ( mem_gnt ), .mem_add_o ( mem_addr ), // byte address diff --git a/test/tb_axi_xbar.sv b/test/tb_axi_xbar.sv index d67b7c3f2..cbd0d45e8 100644 --- a/test/tb_axi_xbar.sv +++ b/test/tb_axi_xbar.sv @@ -14,10 +14,10 @@ // - Andreas Kurth // Directed Random Verification Testbench for `axi_xbar`: The crossbar is instantiated with -// a number of random axi master and slave modules. Each random master executes a fixed number of -// writes and reads over the whole addess map. All masters simultaneously issue transactions +// a number of random axi manager and subordinate modules. Each random manager executes a fixed number of +// writes and reads over the whole addess map. All managers simultaneously issue transactions // through the crossbar, thereby saturating it. A monitor, which snoops the transactions of each -// master and slave port and models the crossbar with a network of FIFOs, checks whether each +// manager and subordinate port and models the crossbar with a network of FIFOs, checks whether each // transaction follows the expected route. `include "axi/typedef.svh" @@ -25,19 +25,19 @@ /// Testbench for the module `axi_xbar`. module tb_axi_xbar #( - /// Number of AXI masters connected to the xbar. (Number of slave ports) - parameter int unsigned TbNumMasters = 32'd6, - /// Number of AXI slaves connected to the xbar. (Number of master ports) - parameter int unsigned TbNumSlaves = 32'd8, - /// Number of write transactions per master. + /// Number of AXI managers connected to the xbar. (Number of subordinate ports) + parameter int unsigned TbNumManagers = 32'd6, + /// Number of AXI subordinates connected to the xbar. (Number of manager ports) + parameter int unsigned TbNumSubordinates = 32'd8, + /// Number of write transactions per manager. parameter int unsigned TbNumWrites = 32'd200, - /// Number of read transactions per master. + /// Number of read transactions per manager. parameter int unsigned TbNumReads = 32'd200, - /// AXI4+ATOP ID width of the masters connected to the slave ports of the DUT. - /// The ID width of the slaves is calculated depending on the xbar configuration. - parameter int unsigned TbIdWidthMasters = 32'd5, + /// AXI4+ATOP ID width of the managers connected to the subordinate ports of the DUT. + /// The ID width of the subordinates is calculated depending on the xbar configuration. + parameter int unsigned TbIdWidthManagers = 32'd5, /// The used ID width of the DUT. - /// Has to be `TbIdWidthMasters >= TbIdUsed`. + /// Has to be `TbIdWidthManagers >= TbIdUsed`. parameter int unsigned TbIdUsed = 32'd3, /// Data width of the AXI channels. parameter int unsigned TbDataWidth = 32'd64, @@ -58,51 +58,51 @@ module tb_axi_xbar #( localparam time TestTime = 8ns; // AXI configuration which is automatically derived. - localparam int unsigned TbIdWidthSlaves = TbIdWidthMasters + $clog2(TbNumMasters); + localparam int unsigned TbIdWidthSubordinates = TbIdWidthManagers + $clog2(TbNumManagers); localparam int unsigned TbAddrWidth = 32'd32; localparam int unsigned TbStrbWidth = TbDataWidth / 8; localparam int unsigned TbUserWidth = 5; // In the bench can change this variables which are set here freely, localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ - NumSlvPorts: TbNumMasters, - NumMstPorts: TbNumSlaves, - MaxMstTrans: 10, - MaxSlvTrans: 6, + NumSbrPorts: TbNumManagers, + NumMgrPorts: TbNumSubordinates, + MaxMgrTrans: 10, + MaxSbrTrans: 6, FallThrough: 1'b0, LatencyMode: axi_pkg::CUT_ALL_AX, PipelineStages: TbPipeline, - IdWidthSlvPorts: TbIdWidthMasters, - IdUsedSlvPorts: TbIdUsed, + IdWidthSbrPorts: TbIdWidthManagers, + IdUsedSbrPorts: TbIdUsed, UniqueIds: TbUniqueIds, AddrWidth: TbAddrWidth, DataWidth: TbDataWidth, - NumAddrRules: TbNumSlaves + NumAddrRules: TbNumSubordinates }; - typedef logic [TbIdWidthMasters-1:0] id_mst_t; - typedef logic [TbIdWidthSlaves-1:0] id_slv_t; + typedef logic [TbIdWidthManagers-1:0] id_mgr_t; + typedef logic [TbIdWidthSubordinates-1:0] id_sbr_t; typedef logic [TbAddrWidth-1:0] addr_t; typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr typedef logic [TbDataWidth-1:0] data_t; typedef logic [TbStrbWidth-1:0] strb_t; typedef logic [TbUserWidth-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mst_t, addr_t, id_mst_t, user_t) - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_slv_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mgr_t, addr_t, id_mgr_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_sbr_t, addr_t, id_sbr_t, user_t) `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_mst_t, id_mst_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_slv_t, id_slv_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mgr_t, id_mgr_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_sbr_t, id_sbr_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mst_t, addr_t, id_mst_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_slv_t, addr_t, id_slv_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_mst_t, data_t, id_mst_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_slv_t, data_t, id_slv_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mgr_t, addr_t, id_mgr_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_sbr_t, addr_t, id_sbr_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mgr_t, data_t, id_mgr_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_sbr_t, data_t, id_sbr_t, user_t) - `AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t) - `AXI_TYPEDEF_RSP_T(mst_rsp_t, b_chan_mst_t, r_chan_mst_t) - `AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t) - `AXI_TYPEDEF_RSP_T(slv_rsp_t, b_chan_slv_t, r_chan_slv_t) + `AXI_TYPEDEF_REQ_T(mgr_req_t, aw_chan_mgr_t, w_chan_t, ar_chan_mgr_t) + `AXI_TYPEDEF_RSP_T(mgr_rsp_t, b_chan_mgr_t, r_chan_mgr_t) + `AXI_TYPEDEF_REQ_T(sbr_req_t, aw_chan_sbr_t, w_chan_t, ar_chan_sbr_t) + `AXI_TYPEDEF_RSP_T(sbr_rsp_t, b_chan_sbr_t, r_chan_sbr_t) - // Each slave has its own address range: + // Each subordinate has its own address range: localparam rule_t [xbar_cfg.NumAddrRules-1:0] AddrMap = addr_map_gen(); function rule_t [xbar_cfg.NumAddrRules-1:0] addr_map_gen (); @@ -116,11 +116,11 @@ module tb_axi_xbar #( end endfunction - typedef axi_test::axi_rand_master #( + typedef axi_test::axi_rand_manager #( // AXI interface parameters .AW ( TbAddrWidth ), .DW ( TbDataWidth ), - .IW ( TbIdWidthMasters ), + .IW ( TbIdWidthManagers ), .UW ( TbUserWidth ), // Stimuli application and test time .TA ( ApplTime ), @@ -131,17 +131,17 @@ module tb_axi_xbar #( .AXI_EXCLS ( TbEnExcl ), .AXI_ATOPS ( TbEnAtop ), .UNIQUE_IDS ( TbUniqueIds ) - ) axi_rand_master_t; - typedef axi_test::axi_rand_slave #( + ) axi_rand_manager_t; + typedef axi_test::axi_rand_subordinate #( // AXI interface parameters .AW ( TbAddrWidth ), .DW ( TbDataWidth ), - .IW ( TbIdWidthSlaves ), + .IW ( TbIdWidthSubordinates ), .UW ( TbUserWidth ), // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) axi_rand_slave_t; + ) axi_rand_subordinate_t; // ------------- // DUT signals @@ -149,15 +149,15 @@ module tb_axi_xbar #( logic clk; // DUT signals logic rst_n; - logic [TbNumMasters-1:0] end_of_sim; + logic [TbNumManagers-1:0] end_of_sim; - // master structs - mst_req_t [TbNumMasters-1:0] masters_req; - mst_rsp_t [TbNumMasters-1:0] masters_rsp; + // manager structs + mgr_req_t [TbNumManagers-1:0] managers_req; + mgr_rsp_t [TbNumManagers-1:0] managers_rsp; - // slave structs - slv_req_t [TbNumSlaves-1:0] slaves_req; - slv_rsp_t [TbNumSlaves-1:0] slaves_rsp; + // subordinate structs + sbr_req_t [TbNumSubordinates-1:0] subordinates_req; + sbr_rsp_t [TbNumSubordinates-1:0] subordinates_rsp; // ------------------------------- // AXI Interfaces @@ -165,76 +165,76 @@ module tb_axi_xbar #( AXI_BUS #( .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), - .AXI_ID_WIDTH ( TbIdWidthMasters ), + .AXI_ID_WIDTH ( TbIdWidthManagers ), .AXI_USER_WIDTH ( TbUserWidth ) - ) master [TbNumMasters-1:0] (); + ) manager [TbNumManagers-1:0] (); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), - .AXI_ID_WIDTH ( TbIdWidthMasters ), + .AXI_ID_WIDTH ( TbIdWidthManagers ), .AXI_USER_WIDTH ( TbUserWidth ) - ) master_dv [TbNumMasters-1:0] (clk); + ) manager_dv [TbNumManagers-1:0] (clk); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), - .AXI_ID_WIDTH ( TbIdWidthMasters ), + .AXI_ID_WIDTH ( TbIdWidthManagers ), .AXI_USER_WIDTH ( TbUserWidth ) - ) master_monitor_dv [TbNumMasters-1:0] (clk); - for (genvar i = 0; i < TbNumMasters; i++) begin : gen_conn_dv_masters - `AXI_ASSIGN (master[i], master_dv[i]) - `AXI_ASSIGN_TO_REQ(masters_req[i], master[i]) - `AXI_ASSIGN_TO_RSP(masters_rsp[i], master[i]) + ) manager_monitor_dv [TbNumManagers-1:0] (clk); + for (genvar i = 0; i < TbNumManagers; i++) begin : gen_conn_dv_managers + `AXI_ASSIGN (manager[i], manager_dv[i]) + `AXI_ASSIGN_TO_REQ(managers_req[i], manager[i]) + `AXI_ASSIGN_TO_RSP(managers_rsp[i], manager[i]) end AXI_BUS #( .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), - .AXI_ID_WIDTH ( TbIdWidthSlaves ), + .AXI_ID_WIDTH ( TbIdWidthSubordinates ), .AXI_USER_WIDTH ( TbUserWidth ) - ) slave [TbNumSlaves-1:0] (); + ) subordinate [TbNumSubordinates-1:0] (); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), - .AXI_ID_WIDTH ( TbIdWidthSlaves ), + .AXI_ID_WIDTH ( TbIdWidthSubordinates ), .AXI_USER_WIDTH ( TbUserWidth ) - ) slave_dv [TbNumSlaves-1:0](clk); + ) subordinate_dv [TbNumSubordinates-1:0](clk); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( TbAddrWidth ), .AXI_DATA_WIDTH ( TbDataWidth ), - .AXI_ID_WIDTH ( TbIdWidthSlaves ), + .AXI_ID_WIDTH ( TbIdWidthSubordinates ), .AXI_USER_WIDTH ( TbUserWidth ) - ) slave_monitor_dv [TbNumSlaves-1:0](clk); - for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_conn_dv_slaves - `AXI_ASSIGN(slave_dv[i], slave[i]) - `AXI_ASSIGN_TO_REQ(slaves_req[i], slave[i]) - `AXI_ASSIGN_TO_RSP(slaves_rsp[i], slave[i]) + ) subordinate_monitor_dv [TbNumSubordinates-1:0](clk); + for (genvar i = 0; i < TbNumSubordinates; i++) begin : gen_conn_dv_subordinates + `AXI_ASSIGN(subordinate_dv[i], subordinate[i]) + `AXI_ASSIGN_TO_REQ(subordinates_req[i], subordinate[i]) + `AXI_ASSIGN_TO_RSP(subordinates_rsp[i], subordinate[i]) end // ------------------------------- - // AXI Rand Masters and Slaves + // AXI Rand Managers and Subordinates // ------------------------------- - // Masters control simulation run time - axi_rand_master_t axi_rand_master [TbNumMasters]; - for (genvar i = 0; i < TbNumMasters; i++) begin : gen_rand_master + // Managers control simulation run time + axi_rand_manager_t axi_rand_manager [TbNumManagers]; + for (genvar i = 0; i < TbNumManagers; i++) begin : gen_rand_manager initial begin - axi_rand_master[i] = new( master_dv[i] ); + axi_rand_manager[i] = new( manager_dv[i] ); end_of_sim[i] <= 1'b0; - axi_rand_master[i].add_memory_region(AddrMap[0].start_addr, + axi_rand_manager[i].add_memory_region(AddrMap[0].start_addr, AddrMap[xbar_cfg.NumAddrRules-1].end_addr, axi_pkg::DEVICE_NONBUFFERABLE); - axi_rand_master[i].reset(); + axi_rand_manager[i].reset(); @(posedge rst_n); - axi_rand_master[i].run(TbNumReads, TbNumWrites); + axi_rand_manager[i].run(TbNumReads, TbNumWrites); end_of_sim[i] <= 1'b1; end end - axi_rand_slave_t axi_rand_slave [TbNumSlaves]; - for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_rand_slave + axi_rand_subordinate_t axi_rand_subordinate [TbNumSubordinates]; + for (genvar i = 0; i < TbNumSubordinates; i++) begin : gen_rand_subordinate initial begin - axi_rand_slave[i] = new( slave_dv[i] ); - axi_rand_slave[i].reset(); + axi_rand_subordinate[i] = new( subordinate_dv[i] ); + axi_rand_subordinate[i].reset(); @(posedge rst_n); - axi_rand_slave[i].run(); + axi_rand_subordinate[i].run(); end end @@ -242,16 +242,16 @@ module tb_axi_xbar #( static tb_axi_xbar_pkg::axi_xbar_monitor #( .AddrWidth ( TbAddrWidth ), .DataWidth ( TbDataWidth ), - .IdWidthMasters ( TbIdWidthMasters ), - .IdWidthSlaves ( TbIdWidthSlaves ), + .IdWidthManagers ( TbIdWidthManagers ), + .IdWidthSubordinates ( TbIdWidthSubordinates ), .UserWidth ( TbUserWidth ), - .NumMasters ( TbNumMasters ), - .NumSlaves ( TbNumSlaves ), + .NumManagers ( TbNumManagers ), + .NumSubordinates ( TbNumSubordinates ), .NumAddrRules ( xbar_cfg.NumAddrRules ), .rule_t ( rule_t ), .AddrMap ( AddrMap ), .TimeTest ( TestTime ) - ) monitor = new( master_monitor_dv, slave_monitor_dv ); + ) monitor = new( manager_monitor_dv, subordinate_monitor_dv ); fork monitor.run(); do begin @@ -287,179 +287,179 @@ module tb_axi_xbar #( .clk_i ( clk ), .rst_ni ( rst_n ), .test_i ( 1'b0 ), - .slv_ports ( master ), - .mst_ports ( slave ), + .sbr_ports ( manager ), + .mgr_ports ( subordinate ), .addr_map_i ( AddrMap ), - .en_default_mst_port_i ( '0 ), - .default_mst_port_i ( '0 ) + .en_default_mgr_port_i ( '0 ), + .default_mgr_port_i ( '0 ) ); - // logger for master modules - for (genvar i = 0; i < TbNumMasters; i++) begin : gen_master_logger + // logger for manager modules + for (genvar i = 0; i < TbNumManagers; i++) begin : gen_manager_logger axi_chan_logger #( .TestTime ( TestTime ), // Time after clock, where sampling happens - .LoggerName( $sformatf("axi_logger_master_%0d", i)), - .aw_chan_t ( aw_chan_mst_t ), // axi AW type + .LoggerName( $sformatf("axi_logger_manager_%0d", i)), + .aw_chan_t ( aw_chan_mgr_t ), // axi AW type .w_chan_t ( w_chan_t ), // axi W type - .b_chan_t ( b_chan_mst_t ), // axi B type - .ar_chan_t ( ar_chan_mst_t ), // axi AR type - .r_chan_t ( r_chan_mst_t ) // axi R type - ) i_mst_channel_logger ( + .b_chan_t ( b_chan_mgr_t ), // axi B type + .ar_chan_t ( ar_chan_mgr_t ), // axi AR type + .r_chan_t ( r_chan_mgr_t ) // axi R type + ) i_mgr_channel_logger ( .clk_i ( clk ), // Clock .rst_ni ( rst_n ), // Asynchronous reset active low, when `1'b0` no sampling .end_sim_i ( &end_of_sim ), // AW channel - .aw_chan_i ( masters_req[i].aw ), - .aw_valid_i ( masters_req[i].aw_valid ), - .aw_ready_i ( masters_rsp[i].aw_ready ), + .aw_chan_i ( managers_req[i].aw ), + .aw_valid_i ( managers_req[i].aw_valid ), + .aw_ready_i ( managers_rsp[i].aw_ready ), // W channel - .w_chan_i ( masters_req[i].w ), - .w_valid_i ( masters_req[i].w_valid ), - .w_ready_i ( masters_rsp[i].w_ready ), + .w_chan_i ( managers_req[i].w ), + .w_valid_i ( managers_req[i].w_valid ), + .w_ready_i ( managers_rsp[i].w_ready ), // B channel - .b_chan_i ( masters_rsp[i].b ), - .b_valid_i ( masters_rsp[i].b_valid ), - .b_ready_i ( masters_req[i].b_ready ), + .b_chan_i ( managers_rsp[i].b ), + .b_valid_i ( managers_rsp[i].b_valid ), + .b_ready_i ( managers_req[i].b_ready ), // AR channel - .ar_chan_i ( masters_req[i].ar ), - .ar_valid_i ( masters_req[i].ar_valid ), - .ar_ready_i ( masters_rsp[i].ar_ready ), + .ar_chan_i ( managers_req[i].ar ), + .ar_valid_i ( managers_req[i].ar_valid ), + .ar_ready_i ( managers_rsp[i].ar_ready ), // R channel - .r_chan_i ( masters_rsp[i].r ), - .r_valid_i ( masters_rsp[i].r_valid ), - .r_ready_i ( masters_req[i].r_ready ) + .r_chan_i ( managers_rsp[i].r ), + .r_valid_i ( managers_rsp[i].r_valid ), + .r_ready_i ( managers_req[i].r_ready ) ); end - // logger for slave modules - for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_slave_logger + // logger for subordinate modules + for (genvar i = 0; i < TbNumSubordinates; i++) begin : gen_subordinate_logger axi_chan_logger #( .TestTime ( TestTime ), // Time after clock, where sampling happens - .LoggerName( $sformatf("axi_logger_slave_%0d",i)), - .aw_chan_t ( aw_chan_slv_t ), // axi AW type + .LoggerName( $sformatf("axi_logger_subordinate_%0d",i)), + .aw_chan_t ( aw_chan_sbr_t ), // axi AW type .w_chan_t ( w_chan_t ), // axi W type - .b_chan_t ( b_chan_slv_t ), // axi B type - .ar_chan_t ( ar_chan_slv_t ), // axi AR type - .r_chan_t ( r_chan_slv_t ) // axi R type - ) i_slv_channel_logger ( + .b_chan_t ( b_chan_sbr_t ), // axi B type + .ar_chan_t ( ar_chan_sbr_t ), // axi AR type + .r_chan_t ( r_chan_sbr_t ) // axi R type + ) i_sbr_channel_logger ( .clk_i ( clk ), // Clock .rst_ni ( rst_n ), // Asynchronous reset active low, when `1'b0` no sampling .end_sim_i ( &end_of_sim ), // AW channel - .aw_chan_i ( slaves_req[i].aw ), - .aw_valid_i ( slaves_req[i].aw_valid ), - .aw_ready_i ( slaves_rsp[i].aw_ready ), + .aw_chan_i ( subordinates_req[i].aw ), + .aw_valid_i ( subordinates_req[i].aw_valid ), + .aw_ready_i ( subordinates_rsp[i].aw_ready ), // W channel - .w_chan_i ( slaves_req[i].w ), - .w_valid_i ( slaves_req[i].w_valid ), - .w_ready_i ( slaves_rsp[i].w_ready ), + .w_chan_i ( subordinates_req[i].w ), + .w_valid_i ( subordinates_req[i].w_valid ), + .w_ready_i ( subordinates_rsp[i].w_ready ), // B channel - .b_chan_i ( slaves_rsp[i].b ), - .b_valid_i ( slaves_rsp[i].b_valid ), - .b_ready_i ( slaves_req[i].b_ready ), + .b_chan_i ( subordinates_rsp[i].b ), + .b_valid_i ( subordinates_rsp[i].b_valid ), + .b_ready_i ( subordinates_req[i].b_ready ), // AR channel - .ar_chan_i ( slaves_req[i].ar ), - .ar_valid_i ( slaves_req[i].ar_valid ), - .ar_ready_i ( slaves_rsp[i].ar_ready ), + .ar_chan_i ( subordinates_req[i].ar ), + .ar_valid_i ( subordinates_req[i].ar_valid ), + .ar_ready_i ( subordinates_rsp[i].ar_ready ), // R channel - .r_chan_i ( slaves_rsp[i].r ), - .r_valid_i ( slaves_rsp[i].r_valid ), - .r_ready_i ( slaves_req[i].r_ready ) + .r_chan_i ( subordinates_rsp[i].r ), + .r_valid_i ( subordinates_rsp[i].r_valid ), + .r_ready_i ( subordinates_req[i].r_ready ) ); end - for (genvar i = 0; i < TbNumMasters; i++) begin : gen_connect_master_monitor - assign master_monitor_dv[i].aw_id = master[i].aw_id ; - assign master_monitor_dv[i].aw_addr = master[i].aw_addr ; - assign master_monitor_dv[i].aw_len = master[i].aw_len ; - assign master_monitor_dv[i].aw_size = master[i].aw_size ; - assign master_monitor_dv[i].aw_burst = master[i].aw_burst ; - assign master_monitor_dv[i].aw_lock = master[i].aw_lock ; - assign master_monitor_dv[i].aw_cache = master[i].aw_cache ; - assign master_monitor_dv[i].aw_prot = master[i].aw_prot ; - assign master_monitor_dv[i].aw_qos = master[i].aw_qos ; - assign master_monitor_dv[i].aw_region = master[i].aw_region; - assign master_monitor_dv[i].aw_atop = master[i].aw_atop ; - assign master_monitor_dv[i].aw_user = master[i].aw_user ; - assign master_monitor_dv[i].aw_valid = master[i].aw_valid ; - assign master_monitor_dv[i].aw_ready = master[i].aw_ready ; - assign master_monitor_dv[i].w_data = master[i].w_data ; - assign master_monitor_dv[i].w_strb = master[i].w_strb ; - assign master_monitor_dv[i].w_last = master[i].w_last ; - assign master_monitor_dv[i].w_user = master[i].w_user ; - assign master_monitor_dv[i].w_valid = master[i].w_valid ; - assign master_monitor_dv[i].w_ready = master[i].w_ready ; - assign master_monitor_dv[i].b_id = master[i].b_id ; - assign master_monitor_dv[i].b_resp = master[i].b_resp ; - assign master_monitor_dv[i].b_user = master[i].b_user ; - assign master_monitor_dv[i].b_valid = master[i].b_valid ; - assign master_monitor_dv[i].b_ready = master[i].b_ready ; - assign master_monitor_dv[i].ar_id = master[i].ar_id ; - assign master_monitor_dv[i].ar_addr = master[i].ar_addr ; - assign master_monitor_dv[i].ar_len = master[i].ar_len ; - assign master_monitor_dv[i].ar_size = master[i].ar_size ; - assign master_monitor_dv[i].ar_burst = master[i].ar_burst ; - assign master_monitor_dv[i].ar_lock = master[i].ar_lock ; - assign master_monitor_dv[i].ar_cache = master[i].ar_cache ; - assign master_monitor_dv[i].ar_prot = master[i].ar_prot ; - assign master_monitor_dv[i].ar_qos = master[i].ar_qos ; - assign master_monitor_dv[i].ar_region = master[i].ar_region; - assign master_monitor_dv[i].ar_user = master[i].ar_user ; - assign master_monitor_dv[i].ar_valid = master[i].ar_valid ; - assign master_monitor_dv[i].ar_ready = master[i].ar_ready ; - assign master_monitor_dv[i].r_id = master[i].r_id ; - assign master_monitor_dv[i].r_data = master[i].r_data ; - assign master_monitor_dv[i].r_resp = master[i].r_resp ; - assign master_monitor_dv[i].r_last = master[i].r_last ; - assign master_monitor_dv[i].r_user = master[i].r_user ; - assign master_monitor_dv[i].r_valid = master[i].r_valid ; - assign master_monitor_dv[i].r_ready = master[i].r_ready ; + for (genvar i = 0; i < TbNumManagers; i++) begin : gen_connect_manager_monitor + assign manager_monitor_dv[i].aw_id = manager[i].aw_id ; + assign manager_monitor_dv[i].aw_addr = manager[i].aw_addr ; + assign manager_monitor_dv[i].aw_len = manager[i].aw_len ; + assign manager_monitor_dv[i].aw_size = manager[i].aw_size ; + assign manager_monitor_dv[i].aw_burst = manager[i].aw_burst ; + assign manager_monitor_dv[i].aw_lock = manager[i].aw_lock ; + assign manager_monitor_dv[i].aw_cache = manager[i].aw_cache ; + assign manager_monitor_dv[i].aw_prot = manager[i].aw_prot ; + assign manager_monitor_dv[i].aw_qos = manager[i].aw_qos ; + assign manager_monitor_dv[i].aw_region = manager[i].aw_region; + assign manager_monitor_dv[i].aw_atop = manager[i].aw_atop ; + assign manager_monitor_dv[i].aw_user = manager[i].aw_user ; + assign manager_monitor_dv[i].aw_valid = manager[i].aw_valid ; + assign manager_monitor_dv[i].aw_ready = manager[i].aw_ready ; + assign manager_monitor_dv[i].w_data = manager[i].w_data ; + assign manager_monitor_dv[i].w_strb = manager[i].w_strb ; + assign manager_monitor_dv[i].w_last = manager[i].w_last ; + assign manager_monitor_dv[i].w_user = manager[i].w_user ; + assign manager_monitor_dv[i].w_valid = manager[i].w_valid ; + assign manager_monitor_dv[i].w_ready = manager[i].w_ready ; + assign manager_monitor_dv[i].b_id = manager[i].b_id ; + assign manager_monitor_dv[i].b_resp = manager[i].b_resp ; + assign manager_monitor_dv[i].b_user = manager[i].b_user ; + assign manager_monitor_dv[i].b_valid = manager[i].b_valid ; + assign manager_monitor_dv[i].b_ready = manager[i].b_ready ; + assign manager_monitor_dv[i].ar_id = manager[i].ar_id ; + assign manager_monitor_dv[i].ar_addr = manager[i].ar_addr ; + assign manager_monitor_dv[i].ar_len = manager[i].ar_len ; + assign manager_monitor_dv[i].ar_size = manager[i].ar_size ; + assign manager_monitor_dv[i].ar_burst = manager[i].ar_burst ; + assign manager_monitor_dv[i].ar_lock = manager[i].ar_lock ; + assign manager_monitor_dv[i].ar_cache = manager[i].ar_cache ; + assign manager_monitor_dv[i].ar_prot = manager[i].ar_prot ; + assign manager_monitor_dv[i].ar_qos = manager[i].ar_qos ; + assign manager_monitor_dv[i].ar_region = manager[i].ar_region; + assign manager_monitor_dv[i].ar_user = manager[i].ar_user ; + assign manager_monitor_dv[i].ar_valid = manager[i].ar_valid ; + assign manager_monitor_dv[i].ar_ready = manager[i].ar_ready ; + assign manager_monitor_dv[i].r_id = manager[i].r_id ; + assign manager_monitor_dv[i].r_data = manager[i].r_data ; + assign manager_monitor_dv[i].r_resp = manager[i].r_resp ; + assign manager_monitor_dv[i].r_last = manager[i].r_last ; + assign manager_monitor_dv[i].r_user = manager[i].r_user ; + assign manager_monitor_dv[i].r_valid = manager[i].r_valid ; + assign manager_monitor_dv[i].r_ready = manager[i].r_ready ; end - for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_connect_slave_monitor - assign slave_monitor_dv[i].aw_id = slave[i].aw_id ; - assign slave_monitor_dv[i].aw_addr = slave[i].aw_addr ; - assign slave_monitor_dv[i].aw_len = slave[i].aw_len ; - assign slave_monitor_dv[i].aw_size = slave[i].aw_size ; - assign slave_monitor_dv[i].aw_burst = slave[i].aw_burst ; - assign slave_monitor_dv[i].aw_lock = slave[i].aw_lock ; - assign slave_monitor_dv[i].aw_cache = slave[i].aw_cache ; - assign slave_monitor_dv[i].aw_prot = slave[i].aw_prot ; - assign slave_monitor_dv[i].aw_qos = slave[i].aw_qos ; - assign slave_monitor_dv[i].aw_region = slave[i].aw_region; - assign slave_monitor_dv[i].aw_atop = slave[i].aw_atop ; - assign slave_monitor_dv[i].aw_user = slave[i].aw_user ; - assign slave_monitor_dv[i].aw_valid = slave[i].aw_valid ; - assign slave_monitor_dv[i].aw_ready = slave[i].aw_ready ; - assign slave_monitor_dv[i].w_data = slave[i].w_data ; - assign slave_monitor_dv[i].w_strb = slave[i].w_strb ; - assign slave_monitor_dv[i].w_last = slave[i].w_last ; - assign slave_monitor_dv[i].w_user = slave[i].w_user ; - assign slave_monitor_dv[i].w_valid = slave[i].w_valid ; - assign slave_monitor_dv[i].w_ready = slave[i].w_ready ; - assign slave_monitor_dv[i].b_id = slave[i].b_id ; - assign slave_monitor_dv[i].b_resp = slave[i].b_resp ; - assign slave_monitor_dv[i].b_user = slave[i].b_user ; - assign slave_monitor_dv[i].b_valid = slave[i].b_valid ; - assign slave_monitor_dv[i].b_ready = slave[i].b_ready ; - assign slave_monitor_dv[i].ar_id = slave[i].ar_id ; - assign slave_monitor_dv[i].ar_addr = slave[i].ar_addr ; - assign slave_monitor_dv[i].ar_len = slave[i].ar_len ; - assign slave_monitor_dv[i].ar_size = slave[i].ar_size ; - assign slave_monitor_dv[i].ar_burst = slave[i].ar_burst ; - assign slave_monitor_dv[i].ar_lock = slave[i].ar_lock ; - assign slave_monitor_dv[i].ar_cache = slave[i].ar_cache ; - assign slave_monitor_dv[i].ar_prot = slave[i].ar_prot ; - assign slave_monitor_dv[i].ar_qos = slave[i].ar_qos ; - assign slave_monitor_dv[i].ar_region = slave[i].ar_region; - assign slave_monitor_dv[i].ar_user = slave[i].ar_user ; - assign slave_monitor_dv[i].ar_valid = slave[i].ar_valid ; - assign slave_monitor_dv[i].ar_ready = slave[i].ar_ready ; - assign slave_monitor_dv[i].r_id = slave[i].r_id ; - assign slave_monitor_dv[i].r_data = slave[i].r_data ; - assign slave_monitor_dv[i].r_resp = slave[i].r_resp ; - assign slave_monitor_dv[i].r_last = slave[i].r_last ; - assign slave_monitor_dv[i].r_user = slave[i].r_user ; - assign slave_monitor_dv[i].r_valid = slave[i].r_valid ; - assign slave_monitor_dv[i].r_ready = slave[i].r_ready ; + for (genvar i = 0; i < TbNumSubordinates; i++) begin : gen_connect_subordinate_monitor + assign subordinate_monitor_dv[i].aw_id = subordinate[i].aw_id ; + assign subordinate_monitor_dv[i].aw_addr = subordinate[i].aw_addr ; + assign subordinate_monitor_dv[i].aw_len = subordinate[i].aw_len ; + assign subordinate_monitor_dv[i].aw_size = subordinate[i].aw_size ; + assign subordinate_monitor_dv[i].aw_burst = subordinate[i].aw_burst ; + assign subordinate_monitor_dv[i].aw_lock = subordinate[i].aw_lock ; + assign subordinate_monitor_dv[i].aw_cache = subordinate[i].aw_cache ; + assign subordinate_monitor_dv[i].aw_prot = subordinate[i].aw_prot ; + assign subordinate_monitor_dv[i].aw_qos = subordinate[i].aw_qos ; + assign subordinate_monitor_dv[i].aw_region = subordinate[i].aw_region; + assign subordinate_monitor_dv[i].aw_atop = subordinate[i].aw_atop ; + assign subordinate_monitor_dv[i].aw_user = subordinate[i].aw_user ; + assign subordinate_monitor_dv[i].aw_valid = subordinate[i].aw_valid ; + assign subordinate_monitor_dv[i].aw_ready = subordinate[i].aw_ready ; + assign subordinate_monitor_dv[i].w_data = subordinate[i].w_data ; + assign subordinate_monitor_dv[i].w_strb = subordinate[i].w_strb ; + assign subordinate_monitor_dv[i].w_last = subordinate[i].w_last ; + assign subordinate_monitor_dv[i].w_user = subordinate[i].w_user ; + assign subordinate_monitor_dv[i].w_valid = subordinate[i].w_valid ; + assign subordinate_monitor_dv[i].w_ready = subordinate[i].w_ready ; + assign subordinate_monitor_dv[i].b_id = subordinate[i].b_id ; + assign subordinate_monitor_dv[i].b_resp = subordinate[i].b_resp ; + assign subordinate_monitor_dv[i].b_user = subordinate[i].b_user ; + assign subordinate_monitor_dv[i].b_valid = subordinate[i].b_valid ; + assign subordinate_monitor_dv[i].b_ready = subordinate[i].b_ready ; + assign subordinate_monitor_dv[i].ar_id = subordinate[i].ar_id ; + assign subordinate_monitor_dv[i].ar_addr = subordinate[i].ar_addr ; + assign subordinate_monitor_dv[i].ar_len = subordinate[i].ar_len ; + assign subordinate_monitor_dv[i].ar_size = subordinate[i].ar_size ; + assign subordinate_monitor_dv[i].ar_burst = subordinate[i].ar_burst ; + assign subordinate_monitor_dv[i].ar_lock = subordinate[i].ar_lock ; + assign subordinate_monitor_dv[i].ar_cache = subordinate[i].ar_cache ; + assign subordinate_monitor_dv[i].ar_prot = subordinate[i].ar_prot ; + assign subordinate_monitor_dv[i].ar_qos = subordinate[i].ar_qos ; + assign subordinate_monitor_dv[i].ar_region = subordinate[i].ar_region; + assign subordinate_monitor_dv[i].ar_user = subordinate[i].ar_user ; + assign subordinate_monitor_dv[i].ar_valid = subordinate[i].ar_valid ; + assign subordinate_monitor_dv[i].ar_ready = subordinate[i].ar_ready ; + assign subordinate_monitor_dv[i].r_id = subordinate[i].r_id ; + assign subordinate_monitor_dv[i].r_data = subordinate[i].r_data ; + assign subordinate_monitor_dv[i].r_resp = subordinate[i].r_resp ; + assign subordinate_monitor_dv[i].r_last = subordinate[i].r_last ; + assign subordinate_monitor_dv[i].r_user = subordinate[i].r_user ; + assign subordinate_monitor_dv[i].r_valid = subordinate[i].r_valid ; + assign subordinate_monitor_dv[i].r_ready = subordinate[i].r_ready ; end endmodule diff --git a/test/tb_axi_xbar.wave.do b/test/tb_axi_xbar.wave.do index 23a9095a2..2b21fe682 100644 --- a/test/tb_axi_xbar.wave.do +++ b/test/tb_axi_xbar.wave.do @@ -4,16 +4,16 @@ quietly WaveActivateNextPane {} 0 add wave -noupdate -label Clock /tb_axi_xbar/i_xbar_dut/clk_i add wave -noupdate -label Reset /tb_axi_xbar/i_xbar_dut/rst_ni add wave -noupdate -label {Test Mode} /tb_axi_xbar/i_xbar_dut/test_i -add wave -noupdate -divider {Slave Ports} -add wave -noupdate /tb_axi_xbar/i_xbar_dut/slv_ports_req_i -add wave -noupdate /tb_axi_xbar/i_xbar_dut/slv_ports_resp_o -add wave -noupdate -divider {Master Ports} -add wave -noupdate /tb_axi_xbar/i_xbar_dut/mst_ports_req_o -add wave -noupdate /tb_axi_xbar/i_xbar_dut/mst_ports_resp_i +add wave -noupdate -divider {Subordinate Ports} +add wave -noupdate /tb_axi_xbar/i_xbar_dut/sbr_ports_req_i +add wave -noupdate /tb_axi_xbar/i_xbar_dut/sbr_ports_resp_o +add wave -noupdate -divider {Manager Ports} +add wave -noupdate /tb_axi_xbar/i_xbar_dut/mgr_ports_req_o +add wave -noupdate /tb_axi_xbar/i_xbar_dut/mgr_ports_resp_i add wave -noupdate -divider {Address Mapping} add wave -noupdate /tb_axi_xbar/i_xbar_dut/addr_map_i -add wave -noupdate /tb_axi_xbar/i_xbar_dut/en_default_mst_port_i -add wave -noupdate /tb_axi_xbar/i_xbar_dut/default_mst_port_i +add wave -noupdate /tb_axi_xbar/i_xbar_dut/en_default_mgr_port_i +add wave -noupdate /tb_axi_xbar/i_xbar_dut/default_mgr_port_i add wave -noupdate -divider Custom TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {148 ns} 0} diff --git a/test/tb_axi_xbar_pkg.sv b/test/tb_axi_xbar_pkg.sv index 57da2369b..7b786dad3 100644 --- a/test/tb_axi_xbar_pkg.sv +++ b/test/tb_axi_xbar_pkg.sv @@ -13,7 +13,7 @@ // - Wolfgang Roenninger // `axi_xbar_monitor` implements an AXI bus monitor that is tuned for the AXI crossbar. -// It snoops on each of the slaves and master ports of the crossbar and +// It snoops on each of the subordinates and manager ports of the crossbar and // populates FIFOs and ID queues to validate that no AXI beats get // lost or sent to the wrong destination. @@ -21,51 +21,51 @@ package tb_axi_xbar_pkg; class axi_xbar_monitor #( parameter int unsigned AddrWidth, parameter int unsigned DataWidth, - parameter int unsigned IdWidthMasters, - parameter int unsigned IdWidthSlaves, + parameter int unsigned IdWidthManagers, + parameter int unsigned IdWidthSubordinates, parameter int unsigned UserWidth, - parameter int unsigned NumMasters, - parameter int unsigned NumSlaves, + parameter int unsigned NumManagers, + parameter int unsigned NumSubordinates, parameter int unsigned NumAddrRules, parameter type rule_t, parameter rule_t [NumAddrRules-1:0] AddrMap, // Stimuli application and test time parameter time TimeTest ); - typedef logic [IdWidthMasters-1:0] mst_axi_id_t; - typedef logic [IdWidthSlaves-1:0] slv_axi_id_t; + typedef logic [IdWidthManagers-1:0] mgr_axi_id_t; + typedef logic [IdWidthSubordinates-1:0] sbr_axi_id_t; typedef logic [AddrWidth-1:0] axi_addr_t; - typedef logic [$clog2(NumMasters)-1:0] idx_mst_t; - typedef int unsigned idx_slv_t; // from rule_t + typedef logic [$clog2(NumManagers)-1:0] idx_mgr_t; + typedef int unsigned idx_sbr_t; // from rule_t typedef struct packed { - mst_axi_id_t mst_axi_id; + mgr_axi_id_t mgr_axi_id; logic last; - } master_exp_t; + } manager_exp_t; typedef struct packed { - slv_axi_id_t slv_axi_id; - axi_addr_t slv_axi_addr; - axi_pkg::len_t slv_axi_len; + sbr_axi_id_t sbr_axi_id; + axi_addr_t sbr_axi_addr; + axi_pkg::len_t sbr_axi_len; } exp_ax_t; typedef struct packed { - slv_axi_id_t slv_axi_id; + sbr_axi_id_t sbr_axi_id; logic last; - } slave_exp_t; + } subordinate_exp_t; typedef rand_id_queue_pkg::rand_id_queue #( - .data_t ( master_exp_t ), - .ID_WIDTH ( IdWidthMasters ) - ) master_exp_queue_t; + .data_t ( manager_exp_t ), + .ID_WIDTH ( IdWidthManagers ) + ) manager_exp_queue_t; typedef rand_id_queue_pkg::rand_id_queue #( .data_t ( exp_ax_t ), - .ID_WIDTH ( IdWidthSlaves ) + .ID_WIDTH ( IdWidthSubordinates ) ) ax_queue_t; typedef rand_id_queue_pkg::rand_id_queue #( - .data_t ( slave_exp_t ), - .ID_WIDTH ( IdWidthSlaves ) - ) slave_exp_queue_t; + .data_t ( subordinate_exp_t ), + .ID_WIDTH ( IdWidthSubordinates ) + ) subordinate_exp_queue_t; //----------------------------------------- // Monitoring virtual interfaces @@ -73,27 +73,27 @@ package tb_axi_xbar_pkg; virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), - .AXI_ID_WIDTH ( IdWidthMasters ), + .AXI_ID_WIDTH ( IdWidthManagers ), .AXI_USER_WIDTH ( UserWidth ) - ) masters_axi [NumMasters-1:0]; + ) managers_axi [NumManagers-1:0]; virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), - .AXI_ID_WIDTH ( IdWidthSlaves ), + .AXI_ID_WIDTH ( IdWidthSubordinates ), .AXI_USER_WIDTH ( UserWidth ) - ) slaves_axi [NumSlaves-1:0]; + ) subordinates_axi [NumSubordinates-1:0]; //----------------------------------------- // Queues and FIFOs to hold the expected ids //----------------------------------------- // Write transactions - ax_queue_t exp_aw_queue [NumSlaves-1:0]; - slave_exp_t exp_w_fifo [NumSlaves-1:0][$]; - slave_exp_t act_w_fifo [NumSlaves-1:0][$]; - master_exp_queue_t exp_b_queue [NumMasters-1:0]; + ax_queue_t exp_aw_queue [NumSubordinates-1:0]; + subordinate_exp_t exp_w_fifo [NumSubordinates-1:0][$]; + subordinate_exp_t act_w_fifo [NumSubordinates-1:0][$]; + manager_exp_queue_t exp_b_queue [NumManagers-1:0]; // Read transactions - ax_queue_t exp_ar_queue [NumSlaves-1:0]; - master_exp_queue_t exp_r_queue [NumMasters-1:0]; + ax_queue_t exp_ar_queue [NumSubordinates-1:0]; + manager_exp_queue_t exp_r_queue [NumManagers-1:0]; //----------------------------------------- // Bookkeeping @@ -110,27 +110,27 @@ package tb_axi_xbar_pkg; virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), - .AXI_ID_WIDTH ( IdWidthMasters ), + .AXI_ID_WIDTH ( IdWidthManagers ), .AXI_USER_WIDTH ( UserWidth ) - ) axi_masters_vif [NumMasters-1:0], + ) axi_managers_vif [NumManagers-1:0], virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), - .AXI_ID_WIDTH ( IdWidthSlaves ), + .AXI_ID_WIDTH ( IdWidthSubordinates ), .AXI_USER_WIDTH ( UserWidth ) - ) axi_slaves_vif [NumSlaves-1:0] + ) axi_subordinates_vif [NumSubordinates-1:0] ); begin - this.masters_axi = axi_masters_vif; - this.slaves_axi = axi_slaves_vif; + this.managers_axi = axi_managers_vif; + this.subordinates_axi = axi_subordinates_vif; this.tests_expected = 0; this.tests_conducted = 0; this.tests_failed = 0; - for (int unsigned i = 0; i < NumMasters; i++) begin + for (int unsigned i = 0; i < NumManagers; i++) begin this.exp_b_queue[i] = new; this.exp_r_queue[i] = new; end - for (int unsigned i = 0; i < NumSlaves; i++) begin + for (int unsigned i = 0; i < NumSubordinates; i++) begin this.exp_aw_queue[i] = new; this.exp_ar_queue[i] = new; end @@ -145,121 +145,121 @@ package tb_axi_xbar_pkg; // when is cycle finished task cycle_end; - @(posedge masters_axi[0].clk_i); + @(posedge managers_axi[0].clk_i); endtask - // This task monitors a slave ports of the crossbar. Every time an AW beat is seen - // it populates an id queue at the right master port (if there is no expected decode error), + // This task monitors a subordinate ports of the crossbar. Every time an AW beat is seen + // it populates an id queue at the right manager port (if there is no expected decode error), // populates the expected b response in its own id_queue and in case when the atomic bit [5] // is set it also injects an expected response in the R channel. - task automatic monitor_mst_aw(input int unsigned i); - idx_slv_t to_slave_idx; + task automatic monitor_mgr_aw(input int unsigned i); + idx_sbr_t to_subordinate_idx; exp_ax_t exp_aw; - slv_axi_id_t exp_aw_id; + sbr_axi_id_t exp_aw_id; bit decerr; - master_exp_t exp_b; + manager_exp_t exp_b; - if (masters_axi[i].aw_valid && masters_axi[i].aw_ready) begin + if (managers_axi[i].aw_valid && managers_axi[i].aw_ready) begin // check if it should go to a decerror decerr = 1'b1; for (int unsigned j = 0; j < NumAddrRules; j++) begin - if ((masters_axi[i].aw_addr >= AddrMap[j].start_addr) && - (masters_axi[i].aw_addr < AddrMap[j].end_addr)) begin - to_slave_idx = idx_slv_t'(AddrMap[j].idx); + if ((managers_axi[i].aw_addr >= AddrMap[j].start_addr) && + (managers_axi[i].aw_addr < AddrMap[j].end_addr)) begin + to_subordinate_idx = idx_sbr_t'(AddrMap[j].idx); decerr = 1'b0; end end - // send the exp aw beat down into the queue of the slave when no decerror + // send the exp aw beat down into the queue of the subordinate when no decerror if (!decerr) begin - exp_aw_id = {idx_mst_t'(i), masters_axi[i].aw_id}; + exp_aw_id = {idx_mgr_t'(i), managers_axi[i].aw_id}; // $display("Test exp aw_id: %b",exp_aw_id); - exp_aw = '{slv_axi_id: exp_aw_id, - slv_axi_addr: masters_axi[i].aw_addr, - slv_axi_len: masters_axi[i].aw_len }; - this.exp_aw_queue[to_slave_idx].push(exp_aw_id, exp_aw); + exp_aw = '{sbr_axi_id: exp_aw_id, + sbr_axi_addr: managers_axi[i].aw_addr, + sbr_axi_len: managers_axi[i].aw_len }; + this.exp_aw_queue[to_subordinate_idx].push(exp_aw_id, exp_aw); incr_expected_tests(3); - $display("%0tns > Master %0d: AW to Slave %0d: Axi ID: %b", - $time, i, to_slave_idx, masters_axi[i].aw_id); + $display("%0tns > Manager %0d: AW to Subordinate %0d: Axi ID: %b", + $time, i, to_subordinate_idx, managers_axi[i].aw_id); end else begin - $display("%0tns > Master %0d: AW to Decerror: Axi ID: %b", - $time, i, to_slave_idx, masters_axi[i].aw_id); + $display("%0tns > Manager %0d: AW to Decerror: Axi ID: %b", + $time, i, to_subordinate_idx, managers_axi[i].aw_id); end // populate the expected b queue anyway - exp_b = '{mst_axi_id: masters_axi[i].aw_id, last: 1'b1}; - this.exp_b_queue[i].push(masters_axi[i].aw_id, exp_b); + exp_b = '{mgr_axi_id: managers_axi[i].aw_id, last: 1'b1}; + this.exp_b_queue[i].push(managers_axi[i].aw_id, exp_b); incr_expected_tests(1); $display(" Expect B response."); // inject expected r beats on this id, if it is an atop - if(masters_axi[i].aw_atop[5]) begin + if(managers_axi[i].aw_atop[5]) begin // push the required r beats into the right fifo (reuse the exp_b variable) - $display(" Expect R response, len: %0d.", masters_axi[i].aw_len); - for (int unsigned j = 0; j <= masters_axi[i].aw_len; j++) begin - exp_b = (j == masters_axi[i].aw_len) ? - '{mst_axi_id: masters_axi[i].aw_id, last: 1'b1} : - '{mst_axi_id: masters_axi[i].aw_id, last: 1'b0}; - this.exp_r_queue[i].push(masters_axi[i].aw_id, exp_b); + $display(" Expect R response, len: %0d.", managers_axi[i].aw_len); + for (int unsigned j = 0; j <= managers_axi[i].aw_len; j++) begin + exp_b = (j == managers_axi[i].aw_len) ? + '{mgr_axi_id: managers_axi[i].aw_id, last: 1'b1} : + '{mgr_axi_id: managers_axi[i].aw_id, last: 1'b0}; + this.exp_r_queue[i].push(managers_axi[i].aw_id, exp_b); incr_expected_tests(1); end end end - endtask : monitor_mst_aw + endtask : monitor_mgr_aw - // This task monitors a slave port of the crossbar. Every time there is an AW vector it + // This task monitors a subordinate port of the crossbar. Every time there is an AW vector it // gets checked for its contents and if it was expected. The task then pushes an expected // amount of W beats in the respective fifo. Emphasis of the last flag. - task automatic monitor_slv_aw(input int unsigned i); + task automatic monitor_sbr_aw(input int unsigned i); exp_ax_t exp_aw; - slave_exp_t exp_slv_w; + subordinate_exp_t exp_sbr_w; // $display("%0t > Was triggered: aw_valid %b, aw_ready: %b", - // $time(), slaves_axi[i].aw_valid, slaves_axi[i].aw_ready); - if (slaves_axi[i].aw_valid && slaves_axi[i].aw_ready) begin + // $time(), subordinates_axi[i].aw_valid, subordinates_axi[i].aw_ready); + if (subordinates_axi[i].aw_valid && subordinates_axi[i].aw_ready) begin // test if the aw beat was expected - exp_aw = this.exp_aw_queue[i].pop_id(slaves_axi[i].aw_id); - $display("%0tns > Slave %0d: AW Axi ID: %b", - $time, i, slaves_axi[i].aw_id); - if (exp_aw.slv_axi_id != slaves_axi[i].aw_id) begin + exp_aw = this.exp_aw_queue[i].pop_id(subordinates_axi[i].aw_id); + $display("%0tns > Subordinate %0d: AW Axi ID: %b", + $time, i, subordinates_axi[i].aw_id); + if (exp_aw.sbr_axi_id != subordinates_axi[i].aw_id) begin incr_failed_tests(1); - $warning("Slave %0d: Unexpected AW with ID: %b", i, slaves_axi[i].aw_id); + $warning("Subordinate %0d: Unexpected AW with ID: %b", i, subordinates_axi[i].aw_id); end - if (exp_aw.slv_axi_addr != slaves_axi[i].aw_addr) begin + if (exp_aw.sbr_axi_addr != subordinates_axi[i].aw_addr) begin incr_failed_tests(1); - $warning("Slave %0d: Unexpected AW with ID: %b and ADDR: %h, exp: %h", - i, slaves_axi[i].aw_id, slaves_axi[i].aw_addr, exp_aw.slv_axi_addr); + $warning("Subordinate %0d: Unexpected AW with ID: %b and ADDR: %h, exp: %h", + i, subordinates_axi[i].aw_id, subordinates_axi[i].aw_addr, exp_aw.sbr_axi_addr); end - if (exp_aw.slv_axi_len != slaves_axi[i].aw_len) begin + if (exp_aw.sbr_axi_len != subordinates_axi[i].aw_len) begin incr_failed_tests(1); - $warning("Slave %0d: Unexpected AW with ID: %b and LEN: %h, exp: %h", - i, slaves_axi[i].aw_id, slaves_axi[i].aw_len, exp_aw.slv_axi_len); + $warning("Subordinate %0d: Unexpected AW with ID: %b and LEN: %h, exp: %h", + i, subordinates_axi[i].aw_id, subordinates_axi[i].aw_len, exp_aw.sbr_axi_len); end incr_conducted_tests(3); // push the required w beats into the right fifo - incr_expected_tests(slaves_axi[i].aw_len + 1); - for (int unsigned j = 0; j <= slaves_axi[i].aw_len; j++) begin - exp_slv_w = (j == slaves_axi[i].aw_len) ? - '{slv_axi_id: slaves_axi[i].aw_id, last: 1'b1} : - '{slv_axi_id: slaves_axi[i].aw_id, last: 1'b0}; - this.exp_w_fifo[i].push_back(exp_slv_w); + incr_expected_tests(subordinates_axi[i].aw_len + 1); + for (int unsigned j = 0; j <= subordinates_axi[i].aw_len; j++) begin + exp_sbr_w = (j == subordinates_axi[i].aw_len) ? + '{sbr_axi_id: subordinates_axi[i].aw_id, last: 1'b1} : + '{sbr_axi_id: subordinates_axi[i].aw_id, last: 1'b0}; + this.exp_w_fifo[i].push_back(exp_sbr_w); end end - endtask : monitor_slv_aw - - // This task just pushes every W beat that gets sent on a master port in its respective fifo. - task automatic monitor_slv_w(input int unsigned i); - slave_exp_t act_slv_w; - if (slaves_axi[i].w_valid && slaves_axi[i].w_ready) begin - // $display("%0t > W beat on Slave %0d, last flag: %b", $time, i, slaves_axi[i].w_last); - act_slv_w = '{last: slaves_axi[i].w_last , default:'0}; - this.act_w_fifo[i].push_back(act_slv_w); + endtask : monitor_sbr_aw + + // This task just pushes every W beat that gets sent on a manager port in its respective fifo. + task automatic monitor_sbr_w(input int unsigned i); + subordinate_exp_t act_sbr_w; + if (subordinates_axi[i].w_valid && subordinates_axi[i].w_ready) begin + // $display("%0t > W beat on Subordinate %0d, last flag: %b", $time, i, subordinates_axi[i].w_last); + act_sbr_w = '{last: subordinates_axi[i].w_last , default:'0}; + this.act_w_fifo[i].push_back(act_sbr_w); end - endtask : monitor_slv_w + endtask : monitor_sbr_w - // This task compares the expected and actual W beats on a master port. The reason that - // this is not done in `monitor_slv_w` is that there can be per protocol W beats on the - // channel, before AW is sent to the slave. - task automatic check_slv_w(input int unsigned i); - slave_exp_t exp_w, act_w; + // This task compares the expected and actual W beats on a manager port. The reason that + // this is not done in `monitor_sbr_w` is that there can be per protocol W beats on the + // channel, before AW is sent to the subordinate. + task automatic check_sbr_w(input int unsigned i); + subordinate_exp_t exp_w, act_w; while (this.exp_w_fifo[i].size() != 0 && this.act_w_fifo[i].size() != 0) begin exp_w = this.exp_w_fifo[i].pop_front(); @@ -268,141 +268,141 @@ package tb_axi_xbar_pkg; incr_conducted_tests(1); if(exp_w.last != act_w.last) begin incr_failed_tests(1); - $warning("Slave %d: unexpected W beat last flag %b, expected: %b.", + $warning("Subordinate %d: unexpected W beat last flag %b, expected: %b.", i, act_w.last, exp_w.last); end end - endtask : check_slv_w + endtask : check_sbr_w - // This task checks if a B response is allowed on a slave port of the crossbar. - task automatic monitor_mst_b(input int unsigned i); - master_exp_t exp_b; - mst_axi_id_t axi_b_id; - if (masters_axi[i].b_valid && masters_axi[i].b_ready) begin + // This task checks if a B response is allowed on a subordinate port of the crossbar. + task automatic monitor_mgr_b(input int unsigned i); + manager_exp_t exp_b; + mgr_axi_id_t axi_b_id; + if (managers_axi[i].b_valid && managers_axi[i].b_ready) begin incr_conducted_tests(1); - axi_b_id = masters_axi[i].b_id; - $display("%0tns > Master %0d: Got last B with id: %b", + axi_b_id = managers_axi[i].b_id; + $display("%0tns > Manager %0d: Got last B with id: %b", $time, i, axi_b_id); if (this.exp_b_queue[i].is_empty()) begin incr_failed_tests(1); - $warning("Master %d: unexpected B beat with ID: %b detected!", i, axi_b_id); + $warning("Manager %d: unexpected B beat with ID: %b detected!", i, axi_b_id); end else begin exp_b = this.exp_b_queue[i].pop_id(axi_b_id); - if (axi_b_id != exp_b.mst_axi_id) begin + if (axi_b_id != exp_b.mgr_axi_id) begin incr_failed_tests(1); - $warning("Master: %d got unexpected B with ID: %b", i, axi_b_id); + $warning("Manager: %d got unexpected B with ID: %b", i, axi_b_id); end end end - endtask : monitor_mst_b + endtask : monitor_mgr_b - // This task monitors the AR channel of a slave port of the crossbar. For each AR it populates + // This task monitors the AR channel of a subordinate port of the crossbar. For each AR it populates // the corresponding ID queue with the number of r beats indicated on the `ar_len` field. // Emphasis on the last flag. We will detect reordering, if the last flags do not match, // as each `random` burst tend to have a different length. - task automatic monitor_mst_ar(input int unsigned i); - mst_axi_id_t mst_axi_id; - axi_addr_t mst_axi_addr; - axi_pkg::len_t mst_axi_len; + task automatic monitor_mgr_ar(input int unsigned i); + mgr_axi_id_t mgr_axi_id; + axi_addr_t mgr_axi_addr; + axi_pkg::len_t mgr_axi_len; - idx_slv_t exp_slv_idx; - slv_axi_id_t exp_slv_axi_id; - exp_ax_t exp_slv_ar; - master_exp_t exp_mst_r; + idx_sbr_t exp_sbr_idx; + sbr_axi_id_t exp_sbr_axi_id; + exp_ax_t exp_sbr_ar; + manager_exp_t exp_mgr_r; logic exp_decerr; - if (masters_axi[i].ar_valid && masters_axi[i].ar_ready) begin + if (managers_axi[i].ar_valid && managers_axi[i].ar_ready) begin exp_decerr = 1'b1; - mst_axi_id = masters_axi[i].ar_id; - mst_axi_addr = masters_axi[i].ar_addr; - mst_axi_len = masters_axi[i].ar_len; - exp_slv_axi_id = {idx_mst_t'(i), mst_axi_id}; - exp_slv_idx = '0; + mgr_axi_id = managers_axi[i].ar_id; + mgr_axi_addr = managers_axi[i].ar_addr; + mgr_axi_len = managers_axi[i].ar_len; + exp_sbr_axi_id = {idx_mgr_t'(i), mgr_axi_id}; + exp_sbr_idx = '0; for (int unsigned j = 0; j < NumAddrRules; j++) begin - if ((mst_axi_addr >= AddrMap[j].start_addr) && (mst_axi_addr < AddrMap[j].end_addr)) begin - exp_slv_idx = AddrMap[j].idx; + if ((mgr_axi_addr >= AddrMap[j].start_addr) && (mgr_axi_addr < AddrMap[j].end_addr)) begin + exp_sbr_idx = AddrMap[j].idx; exp_decerr = 1'b0; end end if (exp_decerr) begin - $display("%0tns > Master %0d: AR to Decerror: Axi ID: %b", - $time, i, mst_axi_id); + $display("%0tns > Manager %0d: AR to Decerror: Axi ID: %b", + $time, i, mgr_axi_id); end else begin - $display("%0tns > Master %0d: AR to Slave %0d: Axi ID: %b", - $time, i, exp_slv_idx, mst_axi_id); - // push the expected vectors AW for exp_slv - exp_slv_ar = '{slv_axi_id: exp_slv_axi_id, - slv_axi_addr: mst_axi_addr, - slv_axi_len: mst_axi_len }; - //$display("Expected Slv Axi Id is: %b", exp_slv_axi_id); - this.exp_ar_queue[exp_slv_idx].push(exp_slv_axi_id, exp_slv_ar); + $display("%0tns > Manager %0d: AR to Subordinate %0d: Axi ID: %b", + $time, i, exp_sbr_idx, mgr_axi_id); + // push the expected vectors AW for exp_sbr + exp_sbr_ar = '{sbr_axi_id: exp_sbr_axi_id, + sbr_axi_addr: mgr_axi_addr, + sbr_axi_len: mgr_axi_len }; + //$display("Expected Sbr Axi Id is: %b", exp_sbr_axi_id); + this.exp_ar_queue[exp_sbr_idx].push(exp_sbr_axi_id, exp_sbr_ar); incr_expected_tests(1); end // push the required r beats into the right fifo - $display(" Expect R response, len: %0d.", masters_axi[i].ar_len); - for (int unsigned j = 0; j <= mst_axi_len; j++) begin - exp_mst_r = (j == mst_axi_len) ? '{mst_axi_id: mst_axi_id, last: 1'b1} : - '{mst_axi_id: mst_axi_id, last: 1'b0}; - this.exp_r_queue[i].push(mst_axi_id, exp_mst_r); + $display(" Expect R response, len: %0d.", managers_axi[i].ar_len); + for (int unsigned j = 0; j <= mgr_axi_len; j++) begin + exp_mgr_r = (j == mgr_axi_len) ? '{mgr_axi_id: mgr_axi_id, last: 1'b1} : + '{mgr_axi_id: mgr_axi_id, last: 1'b0}; + this.exp_r_queue[i].push(mgr_axi_id, exp_mgr_r); incr_expected_tests(1); end end - endtask : monitor_mst_ar + endtask : monitor_mgr_ar - // This task monitors a master port of the crossbar and checks if a transmitted AR beat was + // This task monitors a manager port of the crossbar and checks if a transmitted AR beat was // expected. - task automatic monitor_slv_ar(input int unsigned i); - exp_ax_t exp_slv_ar; - slv_axi_id_t slv_axi_id; - if (slaves_axi[i].ar_valid && slaves_axi[i].ar_ready) begin + task automatic monitor_sbr_ar(input int unsigned i); + exp_ax_t exp_sbr_ar; + sbr_axi_id_t sbr_axi_id; + if (subordinates_axi[i].ar_valid && subordinates_axi[i].ar_ready) begin incr_conducted_tests(1); - slv_axi_id = slaves_axi[i].ar_id; + sbr_axi_id = subordinates_axi[i].ar_id; if (this.exp_ar_queue[i].is_empty()) begin incr_failed_tests(1); end else begin // check that the ids are the same - exp_slv_ar = this.exp_ar_queue[i].pop_id(slv_axi_id); - $display("%0tns > Slave %0d: AR Axi ID: %b", $time, i, slv_axi_id); - if (exp_slv_ar.slv_axi_id != slv_axi_id) begin + exp_sbr_ar = this.exp_ar_queue[i].pop_id(sbr_axi_id); + $display("%0tns > Subordinate %0d: AR Axi ID: %b", $time, i, sbr_axi_id); + if (exp_sbr_ar.sbr_axi_id != sbr_axi_id) begin incr_failed_tests(1); - $warning("Slave %d: Unexpected AR with ID: %b", i, slv_axi_id); + $warning("Subordinate %d: Unexpected AR with ID: %b", i, sbr_axi_id); end end end - endtask : monitor_slv_ar + endtask : monitor_sbr_ar - // This task does the R channel monitoring on a slave port. It compares the last flags, + // This task does the R channel monitoring on a subordinate port. It compares the last flags, // which are determined by the sequence of previously sent AR vectors. - task automatic monitor_mst_r(input int unsigned i); - master_exp_t exp_mst_r; - mst_axi_id_t mst_axi_r_id; - logic mst_axi_r_last; - if (masters_axi[i].r_valid && masters_axi[i].r_ready) begin + task automatic monitor_mgr_r(input int unsigned i); + manager_exp_t exp_mgr_r; + mgr_axi_id_t mgr_axi_r_id; + logic mgr_axi_r_last; + if (managers_axi[i].r_valid && managers_axi[i].r_ready) begin incr_conducted_tests(1); - mst_axi_r_id = masters_axi[i].r_id; - mst_axi_r_last = masters_axi[i].r_last; - if (mst_axi_r_last) begin - $display("%0tns > Master %0d: Got last R with id: %b", - $time, i, mst_axi_r_id); + mgr_axi_r_id = managers_axi[i].r_id; + mgr_axi_r_last = managers_axi[i].r_last; + if (mgr_axi_r_last) begin + $display("%0tns > Manager %0d: Got last R with id: %b", + $time, i, mgr_axi_r_id); end if (this.exp_r_queue[i].is_empty()) begin incr_failed_tests(1); - $warning("Master %d: unexpected R beat with ID: %b detected!", i, mst_axi_r_id); + $warning("Manager %d: unexpected R beat with ID: %b detected!", i, mgr_axi_r_id); end else begin - exp_mst_r = this.exp_r_queue[i].pop_id(mst_axi_r_id); - if (mst_axi_r_id != exp_mst_r.mst_axi_id) begin + exp_mgr_r = this.exp_r_queue[i].pop_id(mgr_axi_r_id); + if (mgr_axi_r_id != exp_mgr_r.mgr_axi_id) begin incr_failed_tests(1); - $warning("Master: %d got unexpected R with ID: %b", i, mst_axi_r_id); + $warning("Manager: %d got unexpected R with ID: %b", i, mgr_axi_r_id); end - if (mst_axi_r_last != exp_mst_r.last) begin + if (mgr_axi_r_last != exp_mgr_r.last) begin incr_failed_tests(1); - $warning("Master: %d got unexpected R with ID: %b and last flag: %b", - i, mst_axi_r_id, mst_axi_r_last); + $warning("Manager: %d got unexpected R with ID: %b and last flag: %b", + i, mgr_axi_r_id, mgr_axi_r_last); end end end - endtask : monitor_mst_r + endtask : monitor_mgr_r // Some tasks to manage bookkeeping of the tests conducted. task incr_expected_tests(input int unsigned times); @@ -435,50 +435,50 @@ package tb_axi_xbar_pkg; // at every cycle span some monitoring processes // execute all processes that put something into the queues PushMon: fork - proc_mst_aw: begin - for (int unsigned i = 0; i < NumMasters; i++) begin - monitor_mst_aw(i); + proc_mgr_aw: begin + for (int unsigned i = 0; i < NumManagers; i++) begin + monitor_mgr_aw(i); end end - proc_mst_ar: begin - for (int unsigned i = 0; i < NumMasters; i++) begin - monitor_mst_ar(i); + proc_mgr_ar: begin + for (int unsigned i = 0; i < NumManagers; i++) begin + monitor_mgr_ar(i); end end join : PushMon // this one pops and pushes something - proc_slv_aw: begin - for (int unsigned i = 0; i < NumSlaves; i++) begin - monitor_slv_aw(i); + proc_sbr_aw: begin + for (int unsigned i = 0; i < NumSubordinates; i++) begin + monitor_sbr_aw(i); end end - proc_slv_w: begin - for (int unsigned i = 0; i < NumSlaves; i++) begin - monitor_slv_w(i); + proc_sbr_w: begin + for (int unsigned i = 0; i < NumSubordinates; i++) begin + monitor_sbr_w(i); end end // These only pop somethong from the queses PopMon: fork - proc_mst_b: begin - for (int unsigned i = 0; i < NumMasters; i++) begin - monitor_mst_b(i); + proc_mgr_b: begin + for (int unsigned i = 0; i < NumManagers; i++) begin + monitor_mgr_b(i); end end - proc_slv_ar: begin - for (int unsigned i = 0; i < NumSlaves; i++) begin - monitor_slv_ar(i); + proc_sbr_ar: begin + for (int unsigned i = 0; i < NumSubordinates; i++) begin + monitor_sbr_ar(i); end end - proc_mst_r: begin - for (int unsigned i = 0; i < NumMasters; i++) begin - monitor_mst_r(i); + proc_mgr_r: begin + for (int unsigned i = 0; i < NumManagers; i++) begin + monitor_mgr_r(i); end end join : PopMon - // check the slave W fifos last - proc_check_slv_w: begin - for (int unsigned i = 0; i < NumSlaves; i++) begin - check_slv_w(i); + // check the subordinate W fifos last + proc_check_sbr_w: begin + for (int unsigned i = 0; i < NumSubordinates; i++) begin + check_sbr_w(i); end end cycle_end();