diff --git a/CHANGELOG.md b/CHANGELOG.md index 4cb1dd336..6ea309aa2 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ### Added ### Changed +- Enforce consistent naming for request and response types. Now uses `axi_req_t` and `axi_resp_t` for axi types, and `axi_lite_req_t` and `axi_lite_resp_t` for axi-lite types. ### Fixed diff --git a/src/axi_atop_filter.sv b/src/axi_atop_filter.sv index 4a2ecff43..ec28a8ebd 100644 --- a/src/axi_atop_filter.sv +++ b/src/axi_atop_filter.sv @@ -40,22 +40,22 @@ module axi_atop_filter #( /// Maximum number of in-flight AXI write transactions parameter int unsigned AxiMaxWriteTxns = 0, /// AXI request type - parameter type req_t = logic, + parameter type axi_req_t = logic, /// AXI response type - parameter type resp_t = logic + parameter type axi_resp_t = logic ) ( /// Rising-edge clock of both ports - input logic clk_i, + input logic clk_i, /// Asynchronous reset, active low - input logic rst_ni, + input logic rst_ni, /// Slave port request - input req_t slv_req_i, + input axi_req_t slv_req_i, /// Slave port response - output resp_t slv_resp_o, + output axi_resp_t slv_resp_o, /// Master port request - output req_t mst_req_o, + output axi_req_t mst_req_o, /// Master port response - input resp_t mst_resp_i + input axi_resp_t mst_resp_i ); // Minimum counter width is 2 to detect underflows. @@ -405,11 +405,11 @@ module axi_atop_filter_intf #( `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) - req_t slv_req, mst_req; - resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_resp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -422,8 +422,8 @@ module axi_atop_filter_intf #( // Maximum number of AXI write bursts outstanding at the same time .AxiMaxWriteTxns ( AXI_MAX_WRITE_TXNS ), // AXI request & response type - .req_t ( req_t ), - .resp_t ( resp_t ) + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) i_axi_atop_filter ( .clk_i, .rst_ni, diff --git a/src/axi_burst_splitter.sv b/src/axi_burst_splitter.sv index a45584790..ad086ed99 100644 --- a/src/axi_burst_splitter.sv +++ b/src/axi_burst_splitter.sv @@ -35,19 +35,19 @@ module axi_burst_splitter #( parameter int unsigned DataWidth = 32'd0, parameter int unsigned IdWidth = 32'd0, parameter int unsigned UserWidth = 32'd0, - parameter type req_t = logic, - parameter type resp_t = logic + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // Input / Slave Port - input req_t slv_req_i, - output resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, // Output / Master Port - output req_t mst_req_o, - input resp_t mst_resp_i + output axi_req_t mst_req_o, + input axi_resp_t mst_resp_i ); typedef logic [AddrWidth-1:0] addr_t; @@ -62,28 +62,28 @@ module axi_burst_splitter #( `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) // Demultiplex between supported and unsupported transactions. - req_t act_req, unsupported_req; - resp_t act_resp, unsupported_resp; + axi_req_t act_req, unsupported_req; + axi_resp_t act_resp, unsupported_resp; logic sel_aw_unsupported, sel_ar_unsupported; localparam int unsigned MaxTxns = (MaxReadTxns > MaxWriteTxns) ? MaxReadTxns : MaxWriteTxns; axi_demux #( - .AxiIdWidth ( IdWidth ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ), - .NoMstPorts ( 2 ), - .MaxTrans ( MaxTxns ), - .AxiLookBits ( IdWidth ), - .FallThrough ( 1'b1 ), - .SpillAw ( 1'b0 ), - .SpillW ( 1'b0 ), - .SpillB ( 1'b0 ), - .SpillAr ( 1'b0 ), - .SpillR ( 1'b0 ) + .AxiIdWidth ( IdWidth ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .NoMstPorts ( 2 ), + .MaxTrans ( MaxTxns ), + .AxiLookBits ( IdWidth ), + .FallThrough ( 1'b1 ), + .SpillAw ( 1'b0 ), + .SpillW ( 1'b0 ), + .SpillB ( 1'b0 ), + .SpillAr ( 1'b0 ), + .SpillR ( 1'b0 ) ) i_demux_supported_vs_unsupported ( .clk_i, .rst_ni, @@ -119,8 +119,8 @@ module axi_burst_splitter #( // Respond to unsupported transactions with slave errors. axi_err_slv #( .AxiIdWidth ( IdWidth ), - .req_t ( req_t ), - .resp_t ( resp_t ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), .Resp ( axi_pkg::RESP_SLVERR ), .ATOPs ( 1'b0 ), // The burst splitter does not support ATOPs. .MaxTrans ( 1 ) // Splitting bursts implies a low-performance bus. diff --git a/src/axi_cut.sv b/src/axi_cut.sv index 6c31321b6..34278ca62 100644 --- a/src/axi_cut.sv +++ b/src/axi_cut.sv @@ -19,25 +19,25 @@ /// Breaks all combinatorial paths between its input and output. module axi_cut #( // bypass enable - parameter bit Bypass = 1'b0, + parameter bit Bypass = 1'b0, // AXI channel structs - parameter type aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type r_chan_t = logic, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, // AXI request & response structs - parameter type req_t = logic, - parameter type resp_t = logic + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // salve port - input req_t slv_req_i, - output resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, // master port - output req_t mst_req_o, - input resp_t mst_resp_i + output axi_req_t mst_req_o, + input axi_resp_t mst_resp_i ); // a spill register for each channel @@ -145,11 +145,11 @@ module axi_cut_intf #( `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) - req_t slv_req, mst_req; - resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_resp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, in) `AXI_ASSIGN_FROM_RESP(in, slv_resp) @@ -158,14 +158,14 @@ module axi_cut_intf #( `AXI_ASSIGN_TO_RESP(mst_resp, out) axi_cut #( - .Bypass ( BYPASS ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ) + .Bypass ( BYPASS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) i_axi_cut ( .clk_i, .rst_ni, @@ -219,11 +219,11 @@ module axi_lite_cut_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) - req_t slv_req, mst_req; - resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_resp_t slv_resp, mst_resp; `AXI_LITE_ASSIGN_TO_REQ(slv_req, in) `AXI_LITE_ASSIGN_FROM_RESP(in, slv_resp) @@ -232,14 +232,14 @@ module axi_lite_cut_intf #( `AXI_LITE_ASSIGN_TO_RESP(mst_resp, out) axi_cut #( - .Bypass ( BYPASS ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ) + .Bypass ( BYPASS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) i_axi_cut ( .clk_i, .rst_ni, diff --git a/src/axi_delayer.sv b/src/axi_delayer.sv index cab18eb59..8d217d14e 100644 --- a/src/axi_delayer.sv +++ b/src/axi_delayer.sv @@ -16,28 +16,28 @@ /// Synthesizable module that (randomly) delays AXI channels. module axi_delayer #( // AXI channel types - parameter type aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type r_chan_t = logic, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, // AXI request & response types - parameter type req_t = logic, - parameter type resp_t = logic, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, // delay parameters parameter bit StallRandomInput = 0, parameter bit StallRandomOutput = 0, parameter int unsigned FixedDelayInput = 1, parameter int unsigned FixedDelayOutput = 1 ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low // slave port - input req_t slv_req_i, - output resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, // master port - output req_t mst_req_o, - input resp_t mst_resp_i + output axi_req_t mst_req_o, + input axi_resp_t mst_resp_i ); // AW stream_delay #( @@ -152,11 +152,11 @@ module axi_delayer_intf #( `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) - req_t slv_req, mst_req; - resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_resp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -170,8 +170,8 @@ module axi_delayer_intf #( .b_chan_t ( b_chan_t ), .ar_chan_t ( ar_chan_t ), .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), .StallRandomInput ( STALL_RANDOM_INPUT ), .StallRandomOutput ( STALL_RANDOM_OUTPUT ), .FixedDelayInput ( FIXED_DELAY_INPUT ), diff --git a/src/axi_demux.sv b/src/axi_demux.sv index 99a18c8dc..b0d6b4202 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -23,8 +23,8 @@ module axi_demux #( parameter type b_chan_t = logic, parameter type ar_chan_t = logic, parameter type r_chan_t = logic, - parameter type req_t = logic, - parameter type resp_t = logic, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, parameter int unsigned NoMstPorts = 32'd0, parameter int unsigned MaxTrans = 32'd8, parameter int unsigned AxiLookBits = 32'd3, @@ -39,17 +39,17 @@ module axi_demux #( parameter int unsigned SelectWidth = (NoMstPorts > 32'd1) ? $clog2(NoMstPorts) : 32'd1, parameter type select_t = logic [SelectWidth-1:0] ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, + input logic clk_i, + input logic rst_ni, + input logic test_i, // Slave Port - input req_t slv_req_i, - input select_t slv_aw_select_i, - input select_t slv_ar_select_i, - output resp_t slv_resp_o, + input axi_req_t slv_req_i, + input select_t slv_aw_select_i, + input select_t slv_ar_select_i, + output axi_resp_t slv_resp_o, // Master Ports - output req_t [NoMstPorts-1:0] mst_reqs_o, - input resp_t [NoMstPorts-1:0] mst_resps_i + output axi_req_t [NoMstPorts-1:0] mst_reqs_o, + input axi_resp_t [NoMstPorts-1:0] mst_resps_i ); localparam int unsigned IdCounterWidth = MaxTrans > 1 ? $clog2(MaxTrans) : 1; @@ -735,13 +735,13 @@ module axi_demux_intf #( `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) - req_t slv_req; - resp_t slv_resp; - req_t [NO_MST_PORTS-1:0] mst_req; - resp_t [NO_MST_PORTS-1:0] mst_resp; + axi_req_t slv_req; + axi_resp_t slv_resp; + axi_req_t [NO_MST_PORTS-1:0] mst_req; + axi_resp_t [NO_MST_PORTS-1:0] mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -753,13 +753,13 @@ module axi_demux_intf #( axi_demux #( .AxiIdWidth ( AXI_ID_WIDTH ), // ID Width - .aw_chan_t ( aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( b_chan_t ), // B Channel Type - .ar_chan_t ( ar_chan_t ), // AR Channel Type - .r_chan_t ( r_chan_t ), // R Channel Type - .req_t ( req_t ), - .resp_t ( resp_t ), + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), .NoMstPorts ( NO_MST_PORTS ), .MaxTrans ( MAX_TRANS ), .AxiLookBits ( AXI_LOOK_BITS ), diff --git a/src/axi_dw_downsizer.sv b/src/axi_dw_downsizer.sv index 2139ac67d..6e467552e 100644 --- a/src/axi_dw_downsizer.sv +++ b/src/axi_dw_downsizer.sv @@ -188,8 +188,8 @@ module axi_dw_downsizer #( axi_err_slv #( .AxiIdWidth(AxiIdWidth ), .Resp (axi_pkg::RESP_SLVERR), - .req_t (axi_mst_req_t ), - .resp_t (axi_mst_resp_t ) + .axi_req_t (axi_mst_req_t ), + .axi_resp_t(axi_mst_resp_t ) ) i_axi_err_slv ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -216,8 +216,8 @@ module axi_dw_downsizer #( .b_chan_t (b_chan_t ), .ar_chan_t (ar_chan_t ), .r_chan_t (mst_r_chan_t ), - .req_t (axi_mst_req_t ), - .resp_t (axi_mst_resp_t), + .axi_req_t (axi_mst_req_t ), + .axi_resp_t (axi_mst_resp_t), .NoMstPorts (2 ), .MaxTrans (AxiMaxReads ), .SpillAw (1'b1 ) // Required to break dependency between AW and W channels diff --git a/src/axi_dw_upsizer.sv b/src/axi_dw_upsizer.sv index 1defebf05..d7bb021f3 100644 --- a/src/axi_dw_upsizer.sv +++ b/src/axi_dw_upsizer.sv @@ -185,8 +185,8 @@ module axi_dw_upsizer #( axi_err_slv #( .AxiIdWidth(AxiIdWidth ), .Resp (axi_pkg::RESP_SLVERR), - .req_t (axi_mst_req_t ), - .resp_t (axi_mst_resp_t ) + .axi_req_t (axi_mst_req_t ), + .axi_resp_t(axi_mst_resp_t ) ) i_axi_err_slv ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -213,8 +213,8 @@ module axi_dw_upsizer #( .b_chan_t (b_chan_t ), .ar_chan_t (ar_chan_t ), .r_chan_t (mst_r_chan_t ), - .req_t (axi_mst_req_t ), - .resp_t (axi_mst_resp_t), + .axi_req_t (axi_mst_req_t ), + .axi_resp_t (axi_mst_resp_t), .NoMstPorts (2 ), .MaxTrans (AxiMaxReads ), .SpillAw (1'b1 ) // Required to break dependency between AW and W channels diff --git a/src/axi_err_slv.sv b/src/axi_err_slv.sv index f3c807dc3..e7719c429 100644 --- a/src/axi_err_slv.sv +++ b/src/axi_err_slv.sv @@ -18,20 +18,20 @@ module axi_err_slv #( parameter int unsigned AxiIdWidth = 0, // AXI ID Width - parameter type req_t = logic, // AXI 4 request struct, with atop field - parameter type resp_t = logic, // AXI 4 response struct + parameter type axi_req_t = logic, // AXI 4 request struct, with atop field + parameter type axi_resp_t = logic, // AXI 4 response struct parameter axi_pkg::resp_t Resp = axi_pkg::RESP_DECERR, // Error generated by this slave. parameter int unsigned RespWidth = 32'd64, // Data response width, gets zero extended or truncated to r.data. parameter logic [RespWidth-1:0] RespData = 64'hCA11AB1EBADCAB1E, // Hexvalue for data return value parameter bit ATOPs = 1'b1, // Activate support for ATOPs. Set to 1 if this slave could ever get an atomic AXI transaction. parameter int unsigned MaxTrans = 1 // Maximum # of accepted transactions before stalling ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable // slave port - input req_t slv_req_i, - output resp_t slv_resp_o + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o ); typedef logic [AxiIdWidth-1:0] id_t; typedef struct packed { @@ -39,15 +39,15 @@ module axi_err_slv #( axi_pkg::len_t len; } r_data_t; - req_t err_req; - resp_t err_resp; + axi_req_t err_req; + axi_resp_t err_resp; if (ATOPs) begin axi_atop_filter #( .AxiIdWidth ( AxiIdWidth ), .AxiMaxWriteTxns ( MaxTrans ), - .req_t ( req_t ), - .resp_t ( resp_t ) + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) i_atop_filter ( .clk_i, .rst_ni, diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv index 2ed43458d..4e81a9017 100644 --- a/src/axi_id_serialize.sv +++ b/src/axi_id_serialize.sv @@ -156,8 +156,8 @@ module axi_id_serialize #( .b_chan_t ( slv_b_t ), .ar_chan_t ( slv_ar_t ), .r_chan_t ( slv_r_t ), - .req_t ( slv_req_t ), - .resp_t ( slv_resp_t ), + .axi_req_t ( slv_req_t ), + .axi_resp_t ( slv_resp_t ), .NoMstPorts ( AxiMstPortMaxUniqIds ), .MaxTrans ( AxiSlvPortMaxTxns ), .AxiLookBits ( AxiSlvPortIdWidth ), @@ -189,8 +189,8 @@ module axi_id_serialize #( .MaxReadTxns ( AxiMstPortMaxTxnsPerId ), .MaxWriteTxns ( AxiMstPortMaxTxnsPerId ), .AxiIdWidth ( AxiSlvPortIdWidth ), - .req_t ( slv_req_t ), - .resp_t ( slv_resp_t ) + .axi_req_t ( slv_req_t ), + .axi_resp_t ( slv_resp_t ) ) i_axi_serializer ( .clk_i, .rst_ni, diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv index 1eb484679..008cbdfa3 100644 --- a/src/axi_isolate.sv +++ b/src/axi_isolate.sv @@ -32,17 +32,17 @@ module axi_isolate #( parameter int unsigned NumPending = 32'd16, // Number of pending requests per channel - parameter type req_t = logic, // AXI request struct definition - parameter type resp_t = logic // AXI response struct definition + parameter type axi_req_t = logic, // AXI request struct definition + parameter type axi_resp_t = logic // AXI response struct definition ) ( - input logic clk_i, // clock - input logic rst_ni, // reset - input req_t slv_req_i, // slave port request struct - output resp_t slv_resp_o, // slave port response struct - output req_t mst_req_o, // master port request struct - input resp_t mst_resp_i, // master port response struct - input logic isolate_i, // isolate master port from slave port - output logic isolated_o // master port is isolated from slave port + input logic clk_i, // clock + input logic rst_ni, // reset + input axi_req_t slv_req_i, // slave port request struct + output axi_resp_t slv_resp_o, // slave port response struct + output axi_req_t mst_req_o, // master port request struct + input axi_resp_t mst_resp_i, // master port response struct + input logic isolate_i, // isolate master port from slave port + output logic isolated_o // master port is isolated from slave port ); // plus 1 in clog for accouning no open transaction, plus one bit for atomic injection localparam int unsigned CounterWidth = $clog2(NumPending + 32'd1) + 32'd1; @@ -305,11 +305,11 @@ module axi_isolate_intf #( `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) - req_t slv_req, mst_req; - resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_resp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) @@ -319,8 +319,8 @@ module axi_isolate_intf #( axi_isolate #( .NumPending ( NUM_PENDING ), // Number of pending requests per channel - .req_t ( req_t ), // AXI request struct definition - .resp_t ( resp_t ) // AXI response struct definition + .axi_req_t ( axi_req_t ), // AXI request struct definition + .axi_resp_t ( axi_resp_t ) // AXI response struct definition ) i_axi_isolate ( .clk_i, // clock .rst_ni, // reset diff --git a/src/axi_lite_demux.sv b/src/axi_lite_demux.sv index 937f843a1..7aa047c2d 100644 --- a/src/axi_lite_demux.sv +++ b/src/axi_lite_demux.sv @@ -19,35 +19,35 @@ // stability rules as the corresponding AXI4-Lite channel. module axi_lite_demux #( - parameter type aw_chan_t = logic, // AXI4-Lite AW channel - parameter type w_chan_t = logic, // AXI4-Lite W channel - parameter type b_chan_t = logic, // AXI4-Lite B channel - parameter type ar_chan_t = logic, // AXI4-Lite AR channel - parameter type r_chan_t = logic, // AXI4-Lite R channel - parameter type req_t = logic, // AXI4-Lite request struct - parameter type resp_t = logic, // AXI4-Lite response struct - parameter int unsigned NoMstPorts = 32'd0, // Number of instantiated ports - parameter int unsigned MaxTrans = 32'd0, // Maximum number of open transactions per channel - parameter bit FallThrough = 1'b0, // FIFOs are in fall through mode - parameter bit SpillAw = 1'b1, // insert one cycle latency on slave AW - parameter bit SpillW = 1'b0, // insert one cycle latency on slave W - parameter bit SpillB = 1'b0, // insert one cycle latency on slave B - parameter bit SpillAr = 1'b1, // insert one cycle latency on slave AR - parameter bit SpillR = 1'b0, // insert one cycle latency on slave R + parameter type aw_chan_t = logic, // AXI4-Lite AW channel + parameter type w_chan_t = logic, // AXI4-Lite W channel + parameter type b_chan_t = logic, // AXI4-Lite B channel + parameter type ar_chan_t = logic, // AXI4-Lite AR channel + parameter type r_chan_t = logic, // AXI4-Lite R channel + parameter type axi_lite_req_t = logic, // AXI4-Lite request struct + parameter type axi_lite_resp_t = logic, // AXI4-Lite response struct + parameter int unsigned NoMstPorts = 32'd0, // Number of instantiated ports + parameter int unsigned MaxTrans = 32'd0, // Maximum number of open transactions per channel + parameter bit FallThrough = 1'b0, // FIFOs are in fall through mode + parameter bit SpillAw = 1'b1, // insert one cycle latency on slave AW + parameter bit SpillW = 1'b0, // insert one cycle latency on slave W + parameter bit SpillB = 1'b0, // insert one cycle latency on slave B + parameter bit SpillAr = 1'b1, // insert one cycle latency on slave AR + parameter bit SpillR = 1'b0, // insert one cycle latency on slave R // Dependent parameters, DO NOT OVERRIDE! - parameter type select_t = logic [$clog2(NoMstPorts)-1:0] + parameter type select_t = logic [$clog2(NoMstPorts)-1:0] ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, + input logic clk_i, + input logic rst_ni, + input logic test_i, // slave port (AXI4-Lite input), connect master module here - input req_t slv_req_i, - input select_t slv_aw_select_i, - input select_t slv_ar_select_i, - output resp_t slv_resp_o, + input axi_lite_req_t slv_req_i, + input select_t slv_aw_select_i, + input select_t slv_ar_select_i, + output axi_lite_resp_t slv_resp_o, // master ports (AXI4-Lite outputs), connect slave modules here - output req_t [NoMstPorts-1:0] mst_reqs_o, - input resp_t [NoMstPorts-1:0] mst_resps_i + output axi_lite_req_t [NoMstPorts-1:0] mst_reqs_o, + input axi_lite_resp_t [NoMstPorts-1:0] mst_resps_i ); //-------------------------------------- @@ -425,13 +425,13 @@ module axi_lite_demux_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_t, r_chan_t) - req_t slv_req; - resp_t slv_resp; - req_t [NoMstPorts-1:0] mst_reqs; - resp_t [NoMstPorts-1:0] mst_resps; + axi_lite_req_t slv_req; + axi_lite_resp_t slv_resp; + axi_lite_req_t [NoMstPorts-1:0] mst_reqs; + axi_lite_resp_t [NoMstPorts-1:0] mst_resps; `AXI_LITE_ASSIGN_TO_REQ(slv_req, slv) `AXI_LITE_ASSIGN_FROM_RESP(slv, slv_resp) @@ -442,21 +442,21 @@ module axi_lite_demux_intf #( end axi_lite_demux #( - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ), - .NoMstPorts ( NoMstPorts ), - .MaxTrans ( MaxTrans ), - .FallThrough ( FallThrough ), - .SpillAw ( SpillAw ), - .SpillW ( SpillW ), - .SpillB ( SpillB ), - .SpillAr ( SpillAr ), - .SpillR ( SpillR ) + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), + .NoMstPorts ( NoMstPorts ), + .MaxTrans ( MaxTrans ), + .FallThrough ( FallThrough ), + .SpillAw ( SpillAw ), + .SpillW ( SpillW ), + .SpillB ( SpillB ), + .SpillAr ( SpillAr ), + .SpillR ( SpillR ) ) i_axi_demux ( .clk_i, .rst_ni, diff --git a/src/axi_lite_mailbox.sv b/src/axi_lite_mailbox.sv index 99304fa3b..63fc63889 100644 --- a/src/axi_lite_mailbox.sv +++ b/src/axi_lite_mailbox.sv @@ -19,24 +19,24 @@ `include "common_cells/registers.svh" module axi_lite_mailbox #( - parameter int unsigned MailboxDepth = 32'd0, - parameter bit unsigned IrqEdgeTrig = 1'b0, - parameter bit unsigned IrqActHigh = 1'b1, - parameter int unsigned AxiAddrWidth = 32'd0, - parameter int unsigned AxiDataWidth = 32'd0, - parameter type req_lite_t = logic, - parameter type resp_lite_t = logic, + parameter int unsigned MailboxDepth = 32'd0, + parameter bit unsigned IrqEdgeTrig = 1'b0, + parameter bit unsigned IrqActHigh = 1'b1, + parameter int unsigned AxiAddrWidth = 32'd0, + parameter int unsigned AxiDataWidth = 32'd0, + parameter type axi_lite_req_t = logic, + parameter type axi_lite_resp_t = logic, // DEPENDENT PARAMETERS, DO NOT OVERRIDE! - parameter type addr_t = logic [AxiAddrWidth-1:0] + parameter type addr_t = logic [AxiAddrWidth-1:0] ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable // slave ports [1:0] - input req_lite_t [1:0] slv_reqs_i, - output resp_lite_t [1:0] slv_resps_o, - output logic [1:0] irq_o, // interrupt output for each port - input addr_t [1:0] base_addr_i // base address for each port + input axi_lite_req_t [1:0] slv_reqs_i, + output axi_lite_resp_t [1:0] slv_resps_o, + output logic [1:0] irq_o, // interrupt output for each port + input addr_t [1:0] base_addr_i // base address for each port ); localparam int unsigned FifoUsageWidth = $clog2(MailboxDepth); typedef logic [AxiDataWidth-1:0] data_t; @@ -55,14 +55,14 @@ module axi_lite_mailbox #( logic [1:0] clear_irq; axi_lite_mailbox_slave #( - .MailboxDepth ( MailboxDepth ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .req_lite_t ( req_lite_t ), - .resp_lite_t ( resp_lite_t ), - .addr_t ( addr_t ), - .data_t ( data_t ), - .usage_t ( usage_t ) // fill pointer from MBOX FIFO + .MailboxDepth ( MailboxDepth ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), + .addr_t ( addr_t ), + .data_t ( data_t ), + .usage_t ( usage_t ) // fill pointer from MBOX FIFO ) i_slv_port_0 ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low @@ -88,14 +88,14 @@ module axi_lite_mailbox #( ); axi_lite_mailbox_slave #( - .MailboxDepth ( MailboxDepth ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .req_lite_t ( req_lite_t ), - .resp_lite_t ( resp_lite_t ), - .addr_t ( addr_t ), - .data_t ( data_t ), - .usage_t ( usage_t ) // fill pointer from MBOX FIFO + .MailboxDepth ( MailboxDepth ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), + .addr_t ( addr_t ), + .data_t ( data_t ), + .usage_t ( usage_t ) // fill pointer from MBOX FIFO ) i_slv_port_1 ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low @@ -202,36 +202,36 @@ endmodule // slave port module module axi_lite_mailbox_slave #( - parameter int unsigned MailboxDepth = 32'd16, - parameter int unsigned AxiAddrWidth = 32'd32, - parameter int unsigned AxiDataWidth = 32'd32, - parameter type req_lite_t = logic, - parameter type resp_lite_t = logic, - parameter type addr_t = logic [AxiAddrWidth-1:0], - parameter type data_t = logic [AxiDataWidth-1:0], - parameter type usage_t = logic // fill pointer from MBOX FIFO + parameter int unsigned MailboxDepth = 32'd16, + parameter int unsigned AxiAddrWidth = 32'd32, + parameter int unsigned AxiDataWidth = 32'd32, + parameter type axi_lite_req_t = logic, + parameter type axi_lite_resp_t = logic, + parameter type addr_t = logic [AxiAddrWidth-1:0], + parameter type data_t = logic [AxiDataWidth-1:0], + parameter type usage_t = logic // fill pointer from MBOX FIFO ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low // slave port - input req_lite_t slv_req_i, - output resp_lite_t slv_resp_o, - input addr_t base_addr_i, // base address for the slave port + input axi_lite_req_t slv_req_i, + output axi_lite_resp_t slv_resp_o, + input addr_t base_addr_i, // base address for the slave port // write FIFO port - output data_t mbox_w_data_o, - input logic mbox_w_full_i, - output logic mbox_w_push_o, - output logic mbox_w_flush_o, - input usage_t mbox_w_usage_i, + output data_t mbox_w_data_o, + input logic mbox_w_full_i, + output logic mbox_w_push_o, + output logic mbox_w_flush_o, + input usage_t mbox_w_usage_i, // read FIFO port - input data_t mbox_r_data_i, - input logic mbox_r_empty_i, - output logic mbox_r_pop_o, - output logic mbox_r_flush_o, - input usage_t mbox_r_usage_i, + input data_t mbox_r_data_i, + input logic mbox_r_empty_i, + output logic mbox_r_pop_o, + output logic mbox_r_flush_o, + input usage_t mbox_r_usage_i, // interrupt output, level triggered, active high, conversion in top - output logic irq_o, - output logic clear_irq_o // clear the edge trigger irq register in `axi_lite_mailbox` + output logic irq_o, + output logic clear_irq_o // clear the edge trigger irq register in `axi_lite_mailbox` ); `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t) @@ -578,11 +578,11 @@ module axi_lite_mailbox_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_lite_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_lite_t, r_chan_lite_t) - req_lite_t [1:0] slv_reqs; - resp_lite_t [1:0] slv_resps; + axi_lite_req_t [1:0] slv_reqs; + axi_lite_resp_t [1:0] slv_resps; for (genvar i = 0; i < 2; i++) begin : gen_port_assign `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) @@ -590,13 +590,13 @@ module axi_lite_mailbox_intf #( end axi_lite_mailbox #( - .MailboxDepth ( MAILBOX_DEPTH ), - .IrqEdgeTrig ( IRQ_EDGE_TRIG ), - .IrqActHigh ( IRQ_ACT_HIGH ), - .AxiAddrWidth ( AXI_ADDR_WIDTH ), - .AxiDataWidth ( AXI_DATA_WIDTH ), - .req_lite_t ( req_lite_t ), - .resp_lite_t ( resp_lite_t ) + .MailboxDepth ( MAILBOX_DEPTH ), + .IrqEdgeTrig ( IRQ_EDGE_TRIG ), + .IrqActHigh ( IRQ_ACT_HIGH ), + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .AxiDataWidth ( AXI_DATA_WIDTH ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ) ) i_axi_lite_mailbox ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low diff --git a/src/axi_lite_mux.sv b/src/axi_lite_mux.sv index c115e7888..31389ef49 100644 --- a/src/axi_lite_mux.sv +++ b/src/axi_lite_mux.sv @@ -27,8 +27,8 @@ module axi_lite_mux #( parameter type b_chan_t = logic, // B LITE Channel Type parameter type ar_chan_t = logic, // AR LITE Channel Type parameter type r_chan_t = logic, // R LITE Channel Type - parameter type req_t = logic, // AXI4-Lite request type - parameter type resp_t = logic, // AXI4-Lite response type + parameter type axi_lite_req_t = logic, // AXI4-Lite request type + parameter type axi_lite_resp_t = logic, // AXI4-Lite response type parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports // Maximum number of outstanding transactions per write or read parameter int unsigned MaxTrans = 32'd0, @@ -42,15 +42,15 @@ module axi_lite_mux #( parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0 ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Test Mode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Test Mode enable // slave ports (AXI4-Lite inputs), connect master modules here - input req_t [NoSlvPorts-1:0] slv_reqs_i, - output resp_t [NoSlvPorts-1:0] slv_resps_o, + input axi_lite_req_t [NoSlvPorts-1:0] slv_reqs_i, + output axi_lite_resp_t [NoSlvPorts-1:0] slv_resps_o, // master port (AXI4-Lite output), connect slave module here - output req_t mst_req_o, - input resp_t mst_resp_i + output axi_lite_req_t mst_req_o, + input axi_lite_resp_t mst_resp_i ); // pass through if only one slave port if (NoSlvPorts == 32'h1) begin : gen_no_mux @@ -422,13 +422,13 @@ module axi_lite_mux_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_t, r_chan_t) - req_t [NoSlvPorts-1:0] slv_reqs; - resp_t [NoSlvPorts-1:0] slv_resps; - req_t mst_req; - resp_t mst_resp; + axi_lite_req_t [NoSlvPorts-1:0] slv_reqs; + axi_lite_resp_t [NoSlvPorts-1:0] slv_resps; + axi_lite_req_t mst_req; + axi_lite_resp_t mst_resp; for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_assign_slv_ports `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) @@ -439,19 +439,21 @@ module axi_lite_mux_intf #( `AXI_LITE_ASSIGN_TO_RESP(mst_resp, mst) axi_lite_mux #( - .aw_chan_t ( aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( b_chan_t ), // B Channel Type - .ar_chan_t ( ar_chan_t ), // AR Channel Type - .r_chan_t ( r_chan_t ), // R Channel Type - .NoSlvPorts ( NoSlvPorts ), // Number of slave ports - .MaxTrans ( MaxTrans ), - .FallThrough ( FallThrough ), - .SpillAw ( SpillAw ), - .SpillW ( SpillW ), - .SpillB ( SpillB ), - .SpillAr ( SpillAr ), - .SpillR ( SpillR ) + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), + .NoSlvPorts ( NoSlvPorts ), // Number of slave ports + .MaxTrans ( MaxTrans ), + .FallThrough ( FallThrough ), + .SpillAw ( SpillAw ), + .SpillW ( SpillW ), + .SpillB ( SpillB ), + .SpillAr ( SpillAr ), + .SpillR ( SpillR ) ) i_axi_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low diff --git a/src/axi_lite_regs.sv b/src/axi_lite_regs.sv index 01ed2a0d8..406e4b7f6 100644 --- a/src/axi_lite_regs.sv +++ b/src/axi_lite_regs.sv @@ -92,18 +92,18 @@ module axi_lite_regs #( /// assigned its value from this array. parameter byte_t [RegNumBytes-1:0] RegRstVal = {RegNumBytes{8'h00}}, /// Request struct of the AXI4-Lite port. - parameter type req_lite_t = logic, + parameter type axi_lite_req_t = logic, /// Response struct of the AXI4-Lite port. - parameter type resp_lite_t = logic + parameter type axi_lite_resp_t = logic ) ( /// Rising-edge clock of all ports input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, /// AXI4-Lite slave request - input req_lite_t axi_req_i, + input axi_lite_req_t axi_req_i, /// AXI4-Lite slave response - output resp_lite_t axi_resp_o, + output axi_lite_resp_t axi_resp_o, /// Signals that a byte is being written from the AXI4-Lite port in the current clock cycle. This /// signal is asserted regardless of the value of `AxiReadOnly` and can therefore be used by /// surrounding logic to react to write-on-read-only-byte errors. @@ -438,25 +438,25 @@ module axi_lite_regs_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_lite_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_lite_t, r_chan_lite_t) - req_lite_t axi_lite_req; - resp_lite_t axi_lite_resp; + axi_lite_req_t axi_lite_req; + axi_lite_resp_t axi_lite_resp; `AXI_LITE_ASSIGN_TO_REQ(axi_lite_req, slv) `AXI_LITE_ASSIGN_FROM_RESP(slv, axi_lite_resp) axi_lite_regs #( - .RegNumBytes ( REG_NUM_BYTES ), - .AxiAddrWidth ( AXI_ADDR_WIDTH ), - .AxiDataWidth ( AXI_DATA_WIDTH ), - .PrivProtOnly ( PRIV_PROT_ONLY ), - .SecuProtOnly ( SECU_PROT_ONLY ), - .AxiReadOnly ( AXI_READ_ONLY ), - .RegRstVal ( REG_RST_VAL ), - .req_lite_t ( req_lite_t ), - .resp_lite_t ( resp_lite_t ) + .RegNumBytes ( REG_NUM_BYTES ), + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .AxiDataWidth ( AXI_DATA_WIDTH ), + .PrivProtOnly ( PRIV_PROT_ONLY ), + .SecuProtOnly ( SECU_PROT_ONLY ), + .AxiReadOnly ( AXI_READ_ONLY ), + .RegRstVal ( REG_RST_VAL ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ) ) i_axi_lite_regs ( .clk_i, .rst_ni, diff --git a/src/axi_lite_to_axi.sv b/src/axi_lite_to_axi.sv index bbeebec10..c1319d83b 100644 --- a/src/axi_lite_to_axi.sv +++ b/src/axi_lite_to_axi.sv @@ -18,20 +18,20 @@ module axi_lite_to_axi #( parameter int unsigned AxiDataWidth = 32'd0, // LITE AXI structs - parameter type req_lite_t = logic, - parameter type resp_lite_t = logic, + parameter type axi_lite_req_t = logic, + parameter type axi_lite_resp_t = logic, // FULL AXI structs - parameter type req_t = logic, - parameter type resp_t = logic + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( // Slave AXI LITE port - input req_lite_t slv_req_lite_i, - output resp_lite_t slv_resp_lite_o, + input axi_lite_req_t slv_req_lite_i, + output axi_lite_resp_t slv_resp_lite_o, input axi_pkg::cache_t slv_aw_cache_i, input axi_pkg::cache_t slv_ar_cache_i, // Master AXI port - output req_t mst_req_o, - input resp_t mst_resp_i + output axi_req_t mst_req_o, + input axi_resp_t mst_resp_i ); localparam int unsigned AxiSize = axi_pkg::size_t'($unsigned($clog2(AxiDataWidth/8))); diff --git a/src/axi_lite_xbar.sv b/src/axi_lite_xbar.sv index cbacf4ceb..fb5b8d822 100644 --- a/src/axi_lite_xbar.sv +++ b/src/axi_lite_xbar.sv @@ -21,27 +21,27 @@ module axi_lite_xbar #( parameter axi_pkg::xbar_cfg_t Cfg = '0, - parameter type aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type r_chan_t = logic, - parameter type req_t = logic, - parameter type resp_t = logic, - parameter type rule_t = axi_pkg::xbar_rule_64_t, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + parameter type axi_lite_req_t = logic, + parameter type axi_lite_resp_t = logic, + parameter type rule_t = axi_pkg::xbar_rule_64_t, // DEPENDENT PARAMETERS, DO NOT OVERWRITE! parameter int unsigned MstIdxWidth = (Cfg.NoMstPorts > 32'd1) ? $clog2(Cfg.NoMstPorts) : 32'd1 ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, - input req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, - output resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, - output req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, - input resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i, - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NoSlvPorts-1:0][MstIdxWidth-1:0] default_mst_port_i + input logic clk_i, + input logic rst_ni, + input logic test_i, + input axi_lite_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, + output axi_lite_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, + output axi_lite_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, + input axi_lite_resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i, + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NoSlvPorts-1:0][MstIdxWidth-1:0] default_mst_port_i ); typedef logic [Cfg.AxiAddrWidth-1:0] addr_t; @@ -60,12 +60,12 @@ module axi_lite_xbar #( `AXI_TYPEDEF_RESP_T(full_resp_t, full_b_chan_t, full_r_chan_t) // signals from the axi_lite_demuxes, one index more for decode error routing - req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; - resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps; + axi_lite_req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; + axi_lite_resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps; // signals into the axi_lite_muxes, are of type slave as the multiplexer extends the ID - req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; - resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; + axi_lite_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; + axi_lite_resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux logic [MstIdxWidth-1:0] dec_aw, dec_ar; @@ -138,21 +138,21 @@ module axi_lite_xbar #( `endif // pragma translate_on axi_lite_demux #( - .aw_chan_t ( aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( b_chan_t ), // B Channel Type - .ar_chan_t ( ar_chan_t ), // AR Channel Type - .r_chan_t ( r_chan_t ), // R Channel Type - .req_t ( req_t ), - .resp_t ( resp_t ), - .NoMstPorts ( Cfg.NoMstPorts + 1 ), - .MaxTrans ( Cfg.MaxMstTrans ), - .FallThrough ( Cfg.FallThrough ), - .SpillAw ( Cfg.LatencyMode[9] ), - .SpillW ( Cfg.LatencyMode[8] ), - .SpillB ( Cfg.LatencyMode[7] ), - .SpillAr ( Cfg.LatencyMode[6] ), - .SpillR ( Cfg.LatencyMode[5] ) + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), + .NoMstPorts ( Cfg.NoMstPorts + 1 ), + .MaxTrans ( Cfg.MaxMstTrans ), + .FallThrough ( Cfg.FallThrough ), + .SpillAw ( Cfg.LatencyMode[9] ), + .SpillW ( Cfg.LatencyMode[8] ), + .SpillB ( Cfg.LatencyMode[7] ), + .SpillAr ( Cfg.LatencyMode[6] ), + .SpillR ( Cfg.LatencyMode[5] ) ) i_axi_lite_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low @@ -168,11 +168,11 @@ module axi_lite_xbar #( // connect the decode error module to the last index of the demux master port // typedef as the decode error slave uses full axi axi_lite_to_axi #( - .AxiDataWidth ( Cfg.AxiDataWidth ), - .req_lite_t ( req_t ), - .resp_lite_t ( resp_t ), - .req_t ( full_req_t ), - .resp_t ( full_resp_t ) + .AxiDataWidth ( Cfg.AxiDataWidth ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), + .axi_req_t ( full_req_t ), + .axi_resp_t ( full_resp_t ) ) i_dec_err_conv ( .slv_req_lite_i ( slv_reqs[i][Cfg.NoMstPorts] ), .slv_resp_lite_o ( slv_resps[i][Cfg.NoMstPorts] ), @@ -184,8 +184,8 @@ module axi_lite_xbar #( axi_err_slv #( .AxiIdWidth ( 32'd1 ), // ID width is one as defined as logic above - .req_t ( full_req_t ), // AXI request struct - .resp_t ( full_resp_t ), // AXI response struct + .axi_req_t ( full_req_t ), // AXI request struct + .axi_resp_t ( full_resp_t ), // AXI response struct .Resp ( axi_pkg::RESP_DECERR ), .ATOPs ( 1'b0 ), // no ATOPs in AXI4-Lite .MaxTrans ( 1 ) // Transactions terminate at this slave, and AXI4-Lite @@ -210,21 +210,21 @@ module axi_lite_xbar #( for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_mst_port_mux axi_lite_mux #( - .aw_chan_t ( aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( b_chan_t ), // B Channel Type - .ar_chan_t ( ar_chan_t ), // AR Channel Type - .r_chan_t ( r_chan_t ), // R Channel Type - .req_t ( req_t ), - .resp_t ( resp_t ), - .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module - .MaxTrans ( Cfg.MaxSlvTrans ), - .FallThrough ( Cfg.FallThrough ), - .SpillAw ( Cfg.LatencyMode[4] ), - .SpillW ( Cfg.LatencyMode[3] ), - .SpillB ( Cfg.LatencyMode[2] ), - .SpillAr ( Cfg.LatencyMode[1] ), - .SpillR ( Cfg.LatencyMode[0] ) + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), + .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module + .MaxTrans ( Cfg.MaxSlvTrans ), + .FallThrough ( Cfg.FallThrough ), + .SpillAw ( Cfg.LatencyMode[4] ), + .SpillW ( Cfg.LatencyMode[3] ), + .SpillB ( Cfg.LatencyMode[2] ), + .SpillAr ( Cfg.LatencyMode[1] ), + .SpillR ( Cfg.LatencyMode[0] ) ) i_axi_lite_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low @@ -261,13 +261,13 @@ module axi_lite_xbar_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_t, r_chan_t) - req_t [Cfg.NoMstPorts-1:0] mst_reqs; - resp_t [Cfg.NoMstPorts-1:0] mst_resps; - req_t [Cfg.NoSlvPorts-1:0] slv_reqs; - resp_t [Cfg.NoSlvPorts-1:0] slv_resps; + axi_lite_req_t [Cfg.NoMstPorts-1:0] mst_reqs; + axi_lite_resp_t [Cfg.NoMstPorts-1:0] mst_resps; + axi_lite_req_t [Cfg.NoSlvPorts-1:0] slv_reqs; + axi_lite_resp_t [Cfg.NoSlvPorts-1:0] slv_resps; for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst `AXI_LITE_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) @@ -280,15 +280,15 @@ module axi_lite_xbar_intf #( end axi_lite_xbar #( - .Cfg (Cfg), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ), - .rule_t ( rule_t ) + .Cfg ( Cfg ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), + .rule_t ( rule_t ) ) i_xbar ( .clk_i, .rst_ni, diff --git a/src/axi_multicut.sv b/src/axi_multicut.sv index 8e5dc2f95..1e42c2da5 100644 --- a/src/axi_multicut.sv +++ b/src/axi_multicut.sv @@ -21,23 +21,23 @@ module axi_multicut #( parameter int unsigned NoCuts = 32'd1, // Number of cuts. // AXI channel structs - parameter type aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type r_chan_t = logic, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, // AXI request & response structs - parameter type req_t = logic, - parameter type resp_t = logic + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low // slave port - input req_t slv_req_i, - output resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, // master port - output req_t mst_req_o, - input resp_t mst_resp_i + output axi_req_t mst_req_o, + input axi_resp_t mst_resp_i ); if (NoCuts == '0) begin : gen_no_cut @@ -46,8 +46,8 @@ module axi_multicut #( assign slv_resp_o = mst_resp_i; end else begin : gen_axi_cut // instantiate all needed cuts - req_t [NoCuts:0] cut_req; - resp_t [NoCuts:0] cut_resp; + axi_req_t [NoCuts:0] cut_req; + axi_resp_t [NoCuts:0] cut_resp; // connect slave to the lowest index assign cut_req[0] = slv_req_i; @@ -56,14 +56,14 @@ module axi_multicut #( // AXI cuts for (genvar i = 0; i < NoCuts; i++) begin : gen_axi_cuts axi_cut #( - .Bypass ( 1'b0 ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ) + .Bypass ( 1'b0 ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) i_cut ( .clk_i, .rst_ni, @@ -117,11 +117,11 @@ module axi_multicut_intf #( `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) - req_t slv_req, mst_req; - resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_resp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, in) `AXI_ASSIGN_FROM_RESP(in, slv_resp) @@ -130,14 +130,14 @@ module axi_multicut_intf #( `AXI_ASSIGN_TO_RESP(mst_resp, out) axi_multicut #( - .NoCuts ( NUM_CUTS ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ) + .NoCuts ( NUM_CUTS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) i_axi_multicut ( .clk_i, .rst_ni, @@ -191,11 +191,11 @@ module axi_lite_multicut_intf #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) - req_t slv_req, mst_req; - resp_t slv_resp, mst_resp; + axi_req_t slv_req, mst_req; + axi_resp_t slv_resp, mst_resp; `AXI_LITE_ASSIGN_TO_REQ(slv_req, in) `AXI_LITE_ASSIGN_FROM_RESP(in, slv_resp) @@ -204,14 +204,14 @@ module axi_lite_multicut_intf #( `AXI_LITE_ASSIGN_TO_RESP(mst_resp, out) axi_multicut #( - .NoCuts ( NUM_CUTS ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ) + .NoCuts ( NUM_CUTS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) i_axi_multicut ( .clk_i, .rst_ni, diff --git a/src/axi_serializer.sv b/src/axi_serializer.sv index df2a35a72..0b064f29e 100644 --- a/src/axi_serializer.sv +++ b/src/axi_serializer.sv @@ -27,22 +27,22 @@ module axi_serializer #( /// AXI4+ATOP ID width. parameter int unsigned AxiIdWidth = 32'd0, /// AXI4+ATOP request struct definition. - parameter type req_t = logic, + parameter type axi_req_t = logic, /// AXI4+ATOP response struct definition. - parameter type resp_t = logic + parameter type axi_resp_t = logic ) ( /// Clock - input logic clk_i, + input logic clk_i, /// Asynchronous reset, active low - input logic rst_ni, + input logic rst_ni, /// Slave port request - input req_t slv_req_i, + input axi_req_t slv_req_i, /// Slave port response - output resp_t slv_resp_o, + output axi_resp_t slv_resp_o, /// Master port request - output req_t mst_req_o, + output axi_req_t mst_req_o, /// Master port response - input resp_t mst_resp_i + input axi_resp_t mst_resp_i ); typedef logic [AxiIdWidth-1:0] id_t; @@ -254,10 +254,10 @@ module axi_serializer_intf #( `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) - req_t slv_req, mst_req; - resp_t slv_resp, mst_resp; + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + axi_req_t slv_req, mst_req; + axi_resp_t slv_resp, mst_resp; `AXI_ASSIGN_TO_REQ(slv_req, slv) `AXI_ASSIGN_FROM_RESP(slv, slv_resp) `AXI_ASSIGN_FROM_REQ(mst, mst_req) @@ -267,8 +267,8 @@ module axi_serializer_intf #( .MaxReadTxns ( MAX_READ_TXNS ), .MaxWriteTxns ( MAX_WRITE_TXNS ), .AxiIdWidth ( AXI_ID_WIDTH ), - .req_t ( req_t ), - .resp_t ( resp_t ) + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) i_axi_serializer ( .clk_i, .rst_ni, diff --git a/src/axi_sim_mem.sv b/src/axi_sim_mem.sv index 4a9ad57b6..77bd09a17 100644 --- a/src/axi_sim_mem.sv +++ b/src/axi_sim_mem.sv @@ -29,9 +29,9 @@ module axi_sim_mem #( /// AXI User Width. parameter int unsigned UserWidth = 32'd0, /// AXI4 request struct definition - parameter type req_t = logic, + parameter type axi_req_t = logic, /// AXI4 response struct definition - parameter type rsp_t = logic, + parameter type axi_resp_t = logic, /// Warn on accesses to uninitialized bytes parameter bit WarnUninitialized = 1'b0, /// Application delay (measured after rising clock edge) @@ -40,13 +40,13 @@ module axi_sim_mem #( parameter time AcqDelay = 0ps ) ( /// Rising-edge clock - input logic clk_i, + input logic clk_i, /// Active-low reset - input logic rst_ni, + input logic rst_ni, /// AXI4 request struct - input req_t axi_req_i, + input axi_req_t axi_req_i, /// AXI4 response struct - output rsp_t axi_rsp_o + output axi_resp_t axi_rsp_o ); localparam int unsigned StrbWidth = DataWidth / 8; diff --git a/src/axi_to_axi_lite.sv b/src/axi_to_axi_lite.sv index c75887a61..29571bf5b 100644 --- a/src/axi_to_axi_lite.sv +++ b/src/axi_to_axi_lite.sv @@ -24,31 +24,31 @@ module axi_to_axi_lite #( parameter int unsigned AxiMaxWriteTxns = 32'd0, parameter int unsigned AxiMaxReadTxns = 32'd0, parameter bit FallThrough = 1'b1, // FIFOs in Fall through mode in ID reflect - parameter type full_req_t = logic, - parameter type full_resp_t = logic, - parameter type lite_req_t = logic, - parameter type lite_resp_t = logic + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, + parameter type axi_lite_req_t = logic, + parameter type axi_lite_resp_t = logic ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable // slave port full AXI4+ATOP - input full_req_t slv_req_i, - output full_resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, // master port AXI4-Lite - output lite_req_t mst_req_o, - input lite_resp_t mst_resp_i + output axi_lite_req_t mst_req_o, + input axi_lite_resp_t mst_resp_i ); // full bus declarations - full_req_t filtered_req, splitted_req; - full_resp_t filtered_resp, splitted_resp; + axi_req_t filtered_req, splitted_req; + axi_resp_t filtered_resp, splitted_resp; // atomics adapter so that atomics can be resolved axi_atop_filter #( .AxiIdWidth ( AxiIdWidth ), .AxiMaxWriteTxns ( AxiMaxWriteTxns ), - .req_t ( full_req_t ), - .resp_t ( full_resp_t ) + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) i_axi_atop_filter( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -66,8 +66,8 @@ module axi_to_axi_lite #( .DataWidth ( AxiDataWidth ), .IdWidth ( AxiIdWidth ), .UserWidth ( AxiUserWidth ), - .req_t ( full_req_t ), - .resp_t ( full_resp_t ) + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) i_axi_burst_splitter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -83,10 +83,10 @@ module axi_to_axi_lite #( .AxiMaxWriteTxns ( AxiMaxWriteTxns ), .AxiMaxReadTxns ( AxiMaxReadTxns ), .FallThrough ( FallThrough ), - .full_req_t ( full_req_t ), - .full_resp_t ( full_resp_t ), - .lite_req_t ( lite_req_t ), - .lite_resp_t ( lite_resp_t ) + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ) ) i_axi_to_axi_lite_id_reflect ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -119,20 +119,20 @@ module axi_to_axi_lite_id_reflect #( parameter int unsigned AxiMaxWriteTxns = 32'd0, parameter int unsigned AxiMaxReadTxns = 32'd0, parameter bit FallThrough = 1'b1, // FIFOs in fall through mode - parameter type full_req_t = logic, - parameter type full_resp_t = logic, - parameter type lite_req_t = logic, - parameter type lite_resp_t = logic + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, + parameter type axi_lite_req_t = logic, + parameter type axi_lite_resp_t = logic ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable // slave port full AXI - input full_req_t slv_req_i, - output full_resp_t slv_resp_o, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, // master port AXI LITE - output lite_req_t mst_req_o, - input lite_resp_t mst_resp_i + output axi_lite_req_t mst_req_o, + input axi_lite_resp_t mst_resp_i ); typedef logic [AxiIdWidth-1:0] id_t; @@ -275,21 +275,21 @@ module axi_to_axi_lite_intf #( `AXI_TYPEDEF_B_CHAN_T(full_b_chan_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(full_ar_chan_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(full_r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(full_req_t, full_aw_chan_t, full_w_chan_t, full_ar_chan_t) - `AXI_TYPEDEF_RESP_T(full_resp_t, full_b_chan_t, full_r_chan_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, full_aw_chan_t, full_w_chan_t, full_ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, full_b_chan_t, full_r_chan_t) // LITE channels typedef `AXI_LITE_TYPEDEF_AW_CHAN_T(lite_aw_chan_t, addr_t) `AXI_LITE_TYPEDEF_W_CHAN_T(lite_w_chan_t, data_t, strb_t) `AXI_LITE_TYPEDEF_B_CHAN_T(lite_b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(lite_ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T (lite_r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(lite_req_t, lite_aw_chan_t, lite_w_chan_t, lite_ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(lite_resp_t, lite_b_chan_t, lite_r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, lite_aw_chan_t, lite_w_chan_t, lite_ar_chan_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, lite_b_chan_t, lite_r_chan_t) - full_req_t full_req; - full_resp_t full_resp; - lite_req_t lite_req; - lite_resp_t lite_resp; + axi_req_t full_req; + axi_resp_t full_resp; + axi_lite_req_t lite_req; + axi_lite_resp_t lite_resp; `AXI_ASSIGN_TO_REQ(full_req, slv) `AXI_ASSIGN_FROM_RESP(slv, full_resp) @@ -305,10 +305,10 @@ module axi_to_axi_lite_intf #( .AxiMaxWriteTxns ( AXI_MAX_WRITE_TXNS ), .AxiMaxReadTxns ( AXI_MAX_READ_TXNS ), .FallThrough ( FALL_THROUGH ), // FIFOs in Fall through mode in ID reflect - .full_req_t ( full_req_t ), - .full_resp_t ( full_resp_t ), - .lite_req_t ( lite_req_t ), - .lite_resp_t ( lite_resp_t ) + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ) ) i_axi_to_axi_lite ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv index 80066dd26..6124d90a7 100644 --- a/src/axi_xbar.sv +++ b/src/axi_xbar.sv @@ -138,8 +138,8 @@ import cf_math_pkg::idx_width; .b_chan_t ( slv_b_chan_t ), // B Channel Type .ar_chan_t ( slv_ar_chan_t ), // AR Channel Type .r_chan_t ( slv_r_chan_t ), // R Channel Type - .req_t ( slv_req_t ), - .resp_t ( slv_resp_t ), + .axi_req_t ( slv_req_t ), + .axi_resp_t ( slv_resp_t ), .NoMstPorts ( Cfg.NoMstPorts + 1 ), .MaxTrans ( Cfg.MaxMstTrans ), .AxiLookBits ( Cfg.AxiIdUsedSlvPorts ), @@ -164,8 +164,8 @@ import cf_math_pkg::idx_width; axi_err_slv #( .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), - .req_t ( slv_req_t ), - .resp_t ( slv_resp_t ), + .axi_req_t ( slv_req_t ), + .axi_resp_t ( slv_resp_t ), .Resp ( axi_pkg::RESP_DECERR ), .ATOPs ( ATOPs ), .MaxTrans ( 4 ) // Transactions terminate at this slave, so minimize diff --git a/test/axi_synth_bench.sv b/test/axi_synth_bench.sv index 84adb96dc..9cb255890 100644 --- a/test/axi_synth_bench.sv +++ b/test/axi_synth_bench.sv @@ -387,8 +387,8 @@ module synth_axi_lite_xbar #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_t, r_chan_t) localparam axi_pkg::xbar_cfg_t XbarCfg = '{ NoSlvPorts: NoSlvMst, NoMstPorts: NoSlvMst, @@ -404,19 +404,19 @@ module synth_axi_lite_xbar #( axi_pkg::xbar_rule_32_t [NoSlvMst-1:0] addr_map; logic test; - req_t [NoSlvMst-1:0] mst_reqs, slv_reqs; - resp_t [NoSlvMst-1:0] mst_resps, slv_resps; + axi_lite_req_t [NoSlvMst-1:0] mst_reqs, slv_reqs; + axi_lite_resp_t [NoSlvMst-1:0] mst_resps, slv_resps; axi_lite_xbar #( - .Cfg ( XbarCfg ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ), - .rule_t ( axi_pkg::xbar_rule_32_t ) + .Cfg ( XbarCfg ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), + .rule_t ( axi_pkg::xbar_rule_32_t ) ) i_xbar_dut ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/test/tb_axi_lite_to_apb.sv b/test/tb_axi_lite_to_apb.sv index 8910198e4..fdf7349a7 100644 --- a/test/tb_axi_lite_to_apb.sv +++ b/test/tb_axi_lite_to_apb.sv @@ -50,8 +50,8 @@ module tb_axi_lite_to_apb #( `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) - `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, b_chan_t, r_chan_t) typedef logic [NoApbSlaves-1:0] sel_t; @@ -113,8 +113,8 @@ module tb_axi_lite_to_apb #( logic end_of_sim; // master structs - axi_req_t axi_req; - axi_resp_t axi_resp; + axi_lite_req_t axi_req; + axi_lite_resp_t axi_resp; // slave structs apb_req_t [NoApbSlaves-1:0] apb_req; @@ -234,8 +234,8 @@ module tb_axi_lite_to_apb #( .DataWidth ( AxiDataWidth ), .PipelineRequest ( TbPipelineRequest ), .PipelineResponse ( TbPipelineResponse ), - .axi_lite_req_t ( axi_req_t ), - .axi_lite_resp_t ( axi_resp_t ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), .apb_req_t ( apb_req_t ), .apb_resp_t ( apb_resp_t ), .rule_t ( rule_t ) diff --git a/test/tb_axi_sim_mem.sv b/test/tb_axi_sim_mem.sv index 711dba0f6..7383a9b31 100644 --- a/test/tb_axi_sim_mem.sv +++ b/test/tb_axi_sim_mem.sv @@ -42,18 +42,18 @@ module tb_axi_sim_mem #( `AXI_TYPEDEF_B_CHAN_T(b_t, id_t, user_t) `AXI_TYPEDEF_AR_CHAN_T(ar_t, addr_t, id_t, user_t) `AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_t, w_t, ar_t) - `AXI_TYPEDEF_RESP_T(rsp_t, b_t, r_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_t, w_t, ar_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_t, r_t) - req_t req; - rsp_t rsp; + axi_req_t req; + axi_resp_t rsp; axi_sim_mem #( .AddrWidth (TbAddrWidth), .DataWidth (TbDataWidth), .IdWidth (TbIdWidth), .UserWidth (TbUserWidth), - .req_t (req_t), - .rsp_t (rsp_t), + .axi_req_t (axi_req_t), + .axi_resp_t (axi_resp_t), .WarnUninitialized (TbWarnUninitialized), .ApplDelay (TbApplDelay), .AcqDelay (TbAcqDelay)