diff --git a/doc/axi_demux.md b/doc/axi_demux.md index 456e2668f..43008ba64 100644 --- a/doc/axi_demux.md +++ b/doc/axi_demux.md @@ -23,7 +23,7 @@ This demultiplexer is configured through the parameters listed in the following | Name | Type | Definition | |:---------------------|:-------------------|:-----------| | `IdWidth` | `int unsigned` | The AXI ID width (of all ports). | -| `NoMstPorts` | `int unsigned` | The number of AXI master ports of the demultiplexer (in other words, how many AXI slave modules can be attached). | +| `NumMstPorts` | `int unsigned` | The number of AXI master ports of the demultiplexer (in other words, how many AXI slave modules can be attached). | | `MaxTrans` | `int unsigned` | The slave port can have at most this many transactions [in flight](../doc#in-flight). | | `LookBits` | `int unsigned` | The number of ID bits (starting at the least significant) the demultiplexer uses to determine the uniqueness of an AXI ID (see section *Ordering and Stalls* below). This value has to be less or equal than `IdWidth`. | | `UniqueIds` | `bit` | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the demultiplexer (see section *Ordering and Stalls* below). Defaults to `1'b0`. | diff --git a/doc/axi_lite_demux.md b/doc/axi_lite_demux.md index cafbf267a..f3cfbd322 100644 --- a/doc/axi_lite_demux.md +++ b/doc/axi_lite_demux.md @@ -19,7 +19,7 @@ This demultiplexer is configured through the parameters listed in the following | Name | Type | Definition | |:---------------------|:-------------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| `NoMstPorts` | `int unsigned` | The number of AXI4-Lite master ports of the demultiplexer (in other words, how many AXI4-Lite slave modules can be attached). | +| `NumMstPorts` | `int unsigned` | The number of AXI4-Lite master ports of the demultiplexer (in other words, how many AXI4-Lite slave modules can be attached). | | `MaxTrans` | `int unsigned` | The slave port can have at most this many transactions [in flight](../doc#in-flight). | | `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel (i.e. don't consume a cycle). Enabling this allows the demultiplexer to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from `slv_aw_select_i`. | | `SpillXX` | `bit` | Inserts one spill register on the respective channel (AW, W, B, AR, and R) before the demultiplexer. | diff --git a/doc/axi_lite_mux.md b/doc/axi_lite_mux.md index a6afd7730..67d596975 100644 --- a/doc/axi_lite_mux.md +++ b/doc/axi_lite_mux.md @@ -10,7 +10,7 @@ The following table shows the parameters of the module. The module further requi | Name | Type | Function | |:--------------|:---------------|:---------------------------------------------------------------------------------------------------------------| -| `NoSlvPorts` | `int unsigned` | How many slave ports the multiplexer features. This many master modules can be connected to the multiplexer. | +| `NumSlvPorts` | `int unsigned` | How many slave ports the multiplexer features. This many master modules can be connected to the multiplexer. | | `MaxWTrans` | `int unsigned` | The depth of the FIFO holding the highest bits of the ID between the AW and W channel. | | `FallThrough` | `bit` | Is the FIFO between the AW and W channel in fall-through mode. Enabling will lead to an additional delay cycle | | `SpillXX` | `bit` | Enables the optional spill-register on the respective channel. | diff --git a/doc/axi_lite_xbar.md b/doc/axi_lite_xbar.md index c80e3d9ca..a1fd87c91 100644 --- a/doc/axi_lite_xbar.md +++ b/doc/axi_lite_xbar.md @@ -28,8 +28,8 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg | Name | Type | Definition | |:------------------|:-------------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| `NoSlvPorts` | `int unsigned` | The number of AXI4-Lite slave ports of the crossbar (in other words, how many AXI4-Lite master modules can be attached). | -| `NoMstPorts` | `int unsigned` | The number of AXI4-Lite master ports of the crossbar (in other words, how many AXI4-Lite slave modules can be attached). | +| `NumSlvPorts` | `int unsigned` | The number of AXI4-Lite slave ports of the crossbar (in other words, how many AXI4-Lite master modules can be attached). | +| `NumMstPorts` | `int unsigned` | The number of AXI4-Lite master ports of the crossbar (in other words, how many AXI4-Lite slave modules can be attached). | | `MaxMstTrans` | `int unsigned` | Each slave port can have at most this many transactions [in flight](../doc#in-flight). | | `MaxSlvTrans` | `int unsigned` | Each master port can have at most this many transactions [in flight](../doc#in-flight). | | `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel. Enabling this allows the crossbar to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from the AW channel. | @@ -38,7 +38,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg | `IdUsedSlvPorts` | `int unsigned` | Not used by the AXI4-Lite crossbar. Set `default: '0`. | | `AddrWidth` | `int unsigned` | The AXI4-Lite address width. | | `DataWidth` | `int unsigned` | The AXI4-Lite data width. | -| `NoAddrRules` | `int unsigned` | The number of address map rules. | +| `NumAddrRules` | `int unsigned` | The number of address map rules. | The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_rsp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses. diff --git a/doc/axi_mux.md b/doc/axi_mux.md index 77d76d71f..e774bd677 100644 --- a/doc/axi_mux.md +++ b/doc/axi_mux.md @@ -7,7 +7,7 @@ The opposite function to the AXI demultiplexer is performed by the AXI Multiplex The Multiplexer module is has a simpler structure than the demultiplexer introduced in the previous section. The requests on the AW and AR channels get merged with the same round robin arbitration used for merging the responses in the demultiplexer. One key difference however is the mechanism how the multiplexer determines from which slave port a request came. It uses for this the higher bits of the `axi_id` field of a request. The number of bits can be calculated with: ```systemverilog -$clog2(NoSlavePorts) +$clog2(NumSlavePorts) ``` This restricts the type of ID which can be sent through each slave port of the module. When the higher ID bits do not correspond to the index of the port the following response will be sent back through to the wrong master, leading to a breakdown of the functionality. So for using this module it is recommended to extend each AXI ID by the required amount of bits indicating the index of the respective slave port, before being sent over this module. @@ -25,7 +25,7 @@ The following table shows the parameters of the module. The module further requi | Name | Type | Function | |:------------ |:-------------- |:----------------------------------------------------------------------------------------------------------- | | `IdWidth` | `int unsigned` | The width of the AXI transaction ID in bits. | -| `NoSlvPorts` | `int unsigned` | How many slave ports the multiplexer features. This many master modules can be connected to the multiplexer.| +| `NumSlvPorts`| `int unsigned` | How many slave ports the multiplexer features. This many master modules can be connected to the multiplexer.| | `MaxWTrans` | `int unsigned` | The depth of the FIFO holding the highest bits of the ID between the AW and W channel. | | `FallThrough`| `bit` | Is the FIFO between the AW and W channel in fall-through mode. Enabling will lead to longer cycle delays. | | `SpillXX` | `bit` | Enables the optional spill-register on the respective channel. | diff --git a/doc/axi_xbar.md b/doc/axi_xbar.md index 1a351dc88..e45514e4f 100644 --- a/doc/axi_xbar.md +++ b/doc/axi_xbar.md @@ -12,7 +12,7 @@ A block-diagram of the crossbar is shown below: The crossbar has a configurable number of slave and master ports. -The ID width of the master ports is wider than that of the slave ports. The additional ID bits are used by the internal multiplexers to route responses. The ID width of the master ports must be `IdWidthSlvPorts + $clog_2(NoSlvPorts)`. +The ID width of the master ports is wider than that of the slave ports. The additional ID bits are used by the internal multiplexers to route responses. The ID width of the master ports must be `IdWidthSlvPorts + $clog_2(NumSlvPorts)`. ## Address Map @@ -41,8 +41,8 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg | Name | Type | Definition | |:------------------|:-------------------|:-----------| -| `NoSlvPorts` | `int unsigned` | The number of AXI slave ports of the crossbar (in other words, how many AXI master modules can be attached). | -| `NoMstPorts` | `int unsigned` | The number of AXI master ports of the crossbar (in other words, how many AXI slave modules can be attached). | +| `NumSlvPorts` | `int unsigned` | The number of AXI slave ports of the crossbar (in other words, how many AXI master modules can be attached). | +| `NumMstPorts` | `int unsigned` | The number of AXI master ports of the crossbar (in other words, how many AXI slave modules can be attached). | | `MaxMstTrans` | `int unsigned` | Each slave port can have at most this many transactions [in flight](../doc#in-flight). | | `MaxSlvTrans` | `int unsigned` | Each master port can have at most this many transactions per ID [in flight](../doc#in-flight). | | `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel. Enabling this allows the crossbar to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from the AW channel. | @@ -52,7 +52,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg | `UniqueIds` | `bit` | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the crossbar. See the [`axi_demux` documentation](axi_demux#ordering-and-stalls) for details. | | `AddrWidth` | `int unsigned` | The AXI address width. | | `DataWidth` | `int unsigned` | The AXI data width. | -| `NoAddrRules` | `int unsigned` | The number of address map rules. | +| `NumAddrRules` | `int unsigned` | The number of address map rules. | The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_rsp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses. diff --git a/scripts/axi_intercon_gen.py b/scripts/axi_intercon_gen.py index 8bc7acac4..da403b314 100644 --- a/scripts/axi_intercon_gen.py +++ b/scripts/axi_intercon_gen.py @@ -329,13 +329,13 @@ def write(self): ns = len(self.slaves) raw += """ - localparam int unsigned NoMasters = 32'd{}; // How many Axi Masters there are - localparam int unsigned NoSlaves = 32'd{}; // How many Axi Slaves there are + localparam int unsigned NumMasters = 32'd{}; // How many Axi Masters there are + localparam int unsigned NumSlaves = 32'd{}; // How many Axi Slaves there are // axi configuration localparam int unsigned IdWidthMasters = 32'd{}; localparam int unsigned IdUsed = 32'd{}; // Has to be <= IdWidthMasters - localparam int unsigned IdWidthSlaves = IdWidthMasters + $clog2(NoMasters); + localparam int unsigned IdWidthSlaves = IdWidthMasters + $clog2(NumMasters); localparam int unsigned AddrWidth = 32'd32; // Address Width localparam int unsigned DataWidth = 32'd64; // Data Width localparam int unsigned StrbWidth = DataWidth / 8; @@ -343,8 +343,8 @@ def write(self): """.format(nm, ns, max_idw, max_idw) raw += " localparam axi_pkg::xbar_cfg_t xbar_cfg = '{\n" raw += """ - NoSlvPorts: NoMasters, - NoMstPorts: NoSlaves, + NumSlvPorts: NumMasters, + NumMstPorts: NumSlaves, MaxMstTrans: 10, MaxSlvTrans: 6, FallThrough: 1'b0, @@ -354,7 +354,7 @@ def write(self): UniqueIds: 1'b0, AddrWidth: AddrWidth, DataWidth: DataWidth, - NoAddrRules: NoSlaves + NumAddrRules: NumSlaves """ raw += " };\n" raw += """ diff --git a/src/axi_burst_splitter.sv b/src/axi_burst_splitter.sv index 3fa9847dc..6dfac3ff9 100644 --- a/src/axi_burst_splitter.sv +++ b/src/axi_burst_splitter.sv @@ -75,7 +75,7 @@ module axi_burst_splitter #( .r_chan_t ( r_chan_t ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ), - .NoMstPorts ( 2 ), + .NumMstPorts ( 2 ), .MaxTrans ( MaxTxns ), .LookBits ( IdWidth ), .FallThrough ( 1'b1 ), diff --git a/src/axi_demux.sv b/src/axi_demux.sv index 5ae1bd06f..c4b566e14 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -47,7 +47,7 @@ module axi_demux #( parameter type r_chan_t = logic, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic, - parameter int unsigned NoMstPorts = 32'd0, + parameter int unsigned NumMstPorts = 32'd0, parameter int unsigned MaxTrans = 32'd8, parameter int unsigned LookBits = 32'd3, parameter bit UniqueIds = 1'b0, @@ -57,7 +57,7 @@ module axi_demux #( parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0, // Dependent parameters, DO NOT OVERRIDE! - parameter int unsigned SelectWidth = (NoMstPorts > 32'd1) ? $clog2(NoMstPorts) : 32'd1, + parameter int unsigned SelectWidth = (NumMstPorts > 32'd1) ? $clog2(NumMstPorts) : 32'd1, parameter type select_t = logic [SelectWidth-1:0] ) ( input logic clk_i, @@ -69,8 +69,8 @@ module axi_demux #( input select_t slv_ar_select_i, output axi_rsp_t slv_rsp_o, // Master Ports - output axi_req_t [NoMstPorts-1:0] mst_reqs_o, - input axi_rsp_t [NoMstPorts-1:0] mst_rsps_i + output axi_req_t [NumMstPorts-1:0] mst_reqs_o, + input axi_rsp_t [NumMstPorts-1:0] mst_rsps_i ); localparam int unsigned IdCounterWidth = cf_math_pkg::idx_width(MaxTrans); @@ -78,7 +78,7 @@ module axi_demux #( // pass through if only one master port - if (NoMstPorts == 32'h1) begin : gen_no_demux + if (NumMstPorts == 32'h1) begin : gen_no_demux spill_register #( .T ( aw_chan_t ), .Bypass ( ~SpillAw ) @@ -177,20 +177,20 @@ module axi_demux #( logic w_cnt_up, w_cnt_down; // Register which locks the AW valid signal - logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock; - logic aw_valid, aw_ready; + logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock; + logic aw_valid, aw_ready; // W channel from spill reg - w_chan_t slv_w_chan; - logic slv_w_valid, slv_w_ready; + w_chan_t slv_w_chan; + logic slv_w_valid, slv_w_ready; // B channles input into the arbitration - b_chan_t [NoMstPorts-1:0] mst_b_chans; - logic [NoMstPorts-1:0] mst_b_valids, mst_b_readies; + b_chan_t [NumMstPorts-1:0] mst_b_chans; + logic [NumMstPorts-1:0] mst_b_valids, mst_b_readies; // B channel to spill register - b_chan_t slv_b_chan; - logic slv_b_valid, slv_b_ready; + b_chan_t slv_b_chan; + logic slv_b_valid, slv_b_ready; //-------------------------------------- // Read Transaction @@ -200,21 +200,21 @@ module axi_demux #( logic slv_ar_ready, slv_ar_ready_chan, slv_ar_ready_sel; // AR ID counter - select_t lookup_ar_select; - logic ar_select_occupied, ar_id_cnt_full; - logic ar_push; + select_t lookup_ar_select; + logic ar_select_occupied, ar_id_cnt_full; + logic ar_push; // Register which locks the AR valid signel - logic lock_ar_valid_d, lock_ar_valid_q, load_ar_lock; - logic ar_valid, ar_ready; + logic lock_ar_valid_d, lock_ar_valid_q, load_ar_lock; + logic ar_valid, ar_ready; // R channles input into the arbitration - r_chan_t [NoMstPorts-1:0] mst_r_chans; - logic [NoMstPorts-1:0] mst_r_valids, mst_r_readies; + r_chan_t [NumMstPorts-1:0] mst_r_chans; + logic [NumMstPorts-1:0] mst_r_valids, mst_r_readies; // R channel to spill register - r_chan_t slv_r_chan; - logic slv_r_valid, slv_r_ready; + r_chan_t slv_r_chan; + logic slv_r_valid, slv_r_ready; //-------------------------------------- //-------------------------------------- @@ -329,7 +329,7 @@ module axi_demux #( assign aw_id_cnt_full = 1'b0; end else begin : gen_aw_id_counter axi_demux_id_counters #( - .IdBits ( LookBits ), + .IdBits ( LookBits ), .CounterWidth ( IdCounterWidth ), .mst_port_select_t ( select_t ) ) i_aw_id_counter ( @@ -410,10 +410,10 @@ module axi_demux #( // Arbitration of the different B responses rr_arb_tree #( - .NumIn ( NoMstPorts ), - .DataType ( b_chan_t ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) + .NumIn ( NumMstPorts ), + .DataType ( b_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) ) i_b_mux ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -522,7 +522,7 @@ module axi_demux #( assign ar_id_cnt_full = 1'b0; end else begin : gen_ar_id_counter axi_demux_id_counters #( - .IdBits ( LookBits ), + .IdBits ( LookBits ), .CounterWidth ( IdCounterWidth ), .mst_port_select_t ( select_t ) ) i_ar_id_counter ( @@ -562,10 +562,10 @@ module axi_demux #( // Arbitration of the different r responses rr_arb_tree #( - .NumIn ( NoMstPorts ), - .DataType ( r_chan_t ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) + .NumIn ( NumMstPorts ), + .DataType ( r_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) ) i_r_mux ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -591,7 +591,7 @@ module axi_demux #( slv_w_ready = 1'b0; w_cnt_down = 1'b0; - for (int unsigned i = 0; i < NoMstPorts; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin // AW channel mst_reqs_o[i].aw = slv_aw_chan; mst_reqs_o[i].aw_valid = 1'b0; @@ -623,7 +623,7 @@ module axi_demux #( end end // unpack the response B and R channels for the arbitration - for (genvar i = 0; i < NoMstPorts; i++) begin : gen_b_channels + for (genvar i = 0; i < NumMstPorts; i++) begin : gen_b_channels assign mst_b_chans[i] = mst_rsps_i[i].b; assign mst_b_valids[i] = mst_rsps_i[i].b_valid; assign mst_r_chans[i] = mst_rsps_i[i].r; @@ -636,20 +636,20 @@ module axi_demux #( `ifndef VERILATOR `ifndef XSIM initial begin: validate_params - no_mst_ports: assume (NoMstPorts > 0) else - $fatal(1, "The Number of slaves (NoMstPorts) has to be at least 1"); + no_mst_ports: assume (NumMstPorts > 0) else + $fatal(1, "The Number of slaves (NumMstPorts) has to be at least 1"); AXI_ID_BITS: assume (IdWidth >= LookBits) else $fatal(1, "IdBits has to be equal or smaller than IdWidth."); end default disable iff (!rst_ni); aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> - (slv_aw_select_i < NoMstPorts))) else + (slv_aw_select_i < NumMstPorts))) else $fatal(1, "slv_aw_select_i is %d: AW has selected a slave that is not defined.\ - NoMstPorts: %d", slv_aw_select_i, NoMstPorts); + NumMstPorts: %d", slv_aw_select_i, NumMstPorts); ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |-> - (slv_ar_select_i < NoMstPorts))) else + (slv_ar_select_i < NumMstPorts))) else $fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\ - NoMstPorts: %d", slv_ar_select_i, NoMstPorts); + NumMstPorts: %d", slv_ar_select_i, NumMstPorts); aw_valid_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) |=> aw_valid) else $fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle."); ar_valid_stable: assert property( @(posedge clk_i) @@ -668,10 +668,10 @@ module axi_demux #( |=> $stable(slv_ar_select)) else $fatal(1, "slv_ar_select unstable with valid set."); internal_ar_select: assert property( @(posedge clk_i) - (ar_valid |-> slv_ar_select < NoMstPorts)) + (ar_valid |-> slv_ar_select < NumMstPorts)) else $fatal(1, "slv_ar_select illegal while ar_valid."); internal_aw_select: assert property( @(posedge clk_i) - (aw_valid |-> slv_aw_select < NoMstPorts)) + (aw_valid |-> slv_aw_select < NumMstPorts)) else $fatal(1, "slv_aw_select illegal while aw_valid."); w_underflow: assert property( @(posedge clk_i) ((w_open == '0) && (w_cnt_up ^ w_cnt_down) |-> !w_cnt_down)) else @@ -707,14 +707,14 @@ module axi_demux_id_counters #( input logic [IdBits-1:0] pop_axi_id_i, input logic pop_i ); - localparam int unsigned NoCounters = 2**IdBits; + localparam int unsigned NumCounters = 2**IdBits; typedef logic [CounterWidth-1:0] cnt_t; // registers, each gets loaded when push_en[i] - mst_port_select_t [NoCounters-1:0] mst_select_q; + mst_port_select_t [NumCounters-1:0] mst_select_q; // counter signals - logic [NoCounters-1:0] push_en, inject_en, pop_en, occupied, cnt_full; + logic [NumCounters-1:0] push_en, inject_en, pop_en, occupied, cnt_full; //----------------------------------- // Lookup @@ -729,7 +729,7 @@ module axi_demux_id_counters #( assign pop_en = (pop_i) ? (1 << pop_axi_id_i) : '0; assign full_o = |cnt_full; // counters - for (genvar i = 0; i < NoCounters; i++) begin : gen_counters + for (genvar i = 0; i < NumCounters; i++) begin : gen_counters logic cnt_en, cnt_down, overflow; cnt_t cnt_delta, in_flight; always_comb begin @@ -871,7 +871,7 @@ module axi_demux_intf #( .r_chan_t ( r_chan_t ), // R Channel Type .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ), - .NoMstPorts ( NO_MST_PORTS ), + .NumMstPorts ( NO_MST_PORTS ), .MaxTrans ( MAX_TRANS ), .LookBits ( AXI_LOOK_BITS ), .UniqueIds ( UNIQUE_IDS ), diff --git a/src/axi_dw_downsizer.sv b/src/axi_dw_downsizer.sv index b668f66e9..07815fab2 100644 --- a/src/axi_dw_downsizer.sv +++ b/src/axi_dw_downsizer.sv @@ -209,18 +209,18 @@ module axi_dw_downsizer #( logic mst_req_aw_err; axi_demux #( - .IdWidth (IdWidth ), - .LookBits (IdWidth ), - .aw_chan_t (aw_chan_t ), - .w_chan_t (mst_w_chan_t ), - .b_chan_t (b_chan_t ), - .ar_chan_t (ar_chan_t ), - .r_chan_t (mst_r_chan_t ), - .axi_req_t (mst_port_axi_req_t), - .axi_rsp_t (mst_port_axi_rsp_t), - .NoMstPorts (2 ), - .MaxTrans (MaxReads ), - .SpillAw (1'b1 ) // Required to break dependency between AW and W channels + .IdWidth (IdWidth ), + .LookBits (IdWidth ), + .aw_chan_t (aw_chan_t ), + .w_chan_t (mst_w_chan_t ), + .b_chan_t (b_chan_t ), + .ar_chan_t (ar_chan_t ), + .r_chan_t (mst_r_chan_t ), + .axi_req_t (mst_port_axi_req_t), + .axi_rsp_t (mst_port_axi_rsp_t), + .NumMstPorts (2 ), + .MaxTrans (MaxReads ), + .SpillAw (1'b1 ) // Required to break dependency between AW and W channels ) i_axi_demux ( .clk_i (clk_i ), .rst_ni (rst_ni ), diff --git a/src/axi_dw_upsizer.sv b/src/axi_dw_upsizer.sv index 38b4caf0a..3d2743825 100644 --- a/src/axi_dw_upsizer.sv +++ b/src/axi_dw_upsizer.sv @@ -206,18 +206,18 @@ module axi_dw_upsizer #( logic mst_req_aw_err; axi_demux #( - .IdWidth (IdWidth ), - .LookBits (IdWidth ), - .aw_chan_t (aw_chan_t ), - .w_chan_t (mst_w_chan_t ), - .b_chan_t (b_chan_t ), - .ar_chan_t (ar_chan_t ), - .r_chan_t (mst_r_chan_t ), - .axi_req_t (mst_port_axi_req_t), - .axi_rsp_t (mst_port_axi_rsp_t), - .NoMstPorts (2 ), - .MaxTrans (MaxReads ), - .SpillAw (1'b1 ) // Required to break dependency between AW and W channels + .IdWidth (IdWidth ), + .LookBits (IdWidth ), + .aw_chan_t (aw_chan_t ), + .w_chan_t (mst_w_chan_t ), + .b_chan_t (b_chan_t ), + .ar_chan_t (ar_chan_t ), + .r_chan_t (mst_r_chan_t ), + .axi_req_t (mst_port_axi_req_t), + .axi_rsp_t (mst_port_axi_rsp_t), + .NumMstPorts (2 ), + .MaxTrans (MaxReads ), + .SpillAw (1'b1 ) // Required to break dependency between AW and W channels ) i_axi_demux ( .clk_i (clk_i ), .rst_ni (rst_ni ), diff --git a/src/axi_id_prepend.sv b/src/axi_id_prepend.sv index 39ce56025..305039cb2 100644 --- a/src/axi_id_prepend.sv +++ b/src/axi_id_prepend.sv @@ -16,7 +16,7 @@ // Constraints enforced through assertions: ID width of slave and master port module axi_id_prepend #( - parameter int unsigned NoBus = 1, // Can take multiple axi busses + parameter int unsigned NumBus = 1, // Can take multiple axi busses parameter int unsigned IdWidthSlvPort = 4, // AXI ID Width of the Slave Ports parameter int unsigned IdWidthMstPort = 6, // AXI ID Width of the Master Ports parameter type slv_aw_chan_t = logic, // AW Channel Type for slv port @@ -35,50 +35,50 @@ module axi_id_prepend #( input logic [PreIdWidth-1:0] pre_id_i, // ID to be prepended // slave port (input), connect master modules here // AW channel - input slv_aw_chan_t [NoBus-1:0] slv_aw_chans_i, - input logic [NoBus-1:0] slv_aw_valids_i, - output logic [NoBus-1:0] slv_aw_readies_o, + input slv_aw_chan_t [NumBus-1:0] slv_aw_chans_i, + input logic [NumBus-1:0] slv_aw_valids_i, + output logic [NumBus-1:0] slv_aw_readies_o, // W channel - input slv_w_chan_t [NoBus-1:0] slv_w_chans_i, - input logic [NoBus-1:0] slv_w_valids_i, - output logic [NoBus-1:0] slv_w_readies_o, + input slv_w_chan_t [NumBus-1:0] slv_w_chans_i, + input logic [NumBus-1:0] slv_w_valids_i, + output logic [NumBus-1:0] slv_w_readies_o, // B channel - output slv_b_chan_t [NoBus-1:0] slv_b_chans_o, - output logic [NoBus-1:0] slv_b_valids_o, - input logic [NoBus-1:0] slv_b_readies_i, + output slv_b_chan_t [NumBus-1:0] slv_b_chans_o, + output logic [NumBus-1:0] slv_b_valids_o, + input logic [NumBus-1:0] slv_b_readies_i, // AR channel - input slv_ar_chan_t [NoBus-1:0] slv_ar_chans_i, - input logic [NoBus-1:0] slv_ar_valids_i, - output logic [NoBus-1:0] slv_ar_readies_o, + input slv_ar_chan_t [NumBus-1:0] slv_ar_chans_i, + input logic [NumBus-1:0] slv_ar_valids_i, + output logic [NumBus-1:0] slv_ar_readies_o, // R channel - output slv_r_chan_t [NoBus-1:0] slv_r_chans_o, - output logic [NoBus-1:0] slv_r_valids_o, - input logic [NoBus-1:0] slv_r_readies_i, + output slv_r_chan_t [NumBus-1:0] slv_r_chans_o, + output logic [NumBus-1:0] slv_r_valids_o, + input logic [NumBus-1:0] slv_r_readies_i, // master ports (output), connect slave modules here // AW channel - output mst_aw_chan_t [NoBus-1:0] mst_aw_chans_o, - output logic [NoBus-1:0] mst_aw_valids_o, - input logic [NoBus-1:0] mst_aw_readies_i, + output mst_aw_chan_t [NumBus-1:0] mst_aw_chans_o, + output logic [NumBus-1:0] mst_aw_valids_o, + input logic [NumBus-1:0] mst_aw_readies_i, // W channel - output mst_w_chan_t [NoBus-1:0] mst_w_chans_o, - output logic [NoBus-1:0] mst_w_valids_o, - input logic [NoBus-1:0] mst_w_readies_i, + output mst_w_chan_t [NumBus-1:0] mst_w_chans_o, + output logic [NumBus-1:0] mst_w_valids_o, + input logic [NumBus-1:0] mst_w_readies_i, // B channel - input mst_b_chan_t [NoBus-1:0] mst_b_chans_i, - input logic [NoBus-1:0] mst_b_valids_i, - output logic [NoBus-1:0] mst_b_readies_o, + input mst_b_chan_t [NumBus-1:0] mst_b_chans_i, + input logic [NumBus-1:0] mst_b_valids_i, + output logic [NumBus-1:0] mst_b_readies_o, // AR channel - output mst_ar_chan_t [NoBus-1:0] mst_ar_chans_o, - output logic [NoBus-1:0] mst_ar_valids_o, - input logic [NoBus-1:0] mst_ar_readies_i, + output mst_ar_chan_t [NumBus-1:0] mst_ar_chans_o, + output logic [NumBus-1:0] mst_ar_valids_o, + input logic [NumBus-1:0] mst_ar_readies_i, // R channel - input mst_r_chan_t [NoBus-1:0] mst_r_chans_i, - input logic [NoBus-1:0] mst_r_valids_i, - output logic [NoBus-1:0] mst_r_readies_o + input mst_r_chan_t [NumBus-1:0] mst_r_chans_i, + input logic [NumBus-1:0] mst_r_valids_i, + output logic [NumBus-1:0] mst_r_readies_o ); // prepend the ID - for (genvar i = 0; i < NoBus; i++) begin : gen_id_prepend + for (genvar i = 0; i < NumBus; i++) begin : gen_id_prepend if (PreIdWidth == 0) begin : gen_no_prepend assign mst_aw_chans_o[i] = slv_aw_chans_i[i]; assign mst_ar_chans_o[i] = slv_ar_chans_i[i]; @@ -112,7 +112,7 @@ module axi_id_prepend #( // pragma translate_off `ifndef VERILATOR initial begin : p_assert - assert(NoBus > 0) + assert(NumBus > 0) else $fatal(1, "Input must be at least one element wide."); assert(PreIdWidth == ($bits(mst_aw_chans_o[0].id) - $bits(slv_aw_chans_i[0].id))) else $fatal(1, "Prepend ID Width must be: $bits(mst_aw_chans_o.id)-$bits(slv_aw_chans_i.id)"); diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv index c60801036..f982b4f60 100644 --- a/src/axi_id_serialize.sv +++ b/src/axi_id_serialize.sv @@ -159,7 +159,7 @@ module axi_id_serialize #( .r_chan_t ( slv_r_t ), .axi_req_t ( slv_port_axi_req_t ), .axi_rsp_t ( slv_port_axi_rsp_t ), - .NoMstPorts ( MstPortMaxUniqIds ), + .NumMstPorts ( MstPortMaxUniqIds ), .MaxTrans ( SlvPortMaxTxns ), .LookBits ( SlvPortIdWidth ), .AtopSupport ( AtopSupport ), @@ -231,7 +231,7 @@ module axi_id_serialize #( .slv_port_axi_rsp_t ( ser_rsp_t ), .mst_port_axi_req_t ( mux_req_t ), .mst_port_axi_rsp_t ( mux_rsp_t ), - .NoSlvPorts ( MstPortMaxUniqIds ), + .NumSlvPorts ( MstPortMaxUniqIds ), .MaxWTrans ( MstPortMaxTxnsPerId ), .FallThrough ( 1'b0 ), .SpillAw ( 1'b1 ), @@ -261,7 +261,7 @@ module axi_id_serialize #( end end else begin : gen_no_id_shift axi_id_prepend #( - .NoBus ( 32'd1 ), + .NumBus ( 32'd1 ), .IdWidthSlvPort ( MuxIdWidth ), .IdWidthMstPort ( MstPortIdWidth ), .slv_aw_chan_t ( mux_aw_t ), diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv index d5a29085c..68626c588 100644 --- a/src/axi_isolate.sv +++ b/src/axi_isolate.sv @@ -102,7 +102,7 @@ module axi_isolate #( .r_chan_t ( r_chan_t ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ), - .NoMstPorts ( 2 ), + .NumMstPorts ( 2 ), .MaxTrans ( NumPending ), // We don't need many bits here as the common case will be to go for the pass-through. .LookBits ( 1 ), diff --git a/src/axi_iw_converter.sv b/src/axi_iw_converter.sv index a1b20038d..377a9af4a 100644 --- a/src/axi_iw_converter.sv +++ b/src/axi_iw_converter.sv @@ -168,7 +168,7 @@ module axi_iw_converter #( end end else if (MstPortIdWidth > SlvPortIdWidth) begin : gen_upsize axi_id_prepend #( - .NoBus ( 32'd1 ), + .NumBus ( 32'd1 ), .IdWidthSlvPort ( SlvPortIdWidth ), .IdWidthMstPort ( MstPortIdWidth ), .slv_aw_chan_t ( slv_aw_t ), diff --git a/src/axi_lite_demux.sv b/src/axi_lite_demux.sv index 9512e1293..9f0901e31 100644 --- a/src/axi_lite_demux.sv +++ b/src/axi_lite_demux.sv @@ -32,7 +32,7 @@ module axi_lite_demux #( parameter type r_chan_t = logic, // AXI4-Lite R channel parameter type axi_lite_req_t = logic, // AXI4-Lite request struct parameter type axi_lite_rsp_t = logic, // AXI4-Lite response struct - parameter int unsigned NoMstPorts = 32'd0, // Number of instantiated ports + parameter int unsigned NumMstPorts = 32'd0, // Number of instantiated ports parameter int unsigned MaxTrans = 32'd0, // Maximum number of open transactions per channel parameter bit FallThrough = 1'b0, // FIFOs are in fall through mode parameter bit SpillAw = 1'b1, // insert one cycle latency on slave AW @@ -41,19 +41,19 @@ module axi_lite_demux #( parameter bit SpillAr = 1'b1, // insert one cycle latency on slave AR parameter bit SpillR = 1'b0, // insert one cycle latency on slave R // Dependent parameters, DO NOT OVERRIDE! - parameter type select_t = logic [$clog2(NoMstPorts)-1:0] + parameter type select_t = logic [$clog2(NumMstPorts)-1:0] ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, + input logic clk_i, + input logic rst_ni, + input logic test_i, // slave port (AXI4-Lite input), connect master module here - input axi_lite_req_t slv_req_i, - input select_t slv_aw_select_i, - input select_t slv_ar_select_i, - output axi_lite_rsp_t slv_rsp_o, + input axi_lite_req_t slv_req_i, + input select_t slv_aw_select_i, + input select_t slv_ar_select_i, + output axi_lite_rsp_t slv_rsp_o, // master ports (AXI4-Lite outputs), connect slave modules here - output axi_lite_req_t [NoMstPorts-1:0] mst_reqs_o, - input axi_lite_rsp_t [NoMstPorts-1:0] mst_rsps_i + output axi_lite_req_t [NumMstPorts-1:0] mst_reqs_o, + input axi_lite_rsp_t [NumMstPorts-1:0] mst_rsps_i ); //-------------------------------------- @@ -68,7 +68,7 @@ module axi_lite_demux #( select_t select; } ar_chan_select_t; - if (NoMstPorts == 32'd1) begin : gen_no_demux + if (NumMstPorts == 32'd1) begin : gen_no_demux // degenerate case, connect slave to master port spill_register #( .T ( aw_chan_t ), @@ -149,26 +149,26 @@ module axi_lite_demux #( //-------------------------------------- // Write Transaction //-------------------------------------- - aw_chan_select_t slv_aw_chan; - logic slv_aw_valid, slv_aw_ready; + aw_chan_select_t slv_aw_chan; + logic slv_aw_valid, slv_aw_ready; - logic [NoMstPorts-1:0] mst_aw_valids, mst_aw_readies; + logic [NumMstPorts-1:0] mst_aw_valids, mst_aw_readies; - logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock; + logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock; - logic w_fifo_push, w_fifo_pop; - logic w_fifo_full, w_fifo_empty; + logic w_fifo_push, w_fifo_pop; + logic w_fifo_full, w_fifo_empty; - w_chan_t slv_w_chan; - select_t w_select; - logic slv_w_valid, slv_w_ready; + w_chan_t slv_w_chan; + select_t w_select; + logic slv_w_valid, slv_w_ready; - logic /*w_pop*/ b_fifo_pop; - logic b_fifo_full, b_fifo_empty; + logic /*w_pop*/ b_fifo_pop; + logic b_fifo_full, b_fifo_empty; - b_chan_t slv_b_chan; - select_t b_select; - logic slv_b_valid, slv_b_ready; + b_chan_t slv_b_chan; + select_t b_select; + logic slv_b_valid, slv_b_ready; //-------------------------------------- // Read Transaction @@ -220,7 +220,7 @@ module axi_lite_demux #( assign slv_aw_chan = slv_aw_chan_select_out_flat; // replicate AW channel to the request output - for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_aw + for (genvar i = 0; i < NumMstPorts; i++) begin : gen_mst_aw assign mst_reqs_o[i].aw = slv_aw_chan.aw; assign mst_reqs_o[i].aw_valid = mst_aw_valids[i]; assign mst_aw_readies[i] = mst_rsps_i[i].aw_ready; @@ -303,7 +303,7 @@ module axi_lite_demux #( ); // replicate W channel - for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_w + for (genvar i = 0; i < NumMstPorts; i++) begin : gen_mst_w assign mst_reqs_o[i].w = slv_w_chan; assign mst_reqs_o[i].w_valid = ~w_fifo_empty & ~b_fifo_full & slv_w_valid & (w_select == select_t'(i)); @@ -349,7 +349,7 @@ module axi_lite_demux #( // connect the response if the FIFO has valid data in it assign slv_b_chan = (!b_fifo_empty) ? mst_rsps_i[b_select].b : '0; assign slv_b_valid = ~b_fifo_empty & mst_rsps_i[b_select].b_valid; - for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_b + for (genvar i = 0; i < NumMstPorts; i++) begin : gen_mst_b assign mst_reqs_o[i].b_ready = ~b_fifo_empty & slv_b_ready & (b_select == select_t'(i)); end assign b_fifo_pop = slv_b_valid & slv_b_ready; @@ -382,7 +382,7 @@ module axi_lite_demux #( assign slv_ar_chan = slv_ar_chan_select_out_flat; // replicate AR channel - for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_ar + for (genvar i = 0; i < NumMstPorts; i++) begin : gen_mst_ar assign mst_reqs_o[i].ar = slv_ar_chan.ar; assign mst_reqs_o[i].ar_valid = ~r_fifo_full & slv_ar_valid & (slv_ar_chan.select == select_t'(i)); @@ -435,7 +435,7 @@ module axi_lite_demux #( end end - for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_r + for (genvar i = 0; i < NumMstPorts; i++) begin : gen_mst_r assign mst_reqs_o[i].r_ready = ~r_fifo_empty & slv_r_ready & (r_select == select_t'(i)); end assign r_fifo_pop = slv_r_valid & slv_r_ready; @@ -444,13 +444,13 @@ module axi_lite_demux #( `ifndef VERILATOR default disable iff (!rst_ni); aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> - (slv_aw_select_i < NoMstPorts))) else + (slv_aw_select_i < NumMstPorts))) else $fatal(1, "slv_aw_select_i is %d: AW has selected a slave that is not defined.\ - NoMstPorts: %d", slv_aw_select_i, NoMstPorts); + NumMstPorts: %d", slv_aw_select_i, NumMstPorts); ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |-> - (slv_ar_select_i < NoMstPorts))) else + (slv_ar_select_i < NumMstPorts))) else $fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\ - NoMstPorts: %d", slv_ar_select_i, NoMstPorts); + NumMstPorts: %d", slv_ar_select_i, NumMstPorts); aw_valid_stable: assert property( @(posedge clk_i) (slv_aw_valid && !slv_aw_ready) |=> slv_aw_valid) else $fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle."); @@ -470,8 +470,8 @@ module axi_lite_demux #( // pragma translate_off `ifndef VERILATOR initial begin: p_assertions - NoPorts: assert (NoMstPorts > 0) else $fatal("Number of master ports must be at least 1!"); - MaxTnx: assert (MaxTrans > 0) else $fatal("Number of transactions must be at least 1!"); + NumPorts: assert (NumMstPorts > 0) else $fatal("Number of master ports must be at least 1!"); + MaxTnx: assert (MaxTrans > 0) else $fatal("Number of transactions must be at least 1!"); end `endif // pragma translate_on @@ -483,7 +483,7 @@ endmodule module axi_lite_demux_intf #( parameter int unsigned AddrWidth = 32'd0, parameter int unsigned DataWidth = 32'd0, - parameter int unsigned NoMstPorts = 32'd0, + parameter int unsigned NumMstPorts = 32'd0, parameter int unsigned MaxTrans = 32'd0, parameter bit FallThrough = 1'b0, parameter bit SpillAw = 1'b1, @@ -492,7 +492,7 @@ module axi_lite_demux_intf #( parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0, // Dependent parameters, DO NOT OVERRIDE! - parameter type select_t = logic [$clog2(NoMstPorts)-1:0] + parameter type select_t = logic [$clog2(NumMstPorts)-1:0] ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -500,7 +500,7 @@ module axi_lite_demux_intf #( input select_t slv_aw_select_i, // has to be stable, when aw_valid input select_t slv_ar_select_i, // has to be stable, when ar_valid AXI_LITE.Slave slv, // slave port - AXI_LITE.Master mst [NoMstPorts-1:0] // master ports + AXI_LITE.Master mst [NumMstPorts-1:0]// master ports ); typedef logic [AddrWidth-1:0] addr_t; typedef logic [DataWidth-1:0] data_t; @@ -513,15 +513,15 @@ module axi_lite_demux_intf #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - axi_lite_req_t slv_req; - axi_lite_rsp_t slv_rsp; - axi_lite_req_t [NoMstPorts-1:0] mst_reqs; - axi_lite_rsp_t [NoMstPorts-1:0] mst_rsps; + axi_lite_req_t slv_req; + axi_lite_rsp_t slv_rsp; + axi_lite_req_t [NumMstPorts-1:0] mst_reqs; + axi_lite_rsp_t [NumMstPorts-1:0] mst_rsps; `AXI_LITE_ASSIGN_TO_REQ(slv_req, slv) `AXI_LITE_ASSIGN_FROM_RSP(slv, slv_rsp) - for (genvar i = 0; i < NoMstPorts; i++) begin : gen_assign_mst_ports + for (genvar i = 0; i < NumMstPorts; i++) begin : gen_assign_mst_ports `AXI_LITE_ASSIGN_FROM_REQ(mst[i], mst_reqs[i]) `AXI_LITE_ASSIGN_TO_RSP(mst_rsps[i], mst[i]) end @@ -534,7 +534,7 @@ module axi_lite_demux_intf #( .r_chan_t ( r_chan_t ), .axi_lite_req_t ( axi_lite_req_t ), .axi_lite_rsp_t ( axi_lite_rsp_t ), - .NoMstPorts ( NoMstPorts ), + .NumMstPorts ( NumMstPorts ), .MaxTrans ( MaxTrans ), .FallThrough ( FallThrough ), .SpillAw ( SpillAw ), diff --git a/src/axi_lite_mailbox.sv b/src/axi_lite_mailbox.sv index a89cf1f1b..56a10d498 100644 --- a/src/axi_lite_mailbox.sv +++ b/src/axi_lite_mailbox.sv @@ -237,7 +237,7 @@ module axi_lite_mailbox_slave #( `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t) `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t) - localparam int unsigned NoRegs = 32'd10; + localparam int unsigned NumRegs = 32'd10; typedef enum logic [3:0] { MBOXW = 4'd0, // Mailbox write register MBOXR = 4'd1, // Mailbox read register @@ -257,7 +257,7 @@ module axi_lite_mailbox_slave #( addr_t end_addr; } rule_t; // output type of the address decoders, to be casted onto the enum type `reg_e` - typedef logic [$clog2(NoRegs)-1:0] idx_t; + typedef logic [$clog2(NumRegs)-1:0] idx_t; // LITE response signals, go into the output spill registers to prevent combinational response logic b_valid, b_ready; @@ -265,8 +265,8 @@ module axi_lite_mailbox_slave #( logic r_valid, r_ready; r_chan_lite_t r_chan; // address map generation - rule_t [NoRegs-1:0] addr_map; - for (genvar i = 0; i < NoRegs; i++) begin : gen_addr_map + rule_t [NumRegs-1:0] addr_map; + for (genvar i = 0; i < NumRegs; i++) begin : gen_addr_map assign addr_map[i] = '{ idx: i, start_addr: base_addr_i + i * (DataWidth / 8), @@ -490,10 +490,10 @@ module axi_lite_mailbox_slave #( // address decoder and response FIFOs for the LITE channel, the port can take a new transaction if // these FIFOs are not full, not fall through to prevent combinational paths to the return path addr_decode #( - .NoIndices( NoRegs ), - .NoRules ( NoRegs ), - .addr_t ( addr_t ), - .rule_t ( rule_t ) + .NoIndices( NumRegs ), + .NoRules ( NumRegs ), + .addr_t ( addr_t ), + .rule_t ( rule_t ) ) i_waddr_decode ( .addr_i ( slv_req_i.aw.addr ), .addr_map_i ( addr_map ), @@ -516,10 +516,10 @@ module axi_lite_mailbox_slave #( .data_o ( slv_rsp_o.b ) ); addr_decode #( - .NoIndices( NoRegs ), - .NoRules ( NoRegs ), - .addr_t ( addr_t ), - .rule_t ( rule_t ) + .NoIndices( NumRegs ), + .NoRules ( NumRegs ), + .addr_t ( addr_t ), + .rule_t ( rule_t ) ) i_raddr_decode ( .addr_i ( slv_req_i.ar.addr ), .addr_map_i ( addr_map ), diff --git a/src/axi_lite_mux.sv b/src/axi_lite_mux.sv index ee4908553..7d0cb477e 100644 --- a/src/axi_lite_mux.sv +++ b/src/axi_lite_mux.sv @@ -29,7 +29,7 @@ module axi_lite_mux #( parameter type r_chan_t = logic, // R LITE Channel Type parameter type axi_lite_req_t = logic, // AXI4-Lite request type parameter type axi_lite_rsp_t = logic, // AXI4-Lite response type - parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports + parameter int unsigned NumSlvPorts = 32'd0, // Number of slave ports // Maximum number of outstanding transactions per write or read parameter int unsigned MaxTrans = 32'd0, // If enabled, this multiplexer is purely combinatorial @@ -42,18 +42,18 @@ module axi_lite_mux #( parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0 ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Test Mode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Test Mode enable // slave ports (AXI4-Lite inputs), connect master modules here - input axi_lite_req_t [NoSlvPorts-1:0] slv_reqs_i, - output axi_lite_rsp_t [NoSlvPorts-1:0] slv_rsps_o, + input axi_lite_req_t [NumSlvPorts-1:0] slv_reqs_i, + output axi_lite_rsp_t [NumSlvPorts-1:0] slv_rsps_o, // master port (AXI4-Lite output), connect slave module here - output axi_lite_req_t mst_req_o, - input axi_lite_rsp_t mst_rsp_i + output axi_lite_req_t mst_req_o, + input axi_lite_rsp_t mst_rsp_i ); // pass through if only one slave port - if (NoSlvPorts == 32'h1) begin : gen_no_mux + if (NumSlvPorts == 32'h1) begin : gen_no_mux spill_register #( .T ( aw_chan_t ), .Bypass ( ~SpillAw ) @@ -123,11 +123,11 @@ module axi_lite_mux #( // other non degenerate cases end else begin : gen_mux // typedef for the FIFO types - typedef logic [$clog2(NoSlvPorts)-1:0] select_t; + typedef logic [$clog2(NumSlvPorts)-1:0] select_t; // input to the AW arbitration tree, unpacked from request struct - aw_chan_t [NoSlvPorts-1:0] slv_aw_chans; - logic [NoSlvPorts-1:0] slv_aw_valids, slv_aw_readies; + aw_chan_t [NumSlvPorts-1:0] slv_aw_chans; + logic [NumSlvPorts-1:0] slv_aw_valids, slv_aw_readies; // AW channel arb tree decision select_t aw_select; @@ -163,8 +163,8 @@ module axi_lite_mux #( logic mst_b_valid, mst_b_ready; // input to the AR arbitration tree, unpacked from request struct - ar_chan_t [NoSlvPorts-1:0] slv_ar_chans; - logic [NoSlvPorts-1:0] slv_ar_valids, slv_ar_readies; + ar_chan_t [NumSlvPorts-1:0] slv_ar_chans; + logic [NumSlvPorts-1:0] slv_ar_valids, slv_ar_readies; // AR channel for when spill is enabled select_t ar_select; @@ -189,16 +189,16 @@ module axi_lite_mux #( // AW Channel //-------------------------------------- // unpach AW channel from request/response array - for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_aw_arb_input + for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_aw_arb_input assign slv_aw_chans[i] = slv_reqs_i[i].aw; assign slv_aw_valids[i] = slv_reqs_i[i].aw_valid; assign slv_rsps_o[i].aw_ready = slv_aw_readies[i]; end rr_arb_tree #( - .NumIn ( NoSlvPorts ), - .DataType ( aw_chan_t ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) + .NumIn ( NumSlvPorts ), + .DataType ( aw_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) ) i_aw_arbiter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -285,7 +285,7 @@ module axi_lite_mux #( // multiplexer assign mst_w_chan = slv_reqs_i[w_select].w; assign mst_w_valid = (!w_fifo_empty && !b_fifo_full) ? slv_reqs_i[w_select].w_valid : 1'b0; - for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_slv_w_ready + for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_slv_w_ready assign slv_rsps_o[i].w_ready = mst_w_ready & ~w_fifo_empty & ~b_fifo_full & (w_select == select_t'(i)); end @@ -327,7 +327,7 @@ module axi_lite_mux #( // B Channel //-------------------------------------- // replicate B channels - for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_slv_rsps_b + for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_slv_rsps_b assign slv_rsps_o[i].b = mst_b_chan; assign slv_rsps_o[i].b_valid = mst_b_valid & ~b_fifo_empty & (b_select == select_t'(i)); end @@ -352,16 +352,16 @@ module axi_lite_mux #( // AR Channel //-------------------------------------- // unpack AR channel from request/response struct - for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_ar_arb_input + for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_ar_arb_input assign slv_ar_chans[i] = slv_reqs_i[i].ar; assign slv_ar_valids[i] = slv_reqs_i[i].ar_valid; assign slv_rsps_o[i].ar_ready = slv_ar_readies[i]; end rr_arb_tree #( - .NumIn ( NoSlvPorts ), - .DataType ( ar_chan_t ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) + .NumIn ( NumSlvPorts ), + .DataType ( ar_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) ) i_ar_arbiter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -418,7 +418,7 @@ module axi_lite_mux #( // R Channel //-------------------------------------- // replicate R channels - for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_slv_rsps_r + for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_slv_rsps_r assign slv_rsps_o[i].r = mst_r_chan; assign slv_rsps_o[i].r_valid = mst_r_valid & ~r_fifo_empty & (r_select == select_t'(i)); end @@ -443,8 +443,8 @@ module axi_lite_mux #( // pragma translate_off `ifndef VERILATOR initial begin: p_assertions - NoPorts: assert (NoSlvPorts > 0) else $fatal("Number of slave ports must be at least 1!"); - MaxTnx: assert (MaxTrans > 0) else $fatal("Number of transactions must be at least 1!"); + NumPorts: assert (NumSlvPorts > 0) else $fatal("Number of slave ports must be at least 1!"); + MaxTnx: assert (MaxTrans > 0) else $fatal("Number of transactions must be at least 1!"); end `endif // pragma translate_on @@ -457,7 +457,7 @@ endmodule module axi_lite_mux_intf #( parameter int unsigned AddrWidth = 32'd0, parameter int unsigned DataWidth = 32'd0, - parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports + parameter int unsigned NumSlvPorts = 32'd0, // Number of slave ports // Maximum number of outstanding transactions per write parameter int unsigned MaxTrans = 32'd0, // if enabled, this multiplexer is purely combinatorial @@ -473,7 +473,7 @@ module axi_lite_mux_intf #( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic test_i, // Testmode enable - AXI_LITE.Slave slv [NoSlvPorts-1:0], // slave ports + AXI_LITE.Slave slv [NumSlvPorts-1:0], // slave ports AXI_LITE.Master mst // master port ); @@ -489,12 +489,12 @@ module axi_lite_mux_intf #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - axi_lite_req_t [NoSlvPorts-1:0] slv_reqs; - axi_lite_rsp_t [NoSlvPorts-1:0] slv_rsps; - axi_lite_req_t mst_req; - axi_lite_rsp_t mst_rsp; + axi_lite_req_t [NumSlvPorts-1:0] slv_reqs; + axi_lite_rsp_t [NumSlvPorts-1:0] slv_rsps; + axi_lite_req_t mst_req; + axi_lite_rsp_t mst_rsp; - for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_assign_slv_ports + for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_assign_slv_ports `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) `AXI_LITE_ASSIGN_FROM_RSP(slv[i], slv_rsps[i]) end @@ -510,7 +510,7 @@ module axi_lite_mux_intf #( .r_chan_t ( r_chan_t ), // R Channel Type .axi_lite_req_t ( axi_lite_req_t ), .axi_lite_rsp_t ( axi_lite_rsp_t ), - .NoSlvPorts ( NoSlvPorts ), // Number of slave ports + .NumSlvPorts ( NumSlvPorts ), // Number of slave ports .MaxTrans ( MaxTrans ), .FallThrough ( FallThrough ), .SpillAw ( SpillAw ), diff --git a/src/axi_lite_to_apb.sv b/src/axi_lite_to_apb.sv index 0137ba597..919172892 100644 --- a/src/axi_lite_to_apb.sv +++ b/src/axi_lite_to_apb.sv @@ -48,32 +48,32 @@ `include "common_cells/registers.svh" module axi_lite_to_apb #( - parameter int unsigned NoApbSlaves = 32'd1, // Number of connected APB slaves - parameter int unsigned NoRules = 32'd1, // Number of APB address rules - parameter int unsigned AddrWidth = 32'd32, // Address width - parameter int unsigned DataWidth = 32'd32, // Data width - parameter bit PipelineRequest = 1'b0, // Pipeline request path - parameter bit PipelineResponse = 1'b0, // Pipeline response path - parameter type axi_lite_req_t = logic, // AXI4-Lite request struct - parameter type axi_lite_rsp_t = logic, // AXI4-Lite response sruct - parameter type apb_req_t = logic, // APB4 request struct - parameter type apb_rsp_t = logic, // APB4 response struct - parameter type rule_t = logic // Address Decoder rule from `common_cells` + parameter int unsigned NumApbSlaves = 32'd1, // Number of connected APB slaves + parameter int unsigned NumRules = 32'd1, // Number of APB address rules + parameter int unsigned AddrWidth = 32'd32, // Address width + parameter int unsigned DataWidth = 32'd32, // Data width + parameter bit PipelineRequest = 1'b0, // Pipeline request path + parameter bit PipelineResponse = 1'b0, // Pipeline response path + parameter type axi_lite_req_t = logic, // AXI4-Lite request struct + parameter type axi_lite_rsp_t = logic, // AXI4-Lite response sruct + parameter type apb_req_t = logic, // APB4 request struct + parameter type apb_rsp_t = logic, // APB4 response struct + parameter type rule_t = logic // Address Decoder rule from `common_cells` ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low // AXI LITE slave port - input axi_lite_req_t axi_lite_req_i, - output axi_lite_rsp_t axi_lite_rsp_o, + input axi_lite_req_t axi_lite_req_i, + output axi_lite_rsp_t axi_lite_rsp_o, // APB master port - output apb_req_t [NoApbSlaves-1:0] apb_req_o, - input apb_rsp_t [NoApbSlaves-1:0] apb_rsp_i, + output apb_req_t [NumApbSlaves-1:0] apb_req_o, + input apb_rsp_t [NumApbSlaves-1:0] apb_rsp_i, // APB Slave Address Map - input rule_t [NoRules-1:0] addr_map_i + input rule_t [NumRules-1:0] addr_map_i ); localparam logic RD = 1'b0; // Encode index of a read request localparam logic WR = 1'b1; // Encode index of a write request - localparam int unsigned SelIdxWidth = (NoApbSlaves > 32'd1) ? $clog2(NoApbSlaves) : 32'd1; + localparam int unsigned SelIdxWidth = (NumApbSlaves > 32'd1) ? $clog2(NumApbSlaves) : 32'd1; typedef logic [AddrWidth-1:0] addr_t; // AXI4-Lite, APB4 and rule_t addr width typedef logic [DataWidth-1:0] data_t; // AXI4-Lite and APB4 data width typedef logic [DataWidth/8-1:0] strb_t; // AXI4-Lite and APB4 strb width @@ -265,10 +265,10 @@ module axi_lite_to_apb #( logic apb_dec_valid; sel_idx_t apb_sel_idx; addr_decode #( - .NoIndices( NoApbSlaves ), - .NoRules ( NoRules ), - .addr_t ( addr_t ), - .rule_t ( rule_t ) + .NoIndices( NumApbSlaves ), + .NoRules ( NumRules ), + .addr_t ( addr_t ), + .rule_t ( rule_t ) ) i_apb_decode ( .addr_i ( apb_req.addr ), .addr_map_i ( addr_map_i ), @@ -381,38 +381,38 @@ endmodule `include "axi/assign.svh" module axi_lite_to_apb_intf #( - parameter int unsigned NoApbSlaves = 32'd1, // Number of connected APB slaves - parameter int unsigned NoRules = 32'd1, // Number of APB address rules - parameter int unsigned AddrWidth = 32'd32, // Address width - parameter int unsigned DataWidth = 32'd32, // Data width - parameter bit PipelineRequest = 1'b0, // Pipeline request path - parameter bit PipelineResponse = 1'b0, // Pipeline response path - parameter type rule_t = logic, // Address Decoder rule from `common_cells` + parameter int unsigned NumApbSlaves = 32'd1, // Number of connected APB slaves + parameter int unsigned NumRules = 32'd1, // Number of APB address rules + parameter int unsigned AddrWidth = 32'd32, // Address width + parameter int unsigned DataWidth = 32'd32, // Data width + parameter bit PipelineRequest = 1'b0, // Pipeline request path + parameter bit PipelineResponse = 1'b0, // Pipeline response path + parameter type rule_t = logic, // Address Decoder rule from `common_cells` // DEPENDENT PARAMERETS, DO NOT OVERWRITE! - parameter type addr_t = logic [AddrWidth-1:0], - parameter type data_t = logic [DataWidth-1:0], - parameter type strb_t = logic [DataWidth/8-1:0], - parameter type sel_t = logic [NoApbSlaves-1:0] + parameter type addr_t = logic [AddrWidth-1:0], + parameter type data_t = logic [DataWidth-1:0], + parameter type strb_t = logic [DataWidth/8-1:0], + parameter type sel_t = logic [NumApbSlaves-1:0] ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low // AXI LITE slave port - AXI_LITE.Slave slv, + AXI_LITE.Slave slv, // APB master port - output addr_t paddr_o, - output logic [2:0] pprot_o, - output sel_t pselx_o, - output logic penable_o, - output logic pwrite_o, - output data_t pwdata_o, - output strb_t pstrb_o, - input logic [NoApbSlaves-1:0] pready_i, - input data_t [NoApbSlaves-1:0] prdata_i, - input [NoApbSlaves-1:0] pslverr_i, + output addr_t paddr_o, + output logic [2:0] pprot_o, + output sel_t pselx_o, + output logic penable_o, + output logic pwrite_o, + output data_t pwdata_o, + output strb_t pstrb_o, + input logic [NumApbSlaves-1:0] pready_i, + input data_t [NumApbSlaves-1:0] prdata_i, + input [NumApbSlaves-1:0] pslverr_i, // APB Slave Address Map - input rule_t [NoRules-1:0] addr_map_i + input rule_t [NumRules-1:0] addr_map_i ); - localparam int unsigned SelIdxWidth = NoApbSlaves > 1 ? $clog2(NoApbSlaves) : 1; + localparam int unsigned SelIdxWidth = NumApbSlaves > 1 ? $clog2(NumApbSlaves) : 1; typedef struct packed { addr_t paddr; // same as AXI4-Lite @@ -438,17 +438,17 @@ module axi_lite_to_apb_intf #( `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t axi_req; - axi_rsp_t axi_rsp; - apb_req_t [NoApbSlaves-1:0] apb_req; - apb_rsp_t [NoApbSlaves-1:0] apb_rsp; - logic [SelIdxWidth-1:0] apb_sel; + axi_req_t axi_req; + axi_rsp_t axi_rsp; + apb_req_t [NumApbSlaves-1:0] apb_req; + apb_rsp_t [NumApbSlaves-1:0] apb_rsp; + logic [SelIdxWidth-1:0] apb_sel; `AXI_LITE_ASSIGN_TO_REQ(axi_req, slv) `AXI_LITE_ASSIGN_FROM_RSP(slv, axi_rsp) onehot_to_bin #( - .ONEHOT_WIDTH ( NoApbSlaves ) + .ONEHOT_WIDTH ( NumApbSlaves ) ) i_onehot_to_bin ( .onehot ( pselx_o ), .bin ( apb_sel ) @@ -460,7 +460,7 @@ module axi_lite_to_apb_intf #( assign pwrite_o = apb_req[apb_sel].pwrite; assign pwdata_o = apb_req[apb_sel].pwdata; assign pstrb_o = apb_req[apb_sel].pstrb; - for (genvar i = 0; i < NoApbSlaves; i++) begin : gen_apb_rsp_assign + for (genvar i = 0; i < NumApbSlaves; i++) begin : gen_apb_rsp_assign assign pselx_o[i] = apb_req[i].psel; assign apb_rsp[i].pready = pready_i[i]; assign apb_rsp[i].prdata = prdata_i[i]; @@ -468,8 +468,8 @@ module axi_lite_to_apb_intf #( end axi_lite_to_apb #( - .NoApbSlaves ( NoApbSlaves ), - .NoRules ( NoRules ), + .NumApbSlaves ( NumApbSlaves ), + .NumRules ( NumRules ), .AddrWidth ( AddrWidth ), .DataWidth ( DataWidth ), .PipelineRequest ( PipelineRequest ), diff --git a/src/axi_lite_xbar.sv b/src/axi_lite_xbar.sv index c4e519b48..623abd34b 100644 --- a/src/axi_lite_xbar.sv +++ b/src/axi_lite_xbar.sv @@ -30,25 +30,25 @@ module axi_lite_xbar #( parameter type axi_lite_rsp_t = logic, parameter type rule_t = axi_pkg::xbar_rule_64_t, // DEPENDENT PARAMETERS, DO NOT OVERWRITE! - parameter int unsigned MstIdxWidth = (Cfg.NoMstPorts > 32'd1) ? $clog2(Cfg.NoMstPorts) : 32'd1 + parameter int unsigned MstIdxWidth = (Cfg.NumMstPorts > 32'd1) ? $clog2(Cfg.NumMstPorts) : 32'd1 ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, - input axi_lite_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, - output axi_lite_rsp_t [Cfg.NoSlvPorts-1:0] slv_ports_rsp_o, - output axi_lite_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, - input axi_lite_rsp_t [Cfg.NoMstPorts-1:0] mst_ports_rsp_i, - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NoSlvPorts-1:0][MstIdxWidth-1:0] default_mst_port_i + input logic clk_i, + input logic rst_ni, + input logic test_i, + input axi_lite_req_t [Cfg.NumSlvPorts-1:0] slv_ports_req_i, + output axi_lite_rsp_t [Cfg.NumSlvPorts-1:0] slv_ports_rsp_o, + output axi_lite_req_t [Cfg.NumMstPorts-1:0] mst_ports_req_o, + input axi_lite_rsp_t [Cfg.NumMstPorts-1:0] mst_ports_rsp_i, + input rule_t [Cfg.NumAddrRules-1:0] addr_map_i, + input logic [Cfg.NumSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NumSlvPorts-1:0][MstIdxWidth-1:0] default_mst_port_i ); typedef logic [Cfg.AddrWidth-1:0] addr_t; typedef logic [Cfg.DataWidth-1:0] data_t; typedef logic [Cfg.DataWidth/8-1:0] strb_t; // to account for the decoding error slave - typedef logic [$clog2(Cfg.NoMstPorts + 1)-1:0] mst_port_idx_t; + typedef logic [$clog2(Cfg.NumMstPorts + 1)-1:0] mst_port_idx_t; // full AXI typedef for the decode error slave, id_t and user_t are logic and will be // removed during logic optimization as they are stable `AXI_TYPEDEF_AW_CHAN_T(full_aw_chan_t, addr_t, logic, logic) @@ -60,14 +60,14 @@ module axi_lite_xbar #( `AXI_TYPEDEF_RSP_T(full_rsp_t, full_b_chan_t, full_r_chan_t) // signals from the axi_lite_demuxes, one index more for decode error routing - axi_lite_req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; - axi_lite_rsp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_rsps; + axi_lite_req_t [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts:0] slv_reqs; + axi_lite_rsp_t [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts:0] slv_rsps; // signals into the axi_lite_muxes, are of type slave as the multiplexer extends the ID - axi_lite_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; - axi_lite_rsp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_rsps; + axi_lite_req_t [Cfg.NumMstPorts-1:0][Cfg.NumSlvPorts-1:0] mst_reqs; + axi_lite_rsp_t [Cfg.NumMstPorts-1:0][Cfg.NumSlvPorts-1:0] mst_rsps; - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux + for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_slv_port_demux logic [MstIdxWidth-1:0] dec_aw, dec_ar; mst_port_idx_t slv_aw_select, slv_ar_select; logic dec_aw_error; @@ -77,10 +77,10 @@ module axi_lite_xbar #( full_rsp_t decerr_rsp; addr_decode #( - .NoIndices ( Cfg.NoMstPorts ), - .NoRules ( Cfg.NoAddrRules ), - .addr_t ( addr_t ), - .rule_t ( rule_t ) + .NoIndices ( Cfg.NumMstPorts ), + .NoRules ( Cfg.NumAddrRules ), + .addr_t ( addr_t ), + .rule_t ( rule_t ) ) i_axi_aw_decode ( .addr_i ( slv_ports_req_i[i].aw.addr ), .addr_map_i ( addr_map_i ), @@ -92,10 +92,10 @@ module axi_lite_xbar #( ); addr_decode #( - .NoIndices ( Cfg.NoMstPorts ), - .addr_t ( addr_t ), - .NoRules ( Cfg.NoAddrRules ), - .rule_t ( rule_t ) + .NoIndices ( Cfg.NumMstPorts ), + .addr_t ( addr_t ), + .NoRules ( Cfg.NumAddrRules ), + .rule_t ( rule_t ) ) i_axi_ar_decode ( .addr_i ( slv_ports_req_i[i].ar.addr ), .addr_map_i ( addr_map_i ), @@ -107,9 +107,9 @@ module axi_lite_xbar #( ); assign slv_aw_select = (dec_aw_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_aw); + mst_port_idx_t'(Cfg.NumMstPorts) : mst_port_idx_t'(dec_aw); assign slv_ar_select = (dec_ar_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_ar); + mst_port_idx_t'(Cfg.NumMstPorts) : mst_port_idx_t'(dec_ar); // make sure that the default slave does not get changed, if there is an unserved Ax // pragma translate_off @@ -138,21 +138,21 @@ module axi_lite_xbar #( `endif // pragma translate_on axi_lite_demux #( - .aw_chan_t ( aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( b_chan_t ), // B Channel Type - .ar_chan_t ( ar_chan_t ), // AR Channel Type - .r_chan_t ( r_chan_t ), // R Channel Type - .axi_lite_req_t ( axi_lite_req_t ), - .axi_lite_rsp_t ( axi_lite_rsp_t ), - .NoMstPorts ( Cfg.NoMstPorts + 1 ), - .MaxTrans ( Cfg.MaxMstTrans ), - .FallThrough ( Cfg.FallThrough ), - .SpillAw ( Cfg.LatencyMode[9] ), - .SpillW ( Cfg.LatencyMode[8] ), - .SpillB ( Cfg.LatencyMode[7] ), - .SpillAr ( Cfg.LatencyMode[6] ), - .SpillR ( Cfg.LatencyMode[5] ) + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_rsp_t ), + .NumMstPorts ( Cfg.NumMstPorts + 1 ), + .MaxTrans ( Cfg.MaxMstTrans ), + .FallThrough ( Cfg.FallThrough ), + .SpillAw ( Cfg.LatencyMode[9] ), + .SpillW ( Cfg.LatencyMode[8] ), + .SpillB ( Cfg.LatencyMode[7] ), + .SpillAr ( Cfg.LatencyMode[6] ), + .SpillR ( Cfg.LatencyMode[5] ) ) i_axi_lite_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low @@ -174,12 +174,12 @@ module axi_lite_xbar #( .axi_req_t ( full_req_t ), .axi_rsp_t ( full_rsp_t ) ) i_dec_err_conv ( - .slv_req_lite_i ( slv_reqs[i][Cfg.NoMstPorts] ), - .slv_rsp_lite_o ( slv_rsps[i][Cfg.NoMstPorts] ), - .slv_aw_cache_i ( 4'd0 ), - .slv_ar_cache_i ( 4'd0 ), - .mst_req_o ( decerr_req ), - .mst_rsp_i ( decerr_rsp ) + .slv_req_lite_i ( slv_reqs[i][Cfg.NumMstPorts] ), + .slv_rsp_lite_o ( slv_rsps[i][Cfg.NumMstPorts] ), + .slv_aw_cache_i ( 4'd0 ), + .slv_ar_cache_i ( 4'd0 ), + .mst_req_o ( decerr_req ), + .mst_rsp_i ( decerr_rsp ) ); axi_err_slv #( @@ -201,14 +201,14 @@ module axi_lite_xbar #( end // cross all channels - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_xbar_slv_cross - for (genvar j = 0; j < Cfg.NoMstPorts; j++) begin : gen_xbar_mst_cross + for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_xbar_slv_cross + for (genvar j = 0; j < Cfg.NumMstPorts; j++) begin : gen_xbar_mst_cross assign mst_reqs[j][i] = slv_reqs[i][j]; assign slv_rsps[i][j] = mst_rsps[j][i]; end end - for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_mst_port_mux + for (genvar i = 0; i < Cfg.NumMstPorts; i++) begin : gen_mst_port_mux axi_lite_mux #( .aw_chan_t ( aw_chan_t ), // AW Channel Type .w_chan_t ( w_chan_t ), // W Channel Type @@ -217,7 +217,7 @@ module axi_lite_xbar #( .r_chan_t ( r_chan_t ), // R Channel Type .axi_lite_req_t ( axi_lite_req_t ), .axi_lite_rsp_t ( axi_lite_rsp_t ), - .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module + .NumSlvPorts ( Cfg.NumSlvPorts ), // Number of Masters for the module .MaxTrans ( Cfg.MaxSlvTrans ), .FallThrough ( Cfg.FallThrough ), .SpillAw ( Cfg.LatencyMode[4] ), @@ -243,14 +243,14 @@ module axi_lite_xbar_intf #( parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter type rule_t = axi_pkg::xbar_rule_64_t ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, - AXI_LITE.Slave slv_ports [Cfg.NoSlvPorts-1:0], - AXI_LITE.Master mst_ports [Cfg.NoMstPorts-1:0], - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0] default_mst_port_i + input logic clk_i, + input logic rst_ni, + input logic test_i, + AXI_LITE.Slave slv_ports [Cfg.NumSlvPorts-1:0], + AXI_LITE.Master mst_ports [Cfg.NumMstPorts-1:0], + input rule_t [Cfg.NumAddrRules-1:0] addr_map_i, + input logic [Cfg.NumSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NumSlvPorts-1:0][$clog2(Cfg.NumMstPorts)-1:0] default_mst_port_i ); typedef logic [Cfg.AddrWidth -1:0] addr_t; @@ -264,17 +264,17 @@ module axi_lite_xbar_intf #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - axi_lite_req_t [Cfg.NoMstPorts-1:0] mst_reqs; - axi_lite_rsp_t [Cfg.NoMstPorts-1:0] mst_rsps; - axi_lite_req_t [Cfg.NoSlvPorts-1:0] slv_reqs; - axi_lite_rsp_t [Cfg.NoSlvPorts-1:0] slv_rsps; + axi_lite_req_t [Cfg.NumMstPorts-1:0] mst_reqs; + axi_lite_rsp_t [Cfg.NumMstPorts-1:0] mst_rsps; + axi_lite_req_t [Cfg.NumSlvPorts-1:0] slv_reqs; + axi_lite_rsp_t [Cfg.NumSlvPorts-1:0] slv_rsps; - for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst + for (genvar i = 0; i < Cfg.NumMstPorts; i++) begin : gen_assign_mst `AXI_LITE_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) `AXI_LITE_ASSIGN_TO_RSP(mst_rsps[i], mst_ports[i]) end - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_assign_slv + for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_assign_slv `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) `AXI_LITE_ASSIGN_FROM_RSP(slv_ports[i], slv_rsps[i]) end diff --git a/src/axi_multicut.sv b/src/axi_multicut.sv index 62fc978a5..6a0b3e3e1 100644 --- a/src/axi_multicut.sv +++ b/src/axi_multicut.sv @@ -19,7 +19,7 @@ // // These can be used to relax timing pressure on very long AXI busses. module axi_multicut #( - parameter int unsigned NoCuts = 32'd1, // Number of cuts. + parameter int unsigned NumCuts = 32'd1, // Number of cuts. // AXI channel structs parameter type aw_chan_t = logic, parameter type w_chan_t = logic, @@ -40,21 +40,21 @@ module axi_multicut #( input axi_rsp_t mst_rsp_i ); - if (NoCuts == '0) begin : gen_no_cut + if (NumCuts == '0) begin : gen_no_cut // degenerate case, connect input to output assign mst_req_o = slv_req_i; assign slv_rsp_o = mst_rsp_i; end else begin : gen_axi_cut // instantiate all needed cuts - axi_req_t [NoCuts:0] cut_req; - axi_rsp_t [NoCuts:0] cut_rsp; + axi_req_t [NumCuts:0] cut_req; + axi_rsp_t [NumCuts:0] cut_rsp; // connect slave to the lowest index assign cut_req[0] = slv_req_i; assign slv_rsp_o = cut_rsp[0]; // AXI cuts - for (genvar i = 0; i < NoCuts; i++) begin : gen_axi_cuts + for (genvar i = 0; i < NumCuts; i++) begin : gen_axi_cuts axi_cut #( .Bypass ( 1'b0 ), .aw_chan_t ( aw_chan_t ), @@ -75,15 +75,15 @@ module axi_multicut #( end // connect master to the highest index - assign mst_req_o = cut_req[NoCuts]; - assign cut_rsp[NoCuts] = mst_rsp_i; + assign mst_req_o = cut_req[NumCuts]; + assign cut_rsp[NumCuts] = mst_rsp_i; end // Check the invariants // pragma translate_off `ifndef VERILATOR initial begin - assert(NoCuts >= 0); + assert(NumCuts >= 0); end `endif // pragma translate_on @@ -130,7 +130,7 @@ module axi_multicut_intf #( `AXI_ASSIGN_TO_RSP(mst_rsp, out) axi_multicut #( - .NoCuts ( NUM_CUTS ), + .NumCuts ( NUM_CUTS ), .aw_chan_t ( aw_chan_t ), .w_chan_t ( w_chan_t ), .b_chan_t ( b_chan_t ), @@ -204,7 +204,7 @@ module axi_lite_multicut_intf #( `AXI_LITE_ASSIGN_TO_RSP(mst_rsp, out) axi_multicut #( - .NoCuts ( NUM_CUTS ), + .NumCuts ( NUM_CUTS ), .aw_chan_t ( aw_chan_t ), .w_chan_t ( w_chan_t ), .b_chan_t ( b_chan_t ), diff --git a/src/axi_mux.sv b/src/axi_mux.sv index 55b316914..6c6a6bbaa 100644 --- a/src/axi_mux.sv +++ b/src/axi_mux.sv @@ -15,8 +15,8 @@ // AXI Multiplexer: This module multiplexes the AXI4 slave ports down to one master port. // The AXI IDs from the slave ports get extended with the respective slave port index. -// The extension width can be calculated with `$clog2(NoSlvPorts)`. This means the AXI -// ID for the master port has to be this `$clog2(NoSlvPorts)` wider than the ID for the +// The extension width can be calculated with `$clog2(NumSlvPorts)`. This means the AXI +// ID for the master port has to be this `$clog2(NumSlvPorts)` wider than the ID for the // slave ports. // Responses are switched based on these bits. For example, with 4 slave ports // a response with ID `6'b100110` will be forwarded to slave port 2 (`2'b10`). @@ -41,7 +41,7 @@ module axi_mux #( parameter type slv_port_axi_rsp_t = logic, // Slave port response type parameter type mst_port_axi_req_t = logic, // Master ports request type parameter type mst_port_axi_rsp_t = logic, // Master ports response type - parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports + parameter int unsigned NumSlvPorts = 32'd0, // Number of slave ports // Maximum number of outstanding transactions per write parameter int unsigned MaxWTrans = 32'd8, // If enabled, this multiplexer is purely combinatorial @@ -54,22 +54,22 @@ module axi_mux #( parameter bit SpillAr = 1'b1, parameter bit SpillR = 1'b0 ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Test Mode enable + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Test Mode enable // slave ports (AXI inputs), connect master modules here - input slv_port_axi_req_t [NoSlvPorts-1:0] slv_reqs_i, - output slv_port_axi_rsp_t [NoSlvPorts-1:0] slv_rsps_o, + input slv_port_axi_req_t [NumSlvPorts-1:0] slv_reqs_i, + output slv_port_axi_rsp_t [NumSlvPorts-1:0] slv_rsps_o, // master port (AXI outputs), connect slave modules here - output mst_port_axi_req_t mst_req_o, - input mst_port_axi_rsp_t mst_rsp_i + output mst_port_axi_req_t mst_req_o, + input mst_port_axi_rsp_t mst_rsp_i ); - localparam int unsigned MstIdxBits = $clog2(NoSlvPorts); + localparam int unsigned MstIdxBits = $clog2(NumSlvPorts); localparam int unsigned MstIDWidth = SlvIDWidth + MstIdxBits; // pass through if only one slave port - if (NoSlvPorts == 32'h1) begin : gen_no_mux + if (NumSlvPorts == 32'h1) begin : gen_no_mux spill_register #( .T ( mst_aw_chan_t ), .Bypass ( ~SpillAw ) @@ -153,16 +153,16 @@ module axi_mux #( typedef logic [MstIdxBits-1:0] switch_id_t; // AXI channels between the ID prepend unit and the rest of the multiplexer - mst_aw_chan_t [NoSlvPorts-1:0] slv_aw_chans; - logic [NoSlvPorts-1:0] slv_aw_valids, slv_aw_readies; - w_chan_t [NoSlvPorts-1:0] slv_w_chans; - logic [NoSlvPorts-1:0] slv_w_valids, slv_w_readies; - mst_b_chan_t [NoSlvPorts-1:0] slv_b_chans; - logic [NoSlvPorts-1:0] slv_b_valids, slv_b_readies; - mst_ar_chan_t [NoSlvPorts-1:0] slv_ar_chans; - logic [NoSlvPorts-1:0] slv_ar_valids, slv_ar_readies; - mst_r_chan_t [NoSlvPorts-1:0] slv_r_chans; - logic [NoSlvPorts-1:0] slv_r_valids, slv_r_readies; + mst_aw_chan_t [NumSlvPorts-1:0] slv_aw_chans; + logic [NumSlvPorts-1:0] slv_aw_valids, slv_aw_readies; + w_chan_t [NumSlvPorts-1:0] slv_w_chans; + logic [NumSlvPorts-1:0] slv_w_valids, slv_w_readies; + mst_b_chan_t [NumSlvPorts-1:0] slv_b_chans; + logic [NumSlvPorts-1:0] slv_b_valids, slv_b_readies; + mst_ar_chan_t [NumSlvPorts-1:0] slv_ar_chans; + logic [NumSlvPorts-1:0] slv_ar_valids, slv_ar_readies; + mst_r_chan_t [NumSlvPorts-1:0] slv_r_chans; + logic [NumSlvPorts-1:0] slv_r_valids, slv_r_readies; // These signals are all ID prepended // AW channel @@ -208,9 +208,9 @@ module axi_mux #( //-------------------------------------- // ID prepend for all slave ports //-------------------------------------- - for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_id_prepend + for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_id_prepend axi_id_prepend #( - .NoBus ( 32'd1 ), // one AXI bus per slave port + .NumBus ( 32'd1 ), // one AXI bus per slave port .IdWidthSlvPort( SlvIDWidth ), .IdWidthMstPort( MstIDWidth ), .slv_aw_chan_t ( slv_aw_chan_t ), @@ -262,7 +262,7 @@ module axi_mux #( // AW Channel //-------------------------------------- rr_arb_tree #( - .NumIn ( NoSlvPorts ), + .NumIn ( NumSlvPorts ), .DataType ( mst_aw_chan_t ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) @@ -384,7 +384,7 @@ module axi_mux #( // B Channel //-------------------------------------- // replicate B channels - assign slv_b_chans = {NoSlvPorts{mst_b_chan}}; + assign slv_b_chans = {NumSlvPorts{mst_b_chan}}; // control B channel handshake assign switch_b_id = mst_b_chan.id[SlvIDWidth+:MstIdxBits]; assign slv_b_valids = (mst_b_valid) ? (1 << switch_b_id) : '0; @@ -407,7 +407,7 @@ module axi_mux #( // AR Channel //-------------------------------------- rr_arb_tree #( - .NumIn ( NoSlvPorts ), + .NumIn ( NumSlvPorts ), .DataType ( mst_ar_chan_t ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) @@ -443,7 +443,7 @@ module axi_mux #( // R Channel //-------------------------------------- // replicate R channels - assign slv_r_chans = {NoSlvPorts{mst_r_chan}}; + assign slv_r_chans = {NumSlvPorts{mst_r_chan}}; // R channel handshake control assign switch_r_id = mst_r_chan.id[SlvIDWidth+:MstIdxBits]; assign slv_r_valids = (mst_r_valid) ? (1 << switch_r_id) : '0; @@ -467,10 +467,10 @@ module axi_mux #( `ifndef VERILATOR initial begin assert (SlvIDWidth > 0) else $fatal(1, "AXI ID width of slave ports must be non-zero!"); - assert (NoSlvPorts > 0) else $fatal(1, "Number of slave ports must be non-zero!"); + assert (NumSlvPorts > 0) else $fatal(1, "Number of slave ports must be non-zero!"); assert (MaxWTrans > 0) else $fatal(1, "Maximum number of outstanding writes must be non-zero!"); - assert (MstIDWidth >= SlvIDWidth + $clog2(NoSlvPorts)) + assert (MstIDWidth >= SlvIDWidth + $clog2(NumSlvPorts)) else $fatal(1, "AXI ID width of master ports must be wide enough to identify slave ports!"); // Assert ID widths (one slave is sufficient since they all have the same type). assert ($unsigned($bits(slv_reqs_i[0].aw.id)) == SlvIDWidth) @@ -578,7 +578,7 @@ module axi_mux_intf #( .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), .mst_port_axi_req_t ( mst_port_axi_req_t ), .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), - .NoSlvPorts ( NO_SLV_PORTS ), // Number of slave ports + .NumSlvPorts ( NO_SLV_PORTS ), // Number of slave ports .MaxWTrans ( MAX_W_TRANS ), .FallThrough ( FALL_THROUGH ), .SpillAw ( SPILL_AW ), diff --git a/src/axi_pkg.sv b/src/axi_pkg.sv index c02d5e453..d708a5649 100644 --- a/src/axi_pkg.sv +++ b/src/axi_pkg.sv @@ -477,10 +477,10 @@ package axi_pkg; typedef struct packed { /// Number of slave ports of the crossbar. /// This many master modules are connected to it. - int unsigned NoSlvPorts; + int unsigned NumSlvPorts; /// Number of master ports of the crossbar. /// This many slave modules are connected to it. - int unsigned NoMstPorts; + int unsigned NumMstPorts; /// Maximum number of open transactions each master connected to the crossbar can have in /// flight at the same time. int unsigned MaxMstTrans; @@ -513,7 +513,7 @@ package axi_pkg; /// The number of address rules defined for routing of the transactions. /// Each master port can have multiple rules, should have however at least one. /// If a transaction can not be routed the xbar will answer with an `axi_pkg::RESP_DECERR`. - int unsigned NoAddrRules; + int unsigned NumAddrRules; } xbar_cfg_t; /// Commonly used rule types for `axi_xbar` (64-bit addresses). diff --git a/src/axi_test.sv b/src/axi_test.sv index 205d396e5..b680fc3f8 100644 --- a/src/axi_test.sv +++ b/src/axi_test.sv @@ -2349,14 +2349,14 @@ module axi_chan_logger #( ); // id width from channel localparam int unsigned IdWidth = $bits(aw_chan_i.id); - localparam int unsigned NoIds = 2**IdWidth; + localparam int unsigned NumIds = 2**IdWidth; // queues for writes and reads aw_chan_t aw_queue[$]; w_chan_t w_queue[$]; b_chan_t b_queue[$]; - aw_chan_t ar_queues[NoIds-1:0][$]; - r_chan_t r_queues[NoIds-1:0][$]; + aw_chan_t ar_queues[NumIds-1:0][$]; + r_chan_t r_queues[NumIds-1:0][$]; // channel sampling into queues always @(posedge clk_i) #TestTime begin : proc_channel_sample @@ -2456,11 +2456,11 @@ module axi_chan_logger #( automatic b_chan_t b_beat; automatic aw_chan_t ar_beat; automatic r_chan_t r_beat; - automatic int unsigned no_r_beat[NoIds]; + automatic int unsigned no_r_beat[NumIds]; automatic int fd; // init r counter - for (int unsigned i = 0; i < NoIds; i++) begin + for (int unsigned i = 0; i < NumIds; i++) begin no_r_beat[i] = 0; end @@ -2477,7 +2477,7 @@ module axi_chan_logger #( $fclose(fd); end else $display("File was NOT opened successfully : %0d", fd); - for (int unsigned i = 0; i < NoIds; i++) begin + for (int unsigned i = 0; i < NumIds; i++) begin log_name = $sformatf("./axi_log/%s/read_%0h.log", LoggerName, i); fd = $fopen(log_name, "w"); if (fd) begin @@ -2533,7 +2533,7 @@ module axi_chan_logger #( end // update the read log files - for (int unsigned i = 0; i < NoIds; i++) begin + for (int unsigned i = 0; i < NumIds; i++) begin while (ar_queues[i].size() != 0 && r_queues[i].size() != 0) begin ar_beat = ar_queues[i][0]; r_beat = r_queues[i].pop_front(); diff --git a/src/axi_to_mem_banked.sv b/src/axi_to_mem_banked.sv index 14b6268fd..a505f1516 100644 --- a/src/axi_to_mem_banked.sv +++ b/src/axi_to_mem_banked.sv @@ -146,8 +146,8 @@ module axi_to_mem_banked #( .ar_chan_t ( axi_ar_chan_t ), .r_chan_t ( axi_r_chan_t ), .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ), - .NoMstPorts ( 32'd2 ), + .axi_rsp_t ( axi_rsp_t ), + .NumMstPorts ( 32'd2 ), .MaxTrans ( MemLatency+2 ), // allow multiple Ax vectors to not starve W channel .LookBits ( 32'd1 ), // select is fixed, do not need it .UniqueIds ( 1'b0 ), diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv index be0209af6..52a48535b 100644 --- a/src/axi_xbar.sv +++ b/src/axi_xbar.sv @@ -19,37 +19,37 @@ module axi_xbar import cf_math_pkg::idx_width; #( /// Configuration struct for the crossbar see `axi_pkg` for fields and definitions. - parameter axi_pkg::xbar_cfg_t Cfg = '0, + parameter axi_pkg::xbar_cfg_t Cfg = '0, /// Enable atomic operations support. - parameter bit ATOPs = 1'b1, + parameter bit ATOPs = 1'b1, /// Connectivity matrix - parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] Connectivity = '1, + parameter bit [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts-1:0] Connectivity = '1, /// AXI4+ATOP AW channel struct type for the slave ports. - parameter type slv_aw_chan_t = logic, + parameter type slv_aw_chan_t = logic, /// AXI4+ATOP AW channel struct type for the master ports. - parameter type mst_aw_chan_t = logic, + parameter type mst_aw_chan_t = logic, /// AXI4+ATOP W channel struct type for all ports. - parameter type w_chan_t = logic, + parameter type w_chan_t = logic, /// AXI4+ATOP B channel struct type for the slave ports. - parameter type slv_b_chan_t = logic, + parameter type slv_b_chan_t = logic, /// AXI4+ATOP B channel struct type for the master ports. - parameter type mst_b_chan_t = logic, + parameter type mst_b_chan_t = logic, /// AXI4+ATOP AR channel struct type for the slave ports. - parameter type slv_ar_chan_t = logic, + parameter type slv_ar_chan_t = logic, /// AXI4+ATOP AR channel struct type for the master ports. - parameter type mst_ar_chan_t = logic, + parameter type mst_ar_chan_t = logic, /// AXI4+ATOP R channel struct type for the slave ports. - parameter type slv_r_chan_t = logic, + parameter type slv_r_chan_t = logic, /// AXI4+ATOP R channel struct type for the master ports. - parameter type mst_r_chan_t = logic, + parameter type mst_r_chan_t = logic, /// AXI4+ATOP request struct type for the slave ports. - parameter type slv_port_axi_req_t = logic, + parameter type slv_port_axi_req_t = logic, /// AXI4+ATOP response struct type for the slave ports. - parameter type slv_port_axi_rsp_t = logic, + parameter type slv_port_axi_rsp_t = logic, /// AXI4+ATOP request struct type for the master ports. - parameter type mst_port_axi_req_t = logic, + parameter type mst_port_axi_req_t = logic, /// AXI4+ATOP response struct type for the master ports - parameter type mst_port_axi_rsp_t = logic, + parameter type mst_port_axi_rsp_t = logic, /// Address rule type for the address decoders from `common_cells:addr_decode`. /// Example types are provided in `axi_pkg`. /// Required struct fields: @@ -60,42 +60,42 @@ import cf_math_pkg::idx_width; /// axi_addr_t end_addr; /// } rule_t; /// ``` - parameter type rule_t = axi_pkg::xbar_rule_64_t + parameter type rule_t = axi_pkg::xbar_rule_64_t `ifdef VCS , localparam int unsigned MstPortsIdxWidth = - (Cfg.NoMstPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NoMstPorts)) + (Cfg.NumMstPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NumMstPorts)) `endif ) ( /// Clock, positive edge triggered. - input logic clk_i, + input logic clk_i, /// Asynchronous reset, active low. - input logic rst_ni, + input logic rst_ni, /// Testmode enable, active high. - input logic test_i, + input logic test_i, /// AXI4+ATOP requests to the slave ports. - input slv_port_axi_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, + input slv_port_axi_req_t [Cfg.NumSlvPorts-1:0] slv_ports_req_i, /// AXI4+ATOP responses of the slave ports. - output slv_port_axi_rsp_t [Cfg.NoSlvPorts-1:0] slv_ports_rsp_o, + output slv_port_axi_rsp_t [Cfg.NumSlvPorts-1:0] slv_ports_rsp_o, /// AXI4+ATOP requests of the master ports. - output mst_port_axi_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, + output mst_port_axi_req_t [Cfg.NumMstPorts-1:0] mst_ports_req_o, /// AXI4+ATOP responses to the master ports. - input mst_port_axi_rsp_t [Cfg.NoMstPorts-1:0] mst_ports_rsp_i, + input mst_port_axi_rsp_t [Cfg.NumMstPorts-1:0] mst_ports_rsp_i, /// Address map array input for the crossbar. This map is global for the whole module. /// It is used for routing the transactions to the respective master ports. /// Each master port can have multiple different rules. - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + input rule_t [Cfg.NumAddrRules-1:0] addr_map_i, /// Enable default master port. - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NumSlvPorts-1:0] en_default_mst_port_i, `ifdef VCS /// Enables a default master port for each slave port. When this is enabled unmapped /// transactions get issued at the master port given by `default_mst_port_i`. /// When not used, tie to `'0`. - input logic [Cfg.NoSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i + input logic [Cfg.NumSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i `else /// Enables a default master port for each slave port. When this is enabled unmapped /// transactions get issued at the master port given by `default_mst_port_i`. /// When not used, tie to `'0`. - input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i + input logic [Cfg.NumSlvPorts-1:0][idx_width(Cfg.NumMstPorts)-1:0] default_mst_port_i `endif ); @@ -104,38 +104,38 @@ import cf_math_pkg::idx_width; // to account for the decoding error slave `ifdef VCS localparam int unsigned MstPortsIdxWidthOne = - (Cfg.NoMstPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NoMstPorts + 1)); + (Cfg.NumMstPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NumMstPorts + 1)); typedef logic [MstPortsIdxWidthOne-1:0] mst_port_idx_t; `else - typedef logic [idx_width(Cfg.NoMstPorts + 1)-1:0] mst_port_idx_t; + typedef logic [idx_width(Cfg.NumMstPorts + 1)-1:0] mst_port_idx_t; `endif // signals from the axi_demuxes, one index more for decode error - slv_port_axi_req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; - slv_port_axi_rsp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_rsps; + slv_port_axi_req_t [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts:0] slv_reqs; + slv_port_axi_rsp_t [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts:0] slv_rsps; // workaround for issue #133 (problem with vsim 10.6c) - localparam int unsigned cfg_NoMstPorts = Cfg.NoMstPorts; + localparam int unsigned cfg_NumMstPorts = Cfg.NumMstPorts; // signals into the axi_muxes, are of type slave as the multiplexer extends the ID - slv_port_axi_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; - slv_port_axi_rsp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_rsps; + slv_port_axi_req_t [Cfg.NumMstPorts-1:0][Cfg.NumSlvPorts-1:0] mst_reqs; + slv_port_axi_rsp_t [Cfg.NumMstPorts-1:0][Cfg.NumSlvPorts-1:0] mst_rsps; - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux + for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_slv_port_demux `ifdef VCS logic [MstPortsIdxWidth-1:0] dec_aw, dec_ar; `else - logic [idx_width(Cfg.NoMstPorts)-1:0] dec_aw, dec_ar; + logic [idx_width(Cfg.NumMstPorts)-1:0] dec_aw, dec_ar; `endif mst_port_idx_t slv_aw_select, slv_ar_select; logic dec_aw_valid, dec_aw_error; logic dec_ar_valid, dec_ar_error; addr_decode #( - .NoIndices ( Cfg.NoMstPorts ), - .NoRules ( Cfg.NoAddrRules ), - .addr_t ( addr_t ), - .rule_t ( rule_t ) + .NoIndices ( Cfg.NumMstPorts ), + .NoRules ( Cfg.NumAddrRules ), + .addr_t ( addr_t ), + .rule_t ( rule_t ) ) i_axi_aw_decode ( .addr_i ( slv_ports_req_i[i].aw.addr ), .addr_map_i ( addr_map_i ), @@ -147,10 +147,10 @@ import cf_math_pkg::idx_width; ); addr_decode #( - .NoIndices ( Cfg.NoMstPorts ), - .addr_t ( addr_t ), - .NoRules ( Cfg.NoAddrRules ), - .rule_t ( rule_t ) + .NoIndices ( Cfg.NumMstPorts ), + .addr_t ( addr_t ), + .NoRules ( Cfg.NumAddrRules ), + .rule_t ( rule_t ) ) i_axi_ar_decode ( .addr_i ( slv_ports_req_i[i].ar.addr ), .addr_map_i ( addr_map_i ), @@ -162,9 +162,9 @@ import cf_math_pkg::idx_width; ); assign slv_aw_select = (dec_aw_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_aw); + mst_port_idx_t'(Cfg.NumMstPorts) : mst_port_idx_t'(dec_aw); assign slv_ar_select = (dec_ar_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_ar); + mst_port_idx_t'(Cfg.NumMstPorts) : mst_port_idx_t'(dec_ar); // make sure that the default slave does not get changed, if there is an unserved Ax // pragma translate_off @@ -204,7 +204,7 @@ import cf_math_pkg::idx_width; .r_chan_t ( slv_r_chan_t ), // R Channel Type .axi_req_t ( slv_port_axi_req_t ), .axi_rsp_t ( slv_port_axi_rsp_t ), - .NoMstPorts ( Cfg.NoMstPorts + 1 ), + .NumMstPorts ( Cfg.NumMstPorts + 1 ), .MaxTrans ( Cfg.MaxMstTrans ), .LookBits ( Cfg.IdUsedSlvPorts ), .UniqueIds ( Cfg.UniqueIds ), @@ -240,17 +240,17 @@ import cf_math_pkg::idx_width; .rst_ni, // Asynchronous reset active low .test_i, // Testmode enable // slave port - .slv_req_i ( slv_reqs[i][Cfg.NoMstPorts] ), - .slv_rsp_o ( slv_rsps[i][cfg_NoMstPorts] ) + .slv_req_i ( slv_reqs[i][Cfg.NumMstPorts] ), + .slv_rsp_o ( slv_rsps[i][cfg_NumMstPorts] ) ); end // cross all channels - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_xbar_slv_cross - for (genvar j = 0; j < Cfg.NoMstPorts; j++) begin : gen_xbar_mst_cross + for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_xbar_slv_cross + for (genvar j = 0; j < Cfg.NumMstPorts; j++) begin : gen_xbar_mst_cross if (Connectivity[i][j]) begin : gen_connection axi_multicut #( - .NoCuts ( Cfg.PipelineStages ), + .NumCuts ( Cfg.PipelineStages ), .aw_chan_t ( slv_aw_chan_t ), .w_chan_t ( w_chan_t ), .b_chan_t ( slv_b_chan_t ), @@ -287,7 +287,7 @@ import cf_math_pkg::idx_width; end end - for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_mst_port_mux + for (genvar i = 0; i < Cfg.NumMstPorts; i++) begin : gen_mst_port_mux axi_mux #( .SlvIDWidth ( Cfg.IdWidthSlvPorts ), // ID width of the slave ports .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports @@ -303,7 +303,7 @@ import cf_math_pkg::idx_width; .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), .mst_port_axi_req_t ( mst_port_axi_req_t ), .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), - .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module + .NumSlvPorts ( Cfg.NumSlvPorts ), // Number of Masters for the module .MaxWTrans ( Cfg.MaxSlvTrans ), .FallThrough ( Cfg.FallThrough ), .SpillAw ( Cfg.LatencyMode[4] ), @@ -345,28 +345,28 @@ import cf_math_pkg::idx_width; parameter int unsigned AXI_USER_WIDTH = 0, parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter bit ATOPS = 1'b1, - parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] CONNECTIVITY = '1, + parameter bit [Cfg.NumSlvPorts-1:0][Cfg.NumMstPorts-1:0] CONNECTIVITY = '1, parameter type rule_t = axi_pkg::xbar_rule_64_t `ifdef VCS , localparam int unsigned MstPortsIdxWidth = - (Cfg.NoMstPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NoMstPorts)) + (Cfg.NumMstPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NumMstPorts)) `endif ) ( input logic clk_i, input logic rst_ni, input logic test_i, - AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], - AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0], - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + AXI_BUS.Slave slv_ports [Cfg.NumSlvPorts-1:0], + AXI_BUS.Master mst_ports [Cfg.NumMstPorts-1:0], + input rule_t [Cfg.NumAddrRules-1:0] addr_map_i, + input logic [Cfg.NumSlvPorts-1:0] en_default_mst_port_i, `ifdef VCS - input logic [Cfg.NoSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i + input logic [Cfg.NumSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i `else - input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i + input logic [Cfg.NumSlvPorts-1:0][idx_width(Cfg.NumMstPorts)-1:0] default_mst_port_i `endif ); - localparam int unsigned IdWidthMstPorts = Cfg.IdWidthSlvPorts + $clog2(Cfg.NoSlvPorts); + localparam int unsigned IdWidthMstPorts = Cfg.IdWidthSlvPorts + $clog2(Cfg.NumSlvPorts); typedef logic [IdWidthMstPorts -1:0] id_mst_t; typedef logic [Cfg.IdWidthSlvPorts -1:0] id_slv_t; @@ -389,17 +389,17 @@ import cf_math_pkg::idx_width; `AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, mst_b_chan_t, mst_r_chan_t) `AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, slv_b_chan_t, slv_r_chan_t) - mst_port_axi_req_t [Cfg.NoMstPorts-1:0] mst_reqs; - mst_port_axi_rsp_t [Cfg.NoMstPorts-1:0] mst_rsps; - slv_port_axi_req_t [Cfg.NoSlvPorts-1:0] slv_reqs; - slv_port_axi_rsp_t [Cfg.NoSlvPorts-1:0] slv_rsps; + mst_port_axi_req_t [Cfg.NumMstPorts-1:0] mst_reqs; + mst_port_axi_rsp_t [Cfg.NumMstPorts-1:0] mst_rsps; + slv_port_axi_req_t [Cfg.NumSlvPorts-1:0] slv_reqs; + slv_port_axi_rsp_t [Cfg.NumSlvPorts-1:0] slv_rsps; - for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst + for (genvar i = 0; i < Cfg.NumMstPorts; i++) begin : gen_assign_mst `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) `AXI_ASSIGN_TO_RSP(mst_rsps[i], mst_ports[i]) end - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_assign_slv + for (genvar i = 0; i < Cfg.NumSlvPorts; i++) begin : gen_assign_slv `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) `AXI_ASSIGN_FROM_RSP(slv_ports[i], slv_rsps[i]) end diff --git a/src/axi_xp.sv b/src/axi_xp.sv index 6f31cf76f..83d8f6720 100644 --- a/src/axi_xp.sv +++ b/src/axi_xp.sv @@ -198,7 +198,7 @@ import cf_math_pkg::idx_width; input rule_t [NumAddrRules-1:0] addr_map_i ); - // localparam int unsigned AxiIdWidthMstPorts = AxiIdWidth + $clog2(NoSlvPorts); + // localparam int unsigned AxiIdWidthMstPorts = AxiIdWidth + $clog2(NumSlvPorts); typedef logic [IdWidth -1:0] id_t; typedef logic [AddrWidth -1:0] addr_t; diff --git a/test/axi_synth_bench.sv b/test/axi_synth_bench.sv index b3e194d40..bcb68e20c 100644 --- a/test/axi_synth_bench.sv +++ b/test/axi_synth_bench.sv @@ -61,7 +61,7 @@ module axi_synth_bench ( // AXI4-Lite crossbar for (genvar i = 0; i < 3; i++) begin synth_axi_lite_xbar #( - .NoSlvMst ( NUM_SLAVE_MASTER[i] ) + .NumSlvMst ( NUM_SLAVE_MASTER[i] ) ) i_lite_xbar (.*); end @@ -84,7 +84,7 @@ module axi_synth_bench ( localparam int unsigned DataWidth = (2**i_data) * 8; for (genvar i_slv = 0; i_slv < 3; i_slv++) begin synth_axi_lite_to_apb #( - .NoApbSlaves ( NUM_SLAVE_MASTER[i_slv] ), + .NumApbSlaves ( NUM_SLAVE_MASTER[i_slv] ), .DataWidth ( DataWidth ) ) i_axi_lite_to_apb (.*); end @@ -285,8 +285,8 @@ endmodule `include "axi/typedef.svh" module synth_axi_lite_to_apb #( - parameter int unsigned NoApbSlaves = 0, - parameter int unsigned DataWidth = 0 + parameter int unsigned NumApbSlaves = 0, + parameter int unsigned DataWidth = 0 ) ( input logic clk_i, // Clock input logic rst_ni // Asynchronous reset active low @@ -320,16 +320,16 @@ module synth_axi_lite_to_apb #( `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t) - axi_req_t axi_req; - axi_rsp_t axi_rsp; - apb_req_t [NoApbSlaves-1:0] apb_req; - apb_rsp_t [NoApbSlaves-1:0] apb_rsp; + axi_req_t axi_req; + axi_rsp_t axi_rsp; + apb_req_t [NumApbSlaves-1:0] apb_req; + apb_rsp_t [NumApbSlaves-1:0] apb_rsp; - axi_pkg::xbar_rule_32_t [NoApbSlaves-1:0] addr_map; + axi_pkg::xbar_rule_32_t [NumApbSlaves-1:0] addr_map; axi_lite_to_apb #( - .NoApbSlaves ( NoApbSlaves ), - .NoRules ( NoApbSlaves ), + .NumApbSlaves ( NumApbSlaves ), + .NumRules ( NumApbSlaves ), .AddrWidth ( 32'd32 ), .DataWidth ( DataWidth ), .axi_lite_req_t ( axi_req_t ), @@ -393,7 +393,7 @@ endmodule `include "axi/typedef.svh" module synth_axi_lite_xbar #( - parameter int unsigned NoSlvMst = 32'd1 + parameter int unsigned NumSlvMst = 32'd1 ) ( input logic clk_i, // Clock input logic rst_ni // Asynchronous reset active low @@ -410,22 +410,22 @@ module synth_axi_lite_xbar #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) localparam axi_pkg::xbar_cfg_t XbarCfg = '{ - NoSlvPorts: NoSlvMst, - NoMstPorts: NoSlvMst, + NumSlvPorts: NumSlvMst, + NumMstPorts: NumSlvMst, MaxMstTrans: 32'd5, MaxSlvTrans: 32'd5, FallThrough: 1'b1, LatencyMode: axi_pkg::CUT_ALL_PORTS, AddrWidth: 32'd32, DataWidth: 32'd32, - NoAddrRules: NoSlvMst, + NumAddrRules: NumSlvMst, default: '0 }; - axi_pkg::xbar_rule_32_t [NoSlvMst-1:0] addr_map; - logic test; - axi_lite_req_t [NoSlvMst-1:0] mst_reqs, slv_reqs; - axi_lite_rsp_t [NoSlvMst-1:0] mst_rsps, slv_rsps; + axi_pkg::xbar_rule_32_t [NumSlvMst-1:0] addr_map; + logic test; + axi_lite_req_t [NumSlvMst-1:0] mst_reqs, slv_reqs; + axi_lite_rsp_t [NumSlvMst-1:0] mst_rsps, slv_rsps; axi_lite_xbar #( .Cfg ( XbarCfg ), diff --git a/test/tb_axi_addr_test.sv b/test/tb_axi_addr_test.sv index be9fec2e5..f4fc00c35 100644 --- a/test/tb_axi_addr_test.sv +++ b/test/tb_axi_addr_test.sv @@ -30,9 +30,9 @@ module tb_axi_addr_test #( localparam int unsigned UserWidth = 32'd1; // Sim print config, how many transactions - localparam int unsigned PrintTnx = 1000; - localparam int unsigned NoReads = 0; - localparam int unsigned NoWrites = NumTests; + localparam int unsigned PrintTnx = 1000; + localparam int unsigned NumReads = 0; + localparam int unsigned NumWrites = NumTests; typedef logic [AddrWidth:0] addr_t; @@ -46,7 +46,7 @@ module tb_axi_addr_test #( endclass // Random master no Transactions - localparam int unsigned NoPendingDut = 16; + localparam int unsigned NumPendingDut = 16; // timing parameters localparam time CyclTime = 10ns; @@ -150,11 +150,11 @@ module tb_axi_addr_test #( end if ((aw % PrintTnx == 0) && ! aw_printed) begin - $display("%t> Transmit AW %d of %d.", $time(), aw, NoWrites); + $display("%t> Transmit AW %d of %d.", $time(), aw, NumWrites); aw_printed = 1'b1; end if ((ar % PrintTnx == 0) && !ar_printed) begin - $display("%t> Transmit AR %d of %d.", $time(), ar, NoReads); + $display("%t> Transmit AR %d of %d.", $time(), ar, NumReads); ar_printed = 1'b1; end diff --git a/test/tb_axi_bus_compare.sv b/test/tb_axi_bus_compare.sv index 76847d49d..81eb00b9f 100644 --- a/test/tb_axi_bus_compare.sv +++ b/test/tb_axi_bus_compare.sv @@ -198,7 +198,7 @@ module tb_axi_bus_compare #( ); axi_multicut #( - .NoCuts (8), + .NumCuts (8), .aw_chan_t (axi_aw_chan_t), .w_chan_t (axi_w_chan_t), .b_chan_t (axi_b_chan_t), diff --git a/test/tb_axi_fifo.sv b/test/tb_axi_fifo.sv index 045630c3b..8a4170fb9 100644 --- a/test/tb_axi_fifo.sv +++ b/test/tb_axi_fifo.sv @@ -17,8 +17,8 @@ module tb_axi_fifo #( parameter int unsigned Depth = 16, parameter int unsigned FallThrough = 0, - parameter int unsigned NoWrites = 200, // How many writes per master - parameter int unsigned NoReads = 200 // How many reads per master + parameter int unsigned NumWrites = 200, // How many writes per master + parameter int unsigned NumReads = 200 // How many reads per master ); // Random Master Atomics localparam int unsigned MaxAW = 30; @@ -124,7 +124,7 @@ module tb_axi_fifo #( axi_rand_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); axi_rand_master.reset(); @(posedge rst_n); - axi_rand_master.run(NoReads, NoWrites); + axi_rand_master.run(NumReads, NumWrites); end_of_sim <= 1'b1; repeat (10000) @(posedge clk); $stop(); @@ -156,11 +156,11 @@ module tb_axi_fifo #( end if ((aw % PrintTnx == 0) && !aw_printed) begin - $display("%t> Transmit AW %d of %d.", $time(), aw, NoWrites); + $display("%t> Transmit AW %d of %d.", $time(), aw, NumWrites); aw_printed = 1'b1; end if ((ar % PrintTnx == 0) && !ar_printed) begin - $display("%t> Transmit AR %d of %d.", $time(), ar, NoReads); + $display("%t> Transmit AR %d of %d.", $time(), ar, NumReads); ar_printed = 1'b1; end diff --git a/test/tb_axi_isolate.sv b/test/tb_axi_isolate.sv index b2e9da18a..959225392 100644 --- a/test/tb_axi_isolate.sv +++ b/test/tb_axi_isolate.sv @@ -16,11 +16,11 @@ `include "axi/assign.svh" module tb_axi_isolate #( - parameter int unsigned NoWrites = 50000, // How many writes per master - parameter int unsigned NoReads = 30000 // How many reads per master + parameter int unsigned NumWrites = 50000, // How many writes per master + parameter int unsigned NumReads = 30000 // How many reads per master ); // Random master no Transactions - localparam int unsigned NoPendingDut = 16; + localparam int unsigned NumPendingDut = 16; // Random Master Atomics localparam int unsigned MaxAW = 32'd30; localparam int unsigned MaxAR = 32'd30; @@ -116,7 +116,7 @@ module tb_axi_isolate #( // DUT //----------------------------------- axi_isolate_intf #( - .NUM_PENDING ( NoPendingDut ), // number of pending requests + .NUM_PENDING ( NumPendingDut ), // number of pending requests .AXI_ID_WIDTH ( IdWidth ), // AXI ID width .AXI_ADDR_WIDTH ( AddrWidth ), // AXI address width .AXI_DATA_WIDTH ( DataWidth ), // AXI data width @@ -138,7 +138,7 @@ module tb_axi_isolate #( axi_rand_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); axi_rand_master.reset(); @(posedge rst_n); - axi_rand_master.run(NoReads, NoWrites); + axi_rand_master.run(NumReads, NumWrites); end_of_sim <= 1'b1; repeat (10000) @(posedge clk); $stop(); @@ -179,11 +179,11 @@ module tb_axi_isolate #( end if ((aw % PrintTnx == 0) && ! aw_printed) begin - $display("%t> Transmit AW %d of %d.", $time(), aw, NoWrites); + $display("%t> Transmit AW %d of %d.", $time(), aw, NumWrites); aw_printed = 1'b1; end if ((ar % PrintTnx == 0) && !ar_printed) begin - $display("%t> Transmit AR %d of %d.", $time(), ar, NoReads); + $display("%t> Transmit AR %d of %d.", $time(), ar, NumReads); ar_printed = 1'b1; end diff --git a/test/tb_axi_lite_regs.sv b/test/tb_axi_lite_regs.sv index affc9481d..32676aa0b 100644 --- a/test/tb_axi_lite_regs.sv +++ b/test/tb_axi_lite_regs.sv @@ -27,9 +27,9 @@ module tb_axi_lite_regs #( /// Define the parameter `SecuProtOnly` of the DUT. parameter bit TbSecuProtOnly = 1'b0, /// Number of random writes generated by the testbench AXI4-Lite random master. - parameter int unsigned TbNoWrites = 32'd1000, + parameter int unsigned TbNumWrites = 32'd1000, /// Number of random reads generated by the testbench AXI4-Lite random master. - parameter int unsigned TbNoReads = 32'd1500 + parameter int unsigned TbNumReads = 32'd1500 ); // AXI configuration localparam int unsigned AddrWidth = 32'd32; // Address Width @@ -126,7 +126,7 @@ module tb_axi_lite_regs #( end // Let random stimuli application checking is separate. - lite_axi_master.run(TbNoReads, TbNoWrites); + lite_axi_master.run(TbNumReads, TbNumWrites); end_of_sim <= 1'b1; end diff --git a/test/tb_axi_lite_to_apb.sv b/test/tb_axi_lite_to_apb.sv index ef4aa12e3..87ef07aa7 100644 --- a/test/tb_axi_lite_to_apb.sv +++ b/test/tb_axi_lite_to_apb.sv @@ -24,11 +24,11 @@ module tb_axi_lite_to_apb #( parameter bit TbPipelineResponse = 1'b0 ); // Dut parameters - localparam int unsigned NoApbSlaves = 8; // How many APB Slaves there are - localparam int unsigned NoAddrRules = 9; // How many address rules for the APB slaves + localparam int unsigned NumApbSlaves = 8; // How many APB Slaves there are + localparam int unsigned NumAddrRules = 9; // How many address rules for the APB slaves // Random master no Transactions - localparam int unsigned NoWrites = 10000; // How many rand writes of the master - localparam int unsigned NoReads = 20000; // How many rand reads of the master + localparam int unsigned NumWrites = 10000; // How many rand writes of the master + localparam int unsigned NumReads = 20000; // How many rand reads of the master // timing parameters localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -53,7 +53,7 @@ module tb_axi_lite_to_apb #( `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t) - typedef logic [NoApbSlaves-1:0] sel_t; + typedef logic [NumApbSlaves-1:0] sel_t; typedef struct packed { addr_t paddr; @@ -71,7 +71,7 @@ module tb_axi_lite_to_apb #( logic pslverr; } apb_rsp_t; - localparam rule_t [NoAddrRules-1:0] AddrMap = '{ + localparam rule_t [NumAddrRules-1:0] AddrMap = '{ '{idx: 32'd7, start_addr: 32'h0001_0000, end_addr: 32'h0001_1000}, '{idx: 32'd6, start_addr: 32'h0000_9000, end_addr: 32'h0001_0000}, '{idx: 32'd5, start_addr: 32'h0000_8000, end_addr: 32'h0000_9000}, @@ -117,8 +117,8 @@ module tb_axi_lite_to_apb #( axi_lite_rsp_t axi_rsp; // slave structs - apb_req_t [NoApbSlaves-1:0] apb_req; - apb_rsp_t [NoApbSlaves-1:0] apb_rsps; + apb_req_t [NumApbSlaves-1:0] apb_req; + apb_rsp_t [NumApbSlaves-1:0] apb_rsps; // ------------------------------- // AXI Interfaces @@ -144,12 +144,12 @@ module tb_axi_lite_to_apb #( end_of_sim <= 1'b0; axi_lite_rand_master.reset(); @(posedge rst_n); - axi_lite_rand_master.run(NoReads, NoWrites); + axi_lite_rand_master.run(NumReads, NumWrites); end_of_sim <= 1'b1; end - for (genvar i = 0; i < NoApbSlaves; i++) begin : gen_apb_slave + for (genvar i = 0; i < NumApbSlaves; i++) begin : gen_apb_slave initial begin : proc_apb_slave apb_rsps[i] <= '0; forever begin @@ -171,7 +171,7 @@ module tb_axi_lite_to_apb #( `ifndef VERILATOR // Assertions to determine correct APB protocol sequencing default disable iff (!rst_n); - for (genvar i = 0; i < NoApbSlaves; i++) begin : gen_apb_assertions + for (genvar i = 0; i < NumApbSlaves; i++) begin : gen_apb_assertions // when psel is not asserted, the bus is in the idle state sequence APB_IDLE; !apb_req[i].psel; @@ -228,8 +228,8 @@ module tb_axi_lite_to_apb #( // DUT //----------------------------------- axi_lite_to_apb #( - .NoApbSlaves ( NoApbSlaves ), - .NoRules ( NoAddrRules ), + .NumApbSlaves ( NumApbSlaves ), + .NumRules ( NumAddrRules ), .AddrWidth ( AddrWidth ), .DataWidth ( DataWidth ), .PipelineRequest ( TbPipelineRequest ), diff --git a/test/tb_axi_lite_xbar.sv b/test/tb_axi_lite_xbar.sv index 6c8c3f25c..13a2d6390 100644 --- a/test/tb_axi_lite_xbar.sv +++ b/test/tb_axi_lite_xbar.sv @@ -23,11 +23,11 @@ module tb_axi_lite_xbar; // Dut parameters - localparam int unsigned NoMasters = 32'd6; // How many Masters there are - localparam int unsigned NoSlaves = 32'd8; // How many Slaves there are + localparam int unsigned NumMasters = 32'd6; // How many Masters there are + localparam int unsigned NumSlaves = 32'd8; // How many Slaves there are // Random master no Transactions - localparam int unsigned NoWrites = 32'd10000; // How many writes per master - localparam int unsigned NoReads = 32'd10000; // How many reads per master + localparam int unsigned NumWrites = 32'd10000; // How many writes per master + localparam int unsigned NumReads = 32'd10000; // How many reads per master // timing parameters localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -38,15 +38,15 @@ module tb_axi_lite_xbar; localparam int unsigned StrbWidth = DataWidth / 32'd8; // in the bench can change this variables which are set here freely localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ - NoSlvPorts: NoMasters, - NoMstPorts: NoSlaves, + NumSlvPorts: NumMasters, + NumMstPorts: NumSlaves, MaxMstTrans: 32'd10, MaxSlvTrans: 32'd6, FallThrough: 1'b0, LatencyMode: axi_pkg::CUT_ALL_AX, AddrWidth: AddrWidth, DataWidth: DataWidth, - NoAddrRules: 32'd8, + NumAddrRules: 32'd8, default: '0 }; typedef logic [AddrWidth-1:0] addr_t; @@ -54,7 +54,7 @@ module tb_axi_lite_xbar; typedef logic [DataWidth-1:0] data_t; typedef logic [StrbWidth-1:0] strb_t; - localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = '{ + localparam rule_t [xbar_cfg.NumAddrRules-1:0] AddrMap = '{ '{idx: 32'd7, start_addr: 32'h0001_0000, end_addr: 32'h0001_1000}, '{idx: 32'd6, start_addr: 32'h0000_9000, end_addr: 32'h0001_0000}, '{idx: 32'd5, start_addr: 32'h0000_8000, end_addr: 32'h0000_9000}, @@ -92,7 +92,7 @@ module tb_axi_lite_xbar; logic clk; // DUT signals logic rst_n; - logic [NoMasters-1:0] end_of_sim; + logic [NumMasters-1:0] end_of_sim; // ------------------------------- // AXI Interfaces @@ -100,31 +100,31 @@ module tb_axi_lite_xbar; AXI_LITE #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) master [NoMasters-1:0] (); + ) master [NumMasters-1:0] (); AXI_LITE_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) master_dv [NoMasters-1:0] (clk); - for (genvar i = 0; i < NoMasters; i++) begin : gen_conn_dv_masters + ) master_dv [NumMasters-1:0] (clk); + for (genvar i = 0; i < NumMasters; i++) begin : gen_conn_dv_masters `AXI_LITE_ASSIGN(master[i], master_dv[i]) end AXI_LITE #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) slave [NoSlaves-1:0] (); + ) slave [NumSlaves-1:0] (); AXI_LITE_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ) - ) slave_dv [NoSlaves-1:0](clk); - for (genvar i = 0; i < NoSlaves; i++) begin : gen_conn_dv_slaves + ) slave_dv [NumSlaves-1:0](clk); + for (genvar i = 0; i < NumSlaves; i++) begin : gen_conn_dv_slaves `AXI_LITE_ASSIGN(slave_dv[i], slave[i]) end // ------------------------------- // AXI Rand Masters and Slaves // ------------------------------- // Masters control simulation run time - for (genvar i = 0; i < NoMasters; i++) begin : gen_rand_master + for (genvar i = 0; i < NumMasters; i++) begin : gen_rand_master initial begin : proc_generate_traffic automatic rand_lite_master_t lite_axi_master = new ( master_dv[i], $sformatf("MST_%0d", i)); automatic data_t data = '0; @@ -134,12 +134,12 @@ module tb_axi_lite_xbar; @(posedge rst_n); lite_axi_master.write(32'h0000_1100, axi_pkg::prot_t'('0), 64'hDEADBEEFDEADBEEF, 8'hFF, resp); lite_axi_master.read(32'h0000_e100, axi_pkg::prot_t'('0), data, resp); - lite_axi_master.run(NoReads, NoWrites); + lite_axi_master.run(NumReads, NumWrites); end_of_sim[i] <= 1'b1; end end - for (genvar i = 0; i < NoSlaves; i++) begin : gen_rand_slave + for (genvar i = 0; i < NumSlaves; i++) begin : gen_rand_slave initial begin : proc_recieve_traffic automatic rand_lite_slave_t lite_axi_slave = new( slave_dv[i] , $sformatf("SLV_%0d", i)); lite_axi_slave.reset(); diff --git a/test/tb_axi_serializer.sv b/test/tb_axi_serializer.sv index 9f321486b..aa027ef41 100644 --- a/test/tb_axi_serializer.sv +++ b/test/tb_axi_serializer.sv @@ -16,11 +16,11 @@ `include "axi/assign.svh" module tb_axi_serializer #( - parameter int unsigned NoWrites = 5000, // How many writes per master - parameter int unsigned NoReads = 3000 // How many reads per master + parameter int unsigned NumWrites = 5000, // How many writes per master + parameter int unsigned NumReads = 3000 // How many reads per master ); // Random master no Transactions - localparam int unsigned NoPendingDut = 4; + localparam int unsigned NumPendingDut = 4; // Random Master Atomics localparam int unsigned MaxAW = 32'd30; localparam int unsigned MaxAR = 32'd30; @@ -113,8 +113,8 @@ module tb_axi_serializer #( // DUT //----------------------------------- axi_serializer_intf #( - .MAX_READ_TXNS ( NoPendingDut ), - .MAX_WRITE_TXNS ( NoPendingDut ), + .MAX_READ_TXNS ( NumPendingDut ), + .MAX_WRITE_TXNS ( NumPendingDut ), .AXI_ID_WIDTH ( IdWidth ), // AXI ID width .AXI_ADDR_WIDTH ( AddrWidth ), // AXI address width .AXI_DATA_WIDTH ( DataWidth ), // AXI data width @@ -134,7 +134,7 @@ module tb_axi_serializer #( axi_rand_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); axi_rand_master.reset(); @(posedge rst_n); - axi_rand_master.run(NoReads, NoWrites); + axi_rand_master.run(NumReads, NumWrites); end_of_sim <= 1'b1; repeat (100) @(posedge clk); $stop(); @@ -267,11 +267,11 @@ module tb_axi_serializer #( end if ((aw % PrintTxn == 0) && ! aw_printed) begin - $display("%t> Transmit AW %d of %d.", $time(), aw, NoWrites); + $display("%t> Transmit AW %d of %d.", $time(), aw, NumWrites); aw_printed = 1'b1; end if ((ar % PrintTxn == 0) && !ar_printed) begin - $display("%t> Transmit AR %d of %d.", $time(), ar, NoReads); + $display("%t> Transmit AR %d of %d.", $time(), ar, NumReads); ar_printed = 1'b1; end diff --git a/test/tb_axi_slave_compare.sv b/test/tb_axi_slave_compare.sv index 1bb63db1b..1b8a37d40 100644 --- a/test/tb_axi_slave_compare.sv +++ b/test/tb_axi_slave_compare.sv @@ -127,7 +127,7 @@ module tb_axi_slave_compare #( ); axi_multicut #( - .NoCuts (8), + .NumCuts (8), .aw_chan_t (axi_aw_chan_t), .w_chan_t (axi_w_chan_t), .b_chan_t (axi_b_chan_t), diff --git a/test/tb_axi_xbar.sv b/test/tb_axi_xbar.sv index e313e49bf..d67b7c3f2 100644 --- a/test/tb_axi_xbar.sv +++ b/test/tb_axi_xbar.sv @@ -64,8 +64,8 @@ module tb_axi_xbar #( localparam int unsigned TbUserWidth = 5; // In the bench can change this variables which are set here freely, localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ - NoSlvPorts: TbNoMasters, - NoMstPorts: TbNoSlaves, + NumSlvPorts: TbNumMasters, + NumMstPorts: TbNumSlaves, MaxMstTrans: 10, MaxSlvTrans: 6, FallThrough: 1'b0, @@ -76,7 +76,7 @@ module tb_axi_xbar #( UniqueIds: TbUniqueIds, AddrWidth: TbAddrWidth, DataWidth: TbDataWidth, - NoAddrRules: TbNoSlaves + NumAddrRules: TbNumSlaves }; typedef logic [TbIdWidthMasters-1:0] id_mst_t; typedef logic [TbIdWidthSlaves-1:0] id_slv_t; @@ -103,10 +103,10 @@ module tb_axi_xbar #( `AXI_TYPEDEF_RSP_T(slv_rsp_t, b_chan_slv_t, r_chan_slv_t) // Each slave has its own address range: - localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = addr_map_gen(); + localparam rule_t [xbar_cfg.NumAddrRules-1:0] AddrMap = addr_map_gen(); - function rule_t [xbar_cfg.NoAddrRules-1:0] addr_map_gen (); - for (int unsigned i = 0; i < xbar_cfg.NoAddrRules; i++) begin + function rule_t [xbar_cfg.NumAddrRules-1:0] addr_map_gen (); + for (int unsigned i = 0; i < xbar_cfg.NumAddrRules; i++) begin addr_map_gen[i] = rule_t'{ idx: unsigned'(i), start_addr: i * 32'h0000_2000, @@ -219,7 +219,7 @@ module tb_axi_xbar #( axi_rand_master[i] = new( master_dv[i] ); end_of_sim[i] <= 1'b0; axi_rand_master[i].add_memory_region(AddrMap[0].start_addr, - AddrMap[xbar_cfg.NoAddrRules-1].end_addr, + AddrMap[xbar_cfg.NumAddrRules-1].end_addr, axi_pkg::DEVICE_NONBUFFERABLE); axi_rand_master[i].reset(); @(posedge rst_n); @@ -245,9 +245,9 @@ module tb_axi_xbar #( .IdWidthMasters ( TbIdWidthMasters ), .IdWidthSlaves ( TbIdWidthSlaves ), .UserWidth ( TbUserWidth ), - .NoMasters ( TbNoMasters ), - .NoSlaves ( TbNoSlaves ), - .NoAddrRules ( xbar_cfg.NoAddrRules ), + .NumMasters ( TbNumMasters ), + .NumSlaves ( TbNumSlaves ), + .NumAddrRules ( xbar_cfg.NumAddrRules ), .rule_t ( rule_t ), .AddrMap ( AddrMap ), .TimeTest ( TestTime ) diff --git a/test/tb_axi_xbar_pkg.sv b/test/tb_axi_xbar_pkg.sv index 6c59d2b71..57da2369b 100644 --- a/test/tb_axi_xbar_pkg.sv +++ b/test/tb_axi_xbar_pkg.sv @@ -24,11 +24,11 @@ package tb_axi_xbar_pkg; parameter int unsigned IdWidthMasters, parameter int unsigned IdWidthSlaves, parameter int unsigned UserWidth, - parameter int unsigned NoMasters, - parameter int unsigned NoSlaves, - parameter int unsigned NoAddrRules, + parameter int unsigned NumMasters, + parameter int unsigned NumSlaves, + parameter int unsigned NumAddrRules, parameter type rule_t, - parameter rule_t [NoAddrRules-1:0] AddrMap, + parameter rule_t [NumAddrRules-1:0] AddrMap, // Stimuli application and test time parameter time TimeTest ); @@ -36,7 +36,7 @@ package tb_axi_xbar_pkg; typedef logic [IdWidthSlaves-1:0] slv_axi_id_t; typedef logic [AddrWidth-1:0] axi_addr_t; - typedef logic [$clog2(NoMasters)-1:0] idx_mst_t; + typedef logic [$clog2(NumMasters)-1:0] idx_mst_t; typedef int unsigned idx_slv_t; // from rule_t typedef struct packed { @@ -75,25 +75,25 @@ package tb_axi_xbar_pkg; .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidthMasters ), .AXI_USER_WIDTH ( UserWidth ) - ) masters_axi [NoMasters-1:0]; + ) masters_axi [NumMasters-1:0]; virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidthSlaves ), .AXI_USER_WIDTH ( UserWidth ) - ) slaves_axi [NoSlaves-1:0]; + ) slaves_axi [NumSlaves-1:0]; //----------------------------------------- // Queues and FIFOs to hold the expected ids //----------------------------------------- // Write transactions - ax_queue_t exp_aw_queue [NoSlaves-1:0]; - slave_exp_t exp_w_fifo [NoSlaves-1:0][$]; - slave_exp_t act_w_fifo [NoSlaves-1:0][$]; - master_exp_queue_t exp_b_queue [NoMasters-1:0]; + ax_queue_t exp_aw_queue [NumSlaves-1:0]; + slave_exp_t exp_w_fifo [NumSlaves-1:0][$]; + slave_exp_t act_w_fifo [NumSlaves-1:0][$]; + master_exp_queue_t exp_b_queue [NumMasters-1:0]; // Read transactions - ax_queue_t exp_ar_queue [NoSlaves-1:0]; - master_exp_queue_t exp_r_queue [NoMasters-1:0]; + ax_queue_t exp_ar_queue [NumSlaves-1:0]; + master_exp_queue_t exp_r_queue [NumMasters-1:0]; //----------------------------------------- // Bookkeeping @@ -112,13 +112,13 @@ package tb_axi_xbar_pkg; .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidthMasters ), .AXI_USER_WIDTH ( UserWidth ) - ) axi_masters_vif [NoMasters-1:0], + ) axi_masters_vif [NumMasters-1:0], virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH ( AddrWidth ), .AXI_DATA_WIDTH ( DataWidth ), .AXI_ID_WIDTH ( IdWidthSlaves ), .AXI_USER_WIDTH ( UserWidth ) - ) axi_slaves_vif [NoSlaves-1:0] + ) axi_slaves_vif [NumSlaves-1:0] ); begin this.masters_axi = axi_masters_vif; @@ -126,11 +126,11 @@ package tb_axi_xbar_pkg; this.tests_expected = 0; this.tests_conducted = 0; this.tests_failed = 0; - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumMasters; i++) begin this.exp_b_queue[i] = new; this.exp_r_queue[i] = new; end - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumSlaves; i++) begin this.exp_aw_queue[i] = new; this.exp_ar_queue[i] = new; end @@ -163,7 +163,7 @@ package tb_axi_xbar_pkg; if (masters_axi[i].aw_valid && masters_axi[i].aw_ready) begin // check if it should go to a decerror decerr = 1'b1; - for (int unsigned j = 0; j < NoAddrRules; j++) begin + for (int unsigned j = 0; j < NumAddrRules; j++) begin if ((masters_axi[i].aw_addr >= AddrMap[j].start_addr) && (masters_axi[i].aw_addr < AddrMap[j].end_addr)) begin to_slave_idx = idx_slv_t'(AddrMap[j].idx); @@ -319,7 +319,7 @@ package tb_axi_xbar_pkg; mst_axi_len = masters_axi[i].ar_len; exp_slv_axi_id = {idx_mst_t'(i), mst_axi_id}; exp_slv_idx = '0; - for (int unsigned j = 0; j < NoAddrRules; j++) begin + for (int unsigned j = 0; j < NumAddrRules; j++) begin if ((mst_axi_addr >= AddrMap[j].start_addr) && (mst_axi_addr < AddrMap[j].end_addr)) begin exp_slv_idx = AddrMap[j].idx; exp_decerr = 1'b0; @@ -436,48 +436,48 @@ package tb_axi_xbar_pkg; // execute all processes that put something into the queues PushMon: fork proc_mst_aw: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumMasters; i++) begin monitor_mst_aw(i); end end proc_mst_ar: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumMasters; i++) begin monitor_mst_ar(i); end end join : PushMon // this one pops and pushes something proc_slv_aw: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumSlaves; i++) begin monitor_slv_aw(i); end end proc_slv_w: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumSlaves; i++) begin monitor_slv_w(i); end end // These only pop somethong from the queses PopMon: fork proc_mst_b: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumMasters; i++) begin monitor_mst_b(i); end end proc_slv_ar: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumSlaves; i++) begin monitor_slv_ar(i); end end proc_mst_r: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumMasters; i++) begin monitor_mst_r(i); end end join : PopMon // check the slave W fifos last proc_check_slv_w: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumSlaves; i++) begin check_slv_w(i); end end