diff --git a/bsp_diff/common/kernel/lts2020-yocto/17_0017-drm-i915-Wrap-all-access-to-i915_vma.node.start-size.patch b/bsp_diff/common/kernel/lts2020-yocto/17_0017-drm-i915-Wrap-all-access-to-i915_vma.node.start-size.patch new file mode 100644 index 0000000000..90ced11c5d --- /dev/null +++ b/bsp_diff/common/kernel/lts2020-yocto/17_0017-drm-i915-Wrap-all-access-to-i915_vma.node.start-size.patch @@ -0,0 +1,1276 @@ +From e81a2d4a6caee8793ede65a47e35b7c5790d38d8 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Thu, 11 Feb 2021 23:38:48 +0000 +Subject: [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size + +We already wrap i915_vma.node.start for use with the GGTT, as there we +can perform additional sanity checks that the node belongs to the GGTT +and fits within the 32b registers. In the next couple of patches, we +will introduce guard pages around the objects _inside_ the drm_mm_node +allocation. That is we will offset the vma->pages so that the first page +is at drm_mm_node.start + vma->guard (not 0 as is currently the case). +All users must then not use i915_vma.node.start directly, but compute +the guard offset, thus all users are converted to use a +i915_vma_offset() wrapper. + +The notable exceptions are the selftests that are testing exact +behaviour of i915_vma_pin/i915_vma_insert. + +Signed-off-by: Chris Wilson +Reviewed-by: Matthew Auld +--- + drivers/gpu/drm/i915/display/intel_display.c | 4 +- + drivers/gpu/drm/i915/display/intel_fbdev.c | 6 +-- + .../gpu/drm/i915/gem/i915_gem_client_blt.c | 3 +- + .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 41 ++++++++++--------- + drivers/gpu/drm/i915/gem/i915_gem_mman.c | 3 +- + .../gpu/drm/i915/gem/i915_gem_object_blt.c | 13 +++--- + drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +- + drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +- + .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- + .../i915/gem/selftests/i915_gem_client_blt.c | 15 +++---- + .../drm/i915/gem/selftests/i915_gem_context.c | 19 ++++++--- + .../drm/i915/gem/selftests/i915_gem_mman.c | 2 +- + .../drm/i915/gem/selftests/igt_gem_utils.c | 7 ++-- + drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +- + drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +- + drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 8 ++-- + drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 ++- + drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +- + drivers/gpu/drm/i915/gt/intel_ppgtt.c | 7 +++- + drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- + .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +- + drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 12 +++--- + drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 ++++---- + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 17 ++++---- + drivers/gpu/drm/i915/gt/selftest_lrc.c | 16 ++++---- + .../drm/i915/gt/selftest_ring_submission.c | 2 +- + drivers/gpu/drm/i915/gt/selftest_rps.c | 12 +++--- + .../gpu/drm/i915/gt/selftest_workarounds.c | 9 ++-- + drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +- + drivers/gpu/drm/i915/i915_debugfs.c | 3 +- + drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- + drivers/gpu/drm/i915/i915_perf.c | 2 +- + drivers/gpu/drm/i915/i915_vma.c | 21 +++++----- + drivers/gpu/drm/i915/i915_vma.h | 23 +++++++++-- + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 +++++- + drivers/gpu/drm/i915/selftests/i915_request.c | 20 ++++----- + drivers/gpu/drm/i915/selftests/igt_spinner.c | 11 +++-- + 37 files changed, 195 insertions(+), 143 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c +index 362bff9beb5c..7cdd6aeff8df 100644 +--- a/drivers/gpu/drm/i915/display/intel_display.c ++++ b/drivers/gpu/drm/i915/display/intel_display.c +@@ -180,7 +180,7 @@ static void dpt_insert_entries(struct i915_address_space *vm, + * not to allow the user to override access to a read only page. + */ + +- i = vma->node.start / I915_GTT_PAGE_SIZE; ++ i = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE; + for_each_sgt_daddr(addr, sgt_iter, vma->pages) + gen8_set_pte(&base[i++], pte_encode | addr); + } +@@ -220,7 +220,7 @@ static void dpt_bind_vma(struct i915_address_space *vm, + + static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma) + { +- vm->clear_range(vm, vma->node.start, vma->size); ++ vm->clear_range(vm, i915_vma_offset(vma), vma->size); + } + + static void dpt_cleanup(struct i915_address_space *vm) +diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c +index 4af40229f5ec..678700266dce 100644 +--- a/drivers/gpu/drm/i915/display/intel_fbdev.c ++++ b/drivers/gpu/drm/i915/display/intel_fbdev.c +@@ -261,8 +261,8 @@ static int intelfb_create(struct drm_fb_helper *helper, + + /* Our framebuffer is the entirety of fbdev's system memory */ + info->fix.smem_start = +- (unsigned long)(ggtt->gmadr.start + vma->node.start); +- info->fix.smem_len = vma->node.size; ++ (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma)); ++ info->fix.smem_len = vma->size; + } + + vaddr = i915_vma_pin_iomap(vma); +@@ -273,7 +273,7 @@ static int intelfb_create(struct drm_fb_helper *helper, + goto out_unpin; + } + info->screen_base = vaddr; +- info->screen_size = vma->node.size; ++ info->screen_size = vma->size; + + drm_fb_helper_fill_info(info, &ifbdev->helper, sizes); + +diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c +index 44821d94544f..864510b3a7fd 100644 +--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c ++++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c +@@ -218,7 +218,8 @@ static void clear_pages_worker(struct work_struct *work) + } + + err = rq->engine->emit_bb_start(rq, +- batch->node.start, batch->node.size, ++ i915_vma_offset(batch), ++ i915_vma_size(batch), + 0); + out_request: + if (unlikely(err)) { +diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +index a8abc9af5ff4..661b4972ff34 100644 +--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c ++++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +@@ -372,22 +372,23 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry, + const struct i915_vma *vma, + unsigned int flags) + { +- if (vma->node.size < entry->pad_to_size) ++ const u64 start = i915_vma_offset(vma); ++ const u64 size = i915_vma_size(vma); ++ ++ if (size < entry->pad_to_size) + return true; + +- if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment)) ++ if (entry->alignment && !IS_ALIGNED(start, entry->alignment)) + return true; + +- if (flags & EXEC_OBJECT_PINNED && +- vma->node.start != entry->offset) ++ if (flags & EXEC_OBJECT_PINNED && start != entry->offset) + return true; + +- if (flags & __EXEC_OBJECT_NEEDS_BIAS && +- vma->node.start < BATCH_OFFSET_BIAS) ++ if (flags & __EXEC_OBJECT_NEEDS_BIAS && start < BATCH_OFFSET_BIAS) + return true; + + if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && +- (vma->node.start + vma->node.size + 4095) >> 32) ++ (start + size + 4095) >> 32) + return true; + + if (flags & __EXEC_OBJECT_NEEDS_MAP && +@@ -433,7 +434,7 @@ eb_pin_vma(struct i915_execbuffer *eb, + int err; + + if (vma->node.size) +- pin_flags = vma->node.start; ++ pin_flags = __i915_vma_offset(vma); + else + pin_flags = entry->offset & PIN_OFFSET_MASK; + +@@ -627,8 +628,8 @@ static int eb_reserve_vma(struct i915_execbuffer *eb, + if (err) + return err; + +- if (entry->offset != vma->node.start) { +- entry->offset = vma->node.start | UPDATE; ++ if (entry->offset != i915_vma_offset(vma)) { ++ entry->offset = i915_vma_offset(vma) | UPDATE; + eb->args->flags |= __EXEC_HAS_RELOC; + } + +@@ -943,8 +944,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb) + return err; + + if (!err) { +- if (entry->offset != vma->node.start) { +- entry->offset = vma->node.start | UPDATE; ++ if (entry->offset != i915_vma_offset(vma)) { ++ entry->offset = i915_vma_offset(vma) | UPDATE; + eb->args->flags |= __EXEC_HAS_RELOC; + } + } else { +@@ -1032,7 +1033,7 @@ static inline u64 + relocation_target(const struct drm_i915_gem_relocation_entry *reloc, + const struct i915_vma *target) + { +- return gen8_canonical_addr((int)reloc->delta + target->node.start); ++ return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target)); + } + + static void reloc_cache_clear(struct reloc_cache *cache) +@@ -1235,7 +1236,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, + if (err) /* no inactive aperture space, use cpu reloc */ + return NULL; + } else { +- cache->node.start = vma->node.start; ++ cache->node.start = i915_ggtt_offset(vma); + cache->node.mm = (void *)vma; + } + } +@@ -1401,7 +1402,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, + goto err_request; + + err = eb->engine->emit_bb_start(rq, +- batch->node.start, PAGE_SIZE, ++ i915_vma_offset(batch), PAGE_SIZE, + cache->graphics_ver > 5 ? 0 : I915_DISPATCH_SECURE); + if (err) + goto skip_request; +@@ -1521,7 +1522,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, + else if (IS_ERR(batch)) + return false; + +- addr = gen8_canonical_addr(vma->node.start + offset); ++ addr = gen8_canonical_addr(i915_vma_offset(vma) + offset); + if (ver >= 8) { + if (offset & 7) { + *batch++ = MI_STORE_DWORD_IMM_GEN4; +@@ -1621,7 +1622,7 @@ relocate_entry(struct i915_vma *vma, + } + } + +- return target->node.start | UPDATE; ++ return i915_vma_offset(target) | UPDATE; + } + + static u64 +@@ -1685,7 +1686,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, + * more work needs to be done. + */ + if (!DBG_FORCE_RELOC && +- gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) ++ gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset) + return 0; + + /* Check that the relocation address is valid... */ +@@ -2733,7 +2734,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch) + } + + err = eb->engine->emit_bb_start(eb->request, +- batch->node.start + ++ i915_vma_offset(batch) + + eb->batch_start_offset, + eb->batch_len, + eb->batch_flags); +@@ -2743,7 +2744,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch) + if (eb->trampoline) { + GEM_BUG_ON(eb->batch_start_offset); + err = eb->engine->emit_bb_start(eb->request, +- eb->trampoline->node.start + ++ i915_vma_offset(eb->trampoline) + + eb->batch_len, + 0, 0); + if (err) +diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c +index 8598a1c78a4c..088a2f3c684b 100644 +--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c ++++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c +@@ -369,9 +369,10 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf) + /* Finally, remap it using the new GTT offset */ + ret = remap_io_mapping(area, + area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT), +- (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT, ++ (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT, + min_t(u64, vma->size, area->vm_end - area->vm_start), + &ggtt->iomap); ++ + if (ret) + goto err_fence; + +diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +index 3e28c68fda3e..4d5445291478 100644 +--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c ++++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +@@ -65,7 +65,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, + } + + rem = vma->size; +- offset = vma->node.start; ++ offset = i915_vma_offset(vma); + + do { + u32 size = min_t(u64, rem, block_size); +@@ -202,8 +202,8 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, + + if (likely(!err)) + err = ce->engine->emit_bb_start(rq, +- batch->node.start, +- batch->node.size, ++ i915_vma_offset(batch), ++ i915_vma_size(batch), + 0); + out_request: + if (unlikely(err)) +@@ -290,8 +290,8 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, + } + + rem = src->size; +- src_offset = src->node.start; +- dst_offset = dst->node.start; ++ src_offset = i915_vma_offset(src); ++ dst_offset = i915_vma_offset(dst); + + do { + size = min_t(u64, rem, block_size); +@@ -429,7 +429,8 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, + } + + err = rq->engine->emit_bb_start(rq, +- batch->node.start, batch->node.size, ++ i915_vma_offset(batch), ++ i915_vma_size(batch), + 0); + + out_request: +diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c +index f4fb68e8955a..572a7b1c3dee 100644 +--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c ++++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c +@@ -399,7 +399,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr + mutex_lock(&i915->ggtt.vm.mutex); + list_for_each_entry_safe(vma, next, + &i915->ggtt.vm.bound_list, vm_link) { +- unsigned long count = vma->node.size >> PAGE_SHIFT; ++ unsigned long count = i915_vma_size(vma) >> PAGE_SHIFT; + + if (!vma->iomap || i915_vma_is_active(vma)) + continue; +diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c +index ef4d0f7dc118..1e49c7c69d80 100644 +--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c ++++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c +@@ -166,11 +166,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma, + return true; + + size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride); +- if (vma->node.size < size) ++ if (i915_vma_size(vma) < size) + return false; + + alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride); +- if (!IS_ALIGNED(vma->node.start, alignment)) ++ if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment)) + return false; + + return true; +diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +index dadd485bc52f..e478dec81aea 100644 +--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c ++++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +@@ -381,7 +381,7 @@ static int igt_check_page_sizes(struct i915_vma *vma) + * Maintaining alignment is required to utilise huge pages in the ppGGT. + */ + if (i915_gem_object_is_lmem(obj) && +- IS_ALIGNED(vma->node.start, SZ_2M) && ++ IS_ALIGNED(i915_vma_offset(vma), SZ_2M) && + vma->page_sizes.sg & SZ_2M && + vma->page_sizes.gtt < SZ_2M) { + pr_err("gtt pages mismatch for LMEM, expected 2M GTT pages, sg(%u), gtt(%u)\n", +diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +index 176e6b22f87f..a514ee03a94d 100644 +--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c ++++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +@@ -198,14 +198,14 @@ static int prepare_blit(const struct tiled_blits *t, + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; + *cs++ = 0; + *cs++ = t->height << 16 | t->width; +- *cs++ = lower_32_bits(dst->vma->node.start); ++ *cs++ = lower_32_bits(i915_vma_offset(dst->vma)); + if (use_64b_reloc) +- *cs++ = upper_32_bits(dst->vma->node.start); ++ *cs++ = upper_32_bits(i915_vma_offset(dst->vma)); + *cs++ = 0; + *cs++ = src_pitch; +- *cs++ = lower_32_bits(src->vma->node.start); ++ *cs++ = lower_32_bits(i915_vma_offset(src->vma)); + if (use_64b_reloc) +- *cs++ = upper_32_bits(src->vma->node.start); ++ *cs++ = upper_32_bits(i915_vma_offset(src->vma)); + + *cs++ = MI_BATCH_BUFFER_END; + +@@ -421,7 +421,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr) + { + int err; + +- if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) { ++ if (drm_mm_node_allocated(&vma->node) && i915_vma_offset(vma) != addr) { + err = i915_vma_unbind(vma); + if (err) + return err; +@@ -431,6 +431,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr) + if (err) + return err; + ++ GEM_BUG_ON(i915_vma_offset(vma) != addr); + return 0; + } + +@@ -477,8 +478,8 @@ tiled_blit(struct tiled_blits *t, + err = move_to_active(dst->vma, rq, 0); + if (!err) + err = rq->engine->emit_bb_start(rq, +- t->batch->node.start, +- t->batch->node.size, ++ i915_vma_offset(t->batch), ++ i915_vma_size(t->batch), + 0); + i915_request_get(rq); + i915_request_add(rq); +diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +index dbcfa28a9d91..fdecd02c1d28 100644 +--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c ++++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +@@ -905,8 +905,8 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v + + *cmd++ = MI_STORE_REGISTER_MEM_GEN8; + *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE); +- *cmd++ = lower_32_bits(vma->node.start); +- *cmd++ = upper_32_bits(vma->node.start); ++ *cmd++ = lower_32_bits(i915_vma_offset(vma)); ++ *cmd++ = upper_32_bits(i915_vma_offset(vma)); + *cmd = MI_BATCH_BUFFER_END; + + __i915_gem_object_flush_map(rpcs, 0, 64); +@@ -994,7 +994,8 @@ emit_rpcs_query(struct drm_i915_gem_object *obj, + } + + err = rq->engine->emit_bb_start(rq, +- batch->node.start, batch->node.size, ++ i915_vma_offset(batch), ++ i915_vma_size(batch), + 0); + if (err) + goto skip_request; +@@ -1563,7 +1564,10 @@ static int write_to_scratch(struct i915_gem_context *ctx, + goto skip_request; + } + +- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0); ++ err = engine->emit_bb_start(rq, ++ i915_vma_offset(vma), ++ i915_vma_size(vma), ++ 0); + if (err) + goto skip_request; + +@@ -1670,7 +1674,7 @@ static int read_from_scratch(struct i915_gem_context *ctx, + *cmd++ = offset; + *cmd++ = MI_STORE_REGISTER_MEM | MI_USE_GGTT; + *cmd++ = reg; +- *cmd++ = vma->node.start + result; ++ *cmd++ = i915_vma_offset(vma) + result; + *cmd = MI_BATCH_BUFFER_END; + + i915_gem_object_flush_map(obj); +@@ -1701,7 +1705,10 @@ static int read_from_scratch(struct i915_gem_context *ctx, + goto skip_request; + } + +- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, flags); ++ err = engine->emit_bb_start(rq, ++ i915_vma_offset(vma), ++ i915_vma_size(vma), ++ flags); + if (err) + goto skip_request; + +diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +index 3a30955285d6..390d903c3608 100644 +--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c ++++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +@@ -1180,7 +1180,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915, + if (err == 0) + err = i915_vma_move_to_active(vma, rq, 0); + +- err = engine->emit_bb_start(rq, vma->node.start, 0, 0); ++ err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0); + i915_request_get(rq); + i915_request_add(rq); + +diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c +index b35c1219c852..548c5d6cd19d 100644 +--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c ++++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c +@@ -61,8 +61,8 @@ igt_emit_store_dw(struct i915_vma *vma, + goto err; + } + +- GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size); +- offset += vma->node.start; ++ GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > i915_vma_size(vma)); ++ offset += i915_vma_offset(vma); + + for (n = 0; n < count; n++) { + if (ver >= 8) { +@@ -150,7 +150,8 @@ int igt_gpu_fill_dw(struct intel_context *ce, + flags |= I915_DISPATCH_SECURE; + + err = rq->engine->emit_bb_start(rq, +- batch->node.start, batch->node.size, ++ i915_vma_offset(batch), ++ i915_vma_size(batch), + flags); + + skip_request: +diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +index 1aee5e6b1b23..d7bbd961765f 100644 +--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c ++++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +@@ -110,7 +110,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, + { + struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); + struct i915_page_directory * const pd = ppgtt->pd; +- unsigned int first_entry = vma->node.start / I915_GTT_PAGE_SIZE; ++ unsigned int first_entry = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE; + unsigned int act_pt = first_entry / GEN6_PTES; + unsigned int act_pte = first_entry % GEN6_PTES; + const u32 pte_encode = vm->pte_encode(0, cache_level, flags); +diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c +index 21f08e53889c..a14f962aaa85 100644 +--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c ++++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c +@@ -105,7 +105,7 @@ static u32 batch_offset(const struct batch_chunk *bc, u32 *cs) + + static u32 batch_addr(const struct batch_chunk *bc) + { +- return bc->vma->node.start; ++ return i915_vma_offset(bc->vma); + } + + static void batch_add(struct batch_chunk *bc, const u32 d) +diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +index 21c8b7350b7a..9b7d917a5469 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c ++++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +@@ -416,7 +416,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, + { + const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags); + unsigned int rem = sg_dma_len(iter->sg); +- u64 start = vma->node.start; ++ u64 start = i915_vma_offset(vma); + + GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm)); + +@@ -498,8 +498,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, + if (maybe_64K != -1 && + (index == I915_PDES || + (i915_vm_has_scratch_64K(vma->vm) && +- !iter->sg && IS_ALIGNED(vma->node.start + +- vma->node.size, ++ !iter->sg && IS_ALIGNED(i915_vma_offset(vma) + ++ i915_vma_size(vma), + I915_GTT_PAGE_SIZE_2M)))) { + vaddr = px_vaddr(pd); + vaddr[maybe_64K] |= GEN8_PDE_IPS_64K; +@@ -541,7 +541,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm, + if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) { + gen8_ppgtt_insert_huge(vma, &iter, cache_level, flags); + } else { +- u64 idx = vma->node.start >> GEN8_PTE_SHIFT; ++ u64 idx = i915_vma_offset(vma) >> GEN8_PTE_SHIFT; + + do { + struct i915_page_directory * const pdp = +diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c +index 20e46b843324..d887d9aed82a 100644 +--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c ++++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c +@@ -441,7 +441,8 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm, + unsigned int flags = (cache_level == I915_CACHE_NONE) ? + AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; + +- intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT, ++ intel_gtt_insert_sg_entries(vma->pages, ++ i915_ggtt_offset(vma) >> PAGE_SHIFT, + flags); + } + +@@ -632,7 +633,7 @@ static void aliasing_gtt_unbind_vma(struct i915_address_space *vm, + struct i915_vma *vma) + { + if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) +- vm->clear_range(vm, vma->node.start, vma->size); ++ vm->clear_range(vm, i915_ggtt_offset(vma), vma->size); + + if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND)) + ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma); +diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +index cac7f3f44642..5bc51e09ce67 100644 +--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c ++++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +@@ -215,7 +215,8 @@ static int fence_update(struct i915_fence_reg *fence, + return ret; + } + +- fence->start = vma->node.start; ++ GEM_BUG_ON(vma->fence_size > i915_vma_size(vma)); ++ fence->start = i915_ggtt_offset(vma); + fence->size = vma->fence_size; + fence->stride = i915_gem_object_get_stride(vma->obj); + fence->tiling = i915_gem_object_get_tiling(vma->obj); +diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c +index 886060f7e6fc..27c4721ee49e 100644 +--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c ++++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c +@@ -185,7 +185,10 @@ void ppgtt_bind_vma(struct i915_address_space *vm, + u32 pte_flags; + + if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) { +- vm->allocate_va_range(vm, stash, vma->node.start, vma->size); ++ GEM_BUG_ON(vma->size > i915_vma_size(vma)); ++ vm->allocate_va_range(vm, stash, ++ i915_vma_offset(vma), ++ vma->size); + set_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma)); + } + +@@ -203,7 +206,7 @@ void ppgtt_bind_vma(struct i915_address_space *vm, + void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma) + { + if (test_and_clear_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) +- vm->clear_range(vm, vma->node.start, vma->size); ++ vm->clear_range(vm, i915_vma_offset(vma), vma->size); + } + + static unsigned long pd_count(u64 size, int shift) +diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c +index b575cd6e0b7a..2630fe6c8142 100644 +--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c ++++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c +@@ -61,7 +61,7 @@ static int render_state_setup(struct intel_renderstate *so, + u32 s = rodata->batch[i]; + + if (i * 4 == rodata->reloc[reloc_index]) { +- u64 r = s + so->vma->node.start; ++ u64 r = s + i915_vma_offset(so->vma); + + s = lower_32_bits(r); + if (HAS_64BIT_RELOC(i915)) { +diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c +index 0c423f096e2b..1d86b7c99dc2 100644 +--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c ++++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c +@@ -844,7 +844,7 @@ static int clear_residuals(struct i915_request *rq) + } + + ret = engine->emit_bb_start(rq, +- engine->wa_ctx.vma->node.start, 0, ++ i915_vma_offset(engine->wa_ctx.vma), 0, + 0); + if (ret) + return ret; +diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c +index 64abf5feabfa..17ab003f905e 100644 +--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c +@@ -165,8 +165,8 @@ static int perf_mi_bb_start(void *arg) + goto out; + + err = rq->engine->emit_bb_start(rq, +- batch->node.start, 8, +- 0); ++ i915_vma_offset(batch), ++ 8, 0); + if (err) + goto out; + +@@ -305,8 +305,8 @@ static int perf_mi_noop(void *arg) + goto out; + + err = rq->engine->emit_bb_start(rq, +- base->node.start, 8, +- 0); ++ i915_vma_offset(base), ++ 8, 0); + if (err) + goto out; + +@@ -315,8 +315,8 @@ static int perf_mi_noop(void *arg) + goto out; + + err = rq->engine->emit_bb_start(rq, +- nop->node.start, +- nop->node.size, ++ i915_vma_offset(nop), ++ i915_vma_size(nop), + 0); + if (err) + goto out; +diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c +index ea2203af0764..ba09e678e4d1 100644 +--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c ++++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c +@@ -2715,11 +2715,11 @@ static int create_gang(struct intel_engine_cs *engine, + MI_SEMAPHORE_POLL | + MI_SEMAPHORE_SAD_EQ_SDD; + *cs++ = 0; +- *cs++ = lower_32_bits(vma->node.start); +- *cs++ = upper_32_bits(vma->node.start); ++ *cs++ = lower_32_bits(i915_vma_offset(vma)); ++ *cs++ = upper_32_bits(i915_vma_offset(vma)); + + if (*prev) { +- u64 offset = (*prev)->batch->node.start; ++ u64 offset = i915_vma_offset((*prev)->batch); + + /* Terminate the spinner in the next lower priority batch. */ + *cs++ = MI_STORE_DWORD_IMM_GEN4; +@@ -2747,7 +2747,7 @@ static int create_gang(struct intel_engine_cs *engine, + err = i915_vma_move_to_active(vma, rq, 0); + if (!err) + err = rq->engine->emit_bb_start(rq, +- vma->node.start, ++ i915_vma_offset(vma), + PAGE_SIZE, 0); + i915_vma_unlock(vma); + i915_request_add(rq); +@@ -3075,7 +3075,7 @@ create_gpr_user(struct intel_engine_cs *engine, + *cs++ = MI_MATH_ADD; + *cs++ = MI_MATH_STORE(MI_MATH_REG(i), MI_MATH_REG_ACCU); + +- addr = result->node.start + offset + i * sizeof(*cs); ++ addr = i915_vma_offset(result) + offset + i * sizeof(*cs); + *cs++ = MI_STORE_REGISTER_MEM_GEN8; + *cs++ = CS_GPR(engine, 2 * i); + *cs++ = lower_32_bits(addr); +@@ -3085,8 +3085,8 @@ create_gpr_user(struct intel_engine_cs *engine, + MI_SEMAPHORE_POLL | + MI_SEMAPHORE_SAD_GTE_SDD; + *cs++ = i; +- *cs++ = lower_32_bits(result->node.start); +- *cs++ = upper_32_bits(result->node.start); ++ *cs++ = lower_32_bits(i915_vma_offset(result)); ++ *cs++ = upper_32_bits(i915_vma_offset(result)); + } + + *cs++ = MI_BATCH_BUFFER_END; +@@ -3170,7 +3170,7 @@ create_gpr_client(struct intel_engine_cs *engine, + err = i915_vma_move_to_active(batch, rq, 0); + if (!err) + err = rq->engine->emit_bb_start(rq, +- batch->node.start, ++ i915_vma_offset(batch), + PAGE_SIZE, 0); + i915_vma_unlock(batch); + i915_vma_unpin(batch); +@@ -3502,7 +3502,7 @@ static int smoke_submit(struct preempt_smoke *smoke, + err = i915_vma_move_to_active(vma, rq, 0); + if (!err) + err = rq->engine->emit_bb_start(rq, +- vma->node.start, ++ i915_vma_offset(vma), + PAGE_SIZE, 0); + i915_vma_unlock(vma); + } +diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +index 853246fad05f..fab2c5d27766 100644 +--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c ++++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +@@ -92,7 +92,8 @@ static int hang_init(struct hang *h, struct intel_gt *gt) + static u64 hws_address(const struct i915_vma *hws, + const struct i915_request *rq) + { +- return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context); ++ return (i915_vma_offset(hws) + ++ offset_in_page(sizeof(u32) * rq->fence.context)); + } + + static int move_to_active(struct i915_vma *vma, +@@ -192,8 +193,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) + + *batch++ = MI_NOOP; + *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; +- *batch++ = lower_32_bits(vma->node.start); +- *batch++ = upper_32_bits(vma->node.start); ++ *batch++ = lower_32_bits(i915_vma_offset(vma)); ++ *batch++ = upper_32_bits(i915_vma_offset(vma)); + } else if (GRAPHICS_VER(gt->i915) >= 6) { + *batch++ = MI_STORE_DWORD_IMM_GEN4; + *batch++ = 0; +@@ -206,7 +207,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) + + *batch++ = MI_NOOP; + *batch++ = MI_BATCH_BUFFER_START | 1 << 8; +- *batch++ = lower_32_bits(vma->node.start); ++ *batch++ = lower_32_bits(i915_vma_offset(vma)); + } else if (GRAPHICS_VER(gt->i915) >= 4) { + *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; + *batch++ = 0; +@@ -219,7 +220,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) + + *batch++ = MI_NOOP; + *batch++ = MI_BATCH_BUFFER_START | 2 << 6; +- *batch++ = lower_32_bits(vma->node.start); ++ *batch++ = lower_32_bits(i915_vma_offset(vma)); + } else { + *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; + *batch++ = lower_32_bits(hws_address(hws, rq)); +@@ -231,7 +232,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) + + *batch++ = MI_NOOP; + *batch++ = MI_BATCH_BUFFER_START | 2 << 6; +- *batch++ = lower_32_bits(vma->node.start); ++ *batch++ = lower_32_bits(i915_vma_offset(vma)); + } + *batch++ = MI_BATCH_BUFFER_END; /* not reached */ + intel_gt_chipset_flush(engine->gt); +@@ -246,7 +247,9 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) + if (GRAPHICS_VER(gt->i915) <= 5) + flags |= I915_DISPATCH_SECURE; + +- err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags); ++ err = rq->engine->emit_bb_start(rq, ++ i915_vma_offset(vma), ++ PAGE_SIZE, flags); + + cancel_rq: + if (err) { +diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c +index 3119016d9910..4621d05a1d9c 100644 +--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c ++++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c +@@ -955,8 +955,8 @@ store_context(struct intel_context *ce, struct i915_vma *scratch) + while (len--) { + *cs++ = MI_STORE_REGISTER_MEM_GEN8; + *cs++ = hw[dw]; +- *cs++ = lower_32_bits(scratch->node.start + x); +- *cs++ = upper_32_bits(scratch->node.start + x); ++ *cs++ = lower_32_bits(i915_vma_offset(scratch) + x); ++ *cs++ = upper_32_bits(i915_vma_offset(scratch) + x); + + dw += 2; + x += 4; +@@ -1038,8 +1038,8 @@ record_registers(struct intel_context *ce, + + *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; + *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8); +- *cs++ = lower_32_bits(b_before->node.start); +- *cs++ = upper_32_bits(b_before->node.start); ++ *cs++ = lower_32_bits(i915_vma_offset(b_before)); ++ *cs++ = upper_32_bits(i915_vma_offset(b_before)); + + *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; + *cs++ = MI_SEMAPHORE_WAIT | +@@ -1054,8 +1054,8 @@ record_registers(struct intel_context *ce, + + *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; + *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8); +- *cs++ = lower_32_bits(b_after->node.start); +- *cs++ = upper_32_bits(b_after->node.start); ++ *cs++ = lower_32_bits(i915_vma_offset(b_after)); ++ *cs++ = upper_32_bits(i915_vma_offset(b_after)); + + intel_ring_advance(rq, cs); + +@@ -1163,8 +1163,8 @@ static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema) + + *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; + *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8); +- *cs++ = lower_32_bits(batch->node.start); +- *cs++ = upper_32_bits(batch->node.start); ++ *cs++ = lower_32_bits(i915_vma_offset(batch)); ++ *cs++ = upper_32_bits(i915_vma_offset(batch)); + + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; + *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + +diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c +index 041954408d0f..8d29f6b979bd 100644 +--- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c ++++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c +@@ -50,7 +50,7 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine) + } else { + *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; + } +- *cs++ = vma->node.start + 4000; ++ *cs++ = i915_vma_offset(vma) + 4000; + *cs++ = STACK_MAGIC; + + *cs++ = MI_BATCH_BUFFER_END; +diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c +index 7ee2513e15f9..d242ed23e609 100644 +--- a/drivers/gpu/drm/i915/gt/selftest_rps.c ++++ b/drivers/gpu/drm/i915/gt/selftest_rps.c +@@ -119,14 +119,14 @@ create_spin_counter(struct intel_engine_cs *engine, + if (srm) { + *cs++ = MI_STORE_REGISTER_MEM_GEN8; + *cs++ = i915_mmio_reg_offset(CS_GPR(COUNT)); +- *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs)); +- *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs)); ++ *cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs)); ++ *cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs)); + } + } + + *cs++ = MI_BATCH_BUFFER_START_GEN8; +- *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs)); +- *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs)); ++ *cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs)); ++ *cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs)); + GEM_BUG_ON(cs - base > end); + + i915_gem_object_flush_map(obj); +@@ -655,7 +655,7 @@ int live_rps_frequency_cs(void *arg) + err = i915_vma_move_to_active(vma, rq, 0); + if (!err) + err = rq->engine->emit_bb_start(rq, +- vma->node.start, ++ i915_vma_offset(vma), + PAGE_SIZE, 0); + i915_request_add(rq); + if (err) +@@ -796,7 +796,7 @@ int live_rps_frequency_srm(void *arg) + err = i915_vma_move_to_active(vma, rq, 0); + if (!err) + err = rq->engine->emit_bb_start(rq, +- vma->node.start, ++ i915_vma_offset(vma), + PAGE_SIZE, 0); + i915_request_add(rq); + if (err) +diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c +index c30754daf4b1..f4a098509a7a 100644 +--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c ++++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c +@@ -502,8 +502,8 @@ static int check_dirty_whitelist(struct intel_context *ce) + + for (i = 0; i < engine->whitelist.count; i++) { + u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); ++ u64 addr = i915_vma_offset(scratch); + struct i915_gem_ww_ctx ww; +- u64 addr = scratch->node.start; + struct i915_request *rq; + u32 srm, lrm, rsvd; + u32 expect; +@@ -626,7 +626,8 @@ static int check_dirty_whitelist(struct intel_context *ce) + goto err_request; + + err = engine->emit_bb_start(rq, +- batch->node.start, PAGE_SIZE, ++ i915_vma_offset(batch), ++ PAGE_SIZE, + 0); + if (err) + goto err_request; +@@ -839,7 +840,7 @@ static int read_whitelisted_registers(struct intel_context *ce, + } + + for (i = 0; i < engine->whitelist.count; i++) { +- u64 offset = results->node.start + sizeof(u32) * i; ++ u64 offset = i915_vma_offset(results) + sizeof(u32) * i; + u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); + + /* Clear non priv flags */ +@@ -913,7 +914,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce) + goto err_request; + + /* Perform the writes from an unprivileged "user" batch */ +- err = engine->emit_bb_start(rq, batch->node.start, 0, 0); ++ err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0); + + err_request: + err = request_add_sync(rq, err); +diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c +index 3992c25a191d..b2c2595a41b6 100644 +--- a/drivers/gpu/drm/i915/i915_cmd_parser.c ++++ b/drivers/gpu/drm/i915/i915_cmd_parser.c +@@ -1450,8 +1450,8 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, + cmd = copy_batch(shadow->obj, batch->obj, batch_offset, batch_length, + shadow_map, batch_map); + +- shadow_addr = gen8_canonical_addr(shadow->node.start); +- batch_addr = gen8_canonical_addr(batch->node.start + batch_offset); ++ shadow_addr = gen8_canonical_addr(i915_vma_offset(shadow)); ++ batch_addr = gen8_canonical_addr(i915_vma_offset(batch) + batch_offset); + + /* + * We use the batch length as size because the shadow object is as +diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c +index cc745751ac53..5da624f6fbff 100644 +--- a/drivers/gpu/drm/i915/i915_debugfs.c ++++ b/drivers/gpu/drm/i915/i915_debugfs.c +@@ -169,7 +169,8 @@ i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) + + seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", + stringify_vma_type(vma), +- vma->node.start, vma->node.size, ++ i915_vma_offset(vma), ++ i915_vma_size(vma), + stringify_page_sizes(vma->page_sizes.gtt, NULL, 0)); + if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { + switch (vma->ggtt_view.type) { +diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c +index 35c97c39f125..02653ce3a064 100644 +--- a/drivers/gpu/drm/i915/i915_gpu_error.c ++++ b/drivers/gpu/drm/i915/i915_gpu_error.c +@@ -1009,8 +1009,8 @@ i915_vma_coredump_create(const struct intel_gt *gt, + strcpy(dst->name, name); + dst->next = NULL; + +- dst->gtt_offset = vma->node.start; +- dst->gtt_size = vma->node.size; ++ dst->gtt_offset = i915_vma_offset(vma); ++ dst->gtt_size = i915_vma_size(vma); + dst->gtt_page_sizes = vma->page_sizes.gtt; + dst->num_pages = num_pages; + dst->page_count = 0; +diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c +index 9f94914958c3..787e6fbfcf32 100644 +--- a/drivers/gpu/drm/i915/i915_perf.c ++++ b/drivers/gpu/drm/i915/i915_perf.c +@@ -2007,7 +2007,7 @@ emit_oa_config(struct i915_perf_stream *stream, + goto err_add_request; + + err = rq->engine->emit_bb_start(rq, +- vma->node.start, 0, ++ i915_vma_offset(vma), 0, + I915_DISPATCH_SECURE); + if (err) + goto err_add_request; +diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c +index 0f227f28b280..05a4fc08d52c 100644 +--- a/drivers/gpu/drm/i915/i915_vma.c ++++ b/drivers/gpu/drm/i915/i915_vma.c +@@ -382,7 +382,7 @@ int i915_vma_bind(struct i915_vma *vma, + u32 vma_flags; + + GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); +- GEM_BUG_ON(vma->size > vma->node.size); ++ GEM_BUG_ON(vma->size > i915_vma_size(vma)); + + if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start, + vma->node.size, +@@ -471,8 +471,8 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma) + vma->obj->base.size); + else + ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap, +- vma->node.start, +- vma->node.size); ++ i915_vma_offset(vma), ++ i915_vma_size(vma)); + if (ptr == NULL) { + err = -ENOMEM; + goto err; +@@ -546,22 +546,22 @@ bool i915_vma_misplaced(const struct i915_vma *vma, + if (test_bit(I915_VMA_ERROR_BIT, __i915_vma_flags(vma))) + return true; + +- if (vma->node.size < size) ++ if (i915_vma_size(vma) < size) + return true; + + GEM_BUG_ON(alignment && !is_power_of_2(alignment)); +- if (alignment && !IS_ALIGNED(vma->node.start, alignment)) ++ if (alignment && !IS_ALIGNED(i915_vma_offset(vma), alignment)) + return true; + + if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma)) + return true; + + if (flags & PIN_OFFSET_BIAS && +- vma->node.start < (flags & PIN_OFFSET_MASK)) ++ i915_vma_offset(vma) < (flags & PIN_OFFSET_MASK)) + return true; + + if (flags & PIN_OFFSET_FIXED && +- vma->node.start != (flags & PIN_OFFSET_MASK)) ++ i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK)) + return true; + + return false; +@@ -574,10 +574,11 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) + GEM_BUG_ON(!i915_vma_is_ggtt(vma)); + GEM_BUG_ON(!vma->fence_size); + +- fenceable = (vma->node.size >= vma->fence_size && +- IS_ALIGNED(vma->node.start, vma->fence_alignment)); ++ fenceable = (i915_vma_size(vma) >= vma->fence_size && ++ IS_ALIGNED(i915_vma_offset(vma), vma->fence_alignment)); + +- mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end; ++ mappable = (i915_ggtt_offset(vma) + vma->fence_size <= ++ i915_vm_to_ggtt(vma->vm)->mappable_end); + + if (mappable && fenceable) + set_bit(I915_VMA_CAN_FENCE_BIT, __i915_vma_flags(vma)); +diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h +index eca452a9851f..7c7fe65ceb0a 100644 +--- a/drivers/gpu/drm/i915/i915_vma.h ++++ b/drivers/gpu/drm/i915/i915_vma.h +@@ -118,13 +118,30 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma) + return !list_empty(&vma->closed_link); + } + ++static inline u64 i915_vma_size(const struct i915_vma *vma) ++{ ++ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); ++ return vma->node.size; ++} ++ ++static inline u64 __i915_vma_offset(const struct i915_vma *vma) ++{ ++ return vma->node.start; ++} ++ ++static inline u64 i915_vma_offset(const struct i915_vma *vma) ++{ ++ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); ++ return __i915_vma_offset(vma); ++} ++ + static inline u32 i915_ggtt_offset(const struct i915_vma *vma) + { + GEM_BUG_ON(!i915_vma_is_ggtt(vma)); + GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); +- GEM_BUG_ON(upper_32_bits(vma->node.start)); +- GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1)); +- return lower_32_bits(vma->node.start); ++ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma))); ++ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) + i915_vma_size(vma) - 1)); ++ return lower_32_bits(i915_vma_offset(vma)); + } + + static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma) +diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +index fccb03ab3e53..7106399c4d08 100644 +--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c ++++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +@@ -245,6 +245,10 @@ static int lowlevel_hole(struct i915_address_space *vm, + if (!mock_vma) + return -ENOMEM; + ++ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &mock_vma->node.flags); ++ if (i915_is_ggtt(vm)) ++ __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(mock_vma)); ++ + /* Keep creating larger objects until one cannot fit into the hole */ + for (size = 12; (hole_end - hole_start) >> size; size++) { + I915_RND_SUBSTATE(prng, seed_prng); +@@ -1981,6 +1985,7 @@ static int igt_cs_tlb(void *arg) + goto end; + + /* Prime the TLB with the dummy pages */ ++ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags); + for (i = 0; i < count; i++) { + vma->node.start = offset + i * PAGE_SIZE; + vm->insert_entries(vm, vma, I915_CACHE_NONE, 0); +@@ -1992,8 +1997,9 @@ static int igt_cs_tlb(void *arg) + } + i915_request_put(rq); + } +- + vma->ops->clear_pages(vma); ++ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT, ++ &vma->node.flags); + + err = context_sync(ce); + if (err) { +@@ -2013,6 +2019,7 @@ static int igt_cs_tlb(void *arg) + goto end; + + /* Replace the TLB with target batches */ ++ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags); + for (i = 0; i < count; i++) { + struct i915_request *rq; + u32 *cs = batch + i * 64 / sizeof(*cs); +@@ -2045,8 +2052,9 @@ static int igt_cs_tlb(void *arg) + i915_request_put(rq); + } + end_spin(batch, count - 1); +- + vma->ops->clear_pages(vma); ++ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT, ++ &vma->node.flags); + + err = context_sync(ce); + if (err) { +diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c +index bd5c96a77ba3..0cf5aebcf3ae 100644 +--- a/drivers/gpu/drm/i915/selftests/i915_request.c ++++ b/drivers/gpu/drm/i915/selftests/i915_request.c +@@ -869,8 +869,8 @@ empty_request(struct intel_engine_cs *engine, + return request; + + err = engine->emit_bb_start(request, +- batch->node.start, +- batch->node.size, ++ i915_vma_offset(batch), ++ i915_vma_size(batch), + I915_DISPATCH_SECURE); + if (err) + goto out_request; +@@ -990,14 +990,14 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915) + + if (ver >= 8) { + *cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; +- *cmd++ = lower_32_bits(vma->node.start); +- *cmd++ = upper_32_bits(vma->node.start); ++ *cmd++ = lower_32_bits(i915_vma_offset(vma)); ++ *cmd++ = upper_32_bits(i915_vma_offset(vma)); + } else if (ver >= 6) { + *cmd++ = MI_BATCH_BUFFER_START | 1 << 8; +- *cmd++ = lower_32_bits(vma->node.start); ++ *cmd++ = lower_32_bits(i915_vma_offset(vma)); + } else { + *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; +- *cmd++ = lower_32_bits(vma->node.start); ++ *cmd++ = lower_32_bits(i915_vma_offset(vma)); + } + *cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */ + +@@ -1081,8 +1081,8 @@ static int live_all_engines(void *arg) + GEM_BUG_ON(err); + + err = engine->emit_bb_start(request[idx], +- batch->node.start, +- batch->node.size, ++ i915_vma_offset(batch), ++ i915_vma_size(batch), + 0); + GEM_BUG_ON(err); + request[idx]->batch = batch; +@@ -1211,8 +1211,8 @@ static int live_sequential_engines(void *arg) + GEM_BUG_ON(err); + + err = engine->emit_bb_start(request[idx], +- batch->node.start, +- batch->node.size, ++ i915_vma_offset(batch), ++ i915_vma_size(batch), + 0); + GEM_BUG_ON(err); + request[idx]->batch = batch; +diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c +index 24d87d0fc747..6bf0b189d69a 100644 +--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c ++++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c +@@ -115,7 +115,7 @@ static unsigned int seqno_offset(u64 fence) + static u64 hws_address(const struct i915_vma *hws, + const struct i915_request *rq) + { +- return hws->node.start + seqno_offset(rq->fence.context); ++ return i915_vma_offset(hws) + seqno_offset(rq->fence.context); + } + + static int move_to_active(struct i915_vma *vma, +@@ -202,8 +202,8 @@ igt_spinner_create_request(struct igt_spinner *spin, + *batch++ = MI_BATCH_BUFFER_START; + else + *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; +- *batch++ = lower_32_bits(vma->node.start); +- *batch++ = upper_32_bits(vma->node.start); ++ *batch++ = lower_32_bits(i915_vma_offset(vma)); ++ *batch++ = upper_32_bits(i915_vma_offset(vma)); + + *batch++ = MI_BATCH_BUFFER_END; /* not reached */ + +@@ -218,7 +218,10 @@ igt_spinner_create_request(struct igt_spinner *spin, + flags = 0; + if (GRAPHICS_VER(rq->engine->i915) <= 5) + flags |= I915_DISPATCH_SECURE; +- err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags); ++ err = engine->emit_bb_start(rq, ++ i915_vma_offset(vma), ++ PAGE_SIZE, ++ flags); + + cancel_rq: + if (err) { +-- +2.31.0 + diff --git a/bsp_diff/common/kernel/lts2020-yocto/18_0018-drm-i915-Introduce-guard-pages-to-i915_vma.patch b/bsp_diff/common/kernel/lts2020-yocto/18_0018-drm-i915-Introduce-guard-pages-to-i915_vma.patch new file mode 100644 index 0000000000..fc5abadc0c --- /dev/null +++ b/bsp_diff/common/kernel/lts2020-yocto/18_0018-drm-i915-Introduce-guard-pages-to-i915_vma.patch @@ -0,0 +1,212 @@ +From e57f4cbd9990c53b470a0f731dd156290ed6ffc3 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Thu, 11 Feb 2021 16:42:59 +0000 +Subject: [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma + +Introduce the concept of padding the i915_vma with guard pages before +and aft. The major consequence is that all ordinary uses of i915_vma +must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size +directly, as the drm_mm_node will include the guard pages that surround +our object. + +The biggest connundrum is how exactly to mix requesting a fixed address +with guard pages, particularly through the existing uABI. The user does +not know about guard pages, so such must be transparent to the user, and +so the execobj.offset must be that of the object itself excluding the +guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages. +The caveat is that some placements will be impossible with guard pages, +as wrap arounds need to be avoided, and the vma itself will require a +larger node. We must we not report EINVAL but ENOSPC as these are +unavailable locations within the GTT rather than conflicting user +requirements. + +In the next patch, we start using guard pages for scanout objects. While +these are limited to GGTT vma, on a few platforms these vma (or at least +an alias of the vma) is shared with userspace, so we may leak the +existence of such guards if we are not careful to ensure that the +execobj.offset is transparent and excludes the guards. (On such platforms +like ivb, without full-ppgtt, userspace has to use relocations so the +presence of more untouchable regions within its GTT such be of no further +issue.) + +v2: Include the guard range in the overflow checks and placement +restrictions. + +v3: Fix the check on the placement upper bound. The request user offset +is relative to the guard offset (not the node.start) and so we should +not include the initial guard offset again when computing the upper +bound of the node. + +Signed-off-by: Chris Wilson +Cc: Matthew Auld +Reviewed-by: Matthew Auld +--- + drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++++++++++-- + drivers/gpu/drm/i915/i915_vma.c | 28 ++++++++++++++++++++++----- + drivers/gpu/drm/i915/i915_vma.h | 5 +++-- + drivers/gpu/drm/i915/i915_vma_types.h | 3 ++- + 4 files changed, 38 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c +index d887d9aed82a..c054348010ce 100644 +--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c ++++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c +@@ -239,8 +239,12 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, + + gte = (gen8_pte_t __iomem *)ggtt->gsm; + gte += vma->node.start / I915_GTT_PAGE_SIZE; +- end = gte + vma->node.size / I915_GTT_PAGE_SIZE; + ++ end = gte + vma->guard / I915_GTT_PAGE_SIZE; ++ while (gte < end) ++ gen8_set_pte(gte++, vm->scratch[0]->encode); ++ ++ end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE; + for_each_sgt_daddr(addr, iter, vma->pages) + gen8_set_pte(gte++, pte_encode | addr); + GEM_BUG_ON(gte > end); +@@ -290,8 +294,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, + + gte = (gen6_pte_t __iomem *)ggtt->gsm; + gte += vma->node.start / I915_GTT_PAGE_SIZE; +- end = gte + vma->node.size / I915_GTT_PAGE_SIZE; + ++ end = gte + vma->guard / I915_GTT_PAGE_SIZE; ++ while (gte < end) ++ gen8_set_pte(gte++, vm->scratch[0]->encode); ++ ++ end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE; + for_each_sgt_daddr(addr, iter, vma->pages) + iowrite32(vm->pte_encode(addr, level, flags), gte++); + GEM_BUG_ON(gte > end); +diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c +index 05a4fc08d52c..fe89ee2764f8 100644 +--- a/drivers/gpu/drm/i915/i915_vma.c ++++ b/drivers/gpu/drm/i915/i915_vma.c +@@ -635,7 +635,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color) + static int + i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) + { +- unsigned long color; ++ unsigned long color, guard; + u64 start, end; + int ret; + +@@ -643,7 +643,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) + GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); + + size = max(size, vma->size); +- alignment = max(alignment, vma->display_alignment); ++ alignment = max_t(typeof(alignment), alignment, vma->display_alignment); + if (flags & PIN_MAPPABLE) { + size = max_t(typeof(size), size, vma->fence_size); + alignment = max_t(typeof(alignment), +@@ -654,6 +654,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) + GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT)); + GEM_BUG_ON(!is_power_of_2(alignment)); + ++ guard = vma->guard; /* retain guard across rebinds */ ++ guard = ALIGN(guard, alignment); ++ + start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; + GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); + +@@ -663,12 +666,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) + if (flags & PIN_ZONE_4G) + end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE); + GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); ++ GEM_BUG_ON(2 * guard > end); + + /* If binding the object/GGTT view requires more space than the entire + * aperture has, reject it early before evicting everything in a vain + * attempt to find space. + */ +- if (size > end) { ++ if (size > end - 2 * guard) { + DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu > %s aperture=%llu\n", + size, flags & PIN_MAPPABLE ? "mappable" : "total", + end); +@@ -681,16 +685,29 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) + + if (flags & PIN_OFFSET_FIXED) { + u64 offset = flags & PIN_OFFSET_MASK; ++ + if (!IS_ALIGNED(offset, alignment) || + range_overflows(offset, size, end)) + return -EINVAL; + ++ /* ++ * The caller knows not of the guard added by others and ++ * requests for the offset of the start of its buffer ++ * to be fixed, which may not be the same as the position ++ * of the vma->node due to the guard pages. ++ */ ++ if (offset < guard || offset + size > end - guard) ++ return -ENOSPC; ++ + ret = i915_gem_gtt_reserve(vma->vm, &vma->node, +- size, offset, color, +- flags); ++ size + 2 * guard, ++ offset - guard, ++ color, flags); + if (ret) + return ret; + } else { ++ size += 2 * guard; ++ + /* + * We only support huge gtt pages through the 48b PPGTT, + * however we also don't want to force any alignment for +@@ -737,6 +754,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) + GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, color)); + + list_add_tail(&vma->vm_link, &vma->vm->bound_list); ++ vma->guard = guard; + + return 0; + } +diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h +index 7c7fe65ceb0a..f650ffdff847 100644 +--- a/drivers/gpu/drm/i915/i915_vma.h ++++ b/drivers/gpu/drm/i915/i915_vma.h +@@ -121,12 +121,13 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma) + static inline u64 i915_vma_size(const struct i915_vma *vma) + { + GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); +- return vma->node.size; ++ return vma->node.size - 2 * vma->guard; + } + + static inline u64 __i915_vma_offset(const struct i915_vma *vma) + { +- return vma->node.start; ++ /* The actual start of the vma->pages is after the guard pages. */ ++ return vma->node.start + vma->guard; + } + + static inline u64 i915_vma_offset(const struct i915_vma *vma) +diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h +index 995b502d7e5d..c00df729cc9a 100644 +--- a/drivers/gpu/drm/i915/i915_vma_types.h ++++ b/drivers/gpu/drm/i915/i915_vma_types.h +@@ -186,14 +186,15 @@ struct i915_vma { + struct i915_fence_reg *fence; + + u64 size; +- u64 display_alignment; + struct i915_page_sizes page_sizes; + + /* mmap-offset associated with fencing for this vma */ + struct i915_mmap_offset *mmo; + ++ u32 guard; /* padding allocated around vma->pages within the node */ + u32 fence_size; + u32 fence_alignment; ++ u32 display_alignment; + + /** + * Count of the number of times this vma has been opened by different +-- +2.31.0 + diff --git a/bsp_diff/common/kernel/lts2020-yocto/19_0019-drm-i915-Refine-VT-d-scanout-workaround.patch b/bsp_diff/common/kernel/lts2020-yocto/19_0019-drm-i915-Refine-VT-d-scanout-workaround.patch new file mode 100644 index 0000000000..8df88ff290 --- /dev/null +++ b/bsp_diff/common/kernel/lts2020-yocto/19_0019-drm-i915-Refine-VT-d-scanout-workaround.patch @@ -0,0 +1,173 @@ +From 1dbb878c52b9cac91951075accb27d44f9860886 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Wed, 10 Feb 2021 23:25:52 +0000 +Subject: [PATCH 3/3] drm/i915: Refine VT-d scanout workaround +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +VT-d may cause overfetch of the scanout PTE, both before and after the +vma (depending on the scanout orientation). bspec recommends that we +provide a tile-row in either directions, and suggests using 168 PTE, +warning that the accesses will wrap around the ends of the GGTT. +Currently, we fill the entire GGTT with scratch pages when using VT-d to +always ensure there are valid entries around every vma, including +scanout. However, writing every PTE is slow as on recent devices we +perform 8MiB of uncached writes, incurring an extra 100ms during resume. + +If instead we focus on only putting guard pages around scanout, we can +avoid touching the whole GGTT. To avoid having to introduce extra nodes +around each scanout vma, we adjust the scanout drm_mm_node to be smaller +than the allocated space, and fixup the extra PTE during dma binding. + +v2: Move the guard from modifying drm_mm_node.start which is still used +by the drm_mm itself, into an adjustment of node.start at the point of +use. + +v3: Pass the requested guard padding from the caller, so we can drop the +VT-d w/a knowledge from the i915_vma allocator. + +v4: Bump minimum padding to 168 PTE and cautiously ensure that a full +tile row around the vma is included with the guard. + +Signed-off-by: Chris Wilson +Cc: Ville Syrjälä +Cc: Matthew Auld +Cc: Imre Deak +Reviewed-by: Matthew Auld +--- + drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++++++++++ + drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +--------------------- + drivers/gpu/drm/i915/i915_gem_gtt.h | 1 + + drivers/gpu/drm/i915/i915_vma.c | 8 +++++++ + 4 files changed, 23 insertions(+), 24 deletions(-) + +diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c +index 073822100da7..fec853c20cbf 100644 +--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c ++++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c +@@ -16,6 +16,8 @@ + #include "i915_gem_lmem.h" + #include "i915_gem_mman.h" + ++#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */ ++ + static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj) + { + return !(obj->cache_level == I915_CACHE_NONE || +@@ -395,6 +397,17 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, + if (ret) + return ERR_PTR(ret); + ++ /* VT-d may overfetch before/after the vma, so pad with scratch */ ++ if (intel_scanout_needs_vtd_wa(i915)) { ++ unsigned int guard = VTD_GUARD; ++ ++ if (i915_gem_object_is_tiled(obj)) ++ guard = max(guard, ++ i915_gem_object_get_tile_row_size(obj)); ++ ++ flags |= PIN_OFFSET_GUARD | guard; ++ } ++ + /* + * As the user may map the buffer once pinned in the display plane + * (e.g. libkms for the bootup splash), we have to ensure that we +diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c +index c054348010ce..6e5999f6adfc 100644 +--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c ++++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c +@@ -320,27 +320,6 @@ static void nop_clear_range(struct i915_address_space *vm, + { + } + +-static void gen8_ggtt_clear_range(struct i915_address_space *vm, +- u64 start, u64 length) +-{ +- struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); +- unsigned int first_entry = start / I915_GTT_PAGE_SIZE; +- unsigned int num_entries = length / I915_GTT_PAGE_SIZE; +- const gen8_pte_t scratch_pte = vm->scratch[0]->encode; +- gen8_pte_t __iomem *gtt_base = +- (gen8_pte_t __iomem *)ggtt->gsm + first_entry; +- const int max_entries = ggtt_total_entries(ggtt) - first_entry; +- int i; +- +- if (WARN(num_entries > max_entries, +- "First entry = %d; Num entries = %d (max=%d)\n", +- first_entry, num_entries, max_entries)) +- num_entries = max_entries; +- +- for (i = 0; i < num_entries; i++) +- gen8_set_pte(>t_base[i], scratch_pte); +-} +- + static void bxt_vtd_ggtt_wa(struct i915_address_space *vm) + { + /* +@@ -924,8 +903,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) + ggtt->vm.cleanup = gen6_gmch_remove; + ggtt->vm.insert_page = gen8_ggtt_insert_page; + ggtt->vm.clear_range = nop_clear_range; +- if (intel_scanout_needs_vtd_wa(i915)) +- ggtt->vm.clear_range = gen8_ggtt_clear_range; + + ggtt->vm.insert_entries = gen8_ggtt_insert_entries; + +@@ -1073,7 +1050,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) + ggtt->vm.alloc_pt_dma = alloc_pt_dma; + + ggtt->vm.clear_range = nop_clear_range; +- if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915)) ++ if (!HAS_FULL_PPGTT(i915)) + ggtt->vm.clear_range = gen6_ggtt_clear_range; + ggtt->vm.insert_page = gen6_ggtt_insert_page; + ggtt->vm.insert_entries = gen6_ggtt_insert_entries; +diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h +index c9b0ee5e1d23..f3ae9afdee15 100644 +--- a/drivers/gpu/drm/i915/i915_gem_gtt.h ++++ b/drivers/gpu/drm/i915/i915_gem_gtt.h +@@ -41,6 +41,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm, + #define PIN_HIGH BIT_ULL(5) + #define PIN_OFFSET_BIAS BIT_ULL(6) + #define PIN_OFFSET_FIXED BIT_ULL(7) ++#define PIN_OFFSET_GUARD BIT_ULL(8) + + #define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */ + #define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */ +diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c +index fe89ee2764f8..0e35062fbbda 100644 +--- a/drivers/gpu/drm/i915/i915_vma.c ++++ b/drivers/gpu/drm/i915/i915_vma.c +@@ -564,6 +564,9 @@ bool i915_vma_misplaced(const struct i915_vma *vma, + i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK)) + return true; + ++ if (flags & PIN_OFFSET_GUARD && vma->guard < (flags & PIN_OFFSET_MASK)) ++ return true; ++ + return false; + } + +@@ -641,6 +644,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) + + GEM_BUG_ON(i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); + GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); ++ GEM_BUG_ON(hweight64(flags & (PIN_OFFSET_GUARD | PIN_OFFSET_FIXED | PIN_OFFSET_BIAS)) > 1); + + size = max(size, vma->size); + alignment = max_t(typeof(alignment), alignment, vma->display_alignment); +@@ -655,6 +659,10 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) + GEM_BUG_ON(!is_power_of_2(alignment)); + + guard = vma->guard; /* retain guard across rebinds */ ++ if (flags & PIN_OFFSET_GUARD) { ++ GEM_BUG_ON(overflows_type(flags & PIN_OFFSET_MASK, u32)); ++ guard = max_t(u32, guard, flags & PIN_OFFSET_MASK); ++ } + guard = ALIGN(guard, alignment); + + start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; +-- +2.31.0 +