From 82971be8a3badc37bf12392be9687554a2953c7f Mon Sep 17 00:00:00 2001
From: Yang Hau <yuanyanghau@gmail.com>
Date: Wed, 21 Feb 2024 23:57:12 +0900
Subject: [PATCH] feat: Add LBU, LHU, LWU

---
 src/memory.rs     |  1 +
 tests/cpu_test.rs | 34 +++++++++++++++++++++++++++++-----
 2 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/src/memory.rs b/src/memory.rs
index 48a78de..20ddd49 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -94,6 +94,7 @@ impl MEMORY {
         self.mem[index] = (value & (std::u8::MAX as u32)) as u8;
         self.mem[index + 1] = ((value >> 8) & (std::u8::MAX as u32)) as u8;
         self.mem[index + 2] = ((value >> 16) & (std::u8::MAX as u32)) as u8;
+        self.mem[index + 3] = ((value >> 24) & (std::u8::MAX as u32)) as u8;
     }
     // fn store64(&mut self, addr: u32, value: u32) {
     //     let index = (addr - MEM_BASE) as usize;
diff --git a/tests/cpu_test.rs b/tests/cpu_test.rs
index 977f76c..6ec78d0 100644
--- a/tests/cpu_test.rs
+++ b/tests/cpu_test.rs
@@ -233,7 +233,7 @@ mod tests {
     fn test_exec_lw() {
         let mut cpu_test = cpu::CPU::new();
         let offset = 3;
-        let val = 11;
+        let val = (-2 as i32) as u32;
         let rd = 5 + MEM_BASE;
         cpu_test.bus.store(rd + offset, 32, val);
         // set x1=5+MEM_BASE
@@ -247,7 +247,7 @@ mod tests {
     fn test_exec_lbu() {
         let mut cpu_test = cpu::CPU::new();
         let offset = 3;
-        let val = 11;
+        let val = (-2 as i32) as u32;
         let rd = 5 + MEM_BASE;
         cpu_test.bus.store(rd + offset, 8, val);
         // set x1=5+MEM_BASE
@@ -255,12 +255,36 @@ mod tests {
         // lbu x31, x1, 3
         let instr: u32 = helper::set_load_type_instruction(offset as i16, 1, LBU as u8, 31);
         cpu::exec_lbu(&mut cpu_test, instr);
-        assert_eq!(cpu_test.xregs.regs[31], val);
+        assert_eq!(cpu_test.xregs.regs[31], val & std::u8::MAX as u32);
     }
     #[test]
-    fn test_exec_lhu() {}
+    fn test_exec_lhu() {
+        let mut cpu_test = cpu::CPU::new();
+        let offset = 3;
+        let val = (-2 as i32) as u32;
+        let rd = 5 + MEM_BASE;
+        cpu_test.bus.store(rd + offset, 16, val);
+        // set x1=5+MEM_BASE
+        helper::set_register_val(&mut cpu_test, 1, rd as i32);
+        // lhu x31, x1, 3
+        let instr: u32 = helper::set_load_type_instruction(offset as i16, 1, LHU as u8, 31);
+        cpu::exec_lhu(&mut cpu_test, instr);
+        assert_eq!(cpu_test.xregs.regs[31], val & std::u16::MAX as u32);
+    }
     #[test]
-    fn test_exec_lwu() {}
+    fn test_exec_lwu() {
+        let mut cpu_test = cpu::CPU::new();
+        let offset = 3;
+        let val = (-2 as i32) as u32;
+        let rd = 5 + MEM_BASE;
+        cpu_test.bus.store(rd + offset, 32, val);
+        // set x1=5+MEM_BASE
+        helper::set_register_val(&mut cpu_test, 1, rd as i32);
+        // lwu x31, x1, 3
+        let instr: u32 = helper::set_load_type_instruction(offset as i16, 1, LWU as u8, 31);
+        cpu::exec_lwu(&mut cpu_test, instr);
+        assert_eq!(cpu_test.xregs.regs[31], val & std::u32::MAX);
+    }
     #[test]
     fn test_exec_sb() {}
     #[test]