diff --git a/src/ppl/README.md b/src/ppl/README.md index 1d6e01de03f..c4137a6fadb 100644 --- a/src/ppl/README.md +++ b/src/ppl/README.md @@ -85,6 +85,13 @@ The `-direction` argument is the pin direction (input, output, inout, or feedthrough). The `-pin_names` argument is a list of names. The `-region` syntax is the same as that of the `-exclude` syntax. +The `-mirrored_pins` argument is a list of pins that sets pairs of pins +that will be symmetrically placed in the vertical or the horizontal edges. +The number of pins in this list must be even. For example, in +`set_io_pin_constraint -mirrored_pins {pin1 pin2 pin3 pin4 pin5 pin6}`, +the pins `pin1` and `pin2` will be placed symmetrically to each other. +Same for `pin3` and `pin4`, and for `pin5` and `pin6`. + Note that if you call `define_pin_shape_pattern` before `set_io_pin_constraint`, the `edge` values are (up, top, bottom, left, right). Where `up` relates to the layer created by diff --git a/src/ppl/include/ppl/IOPlacer.h b/src/ppl/include/ppl/IOPlacer.h index 66c0ded5aa3..516719579e4 100644 --- a/src/ppl/include/ppl/IOPlacer.h +++ b/src/ppl/include/ppl/IOPlacer.h @@ -37,6 +37,7 @@ #include #include +#include #include #include "odb/geom.h" @@ -72,6 +73,7 @@ using utl::Logger; // A list of pins that will be placed together in the die boundary typedef std::set PinList; typedef std::vector PinGroup; +typedef std::unordered_map MirroredPins; enum class Edge { @@ -110,6 +112,7 @@ class IOPlacer int begin, int end); void addTopLayerConstraint(PinList* pins, const odb::Rect& region); + void addMirroredPins(odb::dbBTerm* bterm1, odb::dbBTerm* bterm2); void addHorLayer(odb::dbTechLayer* layer); void addVerLayer(odb::dbTechLayer* layer); void addPinGroup(PinGroup* group); @@ -171,7 +174,8 @@ class IOPlacer std::vector
& sections); int assignGroupToSection(const std::vector& io_group, std::vector
& sections); - std::vector
assignConstrainedPinsToSections(Constraint& constraint); + std::vector
assignConstrainedPinsToSections(Constraint& constraint, + int& mirrored_pins_cnt); std::vector findPinsForConstraint(const Constraint& constraint, Netlist* netlist); int computeIONetsHPWL(Netlist* netlist); @@ -215,6 +219,7 @@ class IOPlacer std::vector excluded_intervals_; std::vector constraints_; std::vector pin_groups_; + MirroredPins mirrored_pins_; Logger* logger_; std::unique_ptr parms_; diff --git a/src/ppl/src/Core.cpp b/src/ppl/src/Core.cpp index da64905352b..d8d464e7b16 100644 --- a/src/ppl/src/Core.cpp +++ b/src/ppl/src/Core.cpp @@ -52,4 +52,25 @@ int Core::getPerimeter() const return (x + y) * 2; } +odb::Point Core::getMirroredPosition(const odb::Point& position) const +{ + odb::Point mirrored_pos = position; + const int x_min = boundary_.xMin(); + const int x_max = boundary_.xMax(); + const int y_min = boundary_.yMin(); + const int y_max = boundary_.yMax(); + + if (position.x() == x_min) { + mirrored_pos.setX(x_max); + } else if (position.x() == x_max) { + mirrored_pos.setX(x_min); + } else if (position.y() == y_min) { + mirrored_pos.setY(y_max); + } else { + mirrored_pos.setY(y_min); + } + + return mirrored_pos; +} + } // namespace ppl diff --git a/src/ppl/src/Core.h b/src/ppl/src/Core.h index 4c97e99bfd2..afee07813c2 100644 --- a/src/ppl/src/Core.h +++ b/src/ppl/src/Core.h @@ -86,6 +86,7 @@ class Core std::vector getMinWidthY() const { return min_width_y_; } int getDatabaseUnit() const { return database_unit_; } int getPerimeter() const; + odb::Point getMirroredPosition(const odb::Point& position) const; private: Rect boundary_; diff --git a/src/ppl/src/HungarianMatching.cpp b/src/ppl/src/HungarianMatching.cpp index 69d8628059b..4595d7d892d 100644 --- a/src/ppl/src/HungarianMatching.cpp +++ b/src/ppl/src/HungarianMatching.cpp @@ -41,9 +41,11 @@ namespace ppl { HungarianMatching::HungarianMatching(Section& section, Netlist* netlist, + Core* core, std::vector& slots, Logger* logger) : netlist_(netlist), + core_(core), pin_indices_(section.pin_indices), pin_groups_(section.pin_groups), slots_(slots) @@ -96,13 +98,16 @@ inline bool samePos(Point& a, Point& b) return (a.x() == b.x() && a.y() == b.y()); } -void HungarianMatching::getFinalAssignment(std::vector& assigment) const +void HungarianMatching::getFinalAssignment(std::vector& assigment, + MirroredPins& mirrored_pins, + bool assign_mirrored) const { size_t rows = non_blocked_slots_; size_t col = 0; int slot_index = 0; for (int idx : pin_indices_) { IOPin& io_pin = netlist_->getIoPin(idx); + if (!io_pin.isInGroup()) { slot_index = begin_slot_; for (size_t row = 0; row < rows; row++) { @@ -119,10 +124,33 @@ void HungarianMatching::getFinalAssignment(std::vector& assigment) const "Not enough space.", io_pin.getName().c_str()); } + + // Make this check here to avoid messing up the correlation between the + // pin sorting and the hungarian matrix values + if ((assign_mirrored + && mirrored_pins.find(io_pin.getBTerm()) == mirrored_pins.end()) + || io_pin.isPlaced()) { + continue; + } io_pin.setPos(slots_[slot_index].pos); io_pin.setLayer(slots_[slot_index].layer); + io_pin.setPlaced(); assigment.push_back(io_pin); slots_[slot_index].used = true; + + if (assign_mirrored) { + odb::dbBTerm* mirrored_term = mirrored_pins[io_pin.getBTerm()]; + int mirrored_pin_idx = netlist_->getIoPinIdx(mirrored_term); + IOPin& mirrored_pin = netlist_->getIoPin(mirrored_pin_idx); + + odb::Point mirrored_pos = core_->getMirroredPosition(io_pin.getPos()); + mirrored_pin.setPos(mirrored_pos); + mirrored_pin.setLayer(slots_[slot_index].layer); + mirrored_pin.setPlaced(); + assigment.push_back(mirrored_pin); + slot_index = getSlotIdxByPosition(mirrored_pos); + slots_[slot_index].used = true; + } break; } col++; @@ -238,4 +266,17 @@ void HungarianMatching::getAssignmentForGroups(std::vector& assigment) assignment_.clear(); } +int HungarianMatching::getSlotIdxByPosition(const odb::Point& position) const +{ + int slot_idx = -1; + for (int i = 0; i < slots_.size(); i++) { + if (slots_[i].pos == position) { + slot_idx = i; + break; + } + } + + return slot_idx; +} + } // namespace ppl diff --git a/src/ppl/src/HungarianMatching.h b/src/ppl/src/HungarianMatching.h index 0ac30f184c9..3880cf92cbf 100644 --- a/src/ppl/src/HungarianMatching.h +++ b/src/ppl/src/HungarianMatching.h @@ -42,6 +42,7 @@ #include #include +#include "Core.h" #include "Hungarian.h" #include "Netlist.h" #include "Slots.h" @@ -62,12 +63,15 @@ class HungarianMatching public: HungarianMatching(Section& section, Netlist* netlist, + Core* core, std::vector& slots, Logger* logger); virtual ~HungarianMatching() = default; void findAssignment(); void findAssignmentForGroups(); - void getFinalAssignment(std::vector& assigment) const; + void getFinalAssignment(std::vector& assigment, + MirroredPins& mirrored_pins, + bool assign_mirrored) const; void getAssignmentForGroups(std::vector& assigment); private: @@ -75,6 +79,7 @@ class HungarianMatching std::vector assignment_; HungarianAlgorithm hungarian_solver_; Netlist* netlist_; + Core* core_; const std::vector& pin_indices_; const std::vector>& pin_groups_; std::vector& slots_; @@ -92,6 +97,7 @@ class HungarianMatching void createMatrix(); void createMatrixForGroups(); + int getSlotIdxByPosition(const odb::Point& position) const; }; } // namespace ppl diff --git a/src/ppl/src/IOPlacer.cpp b/src/ppl/src/IOPlacer.cpp index 15744a8568f..ce1741e69d0 100644 --- a/src/ppl/src/IOPlacer.cpp +++ b/src/ppl/src/IOPlacer.cpp @@ -603,7 +603,8 @@ void IOPlacer::createSections() } std::vector
IOPlacer::assignConstrainedPinsToSections( - Constraint& constraint) + Constraint& constraint, + int& mirrored_pins_cnt) { bool top_layer = constraint.interval.getEdge() == Edge::invalid; std::vector& slots = top_layer ? top_layer_slots_ : slots_; @@ -634,6 +635,9 @@ std::vector
IOPlacer::assignConstrainedPinsToSections( for (int idx : pin_indices) { IOPin& io_pin = netlist_io_pins_->getIoPin(idx); + if (mirrored_pins_.find(io_pin.getBTerm()) != mirrored_pins_.end()) { + mirrored_pins_cnt++; + } assignPinToSection(io_pin, idx, constraint.sections); } @@ -729,7 +733,19 @@ bool IOPlacer::assignPinsToSections(int assigned_pins_count) int total_pins_assigned = assignGroupsToSections(); + // Mirrored pins first int idx = 0; + for (IOPin& io_pin : net->getIOPins()) { + if (mirrored_pins_.find(io_pin.getBTerm()) != mirrored_pins_.end()) { + if (assignPinToSection(io_pin, idx, sections)) { + total_pins_assigned += 2; + } + } + idx++; + } + + // Remaining pins + idx = 0; for (IOPin& io_pin : net->getIOPins()) { if (assignPinToSection(io_pin, idx, sections)) { total_pins_assigned++; @@ -769,6 +785,15 @@ bool IOPlacer::assignPinToSection(IOPin& io_pin, sections[i].used_slots++; pin_assigned = true; io_pin.assignToSection(); + + if (mirrored_pins_.find(io_pin.getBTerm()) != mirrored_pins_.end()) { + odb::dbBTerm* mirrored_term = mirrored_pins_[io_pin.getBTerm()]; + int mirrored_pin_idx = netlist_io_pins_->getIoPinIdx(mirrored_term); + IOPin& mirrored_pin = netlist_io_pins_->getIoPin(mirrored_pin_idx); + // Mark mirrored pin as assigned to section to prevent assigning it to + // another section that is not aligned with his pair + mirrored_pin.assignToSection(); + } break; } } @@ -1038,6 +1063,11 @@ void IOPlacer::addTopLayerConstraint(PinList* pins, const odb::Rect& region) constraints_.push_back(constraint); } +void IOPlacer::addMirroredPins(odb::dbBTerm* bterm1, odb::dbBTerm* bterm2) +{ + mirrored_pins_[bterm1] = bterm2; +} + void IOPlacer::addHorLayer(odb::dbTechLayer* layer) { hor_layers_.insert(layer->getRoutingLevel()); @@ -1175,12 +1205,18 @@ void IOPlacer::findPinAssignment(std::vector
& sections) for (int idx = 0; idx < sections.size(); idx++) { if (sections[idx].pin_indices.size() > 0) { if (sections[idx].edge == Edge::invalid) { - HungarianMatching hg( - sections[idx], netlist_io_pins_.get(), top_layer_slots_, logger_); + HungarianMatching hg(sections[idx], + netlist_io_pins_.get(), + core_.get(), + top_layer_slots_, + logger_); hg_vec.push_back(hg); } else { - HungarianMatching hg( - sections[idx], netlist_io_pins_.get(), slots_, logger_); + HungarianMatching hg(sections[idx], + netlist_io_pins_.get(), + core_.get(), + slots_, + logger_); hg_vec.push_back(hg); } } @@ -1198,8 +1234,14 @@ void IOPlacer::findPinAssignment(std::vector
& sections) hg_vec[idx].findAssignment(); } + if (!mirrored_pins_.empty()) { + for (int idx = 0; idx < hg_vec.size(); idx++) { + hg_vec[idx].getFinalAssignment(assignment_, mirrored_pins_, true); + } + } + for (int idx = 0; idx < hg_vec.size(); idx++) { - hg_vec[idx].getFinalAssignment(assignment_); + hg_vec[idx].getFinalAssignment(assignment_, mirrored_pins_, false); } } @@ -1231,10 +1273,11 @@ void IOPlacer::run(bool random_mode) } else { int constrained_pins_cnt = 0; for (Constraint& constraint : constraints_) { + int mirrored_pins_cnt = 0; std::vector
sections_for_constraint - = assignConstrainedPinsToSections(constraint); + = assignConstrainedPinsToSections(constraint, mirrored_pins_cnt); for (Section& sec : sections_for_constraint) { - constrained_pins_cnt += sec.pin_indices.size(); + constrained_pins_cnt += sec.pin_indices.size() + mirrored_pins_cnt; } findPinAssignment(sections_for_constraint); diff --git a/src/ppl/src/IOPlacer.i b/src/ppl/src/IOPlacer.i index 77d53db607c..78b55ddc74b 100644 --- a/src/ppl/src/IOPlacer.i +++ b/src/ppl/src/IOPlacer.i @@ -170,6 +170,12 @@ add_top_layer_constraint(PinList *pin_list, getIOPlacer()->addTopLayerConstraint(pin_list, odb::Rect(x1, y1, x2, y2)); } +void +add_mirrored_pins(odb::dbBTerm* bterm1, odb::dbBTerm* bterm2) +{ + getIOPlacer()->addMirroredPins(bterm1, bterm2); +} + void set_hor_length(int length) { diff --git a/src/ppl/src/IOPlacer.tcl b/src/ppl/src/IOPlacer.tcl index 03879383b28..7076ff785ad 100644 --- a/src/ppl/src/IOPlacer.tcl +++ b/src/ppl/src/IOPlacer.tcl @@ -115,79 +115,93 @@ proc define_pin_shape_pattern { args } { sta::define_cmd_args "set_io_pin_constraint" {[-direction direction] \ [-pin_names names] \ - [-region region]} + [-region region] \ + [-mirrored_pins pins]} proc set_io_pin_constraint { args } { sta::parse_key_args "set_io_pin_constraint" args \ - keys {-direction -pin_names -region} + keys {-direction -pin_names -region -mirrored_pins} sta::check_argc_eq0 "set_io_pin_constraint" $args - if [info exists keys(-region)] { - set region $keys(-region) - } - set dbTech [ord::get_db_tech] set dbBlock [ord::get_db_block] set lef_units [$dbTech getLefUnits] - if [regexp -all {(top|bottom|left|right):(.+)} $region - edge interval] { - set edge_ [ppl::parse_edge "-region" $edge] + if [info exists keys(-region)] { + set region $keys(-region) + if [regexp -all {(top|bottom|left|right):(.+)} $region - edge interval] { + set edge_ [ppl::parse_edge "-region" $edge] + + if [regexp -all {([0-9]+[.]*[0-9]*|[*]+)-([0-9]+[.]*[0-9]*|[*]+)} $interval - begin end] { + if {$begin == {*}} { + set begin [ppl::get_edge_extreme "-region" 1 $edge] + } else { + set begin [ord::microns_to_dbu $begin] + } - if [regexp -all {([0-9]+[.]*[0-9]*|[*]+)-([0-9]+[.]*[0-9]*|[*]+)} $interval - begin end] { - if {$begin == {*}} { + if {$end == {*}} { + set end [ppl::get_edge_extreme "-region" 0 $edge] + } else { + set end [ord::microns_to_dbu $end] + } + } elseif {$interval == {*}} { set begin [ppl::get_edge_extreme "-region" 1 $edge] - } else { - set begin [ord::microns_to_dbu $begin] + set end [ppl::get_edge_extreme "-region" 0 $edge] } - if {$end == {*}} { - set end [ppl::get_edge_extreme "-region" 0 $edge] - } else { - set end [ord::microns_to_dbu $end] + if {[info exists keys(-direction)] && [info exists keys(-pin_names)]} { + utl::error PPL 16 "Both -direction and -pin_names constraints not allowed." } - } elseif {$interval == {*}} { - set begin [ppl::get_edge_extreme "-region" 1 $edge] - set end [ppl::get_edge_extreme "-region" 0 $edge] - } - if {[info exists keys(-direction)] && [info exists keys(-pin_names)]} { - utl::error PPL 16 "Both -direction and -pin_names constraints not allowed." - } + if [info exists keys(-direction)] { + set direction $keys(-direction) + set dir [ppl::parse_direction "set_io_pin_constraint" $direction] + utl::info PPL 49 "Restrict $direction pins to region [ord::dbu_to_microns $begin]u-[ord::dbu_to_microns $end]u, in the $edge edge." + ppl::add_direction_constraint $dir $edge_ $begin $end + } - if [info exists keys(-direction)] { - set direction $keys(-direction) - set dir [ppl::parse_direction "set_io_pin_constraint" $direction] - utl::info PPL 49 "Restrict $direction pins to region [ord::dbu_to_microns $begin]u-[ord::dbu_to_microns $end]u, in the $edge edge." - ppl::add_direction_constraint $dir $edge_ $begin $end - } + if [info exists keys(-pin_names)] { + set names $keys(-pin_names) + ppl::add_pins_to_constraint "set_io_pin_constraint" $names $edge_ $begin $end $edge + } + } elseif [regexp -all {(up):(.*)} $region - edge box] { + if {$box == "*"} { + set die_area [$dbBlock getDieArea] + set llx [$die_area xMin] + set lly [$die_area yMin] + set urx [$die_area xMax] + set ury [$die_area yMax] + } elseif [regexp -all {([0-9]+[.]*[0-9]*) ([0-9]+[.]*[0-9]*) ([0-9]+[.]*[0-9]*) ([0-9]+[.]*[0-9]*)} $box - llx lly urx ury] { + set llx [ord::microns_to_dbu $llx] + set lly [ord::microns_to_dbu $lly] + set urx [ord::microns_to_dbu $urx] + set ury [ord::microns_to_dbu $ury] + } else { + utl::error PPL 59 "Box at top layer must have 4 values (llx lly urx ury)." + } - if [info exists keys(-pin_names)] { - set names $keys(-pin_names) - ppl::add_pins_to_constraint "set_io_pin_constraint" $names $edge_ $begin $end $edge - } - } elseif [regexp -all {(up):(.*)} $region - edge box] { - if {$box == "*"} { - set die_area [$dbBlock getDieArea] - set llx [$die_area xMin] - set lly [$die_area yMin] - set urx [$die_area xMax] - set ury [$die_area yMax] - } elseif [regexp -all {([0-9]+[.]*[0-9]*) ([0-9]+[.]*[0-9]*) ([0-9]+[.]*[0-9]*) ([0-9]+[.]*[0-9]*)} $box - llx lly urx ury] { - set llx [ord::microns_to_dbu $llx] - set lly [ord::microns_to_dbu $lly] - set urx [ord::microns_to_dbu $urx] - set ury [ord::microns_to_dbu $ury] + if [info exists keys(-pin_names)] { + set names $keys(-pin_names) + ppl::add_pins_to_top_layer "set_io_pin_constraint" $names $llx $lly $urx $ury + } } else { - utl::error PPL 59 "Box at top layer must have 4 values (llx lly urx ury)." + utl::warn PPL 73 "Constraint with region $region has an invalid edge." } + } - if [info exists keys(-pin_names)] { - set names $keys(-pin_names) - ppl::add_pins_to_top_layer "set_io_pin_constraint" $names $llx $lly $urx $ury + if [info exists keys(-mirrored_pins)] { + set mirrored_pins $keys(-mirrored_pins) + if { [expr [llength $mirrored_pins] % 2] != 0 } { + utl::error PPL 81 "List of pins must have an even number of pins." + } + + foreach {pin1 pin2} $mirrored_pins { + utl::info PPL 80 "Mirroring pins $pin1 and $pin2." + set bterm1 [ppl::parse_pin_names "place_pin" $pin1] + set bterm2 [ppl::parse_pin_names "place_pin" $pin2] + ppl::add_mirrored_pins $bterm1 $bterm2 } - } else { - utl::warn PPL 73 "Constraint with region $region has an invalid edge." } } diff --git a/src/ppl/test/add_constraint9.defok b/src/ppl/test/add_constraint9.defok new file mode 100644 index 00000000000..76e70f2bdee --- /dev/null +++ b/src/ppl/test/add_constraint9.defok @@ -0,0 +1,395 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN gcd ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 200260 201600 ) ; +TRACKS X 190 DO 527 STEP 380 LAYER metal1 ; +TRACKS Y 140 DO 720 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 527 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 720 STEP 280 LAYER metal2 ; +TRACKS X 190 DO 527 STEP 380 LAYER metal3 ; +TRACKS Y 140 DO 720 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 358 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 360 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 358 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 360 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 358 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 360 STEP 560 LAYER metal6 ; +TRACKS X 190 DO 126 STEP 1600 LAYER metal7 ; +TRACKS Y 140 DO 126 STEP 1600 LAYER metal7 ; +TRACKS X 190 DO 126 STEP 1600 LAYER metal8 ; +TRACKS Y 140 DO 126 STEP 1600 LAYER metal8 ; +TRACKS X 190 DO 63 STEP 3200 LAYER metal9 ; +TRACKS Y 140 DO 63 STEP 3200 LAYER metal9 ; +TRACKS X 190 DO 63 STEP 3200 LAYER metal10 ; +TRACKS Y 140 DO 63 STEP 3200 LAYER metal10 ; +COMPONENTS 88 ; + - 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_880_ DFF_X1 + PLACED ( 119700 137200 ) N ; + - _881_ DFF_X1 + PLACED ( 150100 84000 ) FS ; + - _882_ DFF_X1 + PLACED ( 154660 106400 ) FS ; + - _883_ DFF_X1 + PLACED ( 124260 84000 ) FS ; + - _884_ DFF_X1 + PLACED ( 134520 114800 ) N ; + - _885_ DFF_X1 + PLACED ( 62700 98000 ) N ; + - _886_ DFF_X1 + PLACED ( 50920 84000 ) FS ; + - _887_ DFF_X1 + PLACED ( 69920 58800 ) N ; + - _888_ DFF_X1 + PLACED ( 109060 70000 ) N ; + - _889_ DFF_X1 + PLACED ( 113620 53200 ) N ; + - _890_ DFF_X1 + PLACED ( 100700 30800 ) N ; + - _891_ DFF_X1 + PLACED ( 69540 50400 ) FS ; + - _892_ DFF_X1 + PLACED ( 103360 75600 ) N ; + - buffer1 BUF_X4 + PLACED ( 165300 176400 ) N ; + - buffer10 BUF_X4 + PLACED ( 170240 22400 ) FS ; + - buffer11 BUF_X4 + PLACED ( 175180 126000 ) N ; + - buffer12 BUF_X4 + PLACED ( 30400 22400 ) FS ; + - buffer13 BUF_X4 + PLACED ( 139840 176400 ) N ; + - buffer14 BUF_X4 + PLACED ( 66120 176400 ) N ; + - buffer15 BUF_X4 + PLACED ( 175180 81200 ) N ; + - buffer16 BUF_X4 + PLACED ( 155800 176400 ) N ; + - buffer17 BUF_X4 + PLACED ( 25460 176400 ) N ; + - buffer18 BUF_X4 + PLACED ( 43700 22400 ) FS ; + - buffer19 BUF_X4 + PLACED ( 147820 22400 ) FS ; + - buffer2 BUF_X4 + PLACED ( 35720 176400 ) N ; + - buffer20 BUF_X4 + PLACED ( 175180 170800 ) N ; + - buffer21 BUF_X4 + PLACED ( 104120 22400 ) FS ; + - buffer22 BUF_X4 + PLACED ( 125400 176400 ) N ; + - buffer23 BUF_X4 + PLACED ( 20520 72800 ) FS ; + - buffer24 BUF_X4 + PLACED ( 30400 176400 ) N ; + - buffer25 BUF_X4 + PLACED ( 175180 156800 ) FS ; + - buffer26 BUF_X4 + PLACED ( 20520 58800 ) N ; + - buffer27 BUF_X4 + PLACED ( 175180 28000 ) FS ; + - buffer28 BUF_X4 + PLACED ( 175180 112000 ) FS ; + - buffer29 BUF_X4 + PLACED ( 20520 173600 ) FS ; + - buffer3 BUF_X4 + PLACED ( 88540 22400 ) FS ; + - buffer30 BUF_X4 + PLACED ( 150860 176400 ) N ; + - buffer31 BUF_X4 + PLACED ( 74100 22400 ) FS ; + - buffer32 BUF_X4 + PLACED ( 175180 140000 ) FS ; + - buffer33 BUF_X4 + PLACED ( 170240 176400 ) N ; + - buffer34 BUF_X4 + PLACED ( 20520 103600 ) N ; + - buffer35 BUF_X4 + PLACED ( 20520 176400 ) N ; + - buffer36 BUF_X4 + PLACED ( 20520 22400 ) FS ; + - buffer37 BUF_X4 + PLACED ( 20520 25200 ) N ; + - buffer38 BUF_X4 + PLACED ( 133380 22400 ) FS ; + - buffer39 BUF_X4 + PLACED ( 175180 22400 ) FS ; + - buffer4 BUF_X4 + PLACED ( 20520 28000 ) FS ; + - buffer40 BUF_X4 + PLACED ( 175180 25200 ) N ; + - buffer41 BUF_X4 + PLACED ( 175180 67200 ) FS ; + - buffer42 BUF_X4 + PLACED ( 20520 89600 ) FS ; + - buffer43 BUF_X4 + PLACED ( 118560 22400 ) FS ; + - buffer44 BUF_X4 + PLACED ( 20520 117600 ) FS ; + - buffer45 BUF_X4 + PLACED ( 175180 176400 ) N ; + - buffer46 BUF_X4 + PLACED ( 20520 44800 ) FS ; + - buffer47 BUF_X4 + PLACED ( 175180 36400 ) N ; + - buffer48 BUF_X4 + PLACED ( 25460 22400 ) FS ; + - buffer49 BUF_X4 + PLACED ( 163400 22400 ) FS ; + - buffer5 BUF_X4 + PLACED ( 110960 176400 ) N ; + - buffer50 BUF_X4 + PLACED ( 20520 134400 ) FS ; + - buffer51 BUF_X4 + PLACED ( 20520 148400 ) N ; + - buffer52 BUF_X4 + PLACED ( 20520 162400 ) FS ; + - buffer53 BUF_X4 + PLACED ( 175180 53200 ) N ; + - buffer6 BUF_X4 + PLACED ( 59280 22400 ) FS ; + - buffer7 BUF_X4 + PLACED ( 51680 176400 ) N ; + - buffer8 BUF_X4 + PLACED ( 175180 95200 ) FS ; + - buffer9 BUF_X4 + PLACED ( 80560 176400 ) N ; +END COMPONENTS +PINS 54 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 76190 70 ) N ; + - req_msg[0] + NET req_msg[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 163940 ) N ; + - req_msg[10] + NET req_msg[10] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 125590 201530 ) N ; + - req_msg[11] + NET req_msg[11] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 104310 70 ) N ; + - req_msg[12] + NET req_msg[12] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 172060 ) N ; + - req_msg[13] + NET req_msg[13] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 152190 70 ) N ; + - req_msg[14] + NET req_msg[14] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 43890 70 ) N ; + - req_msg[15] + NET req_msg[15] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 25650 201530 ) N ; + - req_msg[16] + NET req_msg[16] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 155990 201530 ) N ; + - req_msg[17] + NET req_msg[17] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 82460 ) N ; + - req_msg[18] + NET req_msg[18] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 66310 201530 ) N ; + - req_msg[19] + NET req_msg[19] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 140030 201530 ) N ; + - req_msg[1] + NET req_msg[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 149660 ) N ; + - req_msg[20] + NET req_msg[20] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 30590 70 ) N ; + - req_msg[21] + NET req_msg[21] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 127260 ) N ; + - req_msg[22] + NET req_msg[22] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 170430 70 ) N ; + - req_msg[23] + NET req_msg[23] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 80750 201530 ) N ; + - req_msg[24] + NET req_msg[24] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 96740 ) N ; + - req_msg[25] + NET req_msg[25] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 48070 201530 ) N ; + - req_msg[26] + NET req_msg[26] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 59470 70 ) N ; + - req_msg[27] + NET req_msg[27] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 111150 201530 ) N ; + - req_msg[28] + NET req_msg[28] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 29540 ) N ; + - req_msg[29] + NET req_msg[29] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 88730 70 ) N ; + - req_msg[2] + NET req_msg[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 135940 ) N ; + - req_msg[30] + NET req_msg[30] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 35910 201530 ) N ; + - req_msg[31] + NET req_msg[31] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 165490 201530 ) N ; + - req_msg[3] + NET req_msg[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 165110 201530 ) N ; + - req_msg[4] + NET req_msg[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 113540 ) N ; + - req_msg[5] + NET req_msg[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 29540 ) N ; + - req_msg[6] + NET req_msg[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 60060 ) N ; + - req_msg[7] + NET req_msg[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 158340 ) N ; + - req_msg[8] + NET req_msg[8] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 30590 201530 ) N ; + - req_msg[9] + NET req_msg[9] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 74340 ) N ; + - req_rdy + NET req_rdy + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 23660 ) N ; + - req_val + NET req_val + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 170430 201530 ) N ; + - reset + NET reset + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 104860 ) N ; + - resp_msg[0] + NET resp_msg[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 163940 ) N ; + - resp_msg[10] + NET resp_msg[10] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 91140 ) N ; + - resp_msg[11] + NET resp_msg[11] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 68740 ) N ; + - resp_msg[12] + NET resp_msg[12] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 26460 ) N ; + - resp_msg[13] + NET resp_msg[13] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 176890 70 ) N ; + - resp_msg[14] + NET resp_msg[14] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 135090 70 ) N ; + - resp_msg[15] + NET resp_msg[15] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 26460 ) N ; + - resp_msg[1] + NET resp_msg[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 149660 ) N ; + - resp_msg[2] + NET resp_msg[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 135940 ) N ; + - resp_msg[3] + NET resp_msg[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 165110 70 ) N ; + - resp_msg[4] + NET resp_msg[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 23940 ) N ; + - resp_msg[5] + NET resp_msg[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 37660 ) N ; + - resp_msg[6] + NET resp_msg[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 46340 ) N ; + - resp_msg[7] + NET resp_msg[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 177660 ) N ; + - resp_msg[8] + NET resp_msg[8] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 119140 ) N ; + - resp_msg[9] + NET resp_msg[9] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal2 ( -70 -70 ) ( 70 70 ) + + PLACED ( 120270 70 ) N ; + - resp_rdy + NET resp_rdy + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 70 177660 ) N ; + - resp_val + NET resp_val + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -70 -70 ) ( 70 70 ) + + PLACED ( 200190 54460 ) N ; +END PINS +NETS 54 ; + - clk ( PIN clk ) ( _858_ CK ) ( _859_ CK ) ( _860_ CK ) ( _861_ CK ) ( _862_ CK ) ( _863_ CK ) + ( _864_ CK ) ( _865_ CK ) ( _866_ CK ) ( _867_ CK ) ( _868_ CK ) ( _869_ CK ) ( _870_ CK ) ( _871_ CK ) + ( _872_ CK ) ( _873_ CK ) ( _874_ CK ) ( _875_ CK ) ( _876_ CK ) ( _877_ CK ) ( _878_ CK ) ( _879_ CK ) + ( _880_ CK ) ( _881_ CK ) ( _882_ CK ) ( _883_ CK ) ( _884_ CK ) ( _885_ CK ) ( _886_ CK ) ( _887_ CK ) + ( _888_ CK ) ( _889_ CK ) ( _890_ CK ) ( _891_ CK ) ( _892_ CK ) + USE SIGNAL ; + - req_msg[0] ( PIN req_msg[0] ) ( buffer32 A ) + USE SIGNAL ; + - req_msg[10] ( PIN req_msg[10] ) ( buffer22 A ) + USE SIGNAL ; + - req_msg[11] ( PIN req_msg[11] ) ( buffer21 A ) + USE SIGNAL ; + - req_msg[12] ( PIN req_msg[12] ) ( buffer20 A ) + USE SIGNAL ; + - req_msg[13] ( PIN req_msg[13] ) ( buffer19 A ) + USE SIGNAL ; + - req_msg[14] ( PIN req_msg[14] ) ( buffer18 A ) + USE SIGNAL ; + - req_msg[15] ( PIN req_msg[15] ) ( buffer17 A ) + USE SIGNAL ; + - req_msg[16] ( PIN req_msg[16] ) ( buffer16 A ) + USE SIGNAL ; + - req_msg[17] ( PIN req_msg[17] ) ( buffer15 A ) + USE SIGNAL ; + - req_msg[18] ( PIN req_msg[18] ) ( buffer14 A ) + USE SIGNAL ; + - req_msg[19] ( PIN req_msg[19] ) ( buffer13 A ) + USE SIGNAL ; + - req_msg[1] ( PIN req_msg[1] ) ( buffer31 A ) + USE SIGNAL ; + - req_msg[20] ( PIN req_msg[20] ) ( buffer12 A ) + USE SIGNAL ; + - req_msg[21] ( PIN req_msg[21] ) ( buffer11 A ) + USE SIGNAL ; + - req_msg[22] ( PIN req_msg[22] ) ( buffer10 A ) + USE SIGNAL ; + - req_msg[23] ( PIN req_msg[23] ) ( buffer9 A ) + USE SIGNAL ; + - req_msg[24] ( PIN req_msg[24] ) ( buffer8 A ) + USE SIGNAL ; + - req_msg[25] ( PIN req_msg[25] ) ( buffer7 A ) + USE SIGNAL ; + - req_msg[26] ( PIN req_msg[26] ) ( buffer6 A ) + USE SIGNAL ; + - req_msg[27] ( PIN req_msg[27] ) ( buffer5 A ) + USE SIGNAL ; + - req_msg[28] ( PIN req_msg[28] ) ( buffer4 A ) + USE SIGNAL ; + - req_msg[29] ( PIN req_msg[29] ) ( buffer3 A ) + USE SIGNAL ; + - req_msg[2] ( PIN req_msg[2] ) ( buffer30 A ) + USE SIGNAL ; + - req_msg[30] ( PIN req_msg[30] ) ( buffer2 A ) + USE SIGNAL ; + - req_msg[31] ( PIN req_msg[31] ) ( buffer1 A ) + USE SIGNAL ; + - req_msg[3] ( PIN req_msg[3] ) ( buffer29 A ) + USE SIGNAL ; + - req_msg[4] ( PIN req_msg[4] ) ( buffer28 A ) + USE SIGNAL ; + - req_msg[5] ( PIN req_msg[5] ) ( buffer27 A ) + USE SIGNAL ; + - req_msg[6] ( PIN req_msg[6] ) ( buffer26 A ) + USE SIGNAL ; + - req_msg[7] ( PIN req_msg[7] ) ( buffer25 A ) + USE SIGNAL ; + - req_msg[8] ( PIN req_msg[8] ) ( buffer24 A ) + USE SIGNAL ; + - req_msg[9] ( PIN req_msg[9] ) ( buffer23 A ) + USE SIGNAL ; + - req_rdy ( PIN req_rdy ) ( buffer36 Z ) + USE SIGNAL ; + - req_val ( PIN req_val ) ( buffer33 A ) + USE SIGNAL ; + - reset ( PIN reset ) ( buffer34 A ) + USE SIGNAL ; + - resp_msg[0] ( PIN resp_msg[0] ) ( buffer52 Z ) + USE SIGNAL ; + - resp_msg[10] ( PIN resp_msg[10] ) ( buffer42 Z ) + USE SIGNAL ; + - resp_msg[11] ( PIN resp_msg[11] ) ( buffer41 Z ) + USE SIGNAL ; + - resp_msg[12] ( PIN resp_msg[12] ) ( buffer40 Z ) + USE SIGNAL ; + - resp_msg[13] ( PIN resp_msg[13] ) ( buffer39 Z ) + USE SIGNAL ; + - resp_msg[14] ( PIN resp_msg[14] ) ( buffer38 Z ) + USE SIGNAL ; + - resp_msg[15] ( PIN resp_msg[15] ) ( buffer37 Z ) + USE SIGNAL ; + - resp_msg[1] ( PIN resp_msg[1] ) ( buffer51 Z ) + USE SIGNAL ; + - resp_msg[2] ( PIN resp_msg[2] ) ( buffer50 Z ) + USE SIGNAL ; + - resp_msg[3] ( PIN resp_msg[3] ) ( buffer49 Z ) + USE SIGNAL ; + - resp_msg[4] ( PIN resp_msg[4] ) ( buffer48 Z ) + USE SIGNAL ; + - resp_msg[5] ( PIN resp_msg[5] ) ( buffer47 Z ) + USE SIGNAL ; + - resp_msg[6] ( PIN resp_msg[6] ) ( buffer46 Z ) + USE SIGNAL ; + - resp_msg[7] ( PIN resp_msg[7] ) ( buffer45 Z ) + USE SIGNAL ; + - resp_msg[8] ( PIN resp_msg[8] ) ( buffer44 Z ) + USE SIGNAL ; + - resp_msg[9] ( PIN resp_msg[9] ) ( buffer43 Z ) + USE SIGNAL ; + - resp_rdy ( PIN resp_rdy ) ( buffer35 A ) + USE SIGNAL ; + - resp_val ( PIN resp_val ) ( buffer53 Z ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/ppl/test/add_constraint9.ok b/src/ppl/test/add_constraint9.ok new file mode 100644 index 00000000000..c37b64258bc --- /dev/null +++ b/src/ppl/test/add_constraint9.ok @@ -0,0 +1,24 @@ +[INFO ODB-0222] Reading LEF file: Nangate45/Nangate45.lef +[INFO ODB-0223] Created 22 technology layers +[INFO ODB-0224] Created 27 technology vias +[INFO ODB-0225] Created 135 library cells +[INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef +[INFO ODB-0128] Design: gcd +[INFO ODB-0130] Created 54 pins. +[INFO ODB-0131] Created 88 components and 422 component-terminals. +[INFO ODB-0133] Created 54 nets and 88 connections. +[INFO PPL-0080] Mirroring pins resp_msg[0] and req_msg[0]. +[INFO PPL-0080] Mirroring pins resp_msg[1] and req_msg[1]. +[INFO PPL-0080] Mirroring pins resp_msg[2] and req_msg[2]. +[INFO PPL-0080] Mirroring pins resp_msg[3] and req_msg[3]. +Found 0 macro blocks. +[INFO PPL-0010] Tentative 0 to set up sections. +[INFO PPL-0001] Number of slots 2494 +[INFO PPL-0002] Number of I/O 54 +[INFO PPL-0003] Number of I/O w/sink 54 +[INFO PPL-0004] Number of I/O w/o sink 0 +[INFO PPL-0005] Slots per section 200 +[INFO PPL-0006] Slots increase factor 0.01 +[INFO PPL-0008] Successfully assigned pins to sections. +[INFO PPL-0012] I/O nets HPWL: 987.97 um. +No differences found. diff --git a/src/ppl/test/add_constraint9.py b/src/ppl/test/add_constraint9.py new file mode 100644 index 00000000000..f29095d3a16 --- /dev/null +++ b/src/ppl/test/add_constraint9.py @@ -0,0 +1,18 @@ +# gcd_nangate45 IO placement +from openroad import Design, Tech +import helpers +import ppl_aux + +tech = Tech() +tech.readLef("Nangate45/Nangate45.lef") +design = Design(tech) +design.readDef("gcd.def") + +design.evalTclString("set_io_pin_constraint -mirrored_pins {resp_msg[0] req_msg[0] resp_msg[1] req_msg[1] resp_msg[2] req_msg[2] resp_msg[3] req_msg[3]}") + +ppl_aux.place_pins(design, hor_layers="metal3", ver_layers="metal2", + corner_avoidance=0, min_distance=0.12) + +def_file = helpers.make_result_file("add_constraint9.def") +design.writeDef(def_file) +helpers.diff_files("add_constraint9.defok", def_file) diff --git a/src/ppl/test/add_constraint9.tcl b/src/ppl/test/add_constraint9.tcl new file mode 100644 index 00000000000..a0b87e92a67 --- /dev/null +++ b/src/ppl/test/add_constraint9.tcl @@ -0,0 +1,13 @@ +# gcd_nangate45 IO placement +source "helpers.tcl" +read_lef Nangate45/Nangate45.lef +read_def gcd.def + +set_io_pin_constraint -mirrored_pins {resp_msg[0] req_msg[0] resp_msg[1] req_msg[1] resp_msg[2] req_msg[2] resp_msg[3] req_msg[3]} +place_pins -hor_layers metal3 -ver_layers metal2 -corner_avoidance 0 -min_distance 0.12 + +set def_file [make_result_file add_constraint9.def] + +write_def $def_file + +diff_file add_constraint9.defok $def_file \ No newline at end of file diff --git a/src/ppl/test/add_constraint_error1.ok b/src/ppl/test/add_constraint_error1.ok new file mode 100644 index 00000000000..20c8c93fdb1 --- /dev/null +++ b/src/ppl/test/add_constraint_error1.ok @@ -0,0 +1,11 @@ +[INFO ODB-0222] Reading LEF file: Nangate45/Nangate45.lef +[INFO ODB-0223] Created 22 technology layers +[INFO ODB-0224] Created 27 technology vias +[INFO ODB-0225] Created 135 library cells +[INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef +[INFO ODB-0128] Design: gcd +[INFO ODB-0130] Created 54 pins. +[INFO ODB-0131] Created 88 components and 422 component-terminals. +[INFO ODB-0133] Created 54 nets and 88 connections. +[ERROR PPL-0081] List of pins must have an even number of pins. +PPL-0081 diff --git a/src/ppl/test/add_constraint_error1.tcl b/src/ppl/test/add_constraint_error1.tcl new file mode 100644 index 00000000000..b5a89aaee2a --- /dev/null +++ b/src/ppl/test/add_constraint_error1.tcl @@ -0,0 +1,7 @@ +# gcd_nangate45 IO placement +source "helpers.tcl" +read_lef Nangate45/Nangate45.lef +read_def gcd.def + +catch {set_io_pin_constraint -mirrored_pins {resp_msg[0] req_msg[0] resp_msg[1] req_msg[1] resp_msg[2] req_msg[2] resp_msg[3]}} error +puts $error diff --git a/src/ppl/test/regression_tests.tcl b/src/ppl/test/regression_tests.tcl index c1b27b5df6f..665107c9972 100644 --- a/src/ppl/test/regression_tests.tcl +++ b/src/ppl/test/regression_tests.tcl @@ -30,6 +30,8 @@ record_tests { add_constraint6 add_constraint7 add_constraint8 + add_constraint9 + add_constraint_error1 group_pins1 group_pins2 group_pins3