IFU Page Table Entry Global coverage.

[kjprime]

I am attempting to cover this line specifically the PTE_G high condition.
In the instance /core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[31]

I have read excerpts from the memory management unit (chapter 8)
I spoke with @ross144 a few times, prompting me a few pieces of documentation to look more closely at, various chapters 10, and 5 and primarily 8 with a better idea of what I was looking at in terms of what a page table and page table entry's are.
Additionally recommended was to read some of the excerpts from the privileged instruction set manual about the sv39 syntax, specifically section 4.4.
I've determined that I need to create a global page table entry and access it as an instruction, I think?
I've found a C file and header file within the add-in's that creates page tables and entries I believe, - I've complied it to assembly and looked at it to try to understand its process. This was useful but did not lead us directly to our next step; As page table entrees and the structure leading up to them still seemed to be a bit of a leap in concept.

I have noticed and been following along with @mcook26 's contributions and @Noah-G-L 's global and mega page test that are working in a similar area.

I believe my next step is to coopt this test to store a instruction in the physical address via the page table entry so that I can access this instruction via a globally flagged page table table entry. (This instruction will be a jump to the return address register location to return to the calling location)
Then jump to these instructions via addressing the page table entry that I've previously written an instruction to.
So I need to traverse a page table to get to a specific entry and read the instruction referenced by that entry.

I hope to write up this test soon, and try to address this lack of coverage. Please let me know if you see any errors in my thought process that might better enable getting these coverage gaps filled.
-Kevin

[rosethompson]

Yes. You can do something similar to Noah's code. Make sure you change the leaf PTE previsions to executable.

[infinitymdm]

Out of my own curiosity, how is this done? Is there an executable flag just like there's a global flag?

[rosethompson]

Page 85 of the privilege spec shows the encoding for an sv39 page table entry (PTE). The 10 LSBs of the PTE describe the access control and other properties of the page table entry. For example V (bit 0) indicates if the entry valid. R (bit 1) indicates if the entry is readable by data memory. W (bit 2) indicates if the entry is writable by data memory. X (bit 3) indicates if the entry is executable by instruction memory.

[infinitymdm]

Ok, so just like linux file modes. That makes a lot of sense. Thanks!

[kjprime]

#285 Addressed the issue in this discussion, adding jal's to the test.
I've added some comments and some changes for better test description, in #291