From b5aa6c67900862ff0fe8e54e39638d50dfcc7c2f Mon Sep 17 00:00:00 2001 From: Marcus Mellor Date: Wed, 27 Mar 2024 09:58:37 -0500 Subject: [PATCH] soc: Add RT's lpddrtest and make many small fixes - Add RT's lpddrtest program - Fix bugs in soc/src/ahbxuiconverter - Add if/else block for soc to wally.do - Fix memory address range for external lpddr memory --- config/soc/config.vh | 2 +- sim/regression-wally | 2 +- sim/wally-batch.do | 12 ++++++++---- sim/wally.do | 9 ++++++++- soc/src/ahbxuiconverter.sv | 6 ++++-- testbench/testbench.sv | 22 ++++++++------------- testbench/tests.vh | 1 + tests/custom/lpddrtest/Makefile | 19 ++++++++++++++++++ tests/custom/lpddrtest/header.h | 5 +++++ tests/custom/lpddrtest/lpddr_test.s | 30 +++++++++++++++++++++++++++++ tests/custom/lpddrtest/main.c | 6 ++++++ 11 files changed, 91 insertions(+), 23 deletions(-) create mode 100755 tests/custom/lpddrtest/Makefile create mode 100755 tests/custom/lpddrtest/header.h create mode 100755 tests/custom/lpddrtest/lpddr_test.s create mode 100755 tests/custom/lpddrtest/main.c diff --git a/config/soc/config.vh b/config/soc/config.vh index 0c12af8e4b..e7a18c2f60 100644 --- a/config/soc/config.vh +++ b/config/soc/config.vh @@ -111,7 +111,7 @@ localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; localparam UNCORE_RAM_PRELOAD = 1'b0; localparam EXT_MEM_SUPPORTED = 1'b1; -localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_BASE = 64'h90000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; localparam CLINT_SUPPORTED = 1'b1; localparam logic [63:0] CLINT_BASE = 64'h02000000; diff --git a/sim/regression-wally b/sim/regression-wally index 991b14f5e4..3656d44548 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -452,7 +452,7 @@ def main(): TIMEOUT_DUR = 20*60 # seconds # FIXME: Do we need to run buildroot? else: - TIMEOUT_DUR = 10*60 # seconds + TIMEOUT_DUR = 60 # seconds configs.append(getBuildrootTC(boot=False)) # Scale the number of concurrent processes to the number of test cases, but diff --git a/sim/wally-batch.do b/sim/wally-batch.do index 19315e5587..d245722ae3 100644 --- a/sim/wally-batch.do +++ b/sim/wally-batch.do @@ -66,13 +66,17 @@ if {$argc >= 3} { # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32imc rv32imc -set bsg_dir ../soc/src/basejump_stl -vlog -lint -work wkdir/work_${1}_${2} +define+den2048Mb+sg5+x32+FULL_MEM +incdir+$bsg_dir/bsg_clk_gen+$bsg_dir/bsg_dmc+$bsg_dir/bsg_misc+$bsg_dir/bsg_noc+$bsg_dir/bsg_tag+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model $bsg_dir/bsg_dmc/bsg_dmc_pkg.sv $bsg_dir/bsg_noc/bsg_noc_pkg.sv $bsg_dir/bsg_noc/bsg_mesh_router_pkg.sv $bsg_dir/bsg_noc/bsg_wormhole_router_pkg.sv $bsg_dir/bsg_tag/bsg_tag_pkg.sv $bsg_dir/*/*.sv $bsg_dir/testing/bsg_dmc/lpddr_verilog_model/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388 -vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1+../config/deriv/$1+../config/shared+$bsg_dir/bsg_clk_gen+$bsg_dir/bsg_dmc+$bsg_dir/bsg_misc+$bsg_dir/bsg_tag+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../soc/src/fifo/*.sv ../soc/src/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388 +if {$1 eq "soc"} { + set bsg_dir ../soc/src/basejump_stl + vlog -lint -work wkdir/work_${1}_${2} +define+den2048Mb+sg5+x32+FULL_MEM +incdir+$bsg_dir/bsg_clk_gen+$bsg_dir/bsg_dmc+$bsg_dir/bsg_misc+$bsg_dir/bsg_noc+$bsg_dir/bsg_tag+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model $bsg_dir/bsg_dmc/bsg_dmc_pkg.sv $bsg_dir/bsg_noc/bsg_noc_pkg.sv $bsg_dir/bsg_noc/bsg_mesh_router_pkg.sv $bsg_dir/bsg_noc/bsg_wormhole_router_pkg.sv $bsg_dir/bsg_tag/bsg_tag_pkg.sv $bsg_dir/*/*.sv $bsg_dir/testing/bsg_dmc/lpddr_verilog_model/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1+../config/deriv/$1+../config/shared+$bsg_dir/bsg_clk_gen+$bsg_dir/bsg_dmc+$bsg_dir/bsg_misc+$bsg_dir/bsg_tag+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../soc/src/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388 +} else { + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1+../config/deriv/$1+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +} # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt +acc wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg} +vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg} vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3009,3829,3999,8885 ${CoverageVsimArg} # vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 diff --git a/sim/wally.do b/sim/wally.do index 430146d395..928710400b 100644 --- a/sim/wally.do +++ b/sim/wally.do @@ -77,7 +77,14 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { run 20 ms } else { - vlog +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 + if {$1 eq "soc"} { + set bsg_dir ../soc/src/basejump_stl + vlog -lint -work wkdir/work_${1}_${2} +define+den2048Mb+sg5+x32+FULL_MEM +incdir+$bsg_dir/bsg_clk_gen+$bsg_dir/bsg_dmc+$bsg_dir/bsg_misc+$bsg_dir/bsg_noc+$bsg_dir/bsg_tag+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model $bsg_dir/bsg_dmc/bsg_dmc_pkg.sv $bsg_dir/bsg_noc/bsg_noc_pkg.sv $bsg_dir/bsg_noc/bsg_mesh_router_pkg.sv $bsg_dir/bsg_noc/bsg_wormhole_router_pkg.sv $bsg_dir/bsg_tag/bsg_tag_pkg.sv $bsg_dir/*/*.sv $bsg_dir/testing/bsg_dmc/lpddr_verilog_model/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1+../config/deriv/$1+../config/shared+$bsg_dir/bsg_clk_gen+$bsg_dir/bsg_dmc+$bsg_dir/bsg_misc+$bsg_dir/bsg_tag+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../soc/src/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388 + } + else { + vlog +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 + } vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt vsim workopt +nowarn3829 -fatal 7 diff --git a/soc/src/ahbxuiconverter.sv b/soc/src/ahbxuiconverter.sv index 812f7cd950..9b86af2a2a 100644 --- a/soc/src/ahbxuiconverter.sv +++ b/soc/src/ahbxuiconverter.sv @@ -88,7 +88,8 @@ module ahbxuiconverter #(parameter ADDR_SIZE = 31, // FIFO needs addr + (data + mask) + (enable + write) bsg_async_fifo #( .width_p(ADDR_SIZE + 9*DATA_SIZE/8 + 2), - .lg_size_p(16) + .lg_size_p(16), + .and_data_with_valid_p(1) ) cmdfifo ( .w_data_i({HADDR, HWDATA, HWSTRB, initTrans, HWRITE}), .w_enq_i(enqueueCmd), .w_clk_i(HCLK), .w_reset_i(~HRESETn), @@ -113,7 +114,8 @@ module ahbxuiconverter #(parameter ADDR_SIZE = 31, assign dequeueResp = HSEL & resprvalid; bsg_async_fifo #( .width_p(DATA_SIZE), - .lg_size_p(8) + .lg_size_p(8), + .and_data_with_valid_p(1) ) respfifo ( .w_data_i(app_rd_data), .w_enq_i(enqueueResp), .w_clk_i(ui_clk), .w_reset_i(ui_clk_sync_rst), diff --git a/testbench/testbench.sv b/testbench/testbench.sv index f73e57b169..ac16955062 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -243,7 +243,7 @@ module testbench; initial begin TestBenchReset = 1; - # 100ns; + # 1000ns; TestBenchReset = 0; end @@ -420,9 +420,7 @@ module testbench; readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile); $fclose(memFile); end else - if (~P.USE_BSG_DMC) begin - $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - end + $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); if (TEST == "embench") $display("Read memfile %s", memfilename); end if (CopyRAM) begin @@ -539,7 +537,9 @@ module testbench; force ram.dmc.dmc_clk_rst_gen.dly_lines[3].dly_line_inst.ctrl_rrr = 31; force ram.dmc.dmc_clk_rst_gen.clk_gen_ds_inst.reset_i = 1'b1; force ram.dmc.dmc_clk_rst_gen.clk_gen_ds_inst.strobe_r = 1'b0; - #100ns + ui_clk = 1'b0; + dfi_clk_2x_i = 1'b0; + #100ns; force ram.dmc.dmc_clk_rst_gen.clk_gen_ds_inst.reset_i = 1'b0; force ram.dmc.dmc_clk_rst_gen.clk_gen_ds_inst.strobe_r = 1'b1; end @@ -580,15 +580,9 @@ module testbench; .Cke(ddr_cke), .Cs_n(ddr_cs), .Ras_n(ddr_ras), .Cas_n(ddr_cas), .We_n(ddr_we), .Dm(ddr_dm[dq_group/2*(ddr_i+1)-1:dq_group/2*ddr_i])); end - initial begin: dmc_reset - force ram.sys_reset = 1'b1; - ui_clk = 1'b0; - dfi_clk_2x_i = 1'b0; - #1000ns force ram.sys_reset = 0; - end - end else begin - ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) - ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), + end else begin + ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) + ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end end else begin diff --git a/testbench/tests.vh b/testbench/tests.vh index 573f5c20b3..d8d68e090d 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -2709,6 +2709,7 @@ string arch32zfh_fma[] = '{ string custom[] = '{ `CUSTOM, + "lpddrtest", "simple", "debug", "cacheTest" diff --git a/tests/custom/lpddrtest/Makefile b/tests/custom/lpddrtest/Makefile new file mode 100755 index 0000000000..c67fd825af --- /dev/null +++ b/tests/custom/lpddrtest/Makefile @@ -0,0 +1,19 @@ +TARGETDIR := lpddrtest +TARGET := $(TARGETDIR)/$(TARGETDIR).elf +ROOT := .. +LIBRARY_DIRS := ${ROOT}/crt0 +LIBRARY_FILES := crt0 + +MARCH :=-march=rv64imfdczicbom +MABI :=-mabi=lp64d +LINKER := ${ROOT}/linker8000-0000.x +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map + +CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2 +CC=riscv64-unknown-elf-gcc +DA=riscv64-unknown-elf-objdump -d + + +include $(ROOT)/makefile.inc + + diff --git a/tests/custom/lpddrtest/header.h b/tests/custom/lpddrtest/header.h new file mode 100755 index 0000000000..7e83cb22d4 --- /dev/null +++ b/tests/custom/lpddrtest/header.h @@ -0,0 +1,5 @@ +#ifndef __header +#define __header + +void lpddr_test(); +#endif diff --git a/tests/custom/lpddrtest/lpddr_test.s b/tests/custom/lpddrtest/lpddr_test.s new file mode 100755 index 0000000000..0fe8d77ee4 --- /dev/null +++ b/tests/custom/lpddrtest/lpddr_test.s @@ -0,0 +1,30 @@ +.section .text +.globl lpddr_test +.type lpddr_test, @function +lpddr_test: + li t1, 0x90000000 + addi t5, t1, 0 + li t2, 0xAABBCCDD00112233 + + li t3, 10 + li t4, 0 +loop_write: + beq t4, t3, done_write + sd t2, 0(t5) + cbo.clean 0(t5) + addi t5, t5, 8 + addi t4, t4, 1 + j loop_write +done_write: + + li t4, 0 + addi t5, t1, 0 +loop_read: + beq t4, t3, done_read + ld t6, 0(t5) + addi t5, t5, 8 + addi t4, t4, 1 + j loop_read +done_read: + ret + diff --git a/tests/custom/lpddrtest/main.c b/tests/custom/lpddrtest/main.c new file mode 100755 index 0000000000..feafa5f758 --- /dev/null +++ b/tests/custom/lpddrtest/main.c @@ -0,0 +1,6 @@ +#include "header.h" + +int main(){ + lpddr_test(); + return 0; +}