diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv
index e81152dcf9..0d4a34ccd0 100644
--- a/verif/env/uvme/uvme_cva6_cfg.sv
+++ b/verif/env/uvme/uvme_cva6_cfg.sv
@@ -58,9 +58,6 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
    // Zihpm extension
    rand bit                      ext_zihpm_supported;
 
-   // hypervisor mode
-   rand bit                      mode_h_supported;
-
    // Handle to RTL configuration
    rand cva6_cfg_t         CVA6Cfg;
 
@@ -75,7 +72,6 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
       `uvm_field_int (                         HPDCache_supported          , UVM_DEFAULT          )
       `uvm_field_int (                         nr_pmp_entries              , UVM_DEFAULT          )
       `uvm_field_int (                         ext_zihpm_supported         , UVM_DEFAULT          )
-      `uvm_field_int (                         mode_h_supported            , UVM_DEFAULT          )
       `uvm_field_int (                         sys_clk_period            , UVM_DEFAULT + UVM_DEC)
 
       `uvm_field_object(clknrst_cfg, UVM_DEFAULT)
@@ -297,9 +293,7 @@ function void uvme_cva6_cfg_c::set_unsupported_csr_mask();
    super.set_unsupported_csr_mask();
 
    // Remove unsupported CSRs for Embedded configuration
-   unsupported_csr_mask[uvma_core_cntrl_pkg::MTVAL2] = 1;
    unsupported_csr_mask[uvma_core_cntrl_pkg::MCOUNTINHIBIT] = 1;
-   unsupported_csr_mask[uvma_core_cntrl_pkg::MTINST] = 1;
 
    // Add supported CSRs for Embedded configuration
    for (int i = 0; i < MAX_NUM_HPMCOUNTERS; i++) begin
diff --git a/verif/tb/core/uvma_cva6pkg_utils.sv b/verif/tb/core/uvma_cva6pkg_utils.sv
index d49b0e5c36..0ea140691f 100644
--- a/verif/tb/core/uvma_cva6pkg_utils.sv
+++ b/verif/tb/core/uvma_cva6pkg_utils.sv
@@ -49,6 +49,7 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
     cfg.disable_all_csr_checks = 0;
     cfg.mode_s_supported = CVA6Cfg.RVS;
     cfg.mode_u_supported = CVA6Cfg.RVU;
+    cfg.mode_h_supported = CVA6Cfg.RVH;
 
     cfg.pmp_supported = (CVA6Cfg.NrPMPEntries > 0);
     cfg.pmp_regions = CVA6Cfg.NrPMPEntries;
@@ -57,6 +58,11 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
     cfg.unsupported_csr_mask['h643] = 1; // HTVAL
     cfg.unsupported_csr_mask['h64A] = 1; // HTINST
 
+    if (!cfg.mode_h_supported) begin
+      cfg.unsupported_csr_mask['h34A] = 1; // MTINST
+      cfg.unsupported_csr_mask['h34B] = 1; // MTVAL2
+    end
+
     // Disable comparison
     cfg.unsupported_csr_mask['h7C0] = 1; // ICACHE
     cfg.unsupported_csr_mask['h7C1] = 1; // DCACHE