diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv
index c1c91bae8e..27e40485d9 100644
--- a/core/cache_subsystem/wt_dcache.sv
+++ b/core/cache_subsystem/wt_dcache.sv
@@ -168,7 +168,7 @@ module wt_dcache
   // read controllers (LD unit and PTW/MMU)
   ///////////////////////////////////////////////////////
 
-  // 0 is used by PTW, 1 by READ and 2 by STORE access requests
+  // 0 is used by PTW, 1 by READ and 2 by WRITE access requests
   for (genvar k = 0; k < NumPorts - 1; k++) begin : gen_rd_ports
     // set these to high prio ports
     if (k != 0 || MMU_PRESENT) begin