From ba90355635b16bee93d3ce2c83b6166f3af3d0f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= Date: Fri, 3 Nov 2023 07:02:13 +0100 Subject: [PATCH] Trap DV plan: update after internal review MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: André Sintzoff --- verif/docs/VerifPlans/source/dvplan_traps.md | 155 +++++++++++-------- verif/docs/VerifPlans/traps/VP_IP000.yml | 37 ++++- verif/docs/VerifPlans/traps/VP_IP001.yml | 33 ---- verif/docs/VerifPlans/traps/VP_IP002.yml | 8 +- verif/docs/VerifPlans/traps/VP_IP004.yml | 32 ---- verif/docs/VerifPlans/traps/VP_IP007.yml | 48 ++++-- verif/docs/VerifPlans/traps/VP_IP008.yml | 34 +++- verif/docs/VerifPlans/traps/VP_IP009.yml | 32 +++- verif/docs/VerifPlans/traps/VP_IP010.yml | 4 +- verif/docs/VerifPlans/traps/VP_IP011.yml | 32 +++- verif/docs/VerifPlans/traps/VP_IP012.yml | 79 ---------- verif/docs/VerifPlans/traps/runme.sh | 2 +- 12 files changed, 253 insertions(+), 243 deletions(-) delete mode 100644 verif/docs/VerifPlans/traps/VP_IP001.yml delete mode 100644 verif/docs/VerifPlans/traps/VP_IP004.yml delete mode 100644 verif/docs/VerifPlans/traps/VP_IP012.yml diff --git a/verif/docs/VerifPlans/source/dvplan_traps.md b/verif/docs/VerifPlans/source/dvplan_traps.md index f0a1b99587..e14215b092 100644 --- a/verif/docs/VerifPlans/source/dvplan_traps.md +++ b/verif/docs/VerifPlans/source/dvplan_traps.md @@ -6,13 +6,13 @@ #### Item: 000 -* **Requirement location:** Unprivileged ISA Version 20191213, Chapter 1.5 +* **Requirement location:** Unprivileged ISA Version 20191213, Chapter 2.2 * **Feature Description** - Opcodes that do not decode to a valid, supported instruction for the CVA6 core configuration shall raise an illegal instruction exception. + The behavior upon decoding a reserved instruction is unspecified. Opcodes that do not decode to a valid, supported instruction for the CVA6 core configuration shall raise an illegal instruction exception. * **Verification Goals** - Check that when executing any illegal instruction, an exception is raised with `mcause` CSR set to 0x2. + Check that when executing any illegal instruction, an exception is raised with `mcause` set to 0x2. * **Pass/Fail Criteria:** Check RM * **Test Type:** Constrained Random * **Coverage Method:** Code Coverage @@ -21,30 +21,27 @@ * **Link to Coverage:** * **Comments** - Covered by ISACOV -## Feature: Load x0 - -### Sub-feature: 000_load_x0 + Covered by ISACOV tests, not yet in ISACOV DV plan +### Sub-feature: 001_mtval #### Item: 000 -* **Requirement location:** Unprivileged ISA Version 20191213, Chapter 2.6 +* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.16 * **Feature Description** - `x0` register cannot have a value loaded into it but does not generate an exception when that is attempted, as the exception is not implemented. + When an illegal instruction exception is raised, the corresponding instruction is stored into `mtval` CSR. * **Verification Goals** - Check that loading to `x0` register does not cause an exception. -* **Pass/Fail Criteria:** Check RM -* **Test Type:** Constrained Random -* **Coverage Method:** Functional Coverage + Check that when any illegal instruction exception is raised, `mtval` CSR contains the faulting instruction. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) * **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 -* **Unique verification tag:** VP_traps_F001_S000_I000 +* **Unique verification tag:** VP_traps_F000_S001_I000 * **Link to Coverage:** * **Comments** - *(none)* - + ZERO_TVAL parameter value? ## Feature: CSR Access ### Sub-feature: 000_CSR_access @@ -67,7 +64,8 @@ * **Comments** Covered by CSR DV plan. - Verify if `mcause` value check is covered by CSR DV plan. + VP_csr-embedded-access_F001_S002_I000 + Verify if `mcause` value check is covered by CSR tests. #### Item: 001 * **Requirement location:** Privileged Architecture Version 20211203, Chapter 2.1 @@ -86,7 +84,8 @@ * **Comments** Covered by CSR DV plan. - Verify if `mcause` value check is covered by CSR DV plan. + VP_csr-embedded-access_F001_S001_I000 + Verify if `mcause` value check is covered by CSR tests. ## Feature: Machine Trap Vector ### Sub-feature: 000_mtvec @@ -110,29 +109,6 @@ *(none)* -## Feature: Machine Cause - -### Sub-feature: 000_mcause - -#### Item: 000 - -* **Requirement location:** Privileged Architecture Version 20211203, 3.1.15 -* **Feature Description** - - `mcause` is set to exception cause upon entry into exception. -* **Verification Goals** - - Check that `mcause` correctly identifies the exception taken. -* **Pass/Fail Criteria:** Check RM -* **Test Type:** Constrained Random -* **Coverage Method:** Functional Coverage -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 -* **Unique verification tag:** VP_traps_F004_S000_I000 -* **Link to Coverage:** -* **Comments** - - *(none)* - ## Feature: Machine Exception Program Counter ### Sub-feature: 000_mepc @@ -255,21 +231,23 @@ - code=0x8, 0x9, 0xB: Environment call from U-mode, from S-mode, from M-mode - code=0x3: Environment break - code=0x3: Load/store/AMO address breakpoint - - code=0x4, 0x6: Load address misaligned, store/AMO address misaligned (CHECK IF NOT LOWEST PRIORITY ON CVA6) - - code=0xD, 0xF, 0x5, 0x7: Load page fault, store/AMO page fault, load access fault, store/AMO access fault + - code=0xD, 0xF, 0x5, 0x7: Load page fault, store/AMO page fault, load access fault, store/AMO access fault + - code=0x4, 0x6: Load address misaligned, store/AMO address misaligned * **Verification Goals** Check that when raising an exception together with a lower priority one the cause of the higher priority exception is written in `mcause` register. * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** Directed Non-SelfChk * **Coverage Method:** Testcase -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F007_S000_I000 * **Link to Coverage:** * **Comments** *(none)* +### Sub-feature: 001_exception priority embedded + ## Feature: Address Misaligned ### Sub-feature: 000_instr_misaligned @@ -325,7 +303,7 @@ * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F008_S001_I001 * **Link to Coverage:** * **Comments** @@ -365,7 +343,7 @@ * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F008_S002_I001 * **Link to Coverage:** * **Comments** @@ -380,17 +358,37 @@ If not aligned AMO is attempted, a store/AMO access misaligned exception is taken. * **Verification Goals** - Exception is entered with mcause set to 0x6. + Exception is entered with `mcause` set to 0x6. * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F008_S002_I002 * **Link to Coverage:** * **Comments** *(none)* +### Sub-feature: 003_mtval + +#### Item: 000 + +* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.16 +* **Feature Description** + + When an address misaligned exception is raised, the corresponding address is stored into `mtval` CSR. +* **Verification Goals** + + Check that when any address misaligned exception is raised, `mtval` CSR contains the address of the portion of the access causing the fault. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_traps_F008_S003_I000 +* **Link to Coverage:** +* **Comments** + + ZERO_TVAL parameter value? ## Feature: Access Fault ### Sub-feature: 000_instr_access @@ -465,7 +463,7 @@ * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F009_S001_I001 * **Link to Coverage:** * **Comments** @@ -505,7 +503,7 @@ * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F009_S002_I001 * **Link to Coverage:** * **Comments** @@ -524,13 +522,33 @@ * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F009_S002_I002 * **Link to Coverage:** * **Comments** *(none)* +### Sub-feature: 003_mtval + +#### Item: 000 + +* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.16 +* **Feature Description** + + When an access fault exception is raised, the corresponding address is stored into `mtval` CSR. +* **Verification Goals** + + Check that when any access fault exception is raised, `mtval` CSR contains the address of the portion of the access causing the fault. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_traps_F009_S003_I000 +* **Link to Coverage:** +* **Comments** + + ZERO_TVAL parameter value? ## Feature: Environment Call ### Sub-feature: 000_ecall @@ -566,7 +584,7 @@ * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F010_S000_I001 * **Link to Coverage:** * **Comments** @@ -585,7 +603,7 @@ * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F010_S000_I002 * **Link to Coverage:** * **Comments** @@ -608,7 +626,7 @@ * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F011_S000_I000 * **Link to Coverage:** * **Comments** @@ -628,7 +646,7 @@ * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F011_S001_I000 * **Link to Coverage:** * **Comments** @@ -648,17 +666,30 @@ * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) -* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 * **Unique verification tag:** VP_traps_F011_S002_I000 * **Link to Coverage:** * **Comments** MMU related -## Feature: Breakpoint - -### Sub-feature: 000_instr_bkp - -### Sub-feature: 001_data_bkp +### Sub-feature: 003_mtval -### Sub-feature: 002_environment_break +#### Item: 000 +* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.16 +* **Feature Description** + + When an page fault exception is raised, the corresponding address is stored into `mtval` CSR. +* **Verification Goals** + + Check that when any page fault exception is raised, `mtval` CSR contains the address of the portion of the access causing the fault. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV64A6-step3 +* **Unique verification tag:** VP_traps_F011_S003_I000 +* **Link to Coverage:** +* **Comments** + + MMU related + ZERO_TVAL parameter value? diff --git a/verif/docs/VerifPlans/traps/VP_IP000.yml b/verif/docs/VerifPlans/traps/VP_IP000.yml index fead1b7c42..bf6fc9ef74 100644 --- a/verif/docs/VerifPlans/traps/VP_IP000.yml +++ b/verif/docs/VerifPlans/traps/VP_IP000.yml @@ -1,5 +1,5 @@ !Feature -next_elt_id: 1 +next_elt_id: 2 name: Illegal Instruction id: 0 display_order: 0 @@ -13,21 +13,46 @@ subfeatures: !!omap - '000': !VerifItem name: '000' tag: VP_traps_F000_S000_I000 - description: Opcodes that do not decode to a valid, supported instruction - for the CVA6 core configuration shall raise an illegal instruction exception. - reqt_doc: Unprivileged ISA Version 20191213, Chapter 1.5 + description: The behavior upon decoding a reserved instruction is unspecified. + Opcodes that do not decode to a valid, supported instruction for the CVA6 + core configuration shall raise an illegal instruction exception. + reqt_doc: Unprivileged ISA Version 20191213, Chapter 2.2 ref_mode: page ref_page: '' ref_section: '' ref_viewer: firefox verif_goals: Check that when executing any illegal instruction, an exception - is raised with `mcause` CSR set to 0x2. + is raised with `mcause` set to 0x2. pfc: 3 test_type: 3 cov_method: 3 cores: 56 coverage_loc: '' - comments: Covered by ISACOV + comments: Covered by ISACOV tests, not yet in ISACOV DV plan +- 001_mtval: !Subfeature + name: 001_mtval + tag: VP_traps_F000_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_traps_F000_S001_I000 + description: When an illegal instruction exception is raised, the corresponding + instruction is stored into `mtval` CSR. + reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16 + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that when any illegal instruction exception is raised, + `mtval` CSR contains the faulting instruction. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: ZERO_TVAL parameter value? vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' diff --git a/verif/docs/VerifPlans/traps/VP_IP001.yml b/verif/docs/VerifPlans/traps/VP_IP001.yml deleted file mode 100644 index 3a3c0443f2..0000000000 --- a/verif/docs/VerifPlans/traps/VP_IP001.yml +++ /dev/null @@ -1,33 +0,0 @@ -!Feature -next_elt_id: 1 -name: Load x0 -id: 1 -display_order: 1 -subfeatures: !!omap -- 000_load_x0: !Subfeature - name: 000_load_x0 - tag: VP_traps_F001_S000 - next_elt_id: 1 - display_order: 0 - items: !!omap - - '000': !VerifItem - name: '000' - tag: VP_traps_F001_S000_I000 - description: '`x0` register cannot have a value loaded into it but does not - generate an exception when that is attempted, as the exception is not implemented.' - reqt_doc: Unprivileged ISA Version 20191213, Chapter 2.6 - ref_mode: page - ref_page: '' - ref_section: '' - ref_viewer: firefox - verif_goals: Check that loading to `x0` register does not cause an exception. - pfc: 3 - test_type: 3 - cov_method: 1 - cores: 56 - coverage_loc: '' - comments: '' -vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' -io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' -config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' -ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/traps/VP_IP002.yml b/verif/docs/VerifPlans/traps/VP_IP002.yml index 1c239b2d5e..0138c2de4f 100644 --- a/verif/docs/VerifPlans/traps/VP_IP002.yml +++ b/verif/docs/VerifPlans/traps/VP_IP002.yml @@ -27,8 +27,8 @@ subfeatures: !!omap cov_method: -1 cores: 56 coverage_loc: '' - comments: "Covered by CSR DV plan.\nVerify if `mcause` value check is covered\ - \ by CSR DV plan." + comments: "Covered by CSR DV plan.\nVP_csr-embedded-access_F001_S002_I000\n + Verify if `mcause` value check is covered by CSR tests." - '001': !VerifItem name: '001' tag: VP_traps_F002_S000_I001 @@ -46,8 +46,8 @@ subfeatures: !!omap cov_method: -1 cores: 56 coverage_loc: '' - comments: "Covered by CSR DV plan.\nVerify if `mcause` value check is covered\ - \ by CSR DV plan." + comments: "Covered by CSR DV plan.\nVP_csr-embedded-access_F001_S001_I000\n + Verify if `mcause` value check is covered by CSR tests." vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' diff --git a/verif/docs/VerifPlans/traps/VP_IP004.yml b/verif/docs/VerifPlans/traps/VP_IP004.yml deleted file mode 100644 index edbf042cb8..0000000000 --- a/verif/docs/VerifPlans/traps/VP_IP004.yml +++ /dev/null @@ -1,32 +0,0 @@ -!Feature -next_elt_id: 1 -name: Machine Cause -id: 4 -display_order: 4 -subfeatures: !!omap -- 000_mcause: !Subfeature - name: 000_mcause - tag: VP_traps_F004_S000 - next_elt_id: 1 - display_order: 0 - items: !!omap - - '000': !VerifItem - name: '000' - tag: VP_traps_F004_S000_I000 - description: '`mcause` is set to exception cause upon entry into exception.' - reqt_doc: Privileged Architecture Version 20211203, 3.1.15 - ref_mode: page - ref_page: '' - ref_section: '' - ref_viewer: firefox - verif_goals: Check that `mcause` correctly identifies the exception taken. - pfc: 3 - test_type: 3 - cov_method: 1 - cores: 56 - coverage_loc: '' - comments: '' -vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' -io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' -config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' -ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/traps/VP_IP007.yml b/verif/docs/VerifPlans/traps/VP_IP007.yml index ac10f5e363..dd0ef06b23 100644 --- a/verif/docs/VerifPlans/traps/VP_IP007.yml +++ b/verif/docs/VerifPlans/traps/VP_IP007.yml @@ -1,5 +1,5 @@ !Feature -next_elt_id: 1 +next_elt_id: 2 name: Exception Priority id: 7 display_order: 7 @@ -13,15 +13,14 @@ subfeatures: !!omap - '000': !VerifItem name: '000' tag: VP_traps_F007_S000_I000 - description: "Exceptions are of lower priority than all interrupts.\nException\ - \ priority (high to low)\n- code=0x3: Instruction address breakpoint\n-\ - \ code=0xC, 0x1: Instruction page fault, instruction access fault\n- code=0x2:\ - \ Illegal instruction\n- code=0x8, 0x9, 0xB: Environment call from U-mode,\ - \ from S-mode, from M-mode\n- code=0x3: Environment break\n- code=0x3: Load/store/AMO\ - \ address breakpoint\n- code=0x4, 0x6: Load address misaligned, store/AMO\ - \ address misaligned (CHECK IF NOT LOWEST PRIORITY ON CVA6)\n- code=0xD,\ - \ 0xF, 0x5, 0x7: Load page fault, store/AMO page fault, load access fault,\ - \ store/AMO access fault" + description: "Exceptions are of lower priority than all interrupts.\nException + priority (high to low)\n- code=0x3: Instruction address breakpoint\n- code=0xC, + 0x1: Instruction page fault, instruction access fault\n- code=0x2: Illegal + instruction\n- code=0x8, 0x9, 0xB: Environment call from U-mode, from S-mode, + from M-mode\n- code=0x3: Environment break\n- code=0x3: Load/store/AMO address + breakpoint\n- code=0xD, 0xF, 0x5, 0x7: Load page fault, store/AMO page fault, + load access fault, store/AMO access fault\n- code=0x4, 0x6: Load address + misaligned, store/AMO address misaligned" reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.15 ref_mode: page ref_page: '' @@ -32,7 +31,34 @@ subfeatures: !!omap pfc: -1 test_type: 2 cov_method: 0 - cores: 56 + cores: 40 + coverage_loc: '' + comments: '' +- 001_exception priority embedded: !Subfeature + name: 001_exception priority embedded + tag: VP_traps_F007_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_traps_F007_S001_I000 + description: "Exceptions are of lower priority than all interrupts.\nException + priority (high to low)\n- code=0x1: Instruction access fault\n- code=0x2: + Illegal instruction\n- code=0xB: Environment call from M-mode\n- code=0x5, + 0x7: Load access fault, store access fault\n- code=0x4, 0x6: Load address + misaligned, store address misaligned" + reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.15 + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that when raising an exception together with a lower priority + one the cause of the higher priority exception is written in `mcause` register. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 coverage_loc: '' comments: '' vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' diff --git a/verif/docs/VerifPlans/traps/VP_IP008.yml b/verif/docs/VerifPlans/traps/VP_IP008.yml index c20b9863d2..c33f65672f 100644 --- a/verif/docs/VerifPlans/traps/VP_IP008.yml +++ b/verif/docs/VerifPlans/traps/VP_IP008.yml @@ -1,5 +1,5 @@ !Feature -next_elt_id: 1 +next_elt_id: 2 name: Address Misaligned id: 8 display_order: 8 @@ -64,7 +64,7 @@ subfeatures: !!omap pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: '' - 002_store_misaligned: !Subfeature @@ -104,7 +104,7 @@ subfeatures: !!omap pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: '' - '002': !VerifItem @@ -117,13 +117,37 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: firefox - verif_goals: Exception is entered with mcause set to 0x6. + verif_goals: Exception is entered with `mcause` set to 0x6. pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: '' +- 003_mtval: !Subfeature + name: 003_mtval + tag: VP_traps_F008_S003 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_traps_F008_S003_I000 + description: When an address misaligned exception is raised, the corresponding + address is stored into `mtval` CSR. + reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16 + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that when any address misaligned exception is raised, `mtval` + CSR contains the address of the portion of the access causing the fault. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: ZERO_TVAL parameter value? vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' diff --git a/verif/docs/VerifPlans/traps/VP_IP009.yml b/verif/docs/VerifPlans/traps/VP_IP009.yml index 9c3722f46e..ac175087a8 100644 --- a/verif/docs/VerifPlans/traps/VP_IP009.yml +++ b/verif/docs/VerifPlans/traps/VP_IP009.yml @@ -1,5 +1,5 @@ !Feature -next_elt_id: 1 +next_elt_id: 2 name: Access Fault id: 9 display_order: 9 @@ -81,7 +81,7 @@ subfeatures: !!omap pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: '' - 002_store_amo_access: !Subfeature @@ -122,7 +122,7 @@ subfeatures: !!omap pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: '' - '002': !VerifItem @@ -139,9 +139,33 @@ subfeatures: !!omap pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: '' +- 003_mtval: !Subfeature + name: 003_mtval + tag: VP_traps_F009_S003 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_traps_F009_S003_I000 + description: When an access fault exception is raised, the corresponding address + is stored into `mtval` CSR. + reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16 + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that when any access fault exception is raised, `mtval` + CSR contains the address of the portion of the access causing the fault. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: ZERO_TVAL parameter value? vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' diff --git a/verif/docs/VerifPlans/traps/VP_IP010.yml b/verif/docs/VerifPlans/traps/VP_IP010.yml index 815aee0da1..cf7bac0e81 100644 --- a/verif/docs/VerifPlans/traps/VP_IP010.yml +++ b/verif/docs/VerifPlans/traps/VP_IP010.yml @@ -41,7 +41,7 @@ subfeatures: !!omap pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: '' - '002': !VerifItem @@ -58,7 +58,7 @@ subfeatures: !!omap pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: '' vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' diff --git a/verif/docs/VerifPlans/traps/VP_IP011.yml b/verif/docs/VerifPlans/traps/VP_IP011.yml index 78ffd843d0..e0b9b06153 100644 --- a/verif/docs/VerifPlans/traps/VP_IP011.yml +++ b/verif/docs/VerifPlans/traps/VP_IP011.yml @@ -1,5 +1,5 @@ !Feature -next_elt_id: 1 +next_elt_id: 2 name: Page Fault id: 11 display_order: 11 @@ -24,7 +24,7 @@ subfeatures: !!omap pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: MMU related - 001_load_page: !Subfeature @@ -47,7 +47,7 @@ subfeatures: !!omap pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: MMU related - 002_store_page: !Subfeature @@ -70,9 +70,33 @@ subfeatures: !!omap pfc: -1 test_type: -1 cov_method: -1 - cores: 56 + cores: 40 coverage_loc: '' comments: MMU related +- 003_mtval: !Subfeature + name: 003_mtval + tag: VP_traps_F011_S003 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_traps_F011_S003_I000 + description: When an page fault exception is raised, the corresponding address + is stored into `mtval` CSR. + reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16 + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that when any page fault exception is raised, `mtval` CSR + contains the address of the portion of the access causing the fault. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 40 + coverage_loc: '' + comments: "MMU related\nZERO_TVAL parameter value?" vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' diff --git a/verif/docs/VerifPlans/traps/VP_IP012.yml b/verif/docs/VerifPlans/traps/VP_IP012.yml deleted file mode 100644 index 8223432fba..0000000000 --- a/verif/docs/VerifPlans/traps/VP_IP012.yml +++ /dev/null @@ -1,79 +0,0 @@ -!Feature -next_elt_id: 1 -name: Breakpoint -id: 12 -display_order: 12 -subfeatures: !!omap -- 000_instr_bkp: !Subfeature - name: 000_instr_bkp - tag: VP_traps_F012_S000 - next_elt_id: 2 - display_order: 0 - items: !!omap - - '000': !VerifItem - name: '000' - tag: VP_traps_F012_S000_I000 - description: When an instruction address has a trigger set for it and `mcontrol6.action - == 0` then a breakpoint exception is taken. - reqt_doc: Debug Specification Version 1.0, Chapter 5.6.12 - ref_mode: page - ref_page: '' - ref_section: '' - ref_viewer: firefox - verif_goals: Breakpoint exception is entered with `mcause` set to 0x3. - pfc: 3 - test_type: 3 - cov_method: 1 - cores: 48 - coverage_loc: '' - comments: Need debug support -- 001_data_bkp: !Subfeature - name: 001_data_bkp - tag: VP_traps_F012_S001 - next_elt_id: 1 - display_order: 0 - items: !!omap - - '000': !VerifItem - name: '000' - tag: VP_traps_F012_S001_I000 - description: When a load/store/AMO address has a trigger set for it and `mcontrol6.action - == 0` then a breakpoint exception is taken. - reqt_doc: Debug Specification Version 1.0, Chapter 5.6.12 - ref_mode: page - ref_page: '' - ref_section: '' - ref_viewer: firefox - verif_goals: Breakpoint exception is entered with `mcause` set to 0x3. - pfc: 3 - test_type: 3 - cov_method: 1 - cores: 48 - coverage_loc: '' - comments: Need debug support -- 002_environment_break: !Subfeature - name: 002_environment_break - tag: VP_traps_F012_S002 - next_elt_id: 1 - display_order: 0 - items: !!omap - - '000': !VerifItem - name: '000' - tag: VP_traps_F012_S002_I000 - description: If an `EBREAK` or `C.EBREAK` is executed and `dcsr.ebreakm` is - 0 then a breakpoint exception is taken. - reqt_doc: Debug Specification Version 1.0, Chapter 4.9.1 - ref_mode: page - ref_page: '' - ref_section: '' - ref_viewer: firefox - verif_goals: Breakpoint exception is entered with `mcause` set to 0x3. - pfc: 3 - test_type: 3 - cov_method: 1 - cores: 48 - coverage_loc: '' - comments: Need debug support -vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' -io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' -config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' -ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/traps/runme.sh b/verif/docs/VerifPlans/traps/runme.sh index 1fccec7a68..6df0e9f675 100644 --- a/verif/docs/VerifPlans/traps/runme.sh +++ b/verif/docs/VerifPlans/traps/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* +sh $ROOTDIR/../../../../verif/core-v-verif/tools/vptool/vptool.sh $*