diff --git a/docs/design/build.mk b/docs/design/build.mk
index e7e29085a9..c401016342 100644
--- a/docs/design/build.mk
+++ b/docs/design/build.mk
@@ -26,8 +26,8 @@ setup:
 
 	cp -rf source/* build/source
 
-	cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -i templates/isa_template.yaml -m updaters/cv32a65x/isa_updater.yaml -t cv32a65x -f adoc
-	cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -c ../riscv-config/cv32a65x/generated/custom_gen.yaml -m updaters/cv32a65x/csr_updater.yaml -t cv32a65x -f adoc
+	cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/$(CONFIG)/generated/isa_gen.yaml -i templates/isa_template.yaml -m updaters/$(CONFIG)/isa_updater.yaml -t $(CONFIG) -f adoc
+	cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/$(CONFIG)/generated/isa_gen.yaml -c ../riscv-config/$(CONFIG)/generated/custom_gen.yaml -m updaters/$(CONFIG)/csr_updater.yaml -t $(CONFIG) -f adoc
 	cp -r $(design_dir)/../../config/gen_from_riscv_config/$(CONFIG)/* build/source
 
 	cd ../.. && python3 scripts/spec_builder.py --target $(CONFIG) --gen-config $(current_dir)/build/source/config.adoc --gen-parameters $(current_dir)/build/source/parameters.adoc --gen-ports $(current_dir)/build/source
diff --git a/docs/design/design-manual/source/intro.adoc b/docs/design/design-manual/source/intro.adoc
index 927a69af1a..ba3237458c 100644
--- a/docs/design/design-manual/source/intro.adoc
+++ b/docs/design/design-manual/source/intro.adoc
@@ -74,7 +74,7 @@ https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/.
 University,
 https://parallel.princeton.edu/openpiton/docs/micro_arch.pdf.
 
-CV32A6 is a standards-compliant 32-bit processor fully compliant with
+{ohg-config} is a standards-compliant {XLEN}-bit processor fully compliant with
 RISC-V specifications: [RVunpriv], [RVpriv] and [RVdbg] and passes
 [RVcompat] compatibility tests, as requested by [GEN-10] in [CVA6req].
 
diff --git a/docs/design/design-manual/source/mmu.adoc b/docs/design/design-manual/source/mmu.adoc
index 204fac8232..d41f6859d2 100644
--- a/docs/design/design-manual/source/mmu.adoc
+++ b/docs/design/design-manual/source/mmu.adoc
@@ -622,7 +622,7 @@ shows the entry selection for replacement.
 |*Path Traverse* |*PLRU Bits* |*Entry to replace*
 a|
 0 -> 1 -> 3::
-  * 
+  *
 
  a|
 ___
@@ -642,7 +642,7 @@ _
 
 a|
 0 -> 1 -> 4::
-  * 
+  *
 
  a|
 ___
@@ -662,7 +662,7 @@ _
 
 a|
 0 -> 2 -> 5::
-  * 
+  *
 
  a|
 ___
@@ -682,7 +682,7 @@ _
 
 a|
 0 -> 2 -> 6::
-  * 
+  *
 
  a|
 ___
@@ -931,7 +931,7 @@ Page Table Walker
 -----------------
 
 The "CVA6 Page Table Walker (PTW) for MMU Sv32" is a hardware module
-developed for the CV32A6 processor architecture, designed to facilitate
+developed for the CVA6 processor architecture, designed to facilitate
 the translation of virtual addresses into physical addresses, a crucial
 task in memory access management.
 
@@ -946,7 +946,7 @@ Key features of this PTW module include support for two levels of page
 tables (LVL1 and LVL2) in the Sv32 standard, accommodating instruction
 and data page table walks. It rigorously validates and verifies page
 table entries (PTEs) to ensure translation accuracy and adherence to
-access permissions. This module seamlessly integrates with the CV32A6
+access permissions. This module seamlessly integrates with the CVA6
 processor's memory management unit (MMU), which governs memory access
 control. It also takes into account global mapping, access flags, and
 privilege levels during the translation process, ensuring that memory