From 66dc8f948eafbb36acf700707b31bf313703d0fe Mon Sep 17 00:00:00 2001 From: Olivier Betschi Date: Thu, 3 Oct 2024 18:21:51 +0200 Subject: [PATCH] Retrieve latest updates and apply verible formatting --- core/ahb_adapter/ahb_master_adapter.sv | 16 +-- core/ahb_adapter/ahb_slave_adapter.sv | 191 +++++++++---------------- core/scratchpad/dscr_controller.sv | 41 +++--- core/scratchpad/iscr_controller.sv | 19 ++- core/scratchpad/sram_controller.sv | 28 ++-- 5 files changed, 114 insertions(+), 181 deletions(-) diff --git a/core/ahb_adapter/ahb_master_adapter.sv b/core/ahb_adapter/ahb_master_adapter.sv index 1dbec24afa..84276e0213 100644 --- a/core/ahb_adapter/ahb_master_adapter.sv +++ b/core/ahb_adapter/ahb_master_adapter.sv @@ -50,8 +50,8 @@ module ahb_master_adapter SINGLE, PIPELINE_STALL, SINGLE_STALL - } ahb_ctrl_e; - ahb_ctrl_e ahb_ctrl_fsm; + } ahb_ctrl_m_e; + ahb_ctrl_m_e ahb_ctrl_fsm; // Not supported assign req_port_o.data_ruser = '0; @@ -157,12 +157,12 @@ module ahb_master_adapter assign ahb_p_req_o.hprot = ahb_pkg::AHBProtWidth'('b0011); always_comb begin - htrans_d = '0; + htrans_d = ahb_pkg::AhbTransIdle; haddr_d = '0; - hsize_d = '0; + hsize_d = ahb_pkg::AhbSizeByte; hwrite_d = '0; if (ahb_ctrl_fsm == PIPELINE_STALL) begin //send the registered value during stall - htrans_d = ahb_pkg::AHB_TRANS_NONSEQ; + htrans_d = ahb_pkg::AhbTransNonseq; haddr_d = haddr_q; hsize_d = hsize_q; hwrite_d = hwrite_q; @@ -170,10 +170,10 @@ module ahb_master_adapter haddr_d = req_port_i.vaddr; hsize_d = {1'b0, req_port_i.data_size}; hwrite_d = req_port_i.data_we; - if (req_port_i.data_req) begin - htrans_d = ahb_pkg::AHB_TRANS_NONSEQ; + if (transfer_req) begin + htrans_d = ahb_pkg::AhbTransNonseq; end else begin - htrans_d = ahb_pkg::AHB_TRANS_IDLE; + htrans_d = ahb_pkg::AhbTransIdle; end end end diff --git a/core/ahb_adapter/ahb_slave_adapter.sv b/core/ahb_adapter/ahb_slave_adapter.sv index 82a959cea1..d52ffad7b8 100644 --- a/core/ahb_adapter/ahb_slave_adapter.sv +++ b/core/ahb_adapter/ahb_slave_adapter.sv @@ -23,10 +23,6 @@ module ahb_slave_adapter output ahb_resp_t ahb_s_resp_o, input ahb_req_t ahb_s_req_i, - // Request from AHB acknowledged - input logic req_ack_i, - output logic ahb_burst_o, - // dreq Interface translation input dcache_req_o_t req_port_i, output scratchpad_req_i_t req_port_o @@ -34,30 +30,31 @@ module ahb_slave_adapter // AHB signals logic hready_d; - logic hresp_d; logic [CVA6Cfg.XLEN-1:0] hrdata_d; // Req port signals logic [CVA6Cfg.VLEN-1:0] vaddr_d, vaddr_q; - logic [CVA6Cfg.XLEN-1:0] wdata_d, wdata_q; - logic [1:0] size_d, size_q; - logic data_be_d, data_we_d, data_req_d; + logic [1:0] size_q; + logic data_we_d, data_req_d; + logic [CVA6Cfg.XLEN/8-1:0] data_be_d; + // helper signal + logic ahb_transfer_req; // htrans values - typedef enum logic [2:0] { + typedef enum logic [1:0] { S_IDLE, - S_BUSY, - S_NONSEQ_READ, - S_NONSEQ_WRITE, - S_SEQ_READ, - S_SEQ_WRITE - } ahb_ctrl_e; - ahb_ctrl_e state_q, state_d; + S_WRITE, + S_READ, + S_READ_DATA + } ahb_ctrl_s_e; + ahb_ctrl_s_e state_q, state_d; + + assign ahb_transfer_req = (hready_d && (ahb_s_req_i.htrans == AhbTransNonseq || ahb_s_req_i.htrans == AhbTransSeq)) ? 1'b1 : 1'b0; // ------------------- // FSM: Current State // ------------------- - always_ff @(posedge clk_i or negedge rst_ni) begin : p_next_state + always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_state if (~rst_ni) begin state_q <= S_IDLE; end else begin @@ -68,71 +65,36 @@ module ahb_slave_adapter // -------------------- // FSM: Next State // -------------------- + // Busy value of htrans is handled implicitely like an idle state + // - always_comb begin : p_current_state + always_comb begin : p_fsm_next state_d = state_q; case (state_q) S_IDLE: begin state_d = S_IDLE; - if (ahb_s_req_i.htrans == AHB_TRANS_NONSEQ) begin - if (ahb_s_req_i.hwrite) state_d = S_NONSEQ_WRITE; - else state_d = S_NONSEQ_READ; + if (ahb_transfer_req) begin + if (ahb_s_req_i.hwrite) state_d = S_WRITE; + else state_d = S_READ; end end - S_NONSEQ_READ, S_NONSEQ_WRITE: begin - // BUSY should not happen when NONSEQ ongoing - // Default is then IDLE (no transfer after current one) - state_d = AHB_TRANS_IDLE; - - // If current request not served, should stay in NONSEQ - if (~req_ack_i) state_d = state_q; - // Stay in NONSEQ if one is following - else if (ahb_s_req_i.htrans == AHB_TRANS_NONSEQ) begin - if (ahb_s_req_i.hwrite) state_d = S_NONSEQ_WRITE; - else state_d = S_NONSEQ_READ; - end - // Go to SEQ if this becomes a BURST - else if (ahb_s_req_i.htrans == AHB_TRANS_SEQ) begin - if (ahb_s_req_i.hwrite) state_d = S_SEQ_WRITE; - else state_d = S_SEQ_READ; - end + S_WRITE: begin + if (req_port_i.data_gnt == 1'b1) state_d = S_IDLE; // Write completed end - S_SEQ_READ, S_SEQ_WRITE: begin - // BURST is conneced to every state - // Change state accoding to next transfer type - state_d = AHB_TRANS_IDLE; - if (ahb_s_req_i.htrans == AHB_TRANS_SEQ) begin - if (ahb_s_req_i.hwrite) state_d = S_SEQ_WRITE; - else state_d = S_SEQ_READ; - end - else if (ahb_s_req_i.htrans == AHB_TRANS_BUSY) state_d = S_BUSY; - else if (ahb_s_req_i.htrans == AHB_TRANS_NONSEQ) begin - if (ahb_s_req_i.hwrite) state_d = S_NONSEQ_WRITE; - else state_d = S_NONSEQ_READ; - end + S_READ: begin + if (req_port_i.data_gnt == 1'b1) state_d = S_READ_DATA; // Read command accepted end - S_BUSY: begin - // BUSY can then go IDLE and SINGLE only if the current burst size is undefined - if (ahb_s_req_i.htrans == AHB_TRANS_BUSY) state_d = S_BUSY; - else if (ahb_s_req_i.htrans == AHB_TRANS_SEQ) begin - if (ahb_s_req_i.hwrite) state_d = S_SEQ_WRITE; - else state_d = S_SEQ_READ; - end - else if (ahb_s_req_i.hburst == AHB_BURST_INCR) begin - if (ahb_s_req_i.htrans == AHB_TRANS_IDLE) state_d = S_IDLE; - else if (ahb_s_req_i.htrans == AHB_TRANS_NONSEQ) begin - if (ahb_s_req_i.hwrite) state_d = S_NONSEQ_WRITE; - else state_d = S_NONSEQ_READ; - end - end - - // TODO: Assert when IDLE or NONSEQ for a non undefined length burst + S_READ_DATA: begin + if ((req_port_i.data_rvalid == 1'b1) && ahb_transfer_req) begin // pipeline transfer + if (ahb_s_req_i.hwrite) state_d = S_WRITE; + else state_d = S_READ; + end else if (req_port_i.data_rvalid == 1'b1) state_d = S_IDLE; // no pipeline transfer end - + // TODO: Assert when IDLE or NONSEQ for a non undefined length burst default: state_d = S_IDLE; endcase end @@ -143,24 +105,25 @@ module ahb_slave_adapter assign ahb_s_resp_o.hrdata = hrdata_d; assign ahb_s_resp_o.hready = hready_d; - assign ahb_s_resp_o.hresp = hresp_d; + assign ahb_s_resp_o.hresp = 1'b0; // Exception not yet supported, no errors are sent to AHB BUS always_comb begin : p_ahb_outputs - hready_d = 1'b1; - hresp_d = 1'b0; // Exception not yet supported, no errors are sent to AHB BUS hrdata_d = '0; case (state_q) - S_NONSEQ_READ, S_SEQ_READ: begin + S_IDLE: begin + hready_d = 1'b1; + end + S_READ: begin + hready_d = 1'b0; + end + S_READ_DATA: begin + hready_d = req_port_i.data_rvalid; if (req_port_i.data_rvalid) hrdata_d = req_port_i.data_rdata; - else hready_d = 1'b0; end - - S_NONSEQ_WRITE, S_SEQ_WRITE: begin - if (~req_ack_i) hready_d = 1'b0; + S_WRITE: begin + hready_d = 1'b0; end - - // IDLE and BUSY are in default default: ; endcase end @@ -169,59 +132,46 @@ module ahb_slave_adapter // FSM: Outputs for DREQ interface // -------------------------------- + assign req_port_o.vaddr = vaddr_q; + assign req_port_o.data_wdata = ahb_s_req_i.hwdata; + assign req_port_o.data_req = data_req_d; + assign req_port_o.data_we = data_we_d; + assign req_port_o.data_be = data_be_d; + assign req_port_o.data_size = size_q; + assign req_port_o.data_id = '0; // Not supported: next req is sent when previous one is done + assign req_port_o.kill_req = '0; // Not supported: AHB master cannot kill a req + always_comb begin : p_dreq_outputs - vaddr_d = vaddr_q; - wdata_d = wdata_q; data_req_d = 1'b0; data_we_d = 1'b0; - data_be_d = '0; // TODO: Determine if should be set depending of size or not? - size_d = size_q; - ahb_burst_o = 1'b0; case (state_q) - S_IDLE: begin - // Next state is NONSEQ, then a new request after IDLE juste arrived - // Can send request to ask ARBITER - // Nothing to do if request is write... should wait for wdata before sending) - if (state_d == S_NONSEQ_READ) begin - vaddr_d = CVA6Cfg.VLEN'(ahb_s_req_i.haddr); - data_req_d = 1'b1; - size_d = ahb_s_req_i.hsize[1:0]; - end - end + S_IDLE: ; - S_NONSEQ_READ, S_SEQ_READ: begin - if (req_ack_i && (state_d == S_NONSEQ_READ || state_d == S_SEQ_READ)) begin - vaddr_d = CVA6Cfg.VLEN'(ahb_s_req_i.haddr); - data_req_d = 1'b1; - size_d = ahb_s_req_i.hsize[1:0]; - end else if (~req_ack_i) data_req_d = 1'b1; - - if (state_d == S_SEQ_READ) ahb_burst_o = 1'b1; + S_WRITE: begin + data_req_d = 1'b1; + data_we_d = 1'b1; end - S_NONSEQ_WRITE, S_SEQ_WRITE: begin - data_we_d = 1'b1; - if (req_ack_i && (state_d == S_NONSEQ_WRITE || state_d == S_SEQ_WRITE)) data_req_d = 1'b1; - - if (state_d == S_SEQ_WRITE) ahb_burst_o = 1'b1; + S_READ: begin + data_req_d = 1'b1; end - S_BUSY: begin + S_READ_DATA: begin + data_req_d = 1'b0; end - default: ; endcase end - assign req_port_o.vaddr = vaddr_d; - assign req_port_o.data_wdata = wdata_d; - assign req_port_o.data_req = data_req_d; - assign req_port_o.data_we = data_we_d; - assign req_port_o.data_be = data_be_d; - assign req_port_o.data_size = size_d; - assign req_port_o.data_id = '0; // Not supported: next req is sent when previous one is done - assign req_port_o.kill_req = '0; // Not supported: AHB master cannot kill a req + always_comb begin : p_data_be_gen + if (ahb_s_req_i.hwrite) begin + if (ahb_s_req_i.hsize[1:0] == 3'b000) data_be_d = 4'b0001; + else if (ahb_s_req_i.hsize[1:0] == 3'b001) data_be_d = 4'b0011; + else if (ahb_s_req_i.hsize[1:0] == 3'b010) data_be_d = 4'b1111; + else data_be_d = 4'b1111; + end else data_be_d = 4'h0; + end // ---------------------------- // Req port register process @@ -230,15 +180,12 @@ module ahb_slave_adapter always_ff @(posedge clk_i or negedge rst_ni) begin : p_req_port_regs if (~rst_ni) begin vaddr_q <= '0; - wdata_q <= '0; size_q <= '0; end else begin - // TODO: Find enable - if (req_ack_i || ((state_d == S_NONSEQ_READ || state_d == S_NONSEQ_WRITE) && state_q == S_IDLE)) begin - vaddr_q <= vaddr_d; - size_q <= size_d; + if (ahb_transfer_req) begin + vaddr_q <= ahb_s_req_i.haddr; + size_q <= ahb_s_req_i.hsize[1:0]; end - if (state_q == S_NONSEQ_WRITE || state_q == S_SEQ_WRITE) wdata_q <= wdata_d; end end diff --git a/core/scratchpad/dscr_controller.sv b/core/scratchpad/dscr_controller.sv index 4ba4a4cd1e..4b64ac9e15 100644 --- a/core/scratchpad/dscr_controller.sv +++ b/core/scratchpad/dscr_controller.sv @@ -43,12 +43,12 @@ module dscr_controller ); // Arbitrer signals - logic [DSCR_ARBIT_NUM_IN-1:0] arb_req; - logic arb_gnt; - dscr_arbit_e arb_idx; - logic arb_idx_valid; + logic [ DSCR_ARBIT_NUM_IN-1:0] arb_req; + logic arb_gnt; + logic [$clog2(ISCR_ARBIT_NUM_IN)-1:0] arb_idx; + logic arb_idx_valid; logic ahb_read_ongoing, load_ongoing; - logic ahb_ack, ahb_store_ready_o, ahb_burst; + logic ahb_store_ready_o; // AHB slave adapter signals scratchpad_req_i_t ahb_req_port_o; dcache_req_o_t ahb_req_port_i; @@ -113,8 +113,6 @@ module dscr_controller .rst_ni (rst_ni), .ahb_s_req_i (ahb_s_req_i), .ahb_s_resp_o(ahb_s_resp_o), - .req_ack_i (ahb_ack), - .ahb_burst_o (ahb_burst), .req_port_i (ahb_req_port_i), .req_port_o (ahb_req_port_o) ); @@ -153,21 +151,21 @@ module dscr_controller // arb_idx has only 3 possible values unique if (arb_idx == DSCR_ARBIT_LOAD && arb_idx_valid) begin sram_ctrl_req = ld_req_port_i.data_req && !load_ongoing && !ld_req_port_i.kill_req; - sram_ctrl_addr = ld_req_port_i.vaddr; - sram_ctrl_we = ld_req_port_i.data_we; - sram_ctrl_be = ld_req_port_i.data_be; - sram_ctrl_wdata = ld_req_port_i.data_wdata; - sram_req_id = ld_req_port_i.data_id; + sram_ctrl_addr = ld_req_port_i.vaddr; + sram_ctrl_we = ld_req_port_i.data_we; + sram_ctrl_be = ld_req_port_i.data_be; + sram_ctrl_wdata = ld_req_port_i.data_wdata; + sram_req_id = ld_req_port_i.data_id; - ld_req_port_o.data_rdata = sram_resp_rdata; - ld_req_port_o.data_gnt = sram_resp_gnt; + ld_req_port_o.data_rdata = sram_resp_rdata; + ld_req_port_o.data_gnt = sram_resp_gnt; ld_req_port_o.data_rvalid = sram_resp_rdata_valid; - ld_req_port_o.data_rid = sram_resp_rid; - ld_req_port_o.data_ruser = '0; + ld_req_port_o.data_rid = sram_resp_rid; + ld_req_port_o.data_ruser = '0; - ahb_req_port_i = '0; + ahb_req_port_i = '0; end else if (arb_idx == DSCR_ARBIT_STORE && arb_idx_valid) begin - sram_ctrl_req = st_req_port_i.data_req && !st_req_sent && !st_req_port_i.kill_req; + sram_ctrl_req = st_req_port_i.data_req && !st_req_sent && !st_req_port_i.kill_req; sram_ctrl_addr = st_req_port_i.vaddr; sram_ctrl_we = st_req_port_i.data_we; sram_ctrl_be = st_req_port_i.data_be; @@ -177,7 +175,7 @@ module dscr_controller ld_req_port_o = '0; ahb_req_port_i = '0; end else if (arb_idx == DSCR_ARBIT_AHB && arb_idx_valid) begin - sram_ctrl_req = ahb_req_port_o.data_req; + sram_ctrl_req = ahb_req_port_o.data_req; sram_ctrl_addr = ahb_req_port_o.vaddr; sram_ctrl_we = ahb_req_port_o.data_we; sram_ctrl_be = ahb_req_port_o.data_be; @@ -185,7 +183,7 @@ module dscr_controller sram_req_id = '0; ahb_req_port_i.data_rdata = sram_resp_rdata; - ahb_req_port_i.data_gnt = arb_gnt; + ahb_req_port_i.data_gnt = sram_resp_gnt; ahb_req_port_i.data_rvalid = sram_resp_rdata_valid; ahb_req_port_i.data_rid = sram_resp_rid; ahb_req_port_i.data_ruser = '0; @@ -209,8 +207,7 @@ module dscr_controller assign arb_req[DSCR_ARBIT_LOAD] = ld_req_port_i.data_req || load_ongoing; assign arb_req[DSCR_ARBIT_STORE] = st_req_port_i.data_req; assign arb_req[DSCR_ARBIT_AHB] = ahb_req_port_o.data_req || ahb_read_ongoing; - assign arb_gnt = (st_ready_o || sram_resp_rdata_valid) && !(ahb_ack && ahb_burst); - assign ahb_ack = ahb_store_ready_o || (sram_resp_rdata_valid && ahb_read_ongoing); + assign arb_gnt = (st_ready_o || sram_resp_rdata_valid || (ahb_req_port_o.data_req && ahb_req_port_o.data_we && sram_resp_gnt) ); always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin diff --git a/core/scratchpad/iscr_controller.sv b/core/scratchpad/iscr_controller.sv index 9713d0c306..f48898ccee 100644 --- a/core/scratchpad/iscr_controller.sv +++ b/core/scratchpad/iscr_controller.sv @@ -49,12 +49,12 @@ module iscr_controller ); // Dynamic arbitrer signals - logic [ ISCR_ARBIT_NUM_IN-1:0] arb_req; - logic arb_gnt; - iscr_arbit_e arb_idx; - logic arb_idx_valid; + logic [ISCR_ARBIT_NUM_IN-1:0] arb_req; + logic arb_gnt; + logic [ 1:0] arb_idx; + logic arb_idx_valid; logic ahb_read_ongoing, load_ongoing, frontend_ongoing; - logic ahb_ack, ahb_store_ready_o, ahb_burst; + logic ahb_store_ready_o; // AHB slave adapter signals scratchpad_req_i_t ahb_req_port_o; dcache_req_o_t ahb_req_port_i; @@ -119,8 +119,6 @@ module iscr_controller .rst_ni (rst_ni), .ahb_s_req_i (ahb_s_req_i), .ahb_s_resp_o(ahb_s_resp_o), - .req_ack_i (ahb_ack), - .ahb_burst_o (ahb_burst), .req_port_i (ahb_req_port_i), .req_port_o (ahb_req_port_o) ); @@ -171,8 +169,8 @@ module iscr_controller if_drsp_o.vaddr = sram_resp_addr; if_drsp_o.ex = '0; - ld_req_port_o = '0; - ahb_req_port_i = '0; + ld_req_port_o = '0; + ahb_req_port_i = '0; end else if (arb_idx == ISCR_ARBIT_LOAD && arb_idx_valid) begin sram_ctrl_addr = ld_req_port_i.vaddr; sram_ctrl_req = ld_req_port_i.data_req && !ld_req_port_i.kill_req; @@ -239,8 +237,7 @@ module iscr_controller assign arb_req[ISCR_ARBIT_STORE] = st_req_port_i.data_req; assign arb_req[ISCR_ARBIT_AHB] = ahb_req_port_o.data_req || ahb_read_ongoing; assign arb_req[ISCR_ARBIT_FRONTEND] = if_dreq_i.req || frontend_ongoing; - assign arb_gnt = (st_ready_o || sram_resp_rdata_valid && !(ahb_ack && ahb_burst)); - assign ahb_ack = ahb_store_ready_o || (sram_resp_rdata_valid && ahb_read_ongoing); + assign arb_gnt = (st_ready_o || sram_resp_rdata_valid || (ahb_req_port_o.data_req && ahb_req_port_o.data_we && sram_resp_gnt) ); always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin diff --git a/core/scratchpad/sram_controller.sv b/core/scratchpad/sram_controller.sv index c5a0019613..012ad70941 100644 --- a/core/scratchpad/sram_controller.sv +++ b/core/scratchpad/sram_controller.sv @@ -19,8 +19,6 @@ module sram_controller // Req interface input logic req_data_req_i, - input logic req_kill_s1_i, - input logic req_kill_s2_i, input logic req_data_we_i, input logic [ DATA_WIDTH-1:0] req_data_wdata_i, input logic [ (CVA6Cfg.XLEN/8)-1:0] req_data_be_i, @@ -31,7 +29,6 @@ module sram_controller output logic resp_rdata_valid_o, output logic resp_data_gnt_o, output logic [ CVA6Cfg.VLEN-1:0] resp_address_o, - output logic resp_killed_o, output logic [CVA6Cfg.DcacheIdWidth-1:0] resp_data_rid_o, // SRAM Interface @@ -53,7 +50,8 @@ module sram_controller // Direct assign signals // CVA6Cfg.VLEN should not be lower than $clog2(NUM_WORDS) - assign sram_addr_o = req_address_i[$clog2(NUM_WORDS)-1:0]; + // Shift address: memory in word, not in byte + assign sram_addr_o = $clog2(NUM_WORDS)'(req_address_i >> 2); // TODO: generalize for NUM_WAIT_STATE > 1 if (NUM_WAIT_STATE == 1) begin : gen_fsm_wait_state @@ -72,7 +70,7 @@ module sram_controller case (state_q) IDLE: begin // If a new req and this req is not killed - if (req_data_req_i && !req_kill_s1_i) begin + if (req_data_req_i) begin if (req_data_we_i) state_d = WRITE; else state_d = READ; end else begin @@ -95,13 +93,11 @@ module sram_controller sram_wdata_o = '0; sram_be_o = '0; resp_rdata_o = '0; - resp_killed_o = 1'b0; resp_rdata_valid_o = 1'b0; case (state_q) IDLE: begin - resp_killed_o = req_kill_s1_i; - if (req_data_req_i && !req_kill_s1_i) begin + if (req_data_req_i) begin resp_data_gnt_o = '1; sram_req_o = '1; sram_we_o = req_data_we_i; @@ -114,11 +110,8 @@ module sram_controller WRITE: ; READ: begin - resp_killed_o = req_kill_s1_i || req_kill_s2_i; - if (!req_kill_s1_i) begin - resp_rdata_valid_o = ~req_kill_s2_i; - resp_rdata_o = sram_rdata_i; - end + resp_rdata_valid_o = 1'b1; + resp_rdata_o = sram_rdata_i; end default: ; @@ -132,17 +125,16 @@ module sram_controller assign sram_be_o = req_data_be_i; assign resp_rdata_o = sram_rdata_i; - assign resp_data_gnt_o = req_data_req_i; - assign resp_killed_o = req_data_req_i && req_kill_s1_i && req_data_we_i; + assign resp_data_gnt_o = req_data_req_i; // with no wait state gnt can be combinatorial always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin resp_rdata_valid_o <= 1'b0; end else begin if (req_data_req_i && !req_data_we_i) begin - resp_rdata_valid_o <= ~req_kill_s1_i; - end else if (~req_data_req_i && resp_rdata_valid_o) begin - resp_rdata_valid_o <= '0; + resp_rdata_valid_o <= 1'b1; + end else if ((~req_data_req_i || req_data_we_i) && resp_rdata_valid_o) begin + resp_rdata_valid_o <= 1'b0; end end end