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+# Module: Traps
+
+## Feature: Illegal Instruction
+
+### Sub-feature: 000_illegal_instr
+
+#### Item: 000
+
+* **Requirement location:** Unprivileged ISA Version 20191213, Chapter 1.5
+* **Feature Description**
+  
+  Opcodes that do not decode to a valid, supported instruction for the CVA6 core configuration shall raise an illegal instruction exception.
+* **Verification Goals**
+  
+  Check that when executing any illegal instruction, an exception is raised with `mcause` CSR set to 0x2.
+* **Pass/Fail Criteria:** Check RM
+* **Test Type:** Constrained Random
+* **Coverage Method:** Code Coverage
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F000_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  Covered by ISACOV
+## Feature: Load x0
+
+### Sub-feature: 000_load_x0
+
+#### Item: 000
+
+* **Requirement location:** Unprivileged ISA Version 20191213, Chapter 2.6
+* **Feature Description**
+  
+  `x0` register cannot have a value loaded into it but does not generate an exception when that is attempted, as the exception is not implemented.
+* **Verification Goals**
+  
+  Check that loading to `x0` register does not cause an exception.
+* **Pass/Fail Criteria:** Check RM
+* **Test Type:** Constrained Random
+* **Coverage Method:** Functional Coverage
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F001_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+## Feature: CSR Access
+
+### Sub-feature: 000_CSR_access
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 2.1
+* **Feature Description**
+  
+  Attempted access to non-existent CSRs will generate an illegal instruction exception.
+* **Verification Goals**
+  
+  Check that when accessing any non-existent CSR, an exception is raised with `mcause` set to 0x2.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F002_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  Covered by CSR DV plan.  
+  Verify if `mcause` value check is covered by CSR DV plan.
+#### Item: 001
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 2.1
+* **Feature Description**
+  
+  Attempted store to read-only CSRs will generate an illegal instruction exception.
+* **Verification Goals**
+  
+  Check that when storing to any read-only CSR, an exception is raised with `mcause` set to 0x2.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F002_S000_I001
+* **Link to Coverage:** 
+* **Comments**
+  
+  Covered by CSR DV plan.  
+  Verify if `mcause` value check is covered by CSR DV plan.
+## Feature: Machine Trap Vector
+
+### Sub-feature: 000_mtvec
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.7
+* **Feature Description**
+  
+  `mtvec` provides the starting value of the Interrupt Vector Table as well as the mode (Direct or Vectored) number at the time. Mode number is not relevant to exceptions as it only affects the value jumped to by interrupts.
+* **Verification Goals**
+  
+  Check that exceptions jump to the base value defined in `mtvec` CSR.
+* **Pass/Fail Criteria:** Check RM
+* **Test Type:** Constrained Random
+* **Coverage Method:** Functional Coverage
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F003_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+## Feature: Machine Cause
+
+### Sub-feature: 000_mcause
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, 3.1.15
+* **Feature Description**
+  
+  `mcause` is set to exception cause upon entry into exception.
+* **Verification Goals**
+  
+  Check that `mcause` correctly identifies the exception taken.
+* **Pass/Fail Criteria:** Check RM
+* **Test Type:** Constrained Random
+* **Coverage Method:** Functional Coverage
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F004_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+## Feature: Machine Exception Program Counter
+
+### Sub-feature: 000_mepc
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.15
+* **Feature Description**
+  
+  `mepc` is set to the `pc` value of the instruction that generates an exception.
+* **Verification Goals**
+  
+  Check that when an exception is raised, `mepc` CSR contains the correct `pc`.
+* **Pass/Fail Criteria:** Check RM
+* **Test Type:** Constrained Random
+* **Coverage Method:** Functional Coverage
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F005_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+## Feature: Machine Trap Value
+
+### Sub-feature: 000_mtval_illegal
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.16
+* **Feature Description**
+  
+  When an illegal instruction exception is raised, the corresponding instruction is stored into `mtval` CSR.
+* **Verification Goals**
+  
+  Check that when any illegal instruction exception is raised, `mtval` CSR contains the faulting instruction.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F006_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  ZERO_TVAL parameter value?
+### Sub-feature: 001_mtval_misaligned
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.16
+* **Feature Description**
+  
+  When an address misaligned exception is raised, the corresponding address is stored into `mtval` CSR.
+* **Verification Goals**
+  
+  Check that when any address misaligned exception is raised, `mtval` CSR contains the address of the portion of the access causing the fault.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F006_S001_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  ZERO_TVAL parameter value?
+### Sub-feature: 002_mtval_access
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.16
+* **Feature Description**
+  
+  When an access fault exception is raised, the corresponding address is stored into `mtval` CSR.
+* **Verification Goals**
+  
+  Check that when any access fault exception is raised, `mtval` CSR contains the address of the portion of the access causing the fault.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F006_S002_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  ZERO_TVAL parameter value?
+### Sub-feature: 003_mtval_page
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.16
+* **Feature Description**
+  
+  When an page fault exception is raised, the corresponding address is stored into `mtval` CSR.
+* **Verification Goals**
+  
+  Check that when any page fault exception is raised, `mtval` CSR contains the address of the portion of the access causing the fault.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F006_S003_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  ZERO_TVAL parameter value? Only with MMU support
+## Feature: Exception Priority
+
+### Sub-feature: 000_exception priority
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.15
+* **Feature Description**
+  
+  Exceptions are of lower priority than all interrupts.  
+  Exception priority (high to low)  
+  - code=0x3: Instruction address breakpoint  
+  - code=0xC, 0x1: Instruction page fault, instruction access fault  
+  - code=0x2: Illegal instruction  
+  - code=0x8, 0x9, 0xB: Environment call from U-mode, from S-mode, from M-mode  
+  - code=0x3: Environment break  
+  - code=0x3: Load/store/AMO address breakpoint  
+  - code=0x4, 0x6: Load address misaligned, store/AMO address misaligned (CHECK IF NOT LOWEST PRIORITY ON CVA6)  
+  - code=0xD, 0xF, 0x5, 0x7: Load page fault, store/AMO page fault, load access fault, store/AMO access fault
+* **Verification Goals**
+  
+  Check that when raising an exception together with a lower priority one the cause of the higher priority exception is written in `mcause` register.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** Directed Non-SelfChk
+* **Coverage Method:** Testcase
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F007_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+## Feature: Address Misaligned
+
+### Sub-feature: 000_instr_misaligned
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.1.15
+* **Feature Description**
+  
+  If not aligned address is computed by control-flow instruction, a instruction address misaligned exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x0.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F008_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  Need to check if such exception is possible with instruction set
+### Sub-feature: 001_load_misaligned
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.6.3.3
+* **Feature Description**
+  
+  If not aligned load is attempted, a load address misaligned exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x4.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F008_S001_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+#### Item: 001
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.6.3.3
+* **Feature Description**
+  
+  If not aligned load-reserved is attempted, a load address misaligned exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x4.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F008_S001_I001
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+### Sub-feature: 002_store_misaligned
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.6.3.3
+* **Feature Description**
+  
+  If not aligned store is attempted, a store/AMO access misaligned exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x6.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** Constrained Random
+* **Coverage Method:** Functional Coverage
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F008_S002_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+#### Item: 001
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.6.3.3
+* **Feature Description**
+  
+  If not aligned store-conditional is attempted , a store/AMO access misaligned exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x6.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F008_S002_I001
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+#### Item: 002
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.6.3.3
+* **Feature Description**
+  
+  If not aligned AMO is attempted, a store/AMO access misaligned exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with mcause set to 0x6.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F008_S002_I002
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+## Feature: Access Fault
+
+### Sub-feature: 000_instr_access
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.7.1
+* **Feature Description**
+  
+  If execution is attempted in a PMP region without execute permission, an instruction access fault exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x1.
+* **Pass/Fail Criteria:** Check RM
+* **Test Type:** Constrained Random
+* **Coverage Method:** Functional Coverage
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F009_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+#### Item: 001
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.6
+* **Feature Description**
+  
+  If execution is attempted in a PMA region set to I/O, an instruction access fault exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x1.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F009_S000_I001
+* **Link to Coverage:** 
+* **Comments**
+  
+  CHECK IF RELEVANT ON CVA6
+### Sub-feature: 001_load_access
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.7.1
+* **Feature Description**
+  
+  If aligned or not aligned load is attempted in a PMP region without write permission, a load access fault exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x5.
+* **Pass/Fail Criteria:** Check RM
+* **Test Type:** Constrained Random
+* **Coverage Method:** Functional Coverage
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F009_S001_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+#### Item: 001
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.7.1
+* **Feature Description**
+  
+  If aligned or not aligned load-reserved is attempted in a PMP region without write permission, a load access fault exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x5
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F009_S001_I001
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+### Sub-feature: 002_store_amo_access
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.7.1
+* **Feature Description**
+  
+  If aligned or not aligned store is attempted in a PMP region without write permission, a store/AMO access fault exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x7
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F009_S002_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+#### Item: 001
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.7.1
+* **Feature Description**
+  
+  If aligned or not aligned store conditional is attempted in a PMP region without write permission, a store/AMO access fault exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x7
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F009_S002_I001
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+#### Item: 002
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.7.1
+* **Feature Description**
+  
+  If aligned or not aligned AMO is attempted in a PMP region without write permission, a store/AMO access fault exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x7
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F009_S002_I002
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+## Feature: Environment Call
+
+### Sub-feature: 000_ecall
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.3.1
+* **Feature Description**
+  
+  If an `ECALL` is executed from M-mode then an environment call exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0xB.
+* **Pass/Fail Criteria:** Check RM
+* **Test Type:** Constrained Random
+* **Coverage Method:** Functional Coverage
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F010_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+#### Item: 001
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.3.1
+* **Feature Description**
+  
+  If an `ECALL` is executed from S-mode then an environment call exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x9.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F010_S000_I001
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+#### Item: 002
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 3.3.1
+* **Feature Description**
+  
+  If an `ECALL` is executed from U-mode then an environment call exception is taken.
+* **Verification Goals**
+  
+  Exception is entered with `mcause` set to 0x8.
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F010_S000_I002
+* **Link to Coverage:** 
+* **Comments**
+  
+  *(none)*  
+  
+## Feature: Page Fault
+
+### Sub-feature: 000_instr_page
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 4.3.1, 4.4.1, 4.5.1
+* **Feature Description**
+  
+  TBD
+* **Verification Goals**
+  
+  TBD
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F011_S000_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  MMU related
+### Sub-feature: 001_load_page
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 4.3.1, 4.4.1, 4.5.1
+* **Feature Description**
+  
+  TBD
+* **Verification Goals**
+  
+  TBD
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F011_S001_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  MMU related
+### Sub-feature: 002_store_page
+
+#### Item: 000
+
+* **Requirement location:** Privileged Architecture Version 20211203, Chapter 4.3.1, 4.4.1, 4.5.1
+* **Feature Description**
+  
+  TBD
+* **Verification Goals**
+  
+  TBD
+* **Pass/Fail Criteria:** NDY (Not Defined Yet)
+* **Test Type:** NDY (Not Defined Yet)
+* **Coverage Method:** NDY (Not Defined Yet)
+* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3
+* **Unique verification tag:** VP_traps_F011_S002_I000
+* **Link to Coverage:** 
+* **Comments**
+  
+  MMU related
+## Feature: Breakpoint
+
+### Sub-feature: 000_instr_bkp
+
+### Sub-feature: 001_data_bkp
+
+### Sub-feature: 002_environment_break
+
diff --git a/verif/docs/VerifPlans/source/index.rst b/verif/docs/VerifPlans/source/index.rst
index 3515ac8ff0..d5e7ac5585 100644
--- a/verif/docs/VerifPlans/source/index.rst
+++ b/verif/docs/VerifPlans/source/index.rst
@@ -29,4 +29,5 @@ CV32A6-step1 Design Verification Plan
    dvplan_AXI
    dvplan_FENCEI
    dvplan_csr-access
+   dvplan_traps
 
diff --git a/verif/docs/VerifPlans/traps/VP_IP000.yml b/verif/docs/VerifPlans/traps/VP_IP000.yml
new file mode 100644
index 0000000000..fead1b7c42
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP000.yml
@@ -0,0 +1,34 @@
+!Feature
+next_elt_id: 1
+name: Illegal Instruction
+id: 0
+display_order: 0
+subfeatures: !!omap
+- 000_illegal_instr: !Subfeature
+    name: 000_illegal_instr
+    tag: VP_traps_F000_S000
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F000_S000_I000
+        description: Opcodes that do not decode to a valid, supported instruction
+          for the CVA6 core configuration shall raise an illegal instruction exception.
+        reqt_doc: Unprivileged ISA Version 20191213, Chapter 1.5
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that when executing any illegal instruction, an exception
+          is raised with `mcause` CSR set to 0x2.
+        pfc: 3
+        test_type: 3
+        cov_method: 3
+        cores: 56
+        coverage_loc: ''
+        comments: Covered by ISACOV
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP001.yml b/verif/docs/VerifPlans/traps/VP_IP001.yml
new file mode 100644
index 0000000000..3a3c0443f2
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP001.yml
@@ -0,0 +1,33 @@
+!Feature
+next_elt_id: 1
+name: Load x0
+id: 1
+display_order: 1
+subfeatures: !!omap
+- 000_load_x0: !Subfeature
+    name: 000_load_x0
+    tag: VP_traps_F001_S000
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F001_S000_I000
+        description: '`x0` register cannot have a value loaded into it but does not
+          generate an exception when that is attempted, as the exception is not implemented.'
+        reqt_doc: Unprivileged ISA Version 20191213, Chapter 2.6
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that loading to `x0` register does not cause an exception.
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP002.yml b/verif/docs/VerifPlans/traps/VP_IP002.yml
new file mode 100644
index 0000000000..1c239b2d5e
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP002.yml
@@ -0,0 +1,54 @@
+!Feature
+next_elt_id: 1
+name: CSR Access
+id: 2
+display_order: 2
+subfeatures: !!omap
+- 000_CSR_access: !Subfeature
+    name: 000_CSR_access
+    tag: VP_traps_F002_S000
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F002_S000_I000
+        description: Attempted access to non-existent CSRs will generate an illegal
+          instruction exception.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 2.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that when accessing any non-existent CSR, an exception
+          is raised with `mcause` set to 0x2.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: "Covered by CSR DV plan.\nVerify if `mcause` value check is covered\
+          \ by CSR DV plan."
+    - '001': !VerifItem
+        name: '001'
+        tag: VP_traps_F002_S000_I001
+        description: Attempted store to read-only CSRs will generate an illegal instruction
+          exception.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 2.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that when storing to any read-only CSR, an exception is
+          raised with `mcause` set to 0x2.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: "Covered by CSR DV plan.\nVerify if `mcause` value check is covered\
+          \ by CSR DV plan."
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP003.yml b/verif/docs/VerifPlans/traps/VP_IP003.yml
new file mode 100644
index 0000000000..be017af927
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP003.yml
@@ -0,0 +1,36 @@
+!Feature
+next_elt_id: 1
+name: Machine Trap Vector
+id: 3
+display_order: 3
+subfeatures: !!omap
+- 000_mtvec: !Subfeature
+    name: 000_mtvec
+    tag: VP_traps_F003_S000
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F003_S000_I000
+        description: '`mtvec` provides the starting value of the Interrupt Vector
+          Table as well as the mode (Direct or Vectored) number at the time. Mode
+          number is not relevant to exceptions as it only affects the value jumped
+          to by interrupts.'
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.7
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that exceptions jump to the base value defined in `mtvec`
+          CSR.
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP004.yml b/verif/docs/VerifPlans/traps/VP_IP004.yml
new file mode 100644
index 0000000000..edbf042cb8
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP004.yml
@@ -0,0 +1,32 @@
+!Feature
+next_elt_id: 1
+name: Machine Cause
+id: 4
+display_order: 4
+subfeatures: !!omap
+- 000_mcause: !Subfeature
+    name: 000_mcause
+    tag: VP_traps_F004_S000
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F004_S000_I000
+        description: '`mcause` is set to exception cause upon entry into exception.'
+        reqt_doc: Privileged Architecture Version 20211203, 3.1.15
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that `mcause` correctly identifies the exception taken.
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP005.yml b/verif/docs/VerifPlans/traps/VP_IP005.yml
new file mode 100644
index 0000000000..3498b21ff1
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP005.yml
@@ -0,0 +1,34 @@
+!Feature
+next_elt_id: 1
+name: Machine Exception Program Counter
+id: 5
+display_order: 5
+subfeatures: !!omap
+- 000_mepc: !Subfeature
+    name: 000_mepc
+    tag: VP_traps_F005_S000
+    next_elt_id: 2
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F005_S000_I000
+        description: '`mepc` is set to the `pc` value of the instruction that generates
+          an exception.'
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.15
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that when an exception is raised, `mepc` CSR contains the
+          correct `pc`.
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP006.yml b/verif/docs/VerifPlans/traps/VP_IP006.yml
new file mode 100644
index 0000000000..e2ea8cc991
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP006.yml
@@ -0,0 +1,106 @@
+!Feature
+next_elt_id: 1
+name: Machine Trap Value
+id: 6
+display_order: 6
+subfeatures: !!omap
+- 000_mtval_illegal: !Subfeature
+    name: 000_mtval_illegal
+    tag: VP_traps_F006_S000
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F006_S000_I000
+        description: When an illegal instruction exception is raised, the corresponding
+          instruction is stored into `mtval` CSR.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that when any illegal instruction exception is raised,
+          `mtval` CSR contains the faulting instruction.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ZERO_TVAL parameter value?
+- 001_mtval_misaligned: !Subfeature
+    name: 001_mtval_misaligned
+    tag: VP_traps_F006_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F006_S001_I000
+        description: When an address misaligned exception is raised, the corresponding
+          address is stored into `mtval` CSR.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that when any address misaligned exception is raised, `mtval`
+          CSR contains the address of the portion of the access causing the fault.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ZERO_TVAL parameter value?
+- 002_mtval_access: !Subfeature
+    name: 002_mtval_access
+    tag: VP_traps_F006_S002
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F006_S002_I000
+        description: When an access fault exception is raised, the corresponding address
+          is stored into `mtval` CSR.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that when any access fault exception is raised, `mtval`
+          CSR contains the address of the portion of the access causing the fault.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ZERO_TVAL parameter value?
+- 003_mtval_page: !Subfeature
+    name: 003_mtval_page
+    tag: VP_traps_F006_S003
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F006_S003_I000
+        description: When an page fault exception is raised, the corresponding address
+          is stored into `mtval` CSR.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that when any page fault exception is raised, `mtval` CSR
+          contains the address of the portion of the access causing the fault.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ZERO_TVAL parameter value? Only with MMU support
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP007.yml b/verif/docs/VerifPlans/traps/VP_IP007.yml
new file mode 100644
index 0000000000..ac10f5e363
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP007.yml
@@ -0,0 +1,41 @@
+!Feature
+next_elt_id: 1
+name: Exception Priority
+id: 7
+display_order: 7
+subfeatures: !!omap
+- 000_exception priority: !Subfeature
+    name: 000_exception priority
+    tag: VP_traps_F007_S000
+    next_elt_id: 2
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F007_S000_I000
+        description: "Exceptions are of lower priority than all interrupts.\nException\
+          \ priority (high to low)\n- code=0x3: Instruction address breakpoint\n-\
+          \ code=0xC, 0x1: Instruction page fault, instruction access fault\n- code=0x2:\
+          \ Illegal instruction\n- code=0x8, 0x9, 0xB: Environment call from U-mode,\
+          \ from S-mode, from M-mode\n- code=0x3: Environment break\n- code=0x3: Load/store/AMO\
+          \ address breakpoint\n- code=0x4, 0x6: Load address misaligned, store/AMO\
+          \ address misaligned (CHECK IF NOT LOWEST PRIORITY ON CVA6)\n- code=0xD,\
+          \ 0xF, 0x5, 0x7: Load page fault, store/AMO page fault, load access fault,\
+          \ store/AMO access fault"
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.15
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Check that when raising an exception together with a lower priority
+          one the cause of the higher priority exception is written in `mcause` register.
+        pfc: -1
+        test_type: 2
+        cov_method: 0
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP008.yml b/verif/docs/VerifPlans/traps/VP_IP008.yml
new file mode 100644
index 0000000000..c20b9863d2
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP008.yml
@@ -0,0 +1,130 @@
+!Feature
+next_elt_id: 1
+name: Address Misaligned
+id: 8
+display_order: 8
+subfeatures: !!omap
+- 000_instr_misaligned: !Subfeature
+    name: 000_instr_misaligned
+    tag: VP_traps_F008_S000
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F008_S000_I000
+        description: If not aligned address is computed by control-flow instruction,
+          a instruction address misaligned exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.15
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x0.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: Need to check if such exception is possible with instruction set
+- 001_load_misaligned: !Subfeature
+    name: 001_load_misaligned
+    tag: VP_traps_F008_S001
+    next_elt_id: 2
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F008_S001_I000
+        description: If not aligned load is attempted, a load address misaligned exception
+          is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.6.3.3
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x4.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+    - '001': !VerifItem
+        name: '001'
+        tag: VP_traps_F008_S001_I001
+        description: If not aligned load-reserved is attempted, a load address misaligned
+          exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.6.3.3
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x4.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+- 002_store_misaligned: !Subfeature
+    name: 002_store_misaligned
+    tag: VP_traps_F008_S002
+    next_elt_id: 3
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F008_S002_I000
+        description: If not aligned store is attempted, a store/AMO access misaligned
+          exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.6.3.3
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x6.
+        pfc: -1
+        test_type: 3
+        cov_method: 1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+    - '001': !VerifItem
+        name: '001'
+        tag: VP_traps_F008_S002_I001
+        description: If not aligned store-conditional is attempted , a store/AMO access
+          misaligned exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.6.3.3
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x6.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+    - '002': !VerifItem
+        name: '002'
+        tag: VP_traps_F008_S002_I002
+        description: If not aligned AMO is attempted, a store/AMO access misaligned
+          exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.6.3.3
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with mcause set to 0x6.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP009.yml b/verif/docs/VerifPlans/traps/VP_IP009.yml
new file mode 100644
index 0000000000..9c3722f46e
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP009.yml
@@ -0,0 +1,148 @@
+!Feature
+next_elt_id: 1
+name: Access Fault
+id: 9
+display_order: 9
+subfeatures: !!omap
+- 000_instr_access: !Subfeature
+    name: 000_instr_access
+    tag: VP_traps_F009_S000
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F009_S000_I000
+        description: If execution is attempted in a PMP region without execute permission,
+          an instruction access fault exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.7.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x1.
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+    - '001': !VerifItem
+        name: '001'
+        tag: VP_traps_F009_S000_I001
+        description: If execution is attempted in a PMA region set to I/O, an instruction
+          access fault exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.6
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x1.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: CHECK IF RELEVANT ON CVA6
+- 001_load_access: !Subfeature
+    name: 001_load_access
+    tag: VP_traps_F009_S001
+    next_elt_id: 2
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F009_S001_I000
+        description: If aligned or not aligned load is attempted in a PMP region without
+          write permission, a load access fault exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.7.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x5.
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+    - '001': !VerifItem
+        name: '001'
+        tag: VP_traps_F009_S001_I001
+        description: If aligned or not aligned load-reserved is attempted in a PMP
+          region without write permission, a load access fault exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.7.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x5
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+- 002_store_amo_access: !Subfeature
+    name: 002_store_amo_access
+    tag: VP_traps_F009_S002
+    next_elt_id: 3
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F009_S002_I000
+        description: If aligned or not aligned store is attempted in a PMP region
+          without write permission, a store/AMO access fault exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.7.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x7
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+    - '001': !VerifItem
+        name: '001'
+        tag: VP_traps_F009_S002_I001
+        description: If aligned or not aligned store conditional is attempted in a
+          PMP region without write permission, a store/AMO access fault exception
+          is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.7.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x7
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+    - '002': !VerifItem
+        name: '002'
+        tag: VP_traps_F009_S002_I002
+        description: If aligned or not aligned AMO is attempted in a PMP region without
+          write permission, a store/AMO access fault exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.7.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x7
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP010.yml b/verif/docs/VerifPlans/traps/VP_IP010.yml
new file mode 100644
index 0000000000..815aee0da1
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP010.yml
@@ -0,0 +1,67 @@
+!Feature
+next_elt_id: 1
+name: Environment Call
+id: 10
+display_order: 10
+subfeatures: !!omap
+- 000_ecall: !Subfeature
+    name: 000_ecall
+    tag: VP_traps_F010_S000
+    next_elt_id: 3
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F010_S000_I000
+        description: If an `ECALL` is executed from M-mode then an environment call
+          exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.3.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0xB.
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+    - '001': !VerifItem
+        name: '001'
+        tag: VP_traps_F010_S000_I001
+        description: If an `ECALL` is executed from S-mode then an environment call
+          exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.3.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x9.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+    - '002': !VerifItem
+        name: '002'
+        tag: VP_traps_F010_S000_I002
+        description: If an `ECALL` is executed from U-mode then an environment call
+          exception is taken.
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 3.3.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Exception is entered with `mcause` set to 0x8.
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP011.yml b/verif/docs/VerifPlans/traps/VP_IP011.yml
new file mode 100644
index 0000000000..78ffd843d0
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP011.yml
@@ -0,0 +1,79 @@
+!Feature
+next_elt_id: 1
+name: Page Fault
+id: 11
+display_order: 11
+subfeatures: !!omap
+- 000_instr_page: !Subfeature
+    name: 000_instr_page
+    tag: VP_traps_F011_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F011_S000_I000
+        description: TBD
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 4.3.1, 4.4.1,
+          4.5.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: TBD
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: MMU related
+- 001_load_page: !Subfeature
+    name: 001_load_page
+    tag: VP_traps_F011_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F011_S001_I000
+        description: TBD
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 4.3.1, 4.4.1,
+          4.5.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: TBD
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: MMU related
+- 002_store_page: !Subfeature
+    name: 002_store_page
+    tag: VP_traps_F011_S002
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F011_S002_I000
+        description: TBD
+        reqt_doc: Privileged Architecture Version 20211203, Chapter 4.3.1, 4.4.1,
+          4.5.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: TBD
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: 56
+        coverage_loc: ''
+        comments: MMU related
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/VP_IP012.yml b/verif/docs/VerifPlans/traps/VP_IP012.yml
new file mode 100644
index 0000000000..8223432fba
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/VP_IP012.yml
@@ -0,0 +1,79 @@
+!Feature
+next_elt_id: 1
+name: Breakpoint
+id: 12
+display_order: 12
+subfeatures: !!omap
+- 000_instr_bkp: !Subfeature
+    name: 000_instr_bkp
+    tag: VP_traps_F012_S000
+    next_elt_id: 2
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F012_S000_I000
+        description: When an instruction address has a trigger set for it and `mcontrol6.action
+          == 0` then a breakpoint exception is taken.
+        reqt_doc: Debug Specification Version 1.0, Chapter 5.6.12
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Breakpoint exception is entered with `mcause` set to 0x3.
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: 48
+        coverage_loc: ''
+        comments: Need debug support
+- 001_data_bkp: !Subfeature
+    name: 001_data_bkp
+    tag: VP_traps_F012_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F012_S001_I000
+        description: When a load/store/AMO address has a trigger set for it and `mcontrol6.action
+          == 0` then a breakpoint exception is taken.
+        reqt_doc: Debug Specification Version 1.0, Chapter 5.6.12
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Breakpoint exception is entered with `mcause` set to 0x3.
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: 48
+        coverage_loc: ''
+        comments: Need debug support
+- 002_environment_break: !Subfeature
+    name: 002_environment_break
+    tag: VP_traps_F012_S002
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_traps_F012_S002_I000
+        description: If an `EBREAK` or `C.EBREAK` is executed and `dcsr.ebreakm` is
+          0 then a breakpoint exception is taken.
+        reqt_doc: Debug Specification Version 1.0, Chapter 4.9.1
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: Breakpoint exception is entered with `mcause` set to 0x3.
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: 48
+        coverage_loc: ''
+        comments: Need debug support
+vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
+io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
+config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
+ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
diff --git a/verif/docs/VerifPlans/traps/runme.sh b/verif/docs/VerifPlans/traps/runme.sh
new file mode 100644
index 0000000000..1fccec7a68
--- /dev/null
+++ b/verif/docs/VerifPlans/traps/runme.sh
@@ -0,0 +1,34 @@
+#############################################################################
+# Copyright (C) 2022 Thales DIS France SAS
+#
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.
+#
+# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com)
+#############################################################################
+#!/bin/sh
+
+# Location of project-specific directories
+ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")`
+
+# Set up platform location.  It can be anywhere but should contain
+# a valid `vp_config.py` file in `vptool` directory.
+# Here we use the verification tree from the example directory.
+export PLATFORM_TOP_DIR="$ROOTDIR"
+
+# Set the printable name for the project that will be used
+# in the human-readable documentation.
+export PROJECT_NAME="Traps"
+
+# Set the alphanumerical identifier of the project that
+# will be used to construct file names etc.
+export PROJECT_IDENT="traps"
+
+# Set the destination directory of Markdown files for this project.
+# Since it will be used by VPTOOL, it shall NOT be a relative path.
+export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"`
+
+# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'.
+# FIXME: Introduce a suitably named shell variable that points to the root
+# directory of the tool set (TOOL_TOP etc.)
+# FORNOW use a hardcoded relative path.
+sh $ROOTDIR/../../../../tools/vptool/vptool.sh $*