diff --git a/config/gen_from_riscv_config/cv32a65x/csr/csr.md b/config/gen_from_riscv_config/cv32a65x/csr/csr.md index ada6ddbe51..1c43fe25bf 100644 --- a/config/gen_from_riscv_config/cv32a65x/csr/csr.md +++ b/config/gen_from_riscv_config/cv32a65x/csr/csr.md @@ -17,14 +17,15 @@ Author: Abdessamii Oukalrazqou |0x301|[MISA](#MISA)|misa is a read-write register reporting the ISA supported by the hart.| |0x304|[MIE](#MIE)|The mie register is an MXLEN-bit read/write register containing interrupt enable bits.| |0x305|[MTVEC](#MTVEC)|MXLEN-bit read/write register that holds trap vector configuration.| +|0x320|[MCOUNTINHIBIT](#MCOUNTINHIBIT)|The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment.| |0x323-0x33f|[MHPMEVENT[3-31]](#MHPMEVENT[3-31])|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.| |0x340|[MSCRATCH](#MSCRATCH)|The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.| |0x341|[MEPC](#MEPC)|The mepc is a warl register that must be able to hold all valid physical and virtual addresses.| |0x342|[MCAUSE](#MCAUSE)|The mcause register stores the information regarding the trap.| |0x343|[MTVAL](#MTVAL)|The mtval is a warl register that holds the address of the instruction which caused the exception.| |0x344|[MIP](#MIP)|The mip register is an MXLEN-bit read/write register containing information on pending interrupts.| -|0x3a0-0x3a1|[PMPCFG[0-1]](#PMPCFG[0-1])|PMP configuration register| -|0x3b0-0x3b7|[PMPADDR[0-7]](#PMPADDR[0-7])|Physical memory protection address register| +|0x3a0-0x3a3|[PMPCFG[0-3]](#PMPCFG[0-3])|PMP configuration register| +|0x3b0-0x3bf|[PMPADDR[0-15]](#PMPADDR[0-15])|Physical memory protection address register| |0xb00|[MCYCLE](#MCYCLE)|Counts the number of clock cycles executed from an arbitrary point in time.| |0xb02|[MINSTRET](#MINSTRET)|Counts the number of instructions completed from an arbitrary point in time.| |0xb03-0xb1f|[MHPMCOUNTER[3-31]](#MHPMCOUNTER[3-31])|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.| @@ -53,7 +54,7 @@ Author: Abdessamii Oukalrazqou |3|MIE|[0 , 1]|0x0|WLRL|Stores the state of the machine mode interrupts.| |4|UPIE||0x0|WARL|Stores the state of the user mode interrupts prior to the trap.| |5|SPIE||0x0|WARL|Stores the state of the supervisor mode interrupts prior to the trap.| -|6|RESERVED_6||0x0|WPRI|RESERVED| +|6|UBE||0x0|WARL|control the endianness of memory accesses other than instruction fetches for user mode| |7|MPIE|[0 , 1]|0x0|WLRL|Stores the state of the machine mode interrupts prior to the trap.| |8|SPP||0x0|WARL|Stores the previous priority mode for supervisor.| |[10:9]|RESERVED_9||0x0|WPRI|RESERVED| @@ -97,7 +98,7 @@ Author: Abdessamii Oukalrazqou **Description** misa is a read-write register reporting the ISA supported by the hart. |Bits|Field Name|Legal Values|Reset|Type|Description| | :--- | :--- | :--- | :--- | :--- | :--- | -|[25:0]|EXTENSIONS|[0x0000000:0x3FFFFFF]|0x1106|WARL|Encodes the presence of the standard extensions, with a single bit per letter of the alphabet.| +|[25:0]|EXTENSIONS|0x1106|0x1106|RO_CONSTANT|Encodes the presence of the standard extensions, with a single bit per letter of the alphabet.| |[29:26]|RESERVED_26||0x0|WPRI|RESERVED| |[31:30]|MXL|[0x1]|0x1|WARL|Encodes the native base integer ISA width.| @@ -113,7 +114,7 @@ Author: Abdessamii Oukalrazqou |0|USIE||0x0|WARL|User Software Interrupt enable.| |1|SSIE||0x0|WARL|Supervisor Software Interrupt enable.| |2|VSSIE||0x0|WARL|VS-level Software Interrupt enable.| -|3|MSIE|[0x0 , 0x1]|0x0|WLRL|Machine Software Interrupt enable.| +|3|MSIE||0x0|WARL|Machine Software Interrupt enable.| |4|UTIE||0x0|WARL|User Timer Interrupt enable.| |5|STIE||0x0|WARL|Supervisor Timer Interrupt enable.| |6|VSTIE||0x0|WARL|VS-level Timer Interrupt enable.| @@ -137,6 +138,17 @@ Author: Abdessamii Oukalrazqou |[1:0]|MODE|[0x0]|0x0|WARL|Vector mode.| |[31:2]|BASE|[0x3FFFFFFF, 0x00000000]|0x20004000|WARL|Vector base address.| +#### MCOUNTINHIBIT + +--- +**Address** 0x320 +**Reset Value** 0x0 +**Privilege Mode** M +**Description** The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. +|Bits|Field Name|Legal Values|Reset|Type|Description| +| :--- | :--- | :--- | :--- | :--- | :--- | +|[31:0]|MCOUNTINHIBIT|0x00000000|0x00000000|RO_CONSTANT|The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment.| + #### MHPMEVENT[3-31] --- @@ -146,7 +158,7 @@ Author: Abdessamii Oukalrazqou **Description** The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. |Bits|Field Name|Legal Values|Reset|Type|Description| | :--- | :--- | :--- | :--- | :--- | :--- | -|[31:0]|MHPMEVENT[I]|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.| +|[31:0]|MHPMEVENT[I]|0x00000000|0x00000000|RO_CONSTANT|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.| #### MSCRATCH @@ -191,7 +203,7 @@ Author: Abdessamii Oukalrazqou **Description** The mtval is a warl register that holds the address of the instruction which caused the exception. |Bits|Field Name|Legal Values|Reset|Type|Description| | :--- | :--- | :--- | :--- | :--- | :--- | -|[31:0]|MTVAL|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|The mtval is a warl register that holds the address of the instruction which caused the exception.| +|[31:0]|MTVAL|0x00000000|0x00000000|RO_CONSTANT|The mtval is a warl register that holds the address of the instruction which caused the exception.| #### MIP @@ -205,7 +217,7 @@ Author: Abdessamii Oukalrazqou |0|USIP||0x0|WARL|User Software Interrupt Pending.| |1|SSIP||0x0|WARL|Supervisor Software Interrupt Pending.| |2|VSSIP||0x0|WARL|VS-level Software Interrupt Pending.| -|3|MSIP|0x1|0x0|RO_VARIABLE|Machine Software Interrupt Pending.| +|3|MSIP||0x0|WARL|Machine Software Interrupt Pending.| |4|UTIP||0x0|WARL|User Timer Interrupt Pending.| |5|STIP||0x0|WARL|Supervisor Timer Interrupt Pending.| |6|VSTIP||0x0|WARL|VS-level Timer Interrupt Pending.| @@ -217,10 +229,10 @@ Author: Abdessamii Oukalrazqou |12|SGEIP||0x0|WARL|HS-level External Interrupt Pending.| |[31:13]|RESERVED_13||0x0|WPRI|RESERVED| -#### PMPCFG[0-1] +#### PMPCFG[0-3] --- -**Address** 0x3a0-0x3a1 +**Address** 0x3a0-0x3a3 **Reset Value** 0x0 **Privilege Mode** M **Description** PMP configuration register @@ -231,10 +243,10 @@ Author: Abdessamii Oukalrazqou |[23:16]|PMP[I*4 + 2]CFG|[0x00:0xFF]|0x0|WARL|pmp configuration bits| |[31:24]|PMP[I*4 + 3]CFG|[0x00:0xFF]|0x0|WARL|pmp configuration bits| -#### PMPADDR[0-7] +#### PMPADDR[0-15] --- -**Address** 0x3b0-0x3b7 +**Address** 0x3b0-0x3bf **Reset Value** 0x0 **Privilege Mode** M **Description** Physical memory protection address register @@ -273,7 +285,7 @@ Author: Abdessamii Oukalrazqou **Description** The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. |Bits|Field Name|Legal Values|Reset|Type|Description| | :--- | :--- | :--- | :--- | :--- | :--- | -|[31:0]|MHPMCOUNTER[I]|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.| +|[31:0]|MHPMCOUNTER[I]|0x00000000|0x00000000|RO_CONSTANT|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.| #### MCYCLEH @@ -306,7 +318,7 @@ Author: Abdessamii Oukalrazqou **Description** The mhpmcounterh returns the upper half word in RV32I systems. |Bits|Field Name|Legal Values|Reset|Type|Description| | :--- | :--- | :--- | :--- | :--- | :--- | -|[31:0]|MHPMCOUNTER[I]H|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|The mhpmcounterh returns the upper half word in RV32I systems.| +|[31:0]|MHPMCOUNTER[I]H|0x00000000|0x00000000|RO_CONSTANT|The mhpmcounterh returns the upper half word in RV32I systems.| #### MVENDORID diff --git a/config/gen_from_riscv_config/cv32a65x/csr/csr.rst b/config/gen_from_riscv_config/cv32a65x/csr/csr.rst index 8eaf9afe39..d791028d1d 100644 --- a/config/gen_from_riscv_config/cv32a65x/csr/csr.rst +++ b/config/gen_from_riscv_config/cv32a65x/csr/csr.rst @@ -12,55 +12,57 @@ csr Register Summary ---------------- -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| Address | Register Name | Description | -+=============+====================+====================================================================================================+ -| 0x300 | MSTATUS | The mstatus register keeps track of and controls the hart’s current operating state. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x300 | MSTATUSH | The mstatush register keeps track of and controls the hart’s current operating state. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x301 | MISA | misa is a read-write register reporting the ISA supported by the hart. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x304 | MIE | The mie register is an MXLEN-bit read/write register containing interrupt enable bits. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x305 | MTVEC | MXLEN-bit read/write register that holds trap vector configuration. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x323-0x33f | MHPMEVENT[3-31] | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x340 | MSCRATCH | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x341 | MEPC | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x342 | MCAUSE | The mcause register stores the information regarding the trap. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x343 | MTVAL | The mtval is a warl register that holds the address of the instruction which caused the exception. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x344 | MIP | The mip register is an MXLEN-bit read/write register containing information on pending interrupts. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x3a0-0x3a1 | PMPCFG[0-1] | PMP configuration register | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0x3b0-0x3b7 | PMPADDR[0-7] | Physical memory protection address register | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0xb00 | MCYCLE | Counts the number of clock cycles executed from an arbitrary point in time. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0xb02 | MINSTRET | Counts the number of instructions completed from an arbitrary point in time. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0xb03-0xb1f | MHPMCOUNTER[3-31] | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0xb80 | MCYCLEH | upper 32 bits of mcycle | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0xb82 | MINSTRETH | Upper 32 bits of minstret. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0xb83-0xb9f | MHPMCOUNTER[3-31]H | The mhpmcounterh returns the upper half word in RV32I systems. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0xf11 | MVENDORID | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0xf12 | MARCHID | MXLEN-bit read-only register encoding the base microarchitecture of the hart. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0xf13 | MIMPID | Provides a unique encoding of the version of the processor implementation. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ -| 0xf14 | MHARTID | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. | -+-------------+--------------------+----------------------------------------------------------------------------------------------------+ ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| Address | Register Name | Description | ++=============+====================+============================================================================================================================+ +| 0x300 | MSTATUS | The mstatus register keeps track of and controls the hart’s current operating state. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x300 | MSTATUSH | The mstatush register keeps track of and controls the hart’s current operating state. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x301 | MISA | misa is a read-write register reporting the ISA supported by the hart. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x304 | MIE | The mie register is an MXLEN-bit read/write register containing interrupt enable bits. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x305 | MTVEC | MXLEN-bit read/write register that holds trap vector configuration. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x320 | MCOUNTINHIBIT | The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x323-0x33f | MHPMEVENT[3-31] | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x340 | MSCRATCH | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x341 | MEPC | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x342 | MCAUSE | The mcause register stores the information regarding the trap. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x343 | MTVAL | The mtval is a warl register that holds the address of the instruction which caused the exception. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x344 | MIP | The mip register is an MXLEN-bit read/write register containing information on pending interrupts. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x3a0-0x3a3 | PMPCFG[0-3] | PMP configuration register | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0x3b0-0x3bf | PMPADDR[0-15] | Physical memory protection address register | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0xb00 | MCYCLE | Counts the number of clock cycles executed from an arbitrary point in time. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0xb02 | MINSTRET | Counts the number of instructions completed from an arbitrary point in time. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0xb03-0xb1f | MHPMCOUNTER[3-31] | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0xb80 | MCYCLEH | upper 32 bits of mcycle | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0xb82 | MINSTRETH | Upper 32 bits of minstret. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0xb83-0xb9f | MHPMCOUNTER[3-31]H | The mhpmcounterh returns the upper half word in RV32I systems. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0xf11 | MVENDORID | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0xf12 | MARCHID | MXLEN-bit read-only register encoding the base microarchitecture of the hart. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0xf13 | MIMPID | Provides a unique encoding of the version of the processor implementation. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ +| 0xf14 | MHARTID | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. | ++-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+ Register Description -------------------- @@ -88,7 +90,7 @@ MSTATUS +---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+ | 5 | SPIE | | 0x0 | WARL | Stores the state of the supervisor mode interrupts prior to the trap. | +---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+ -| 6 | RESERVED_6 | | 0x0 | WPRI | RESERVED | +| 6 | UBE | | 0x0 | WARL | control the endianness of memory accesses other than instruction fetches for user mode | +---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+ | 7 | MPIE | [0 , 1] | 0x0 | WLRL | Stores the state of the machine mode interrupts prior to the trap. | +---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+ @@ -159,15 +161,15 @@ MISA :Description: misa is a read-write register reporting the ISA supported by the hart. -+---------+--------------+-----------------------+---------+--------+------------------------------------------------------------------------------------------------+ -| Bits | Field Name | Legal Values | Reset | Type | Description | -+=========+==============+=======================+=========+========+================================================================================================+ -| [25:0] | EXTENSIONS | [0x0000000:0x3FFFFFF] | 0x1106 | WARL | Encodes the presence of the standard extensions, with a single bit per letter of the alphabet. | -+---------+--------------+-----------------------+---------+--------+------------------------------------------------------------------------------------------------+ -| [29:26] | RESERVED_26 | | 0x0 | WPRI | RESERVED | -+---------+--------------+-----------------------+---------+--------+------------------------------------------------------------------------------------------------+ -| [31:30] | MXL | [0x1] | 0x1 | WARL | Encodes the native base integer ISA width. | -+---------+--------------+-----------------------+---------+--------+------------------------------------------------------------------------------------------------+ ++---------+--------------+----------------+---------+-------------+------------------------------------------------------------------------------------------------+ +| Bits | Field Name | Legal Values | Reset | Type | Description | ++=========+==============+================+=========+=============+================================================================================================+ +| [25:0] | EXTENSIONS | 0x1106 | 0x1106 | RO_CONSTANT | Encodes the presence of the standard extensions, with a single bit per letter of the alphabet. | ++---------+--------------+----------------+---------+-------------+------------------------------------------------------------------------------------------------+ +| [29:26] | RESERVED_26 | | 0x0 | WPRI | RESERVED | ++---------+--------------+----------------+---------+-------------+------------------------------------------------------------------------------------------------+ +| [31:30] | MXL | [0x1] | 0x1 | WARL | Encodes the native base integer ISA width. | ++---------+--------------+----------------+---------+-------------+------------------------------------------------------------------------------------------------+ MIE --- @@ -187,7 +189,7 @@ MIE +---------+--------------+----------------+---------+--------+---------------------------------------+ | 2 | VSSIE | | 0x0 | WARL | VS-level Software Interrupt enable. | +---------+--------------+----------------+---------+--------+---------------------------------------+ -| 3 | MSIE | [0x0 , 0x1] | 0x0 | WLRL | Machine Software Interrupt enable. | +| 3 | MSIE | | 0x0 | WARL | Machine Software Interrupt enable. | +---------+--------------+----------------+---------+--------+---------------------------------------+ | 4 | UTIE | | 0x0 | WARL | User Timer Interrupt enable. | +---------+--------------+----------------+---------+--------+---------------------------------------+ @@ -227,6 +229,21 @@ MTVEC | [31:2] | BASE | [0x3FFFFFFF, 0x00000000] | 0x20004000 | WARL | Vector base address. | +--------+--------------+--------------------------+------------+--------+----------------------+ +MCOUNTINHIBIT +------------- + +:Address: 0x320 +:Reset Value: 0x00000000 +:Privilege Mode: M +:Description: The mcountinhibit is a 32-bit WARL register that controls + which of the hardware performance-monitoring counters increment. + ++--------+---------------+----------------+------------+-------------+----------------------------------------------------------------------------------------------------------------------------+ +| Bits | Field Name | Legal Values | Reset | Type | Description | ++========+===============+================+============+=============+============================================================================================================================+ +| [31:0] | MCOUNTINHIBIT | 0x00000000 | 0x00000000 | RO_CONSTANT | The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. | ++--------+---------------+----------------+------------+-------------+----------------------------------------------------------------------------------------------------------------------------+ + MHPMEVENT[3-31] --------------- @@ -236,11 +253,11 @@ MHPMEVENT[3-31] :Description: The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. -+--------+--------------+---------------------------+------------+--------+--------------------------------------------------------------------------+ -| Bits | Field Name | Legal Values | Reset | Type | Description | -+========+==============+===========================+============+========+==========================================================================+ -| [31:0] | MHPMEVENT[I] | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. | -+--------+--------------+---------------------------+------------+--------+--------------------------------------------------------------------------+ ++--------+--------------+----------------+------------+-------------+--------------------------------------------------------------------------+ +| Bits | Field Name | Legal Values | Reset | Type | Description | ++========+==============+================+============+=============+==========================================================================+ +| [31:0] | MHPMEVENT[I] | 0x00000000 | 0x00000000 | RO_CONSTANT | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. | ++--------+--------------+----------------+------------+-------------+--------------------------------------------------------------------------+ MSCRATCH -------- @@ -298,11 +315,11 @@ MTVAL :Description: The mtval is a warl register that holds the address of the instruction which caused the exception. -+--------+--------------+---------------------------+------------+--------+----------------------------------------------------------------------------------------------------+ -| Bits | Field Name | Legal Values | Reset | Type | Description | -+========+==============+===========================+============+========+====================================================================================================+ -| [31:0] | MTVAL | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | The mtval is a warl register that holds the address of the instruction which caused the exception. | -+--------+--------------+---------------------------+------------+--------+----------------------------------------------------------------------------------------------------+ ++--------+--------------+----------------+------------+-------------+----------------------------------------------------------------------------------------------------+ +| Bits | Field Name | Legal Values | Reset | Type | Description | ++========+==============+================+============+=============+====================================================================================================+ +| [31:0] | MTVAL | 0x00000000 | 0x00000000 | RO_CONSTANT | The mtval is a warl register that holds the address of the instruction which caused the exception. | ++--------+--------------+----------------+------------+-------------+----------------------------------------------------------------------------------------------------+ MIP --- @@ -322,7 +339,7 @@ MIP +---------+--------------+----------------+---------+-------------+----------------------------------------+ | 2 | VSSIP | | 0x0 | WARL | VS-level Software Interrupt Pending. | +---------+--------------+----------------+---------+-------------+----------------------------------------+ -| 3 | MSIP | 0x1 | 0x0 | RO_VARIABLE | Machine Software Interrupt Pending. | +| 3 | MSIP | | 0x0 | WARL | Machine Software Interrupt Pending. | +---------+--------------+----------------+---------+-------------+----------------------------------------+ | 4 | UTIP | | 0x0 | WARL | User Timer Interrupt Pending. | +---------+--------------+----------------+---------+-------------+----------------------------------------+ @@ -345,10 +362,10 @@ MIP | [31:13] | RESERVED_13 | | 0x0 | WPRI | RESERVED | +---------+--------------+----------------+---------+-------------+----------------------------------------+ -PMPCFG[0-1] +PMPCFG[0-3] ----------- -:Address: 0x3a0-0x3a1 +:Address: 0x3a0-0x3a3 :Reset Value: 0x00000000 :Privilege Mode: M :Description: PMP configuration register @@ -365,10 +382,10 @@ PMPCFG[0-1] | [31:24] | PMP[I*4 + 3]CFG | [0x00:0xFF] | 0x0 | WARL | pmp configuration bits | +---------+-----------------+----------------+---------+--------+------------------------+ -PMPADDR[0-7] ------------- +PMPADDR[0-15] +------------- -:Address: 0x3b0-0x3b7 +:Address: 0x3b0-0x3bf :Reset Value: 0x00000000 :Privilege Mode: M :Description: Physical memory protection address register @@ -418,11 +435,11 @@ MHPMCOUNTER[3-31] :Description: The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. -+--------+----------------+---------------------------+------------+--------+---------------------------------------------------------------------------+ -| Bits | Field Name | Legal Values | Reset | Type | Description | -+========+================+===========================+============+========+===========================================================================+ -| [31:0] | MHPMCOUNTER[I] | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. | -+--------+----------------+---------------------------+------------+--------+---------------------------------------------------------------------------+ ++--------+----------------+----------------+------------+-------------+---------------------------------------------------------------------------+ +| Bits | Field Name | Legal Values | Reset | Type | Description | ++========+================+================+============+=============+===========================================================================+ +| [31:0] | MHPMCOUNTER[I] | 0x00000000 | 0x00000000 | RO_CONSTANT | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. | ++--------+----------------+----------------+------------+-------------+---------------------------------------------------------------------------+ MCYCLEH ------- @@ -461,11 +478,11 @@ MHPMCOUNTER[3-31]H :Description: The mhpmcounterh returns the upper half word in RV32I systems. -+--------+-----------------+---------------------------+------------+--------+----------------------------------------------------------------+ -| Bits | Field Name | Legal Values | Reset | Type | Description | -+========+=================+===========================+============+========+================================================================+ -| [31:0] | MHPMCOUNTER[I]H | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | The mhpmcounterh returns the upper half word in RV32I systems. | -+--------+-----------------+---------------------------+------------+--------+----------------------------------------------------------------+ ++--------+-----------------+----------------+------------+-------------+----------------------------------------------------------------+ +| Bits | Field Name | Legal Values | Reset | Type | Description | ++========+=================+================+============+=============+================================================================+ +| [31:0] | MHPMCOUNTER[I]H | 0x00000000 | 0x00000000 | RO_CONSTANT | The mhpmcounterh returns the upper half word in RV32I systems. | ++--------+-----------------+----------------+------------+-------------+----------------------------------------------------------------+ MVENDORID --------- diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.md b/config/gen_from_riscv_config/cv32a65x/isa/isa.md index 544e208654..b587dfd5fc 100644 --- a/config/gen_from_riscv_config/cv32a65x/isa/isa.md +++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.md @@ -17,11 +17,11 @@ Author: Abdessamii Oukalrazqou |C|[RV32C Compressed Instructions](#RV32C Compressed Instructions)|RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V instructions when: the immediate or address offset is small; one of the registers is the zero register (x0), the ABI link register (x1), or the ABI stack pointer (x2); the destination register and the first source register are identical; the registers used are the 8 most popular ones. The C extension is compatible with all other standard instruction extensions. The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary. With the addition of the C extension, JAL and JALR instructions will no longer raise an instruction misaligned exception | |Zicsr|[RV32Zicsr Control and Status Register Instructions](#RV32Zicsr Control and Status Register Instructions)|All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field. | |Zifencei|[RVZifencei Instruction Fetch Fence](#RVZifencei Instruction Fetch Fence)|FENCE.I instruction that provides explicit synchronization between writes to instruction memory and instruction fetches on the same hart. Currently, this instruction is the only standard mechanism to ensure that stores visible to a hart will also be visible to it instruction fetches. | +|Zcb|[RV32Zcb Code Size Reduction Instructions](#RV32Zcb Code Size Reduction Instructions)|Zcb belongs to the group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of the Standard C extension adding more 16-bit instructions to the ISA. Zcb includes the 16-bit version of additional Integer (I), Multiply (M), and Bit-Manipulation (Zbb) Instructions. All the Zcb instructions require at least standard C extension support as a prerequisite, along with M and Zbb extensions for the 16-bit version of the respective instructions. | |Zba|[RVZba Address generation instructions](#RVZba Address generation instructions)|The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address. The shift and add instructions do a left shift of 1, 2, or 3 because these are commonly found in real-world code and because they can be implemented with a minimal amount of additional hardware beyond that of the simple adder. This avoids lengthening the critical path in implementations. While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements. The slli.uw added in this extension can be used when the index is to be interpreted as an unsigned word. | |Zbb|[RVZbb Basic bit-manipulation](#RVZbb Basic bit-manipulation)|The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction. While the instructions are intended to have general use, some instructions are more useful in some domains than others. Hence, several smaller bitmanip extensions are provided. Each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name. | |Zbc|[RVZbc Carry-less multiplication](#RVZbc Carry-less multiplication)|Carry-less multiplication is the multiplication in the polynomial ring over GF(2). clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2✕XLEN carry-less product. clmulr produces bits 2✕XLEN−2:XLEN-1 of the 2✕XLEN carry-less product. | |Zbs|[RVZbs Single bit Instructions](#RVZbs Single bit Instructions)|The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index. | -|Zcb|[RV32Zcb Code Size Reduction Instructions](#RV32Zcb Code Size Reduction Instructions)|Zcb belongs to the group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of the Standard C extension adding more 16-bit instructions to the ISA. Zcb includes the 16-bit version of additional Integer (I), Multiply (M), and Bit-Manipulation (Zbb) Instructions. All the Zcb instructions require at least standard C extension support as a prerequisite, along with M and Zbb extensions for the 16-bit version of the respective instructions. | |Zicntr|[Zicntr](#Zicntr)|No info found yet for extension Zicntr| ### RV32I Base Integer Instructions @@ -130,6 +130,22 @@ Author: Abdessamii Oukalrazqou | :--- | :--- | :--- | :--- | :--- | :--- | :--- | |FENCE.I |[fence.i](#fence.i)|Fence(Store, Fetch)|NONE|NONE |The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on the same RISC-V hart until a FENCE.I instruction is executed. A FENCE.I instruction only ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. |Fetch Fence Operations| +### RV32Zcb Code Size Reduction Instructions + +|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name| +| :--- | :--- | :--- | :--- | :--- | :--- | :--- | +|C.ZEXT.B |[c.zext.b rd'](#c.zext.b rd')|x[8 + rd'] = zext(x[8 + rd'][7:0])|NONE|NONE |This instruction takes a single source/destination operand. It zero-extends the least-significant byte of the operand by inserting zeros into all of the bits more significant than 7. |Code Size Reduction Operations| +|C.SEXT.B |[c.sext.b rd'](#c.sext.b rd')|x[8 + rd'] = sext(x[8 + rd'][7:0])|NONE|NONE |This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. |Code Size Reduction Operations| +|C.ZEXT.H |[c.zext.h rd'](#c.zext.h rd')|x[8 + rd'] = zext(x[8 + rd'][15:0])|NONE|NONE |This instruction takes a single source/destination operand. It zero-extends the least-significant halfword of the operand by inserting zeros into all of the bits more significant than 15. It also requires Bit-Manipulation (Zbb) extension support. |Code Size Reduction Operations| +|C.SEXT.H |[c.sext.h rd'](#c.sext.h rd')|x[8 + rd'] = sext(x[8 + rd'][15:0])|NONE|NONE |This instruction takes a single source/destination operand. It sign-extends the least-significant halfword in the operand by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. |Code Size Reduction Operations| +|C.NOT |[c.not rd'](#c.not rd')|x[8 + rd'] = x[8 + rd'] ^ -1|NONE|NONE |This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register. |Code Size Reduction Operations| +|C.MUL |[c.mul rd', rs2'](#c.mul rd', rs2')|x[8 + rd'] = (x[8 + rd'] * x[8 + rs2'])[31:0]|NONE|NONE |performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rd' and rs2' treated as signed numbers). It also requires M extension support. |Code Size Reduction Operations| +|C.LHU |[c.lhu rd', uimm(rs1')](#c.lhu rd', uimm(rs1'))|x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1])][15:0])|NONE|an exception raised if the memory address isn't aligned (2-byte boundary).|This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended and is written to rd'. |Code Size Reduction Operations| +|C.LH |[c.lh rd', uimm(rs1')](#c.lh rd', uimm(rs1'))|x[8+rd'] = sext(M[x[8+rs1'] + zext(uimm[1])][15:0])|NONE|an exception raised if the memory address isn't aligned (2-byte boundary).|This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended and is written to rd'. |Code Size Reduction Operations| +|C.LBU |[c.lbu rd', uimm(rs1')](#c.lbu rd', uimm(rs1'))|x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1:0])][7:0])|NONE|NONE |This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended and is written to rd'. |Code Size Reduction Operations| +|C.SH |[c.sh rs2', uimm(rs1')](#c.sh rs2', uimm(rs1'))|M[x[8+rs1'] + zext(uimm[1])][15:0] = x[8+rs2']|NONE|an exception raised if the memory address isn't aligned (2-byte boundary).|This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. |Code Size Reduction Operations| +|C.SB |[c.sb rs2', uimm(rs1')](#c.sb rs2', uimm(rs1'))|M[x[8+rs1'] + zext(uimm[1:0])][7:0] = x[8+rs2']|NONE|NONE |This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. |Code Size Reduction Operations| + ### RVZba Address generation instructions |Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name| @@ -192,19 +208,3 @@ Author: Abdessamii Oukalrazqou |BINVI |[binvi rd, rs1, shamt](#binvi rd, rs1, shamt)|X(rd) = X(rs1) ^ (1 << (shamt & (XLEN - 1)))|NONE|NONE |This instruction returns rs1 with a single bit inverted at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. |Single_bit_Operations| |BSET |[bset rd, rs1, rs2](#bset rd, rs1, rs2)|X(rd) = X(rs1) \| (1 << (X(rs2) & (XLEN - 1)))|NONE|NONE |This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2. |Single_bit_Operations| |BSETI |[bseti rd, rs1, shamt](#bseti rd, rs1, shamt)|X(rd) = X(rs1) \| (1 << (shamt & (XLEN - 1)))|NONE|NONE |This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. |Single_bit_Operations| - -### RV32Zcb Code Size Reduction Instructions - -|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name| -| :--- | :--- | :--- | :--- | :--- | :--- | :--- | -|C.ZEXT.B |[c.zext.b rd'](#c.zext.b rd')|x[8 + rd'] = zext(x[8 + rd'][7:0])|NONE|NONE |This instruction takes a single source/destination operand. It zero-extends the least-significant byte of the operand by inserting zeros into all of the bits more significant than 7. |Code Size Reduction Operations| -|C.SEXT.B |[c.sext.b rd'](#c.sext.b rd')|x[8 + rd'] = sext(x[8 + rd'][7:0])|NONE|NONE |This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. |Code Size Reduction Operations| -|C.ZEXT.H |[c.zext.h rd'](#c.zext.h rd')|x[8 + rd'] = zext(x[8 + rd'][15:0])|NONE|NONE |This instruction takes a single source/destination operand. It zero-extends the least-significant halfword of the operand by inserting zeros into all of the bits more significant than 15. It also requires Bit-Manipulation (Zbb) extension support. |Code Size Reduction Operations| -|C.SEXT.H |[c.sext.h rd'](#c.sext.h rd')|x[8 + rd'] = sext(x[8 + rd'][15:0])|NONE|NONE |This instruction takes a single source/destination operand. It sign-extends the least-significant halfword in the operand by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. |Code Size Reduction Operations| -|C.NOT |[c.not rd'](#c.not rd')|x[8 + rd'] = x[8 + rd'] ^ -1|NONE|NONE |This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register. |Code Size Reduction Operations| -|C.MUL |[c.mul rd', rs2'](#c.mul rd', rs2')|x[8 + rd'] = (x[8 + rd'] * x[8 + rs2'])[31:0]|NONE|NONE |performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rd' and rs2' treated as signed numbers). It also requires M extension support. |Code Size Reduction Operations| -|C.LHU |[c.lhu rd', uimm(rs1')](#c.lhu rd', uimm(rs1'))|x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1])][15:0])|NONE|an exception raised if the memory address isn't aligned (2-byte boundary).|This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended and is written to rd'. |Code Size Reduction Operations| -|C.LH |[c.lh rd', uimm(rs1')](#c.lh rd', uimm(rs1'))|x[8+rd'] = sext(M[x[8+rs1'] + zext(uimm[1])][15:0])|NONE|an exception raised if the memory address isn't aligned (2-byte boundary).|This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended and is written to rd'. |Code Size Reduction Operations| -|C.LBU |[c.lbu rd', uimm(rs1')](#c.lbu rd', uimm(rs1'))|x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1:0])][7:0])|NONE|NONE |This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended and is written to rd'. |Code Size Reduction Operations| -|C.SH |[c.sh rs2', uimm(rs1')](#c.sh rs2', uimm(rs1'))|M[x[8+rs1'] + zext(uimm[1])][15:0] = x[8+rs2']|NONE|an exception raised if the memory address isn't aligned (2-byte boundary).|This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. |Code Size Reduction Operations| -|C.SB |[c.sb rs2', uimm(rs1')](#c.sb rs2', uimm(rs1'))|M[x[8+rs1'] + zext(uimm[1:0])][7:0] = x[8+rs2']|NONE|NONE |This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. |Code Size Reduction Operations| diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst index 9b5c3f4774..21bf0a004d 100644 --- a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst +++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst @@ -35,6 +35,8 @@ Instructions | Zifencei | RVZifencei Instruction Fetch Fence_ | FENCE.I instruction that provides explicit synchronization between writes to instruction memory and instruction fetches on the same hart. | | | | Currently, this instruction is the only standard mechanism to ensure that stores visible to a hart will also be visible to it instruction fetches. | +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Zcb | RV32Zcb Code Size Reduction Instructions_ | Zcb belongs to the group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of the Standard C extension adding more 16-bit instructions to the ISA. Zcb includes the 16-bit version of additional Integer (I), Multiply (M), and Bit-Manipulation (Zbb) Instructions. All the Zcb instructions require at least standard C extension support as a prerequisite, along with M and Zbb extensions for the 16-bit version of the respective instructions. | ++---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Zba | RVZba Address generation instructions_ | The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address. The shift and add instructions do a left shift of 1, 2, or 3 because these are commonly found in real-world code and because they can be implemented with a minimal amount of additional hardware beyond that of the simple adder. This avoids lengthening the critical path in implementations. While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements. The slli.uw added in this extension can be used when the index is to be interpreted as an unsigned word. | +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Zbb | RVZbb Basic bit-manipulation_ | The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction. | @@ -46,8 +48,6 @@ Instructions +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Zbs | RVZbs Single bit Instructions_ | The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index. | +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| Zcb | RV32Zcb Code Size Reduction Instructions_ | Zcb belongs to the group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of the Standard C extension adding more 16-bit instructions to the ISA. Zcb includes the 16-bit version of additional Integer (I), Multiply (M), and Bit-Manipulation (Zbb) Instructions. All the Zcb instructions require at least standard C extension support as a prerequisite, along with M and Zbb extensions for the 16-bit version of the respective instructions. | -+---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Zicntr | Zicntr_ | No info found yet for extension Zicntr | +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -253,6 +253,36 @@ RVZifencei Instruction Fetch Fence | FENCE.I | fence.i | Fence(Store, Fetch) | NONE | NONE | The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on the same RISC-V hart until a FENCE.I instruction is executed. A FENCE.I instruction only ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. | Fetch Fence Operations | +---------+----------+---------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+ +RV32Zcb Code Size Reduction Instructions +---------------------------------------- + + ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name | ++==========+=======================+======================================================+==================+============================================================================+==============================================================================================================================================================================================================================================================================================+================================+ +| C.ZEXT.B | c.zext.b rd' | x[8 + rd'] = zext(x[8 + rd'][7:0]) | NONE | NONE | This instruction takes a single source/destination operand. It zero-extends the least-significant byte of the operand by inserting zeros into all of the bits more significant than 7. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| C.SEXT.B | c.sext.b rd' | x[8 + rd'] = sext(x[8 + rd'][7:0]) | NONE | NONE | This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| C.ZEXT.H | c.zext.h rd' | x[8 + rd'] = zext(x[8 + rd'][15:0]) | NONE | NONE | This instruction takes a single source/destination operand. It zero-extends the least-significant halfword of the operand by inserting zeros into all of the bits more significant than 15. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| C.SEXT.H | c.sext.h rd' | x[8 + rd'] = sext(x[8 + rd'][15:0]) | NONE | NONE | This instruction takes a single source/destination operand. It sign-extends the least-significant halfword in the operand by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| C.NOT | c.not rd' | x[8 + rd'] = x[8 + rd'] ^ -1 | NONE | NONE | This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| C.MUL | c.mul rd', rs2' | x[8 + rd'] = (x[8 + rd'] * x[8 + rs2'])[31:0] | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rd' and rs2' treated as signed numbers). It also requires M extension support. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| C.LHU | c.lhu rd', uimm(rs1') | x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1])][15:0]) | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended and is written to rd'. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| C.LH | c.lh rd', uimm(rs1') | x[8+rd'] = sext(M[x[8+rs1'] + zext(uimm[1])][15:0]) | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended and is written to rd'. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| C.LBU | c.lbu rd', uimm(rs1') | x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1:0])][7:0]) | NONE | NONE | This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended and is written to rd'. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| C.SH | c.sh rs2', uimm(rs1') | M[x[8+rs1'] + zext(uimm[1])][15:0] = x[8+rs2'] | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ +| C.SB | c.sb rs2', uimm(rs1') | M[x[8+rs1'] + zext(uimm[1:0])][7:0] = x[8+rs2'] | NONE | NONE | This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. | Code Size Reduction Operations | ++----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ + RVZba Address generation instructions ------------------------------------- @@ -377,33 +407,3 @@ RVZbs Single bit Instructions | BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) | (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations | +--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+ -RV32Zcb Code Size Reduction Instructions ----------------------------------------- - - -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name | -+==========+=======================+======================================================+==================+============================================================================+==============================================================================================================================================================================================================================================================================================+================================+ -| C.ZEXT.B | c.zext.b rd' | x[8 + rd'] = zext(x[8 + rd'][7:0]) | NONE | NONE | This instruction takes a single source/destination operand. It zero-extends the least-significant byte of the operand by inserting zeros into all of the bits more significant than 7. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| C.SEXT.B | c.sext.b rd' | x[8 + rd'] = sext(x[8 + rd'][7:0]) | NONE | NONE | This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| C.ZEXT.H | c.zext.h rd' | x[8 + rd'] = zext(x[8 + rd'][15:0]) | NONE | NONE | This instruction takes a single source/destination operand. It zero-extends the least-significant halfword of the operand by inserting zeros into all of the bits more significant than 15. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| C.SEXT.H | c.sext.h rd' | x[8 + rd'] = sext(x[8 + rd'][15:0]) | NONE | NONE | This instruction takes a single source/destination operand. It sign-extends the least-significant halfword in the operand by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| C.NOT | c.not rd' | x[8 + rd'] = x[8 + rd'] ^ -1 | NONE | NONE | This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| C.MUL | c.mul rd', rs2' | x[8 + rd'] = (x[8 + rd'] * x[8 + rs2'])[31:0] | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rd' and rs2' treated as signed numbers). It also requires M extension support. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| C.LHU | c.lhu rd', uimm(rs1') | x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1])][15:0]) | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended and is written to rd'. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| C.LH | c.lh rd', uimm(rs1') | x[8+rd'] = sext(M[x[8+rs1'] + zext(uimm[1])][15:0]) | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended and is written to rd'. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| C.LBU | c.lbu rd', uimm(rs1') | x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1:0])][7:0]) | NONE | NONE | This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended and is written to rd'. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| C.SH | c.sh rs2', uimm(rs1') | M[x[8+rs1'] + zext(uimm[1])][15:0] = x[8+rs2'] | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ -| C.SB | c.sb rs2', uimm(rs1') | M[x[8+rs1'] + zext(uimm[1:0])][7:0] = x[8+rs2'] | NONE | NONE | This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. | Code Size Reduction Operations | -+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+ - diff --git a/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml b/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml index 132d09dc7d..e98fbf705e 100644 --- a/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml +++ b/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml @@ -3,20 +3,11 @@ # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # Author: Abdessamii Oukalrazqou - -misa: - reset-val: 0x40001106 - -mcountinhibit: - rv32 : - accessible : false -pmpaddr0: - reset-val: 0x0 # Range control pmpaddr : - range: 8 + range : 16 pmpcfg : - range : 2 + range : 4 # Exclude mode exclude : key : priv_mode diff --git a/config/riscv-config/cv32a65x/generated/custom_gen.yaml b/config/riscv-config/cv32a65x/generated/custom_gen.yaml index d2643a54e2..870466d690 100644 --- a/config/riscv-config/cv32a65x/generated/custom_gen.yaml +++ b/config/riscv-config/cv32a65x/generated/custom_gen.yaml @@ -27,22 +27,16 @@ hart0: type: rw: true description: bit for cache-enable of instruction cache - shadow: - shadow_type: msb: 0 lsb: 0 - reserved_0: - implemented: true - description: reserved for future use - type: - ro_constant: 0x0 shadow: shadow_type: - msb: 31 - lsb: 1 fields: - icache - - reserved_0 + - + - + - 1 + - 31 description: the register controls the operation of the i-cache unit. address: 0x7c0 priv_mode: M @@ -61,18 +55,12 @@ hart0: shadow_type: msb: 0 lsb: 0 - reserved_0: - implemented: true - description: reserved for future use - type: - ro_constant: 0x0 - shadow: - shadow_type: - msb: 31 - lsb: 1 fields: - dcache - - reserved_0 + - + - + - 1 + - 31 description: the register controls the operation of the d-cache unit. address: 0x7c1 priv_mode: M diff --git a/config/riscv-config/cv32a65x/generated/isa_gen.yaml b/config/riscv-config/cv32a65x/generated/isa_gen.yaml index 7b7bebfdde..66f7fb3567 100644 --- a/config/riscv-config/cv32a65x/generated/isa_gen.yaml +++ b/config/riscv-config/cv32a65x/generated/isa_gen.yaml @@ -16,14 +16,14 @@ hart_ids: [0] hart0: - ISA: RV32IMCZicsr_Zicntr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV32IMCZicsr_Zicntr_Zifencei_Zcb_Zba_Zbb_Zbc_Zbs User_Spec_Version: '2.3' supported_xlen: - 32 physical_addr_sz: 32 - pmp_granularity: 5 + pmp_granularity: 4 misa: - reset-val: 0x40001104 + reset-val: 0x40001106 rv32: accessible: true mxl: @@ -43,12 +43,7 @@ hart0: extensions: implemented: true type: - warl: - dependency_fields: [] - legal: - - extensions[25:0] in [0x0000000:0x3FFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0001106 description: Encodes the presence of the standard extensions, with a single bit per letter of the alphabet. shadow: @@ -95,6 +90,7 @@ hart0: warl: dependency_fields: [] legal: + # All bits writable (first value of bitmask w/o cleared bits) - base[29:0] bitmask [0x3FFFFFFF, 0x00000000] wr_illegal: - Unchanged @@ -189,6 +185,14 @@ hart0: shadow_type: rw msb: 5 lsb: 5 + ube: + implemented: false + description: control the endianness of memory accesses other than + instruction fetches for user mode + shadow: + shadow_type: rw + msb: 6 + lsb: 6 mpie: implemented: true description: Stores the state of the machine mode interrupts prior @@ -298,6 +302,7 @@ hart0: - mie - upie - spie + - ube - mpie - spp - mpp @@ -314,8 +319,6 @@ hart0: - - - 2 - - - - 6 - - 9 - 10 @@ -354,14 +357,12 @@ hart0: msb: 1 lsb: 1 msip: - implemented: true + implemented: false description: Machine Software Interrupt Pending. shadow: shadow_type: rw msb: 3 lsb: 3 - type: - ro_variable: true utip: implemented: false description: User Timer Interrupt Pending. @@ -489,15 +490,12 @@ hart0: msb: 1 lsb: 1 msie: - implemented: true + implemented: false description: Machine Software Interrupt enable. shadow: shadow_type: rw msb: 3 lsb: 3 - type: - wlrl: - - 0x0:0x1 utie: implemented: false description: User Timer Interrupt enable. @@ -634,18 +632,13 @@ hart0: reset-val: 0x0 rv32: accessible: true + type: + ro_constant: 0x0 fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 - type: - warl: - dependency_fields: [] - legal: - - mtval[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged rv64: accessible: false description: The mtval is a warl register that holds the address of the instruction @@ -744,12 +737,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter3[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -762,35 +750,11 @@ hart0: RV32I mode. address: 0xB03 priv_mode: M - hpmcounter3: - rv32: - accessible: false - rv64: - accessible: false - reset-val: 0x0 - priv_mode: U - description: The hpmcounter3 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC03 - hpmcounter3h: - rv32: - accessible: false - rv64: - accessible: false - reset-val: 0x0 - priv_mode: U - description: The hpmcounter3h returns the upper half word in RV32I systems. - address: 0xC83 mhpmcounter4: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter4[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -803,37 +767,11 @@ hart0: RV42I mode. address: 0xB04 priv_mode: M - mhpmcounter4h: - rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - mhpmcounter4h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - rv64: - accessible: false - reset-val: 0x0 - description: The mhpmcounter4h returns the upper half word in RV42I systems. - address: 0xB84 - priv_mode: M mhpmcounter5: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter5[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -850,12 +788,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter6[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -872,12 +805,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter7[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -894,12 +822,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter8[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -916,12 +839,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter9[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -938,12 +856,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter10[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -960,12 +873,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter11[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -982,12 +890,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter12[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1004,12 +907,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter13[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1026,12 +924,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter14[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1048,12 +941,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter15[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1070,12 +958,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter16[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1092,12 +975,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter17[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1114,12 +992,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter18[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1136,12 +1009,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter19[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1158,12 +1026,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter20[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1180,12 +1043,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter21[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1202,12 +1060,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter22[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1224,12 +1077,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter23[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1246,12 +1094,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter24[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1268,12 +1111,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter25[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1290,12 +1128,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter26[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1312,12 +1145,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter27[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1334,12 +1162,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter28[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1356,12 +1179,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter29[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1378,12 +1196,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter30[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1400,12 +1213,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter31[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1422,12 +1230,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter3h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1439,16 +1242,27 @@ hart0: description: The mhpmcounter3h returns the upper half word in RV32I systems. address: 0xB83 priv_mode: M - mhpmcounter5h: + mhpmcounter4h: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter5h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + rv64: + accessible: false + reset-val: 0x0 + description: The mhpmcounter4h returns the upper half word in RV42I systems. + address: 0xB84 + priv_mode: M + mhpmcounter5h: + rv32: + accessible: true + type: + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1464,12 +1278,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter6h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1485,12 +1294,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter7h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1506,12 +1310,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter8h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1527,12 +1326,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter9h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1548,12 +1342,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter10h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1569,12 +1358,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter11h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1590,12 +1374,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter12h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1611,12 +1390,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter13h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1632,12 +1406,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter14h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1653,12 +1422,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter15h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1674,12 +1438,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter16h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1695,12 +1454,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter17h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1716,12 +1470,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter18h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1737,12 +1486,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter19h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1758,12 +1502,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter20h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1779,12 +1518,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter21h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1800,12 +1534,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter22h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1821,12 +1550,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter23h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1842,12 +1566,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter24h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1863,12 +1582,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter25h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1884,12 +1598,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter26h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1905,12 +1614,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter27h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1926,12 +1630,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter28h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1947,12 +1646,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter29h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1968,12 +1662,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter30h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -1989,12 +1678,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter31h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2010,12 +1694,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcountinhibit[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2032,12 +1711,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent3[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2053,12 +1727,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent4[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2074,12 +1743,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent5[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2095,12 +1759,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent6[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2116,12 +1775,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent7[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2137,12 +1791,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent8[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2158,12 +1807,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent9[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2179,12 +1823,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent10[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2201,12 +1840,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent11[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2223,12 +1857,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent12[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2245,12 +1874,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent13[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2267,12 +1891,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent14[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2289,12 +1908,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent15[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2311,12 +1925,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent16[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2333,12 +1942,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent17[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2355,12 +1959,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent18[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2377,12 +1976,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent19[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2399,12 +1993,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent20[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2421,12 +2010,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent21[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2443,12 +2027,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent22[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2465,12 +2044,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent23[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2487,12 +2061,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent24[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2509,12 +2078,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent25[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2531,12 +2095,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent26[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2553,12 +2112,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent27[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2575,12 +2129,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent28[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2597,12 +2146,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent29[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2619,12 +2163,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent30[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2641,12 +2180,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent31[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -2968,68 +2502,7 @@ hart0: priv_mode: M pmpcfg4: rv32: - accessible: true - pmp16cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp16cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp17cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp17cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp18cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp18cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp19cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp19cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp16cfg - - pmp17cfg - - pmp18cfg - - pmp19cfg + accessible: false rv64: accessible: false reset-val: 0 @@ -3038,68 +2511,7 @@ hart0: priv_mode: M pmpcfg5: rv32: - accessible: true - pmp20cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp20cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp21cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp21cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp22cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp22cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp23cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp23cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp20cfg - - pmp21cfg - - pmp22cfg - - pmp23cfg + accessible: false rv64: accessible: false reset-val: 0 @@ -3108,68 +2520,7 @@ hart0: priv_mode: M pmpcfg6: rv32: - accessible: true - pmp24cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp24cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp25cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp25cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp26cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp26cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp27cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp27cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp24cfg - - pmp25cfg - - pmp26cfg - - pmp27cfg + accessible: false rv64: accessible: false reset-val: 0 @@ -3178,68 +2529,7 @@ hart0: priv_mode: M pmpcfg7: rv32: - accessible: true - pmp28cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp28cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp29cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp29cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp30cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp30cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp31cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp31cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp28cfg - - pmp29cfg - - pmp30cfg - - pmp31cfg + accessible: false rv64: accessible: false reset-val: 0 @@ -3248,68 +2538,7 @@ hart0: priv_mode: M pmpcfg8: rv32: - accessible: true - pmp32cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp32cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp33cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp33cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp34cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp34cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp35cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp35cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp32cfg - - pmp33cfg - - pmp34cfg - - pmp35cfg + accessible: false rv64: accessible: false reset-val: 0 @@ -3318,68 +2547,7 @@ hart0: priv_mode: M pmpcfg9: rv32: - accessible: true - pmp36cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp36cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp37cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp37cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp38cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp38cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp39cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp39cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp36cfg - - pmp37cfg - - pmp38cfg - - pmp39cfg + accessible: false rv64: accessible: false reset-val: 0 @@ -3388,68 +2556,7 @@ hart0: priv_mode: M pmpcfg10: rv32: - accessible: true - pmp40cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp40cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp41cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp41cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp42cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp42cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp43cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp43cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp40cfg - - pmp41cfg - - pmp42cfg - - pmp43cfg + accessible: false rv64: accessible: false reset-val: 0 @@ -3458,68 +2565,7 @@ hart0: priv_mode: M pmpcfg11: rv32: - accessible: true - pmp44cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp44cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp45cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp45cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp46cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp46cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp47cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp47cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp44cfg - - pmp45cfg - - pmp46cfg - - pmp47cfg + accessible: false rv64: accessible: false reset-val: 0 @@ -3528,68 +2574,7 @@ hart0: priv_mode: M pmpcfg12: rv32: - accessible: true - pmp48cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp48cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp49cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp49cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp50cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp50cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp51cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp51cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp48cfg - - pmp49cfg - - pmp50cfg - - pmp51cfg + accessible: false rv64: accessible: false reset-val: 0 @@ -3598,138 +2583,16 @@ hart0: priv_mode: M pmpcfg13: rv32: - accessible: true - pmp52cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp52cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp53cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp53cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp54cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp54cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp55cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp55cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp52cfg - - pmp53cfg - - pmp54cfg - - pmp55cfg + accessible: false rv64: accessible: false - reset-val: 0 - description: PMP configuration register - address: 0x3AD - priv_mode: M - pmpcfg14: - rv32: - accessible: true - pmp56cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp56cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp57cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp57cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp58cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp58cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp59cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp59cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp56cfg - - pmp57cfg - - pmp58cfg - - pmp59cfg + reset-val: 0 + description: PMP configuration register + address: 0x3AD + priv_mode: M + pmpcfg14: + rv32: + accessible: false rv64: accessible: false reset-val: 0 @@ -3738,68 +2601,7 @@ hart0: priv_mode: M pmpcfg15: rv32: - accessible: true - pmp60cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp60cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 7 - lsb: 0 - pmp61cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp61cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 15 - lsb: 8 - pmp62cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp62cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 23 - lsb: 16 - pmp63cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp63cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - description: pmp configuration bits - shadow: - shadow_type: rw - msb: 31 - lsb: 24 - fields: - - pmp60cfg - - pmp61cfg - - pmp62cfg - - pmp63cfg + accessible: false rv64: accessible: false reset-val: 0 @@ -3909,7 +2711,7 @@ hart0: lsb: 0 rv64: accessible: false - reset-val: 0x20 + reset-val: 0 description: Physical memory protection address register address: 0x3B0 priv_mode: M @@ -4064,12 +2866,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr8[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -4085,12 +2882,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr9[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -4106,12 +2898,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr10[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -4127,12 +2914,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr11[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -4148,12 +2930,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr12[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -4169,12 +2946,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr13[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -4190,12 +2962,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr14[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -4211,12 +2978,7 @@ hart0: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr15[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 fields: [] shadow: shadow_type: rw @@ -4230,19 +2992,7 @@ hart0: priv_mode: M pmpaddr16: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr16[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4251,19 +3001,7 @@ hart0: priv_mode: M pmpaddr17: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr17[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4272,19 +3010,7 @@ hart0: priv_mode: M pmpaddr18: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr18[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4293,19 +3019,7 @@ hart0: priv_mode: M pmpaddr19: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr19[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4314,19 +3028,7 @@ hart0: priv_mode: M pmpaddr20: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr20[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4335,19 +3037,7 @@ hart0: priv_mode: M pmpaddr21: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr21[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4356,19 +3046,7 @@ hart0: priv_mode: M pmpaddr22: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr22[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4377,19 +3055,7 @@ hart0: priv_mode: M pmpaddr23: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr23[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4398,19 +3064,7 @@ hart0: priv_mode: M pmpaddr24: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr24[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4419,40 +3073,16 @@ hart0: priv_mode: M pmpaddr25: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr25[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - rv64: accessible: false - reset-val: 0 - description: Physical memory protection address register - address: 0x3C9 - priv_mode: M - pmpaddr26: - rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr26[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + rv64: + accessible: false + reset-val: 0 + description: Physical memory protection address register + address: 0x3C9 + priv_mode: M + pmpaddr26: + rv32: + accessible: false rv64: accessible: false reset-val: 0 @@ -4461,19 +3091,7 @@ hart0: priv_mode: M pmpaddr27: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr27[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4482,19 +3100,7 @@ hart0: priv_mode: M pmpaddr28: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr28[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4503,19 +3109,7 @@ hart0: priv_mode: M pmpaddr29: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr29[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4524,19 +3118,7 @@ hart0: priv_mode: M pmpaddr30: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr30[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4545,19 +3127,7 @@ hart0: priv_mode: M pmpaddr31: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr31[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4566,19 +3136,7 @@ hart0: priv_mode: M pmpaddr32: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr32[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4587,19 +3145,7 @@ hart0: priv_mode: M pmpaddr33: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr33[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4608,19 +3154,7 @@ hart0: priv_mode: M pmpaddr34: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr34[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4629,19 +3163,7 @@ hart0: priv_mode: M pmpaddr35: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr35[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4650,19 +3172,7 @@ hart0: priv_mode: M pmpaddr36: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr36[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4671,19 +3181,7 @@ hart0: priv_mode: M pmpaddr37: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr37[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4692,19 +3190,7 @@ hart0: priv_mode: M pmpaddr38: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr38[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4713,19 +3199,7 @@ hart0: priv_mode: M pmpaddr39: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr39[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4734,19 +3208,7 @@ hart0: priv_mode: M pmpaddr40: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr40[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4755,19 +3217,7 @@ hart0: priv_mode: M pmpaddr41: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr41[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4776,19 +3226,7 @@ hart0: priv_mode: M pmpaddr42: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr42[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4797,19 +3235,7 @@ hart0: priv_mode: M pmpaddr43: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr43[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4818,40 +3244,16 @@ hart0: priv_mode: M pmpaddr44: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr44[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 description: Physical memory protection address register address: 0x3DC priv_mode: M - pmpaddr45: - rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr45[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + pmpaddr45: + rv32: + accessible: false rv64: accessible: false reset-val: 0 @@ -4860,19 +3262,7 @@ hart0: priv_mode: M pmpaddr46: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr46[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4881,19 +3271,7 @@ hart0: priv_mode: M pmpaddr47: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr47[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4902,19 +3280,7 @@ hart0: priv_mode: M pmpaddr48: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr48[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4923,19 +3289,7 @@ hart0: priv_mode: M pmpaddr49: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr49[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4944,19 +3298,7 @@ hart0: priv_mode: M pmpaddr50: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr50[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4965,19 +3307,7 @@ hart0: priv_mode: M pmpaddr51: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr51[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -4986,19 +3316,7 @@ hart0: priv_mode: M pmpaddr52: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr52[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5007,19 +3325,7 @@ hart0: priv_mode: M pmpaddr53: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr53[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5028,19 +3334,7 @@ hart0: priv_mode: M pmpaddr54: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr54[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5049,19 +3343,7 @@ hart0: priv_mode: M pmpaddr55: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr55[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5070,19 +3352,7 @@ hart0: priv_mode: M pmpaddr56: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr56[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5091,19 +3361,7 @@ hart0: priv_mode: M pmpaddr57: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr57[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5112,19 +3370,7 @@ hart0: priv_mode: M pmpaddr58: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr58[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5133,19 +3379,7 @@ hart0: priv_mode: M pmpaddr59: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr59[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5154,19 +3388,7 @@ hart0: priv_mode: M pmpaddr60: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr60[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5175,19 +3397,7 @@ hart0: priv_mode: M pmpaddr61: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr61[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5196,19 +3406,7 @@ hart0: priv_mode: M pmpaddr62: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr62[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5217,19 +3415,7 @@ hart0: priv_mode: M pmpaddr63: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr63[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 + accessible: false rv64: accessible: false reset-val: 0 @@ -5424,6 +3610,16 @@ hart0: address: 0xC82 priv_mode: U reset-val: 0 + hpmcounter3: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter3 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC03 hpmcounter4: rv32: accessible: false @@ -5704,6 +3900,15 @@ hart0: description: The hpmcounter31 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1F + hpmcounter3h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter3h returns the upper half word in RV32I systems. + address: 0xC83 hpmcounter4h: rv32: accessible: false diff --git a/config/riscv-config/cv32a65x/spec/custom_spec.yaml b/config/riscv-config/cv32a65x/spec/custom_spec.yaml index 8928463d52..44e7429cee 100644 --- a/config/riscv-config/cv32a65x/spec/custom_spec.yaml +++ b/config/riscv-config/cv32a65x/spec/custom_spec.yaml @@ -27,19 +27,10 @@ hart0: type: rw: true description: bit for cache-enable of instruction cache - shadow: - shadow_type: msb: 0 lsb: 0 - reserved_0: - implemented: true - description: reserved for future use - type: - ro_constant: 0x0 shadow: shadow_type: - msb: 31 - lsb: 1 description: the register controls the operation of the i-cache unit. address: 0x7c0 priv_mode: M @@ -58,15 +49,6 @@ hart0: shadow_type: msb: 0 lsb: 0 - reserved_0: - implemented: true - description: reserved for future use - type: - ro_constant: 0x0 - shadow: - shadow_type: - msb: 31 - lsb: 1 description: the register controls the operation of the d-cache unit. address: 0x7c1 priv_mode: M diff --git a/config/riscv-config/cv32a65x/spec/isa_spec.yaml b/config/riscv-config/cv32a65x/spec/isa_spec.yaml index 65eb636b99..1da7a13f70 100644 --- a/config/riscv-config/cv32a65x/spec/isa_spec.yaml +++ b/config/riscv-config/cv32a65x/spec/isa_spec.yaml @@ -16,13 +16,13 @@ hart_ids: [0] hart0: &hart0 - ISA: RV32IMCZicsr_Zicntr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV32IMCZicsr_Zicntr_Zifencei_Zcb_Zba_Zbb_Zbc_Zbs User_Spec_Version: '2.3' supported_xlen: [32] physical_addr_sz: 32 - pmp_granularity: 5 + pmp_granularity: 4 misa: - reset-val: 0x40001104 # B: bit 1, C: bit 2, I = bit 8, M = bit 12, Z = bit 25 + reset-val: 0x40001106 # B: bit 1, C: bit 2, I = bit 8, M = bit 12, Z = bit 25 rv32: accessible: true mxl: @@ -37,12 +37,7 @@ hart0: &hart0 extensions: implemented: true type: - warl: - dependency_fields: [] - legal: - - extensions[25:0] in [0x0000000:0x3FFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0001106 mvendorid: reset-val: 0x00000602 rv32: @@ -61,6 +56,7 @@ hart0: &hart0 warl: dependency_fields: [] legal: + # All bits writable (first value of bitmask w/o cleared bits) - base[29:0] bitmask [0x3FFFFFFF, 0x00000000] wr_illegal: - Unchanged @@ -77,52 +73,12 @@ hart0: &hart0 reset-val: 0x0 rv32: accessible: false - uie: - implemented: false - sie: - implemented: false - upie: - implemented: false - spie: - implemented: false - spp: - implemented: false - fs: - implemented: false - xs: - implemented: false - sum: - implemented: false - mxr: - implemented: false - sd: - implemented: false rv64: accessible: false vsstatus: reset-val: 0x0 rv32: accessible: false - uie: - implemented: false - sie: - implemented: false - upie: - implemented: false - spie: - implemented: false - spp: - implemented: false - fs: - implemented: false - xs: - implemented: false - sum: - implemented: false - mxr: - implemented: false - sd: - implemented: false rv64: accessible: false mstatus: @@ -139,6 +95,8 @@ hart0: &hart0 implemented: false spie: implemented: false + ube: + implemented: false mpie: implemented: true spp: @@ -172,7 +130,6 @@ hart0: &hart0 implemented: false rv64: accessible: false - mip: reset-val: 0 rv32: @@ -182,9 +139,7 @@ hart0: &hart0 ssip: implemented: false msip: - implemented: true - type: - ro_variable: true + implemented: false utip: implemented: false stip: @@ -215,8 +170,6 @@ hart0: &hart0 implemented: false sgeip: implemented: false - type: - ro_variable: true rv64: accessible: false mie: @@ -228,9 +181,7 @@ hart0: &hart0 ssie: implemented: false msie: - implemented: true - type: - ro_variable: true + implemented: false utie: implemented: false stie: @@ -269,6 +220,8 @@ hart0: &hart0 reset-val: 0x0 rv32: accessible: true + type: + ro_constant: 0x0 rv64: accessible: false mcause: @@ -281,7 +234,6 @@ hart0: &hart0 implemented: true rv64: accessible: false - marchid: rv32: accessible: true @@ -315,24 +267,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter3[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - rv64: - accessible: false - reset-val: 0x0 - hpmcounter3: - rv32: - accessible: false - rv64: - accessible: false - reset-val: 0x0 - hpmcounter3h: - rv32: - accessible: false + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -340,25 +275,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter4[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - rv64: - accessible: false - reset-val: 0x0 - mhpmcounter4h: - rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - mhpmcounter4h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -366,12 +283,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter5[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -379,12 +291,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter6[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -392,12 +299,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter7[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -405,12 +307,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter8[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -418,12 +315,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter9[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -431,12 +323,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter10[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -444,12 +331,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter11[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -457,12 +339,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter12[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -470,12 +347,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter13[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -483,12 +355,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter14[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -496,12 +363,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter15[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -509,12 +371,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter16[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -522,12 +379,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter17[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -535,12 +387,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter18[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -548,12 +395,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter19[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -561,12 +403,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter20[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -574,12 +411,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter21[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -587,12 +419,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter22[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -600,12 +427,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter23[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -613,12 +435,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter24[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -626,12 +443,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter25[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -639,12 +451,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter26[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -652,12 +459,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter27[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -665,12 +467,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter28[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -678,12 +475,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter29[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -691,12 +483,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter30[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -704,26 +491,23 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter31[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 - mhpmcounter3h: rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter3h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter4h: + rv32: + accessible: true + type: + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -731,12 +515,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter5h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -744,12 +523,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter6h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -757,12 +531,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter7h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -770,12 +539,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter8h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -783,12 +547,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter9h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -796,12 +555,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter10h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -809,12 +563,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter11h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -822,12 +571,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter12h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -835,12 +579,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter13h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -848,12 +587,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter14h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -861,12 +595,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter15h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -874,12 +603,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter16h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -887,12 +611,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter17h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -900,12 +619,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter18h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -913,12 +627,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter19h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -926,12 +635,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter20h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -939,12 +643,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter21h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -952,12 +651,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter22h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -965,12 +659,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter23h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -978,12 +667,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter24h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -991,12 +675,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter25h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1004,12 +683,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter26h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1017,12 +691,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter27h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1030,12 +699,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter28h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1043,12 +707,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter29h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1056,12 +715,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter30h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1069,12 +723,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcounter31h[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1082,12 +731,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmcountinhibit[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1095,12 +739,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent3[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1108,12 +747,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent4[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1121,12 +755,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent5[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1134,12 +763,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent6[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1147,12 +771,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent7[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1160,12 +779,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent8[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1173,12 +787,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent9[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1186,12 +795,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent10[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1199,12 +803,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent11[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1212,12 +811,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent12[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1225,12 +819,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent13[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1238,12 +827,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent14[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1251,12 +835,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent15[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1264,12 +843,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent16[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1277,12 +851,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent17[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1290,12 +859,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent18[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1303,12 +867,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent19[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1316,12 +875,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent20[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1329,12 +883,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent21[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1342,12 +891,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent22[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1355,12 +899,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent23[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1368,12 +907,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent24[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1381,12 +915,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent25[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1394,12 +923,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent26[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1407,12 +931,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent27[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1420,12 +939,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent28[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1433,12 +947,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent29[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1446,12 +955,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent30[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1459,12 +963,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - mhpmevent31[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0x0 @@ -1652,505 +1151,73 @@ hart0: &hart0 reset-val: 0 pmpcfg4: rv32: - accessible: true - pmp16cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp16cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp17cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp17cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp18cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp18cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp19cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp19cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg5: rv32: - accessible: true - pmp20cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp20cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp21cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp21cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp22cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp22cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp23cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp23cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg6: rv32: - accessible: true - pmp24cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp24cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp25cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp25cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp26cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp26cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp27cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp27cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg7: rv32: - accessible: true - pmp28cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp28cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp29cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp29cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp30cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp30cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp31cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp31cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg8: rv32: - accessible: true - pmp32cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp32cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp33cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp33cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp34cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp34cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp35cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp35cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg9: rv32: - accessible: true - pmp36cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp36cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp37cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp37cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp38cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp38cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp39cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp39cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg10: rv32: - accessible: true - pmp40cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp40cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp41cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp41cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp42cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp42cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp43cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp43cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg11: rv32: - accessible: true - pmp44cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp44cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp45cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp45cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp46cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp46cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp47cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp47cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg12: rv32: - accessible: true - pmp48cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp48cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp49cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp49cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp50cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp50cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp51cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp51cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg13: rv32: - accessible: true - pmp52cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp52cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp53cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp53cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp54cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp54cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp55cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp55cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg14: rv32: - accessible: true - pmp56cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp56cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp57cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp57cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp58cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp58cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp59cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp59cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 pmpcfg15: rv32: - accessible: true - pmp60cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp60cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp61cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp61cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp62cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp62cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged - pmp63cfg: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - pmp63cfg[7:0] in [0x00:0xFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 @@ -2218,7 +1285,7 @@ hart0: &hart0 - unchanged rv64: accessible: false - reset-val: 0x20 + reset-val: 0 pmpaddr1: rv32: accessible: true @@ -2314,12 +1381,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr8[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0 @@ -2327,12 +1389,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr9[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0 @@ -2340,12 +1397,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr10[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0 @@ -2353,12 +1405,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr11[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0 @@ -2366,12 +1413,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr12[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0 @@ -2379,12 +1421,7 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr13[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0 @@ -2392,660 +1429,306 @@ hart0: &hart0 rv32: accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr14[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0 pmpaddr15: rv32: - accessible: true + accessible: true type: - warl: - dependency_fields: [] - legal: - - pmpaddr15[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + ro_constant: 0x0 rv64: accessible: false reset-val: 0 pmpaddr16: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr16[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false reset-val: 0 - pmpaddr17: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr17[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr18: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr18[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr19: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr19[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr20: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr20[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr21: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr21[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr22: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr22[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 - + reset-val: 0 pmpaddr23: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr23[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr24: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr24[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr25: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr25[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr26: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr26[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr27: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr27[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr28: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr28[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 - + reset-val: 0 pmpaddr29: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr29[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr30: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr30[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr31: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr31[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr32: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr32[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr33: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr33[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr34: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr34[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 - + reset-val: 0 pmpaddr35: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr35[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr36: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr36[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr37: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr37[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr38: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr38[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr39: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr39[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr40: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr40[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 - + reset-val: 0 pmpaddr41: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr41[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr42: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr42[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr43: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr43[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr44: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr44[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr45: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr45[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr46: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr46[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 - + reset-val: 0 pmpaddr47: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr47[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr48: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr48[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr49: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr49[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr50: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr50[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr51: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr51[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr52: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr52[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 - + reset-val: 0 pmpaddr53: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr53[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr54: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr54[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr55: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr55[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr56: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr56[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr57: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr57[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr58: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr58[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 - + reset-val: 0 pmpaddr59: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr59[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr60: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr60[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr61: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr61[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr62: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr62[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 pmpaddr63: rv32: - accessible: true - type: - warl: - dependency_fields: [] - legal: - - pmpaddr63[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged + accessible: false rv64: accessible: false - reset-val: 0 + reset-val: 0 fcsr: rv64: accessible: false