From 5131fb030c7a5ea1d932b157e0d9ee93ad851914 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= <61976467+ASintzoff@users.noreply.github.com> Date: Fri, 11 Oct 2024 09:12:22 +0200 Subject: [PATCH] doc PMP: rephrase PMP configuration description (#2540) --- docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html | 9 +++++---- docs/06_cv64a6_mmu/riscv/priv-isa-cv64a6_mmu.html | 9 +++++---- docs/riscv-isa/src/machine.adoc | 7 ++++--- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html b/docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html index a09a365519..d686c75b12 100644 --- a/docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html +++ b/docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html @@ -4395,10 +4395,10 @@

3.7.1. Physical Memory Protection CSRs

[CV32A65X] The PMP configuration registers are densely packed into CSRs to minimize -context-switch time. For CV32A65X with sixty four CSRs, pmpcfg0–pmpcfg15, hold -the configurations as shown +context-switch time. For CV32A65X, sixteen CSRs, pmpcfg0–pmpcfg15, hold +the configurations pmp0cfg–pmp63cfg for the 64 PMP entries, as shown in Figure 22. -The 14 upper entries are read-only zero.

+The 14 upper PMP configuration CSRs, pmpcfg2-pmpcfg15, are read-only zero.

@@ -4411,7 +4411,8 @@

3.7.1. Physical Memory Protection CSRs PMP address register encodes bits 33-2 of a 34-bit physical address for RV32, as shown in Figure 23. Not all physical address bits may be implemented, and so the pmpaddr registers -are WARL.

+are WARL. +The 56 upper PMP address CSRs, pmpaddr8-pmpaddr63, are read-only zero.

diff --git a/docs/06_cv64a6_mmu/riscv/priv-isa-cv64a6_mmu.html b/docs/06_cv64a6_mmu/riscv/priv-isa-cv64a6_mmu.html index 0c9a68a904..5a4819f6bc 100644 --- a/docs/06_cv64a6_mmu/riscv/priv-isa-cv64a6_mmu.html +++ b/docs/06_cv64a6_mmu/riscv/priv-isa-cv64a6_mmu.html @@ -4656,10 +4656,10 @@

3.7.1. Physical Memory Protection CSRs

[CV64A6_MMU] The PMP configuration registers are densely packed into CSRs to minimize -context-switch time. For CV64A6_MMU with sixty four CSRs, pmpcfg0–pmpcfg15, hold -the configurations as shown +context-switch time. For CV64A6_MMU, sixteen CSRs, pmpcfg0–pmpcfg15, hold +the configurations pmp0cfg–pmp63cfg for the 64 PMP entries, as shown in Figure 25. -The 14 upper entries are read-only zero.

+The 14 upper PMP configuration CSRs, pmpcfg2-pmpcfg15, are read-only zero.

@@ -4672,7 +4672,8 @@

3.7.1. Physical Memory Protection CSRs PMP address register encodes bits 33-2 of a 34-bit physical address for RV32, as shown in Figure 26. Not all physical address bits may be implemented, and so the pmpaddr registers -are WARL.

+are WARL. +The 56 upper PMP address CSRs, pmpaddr8-pmpaddr63, are read-only zero.

diff --git a/docs/riscv-isa/src/machine.adoc b/docs/riscv-isa/src/machine.adoc index 9a4caf9f65..6bb419d60f 100644 --- a/docs/riscv-isa/src/machine.adoc +++ b/docs/riscv-isa/src/machine.adoc @@ -4194,10 +4194,10 @@ implemented first. All PMP CSR fields are *WARL* and 56 upper entries are read-only zero. PMP CSRs are only accessible to M-mode. [{ohg-config}] The PMP configuration registers are densely packed into CSRs to minimize -context-switch time. For {ohg-config} with sixty four CSRs, `pmpcfg0`–`pmpcfg15`, hold -the configurations as shown +context-switch time. For {ohg-config}, sixteen CSRs, `pmpcfg0`–`pmpcfg15`, hold +the configurations `pmp0cfg`–`pmp63cfg` for the 64 PMP entries, as shown in <>. -The 14 upper entries are read-only zero. +The 14 upper PMP configuration CSRs, `pmpcfg2`-`pmpcfg15`, are read-only zero. [[pmpcfg-rv32]] .RV32 PMP configuration CSR layout. @@ -4208,6 +4208,7 @@ PMP address register encodes bits 33-2 of a 34-bit physical address for RV32, as shown in <>. Not all physical address bits may be implemented, and so the `pmpaddr` registers are *WARL*. +The 56 upper PMP address CSRs, `pmpaddr8`-`pmpaddr63`, are read-only zero. [[pmpaddr-rv32]] .PMP address register format, RV32.