From 45eaace82b0c82d3e9b22c758c8976873fcdbd18 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Wed, 23 Oct 2024 18:12:49 +0200 Subject: [PATCH] =?UTF-8?q?Revert=20"Multicommits=20to=20shorten=20smoke-t?= =?UTF-8?q?ests=20duration,=20to=20declare=20VLEN=20as=20para=E2=80=A6"=20?= =?UTF-8?q?(#2564)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 0877e8e4464bcdc8e64f791d0a3f29434ae51cd3. --- .gitlab-ci.yml | 65 ++++------------- .gitlab-ci/scripts/report_benchmark.py | 12 +-- README.md | 2 +- core/frontend/instr_queue.sv | 2 +- core/include/build_config_pkg.sv | 2 +- core/include/config_pkg.sv | 2 - core/include/cv32a65x_config_pkg.sv | 1 - .../cv32a6_ima_sv32_fpga_config_pkg.sv | 1 - core/include/cv32a6_imac_sv0_config_pkg.sv | 1 - core/include/cv32a6_imac_sv32_config_pkg.sv | 1 - core/include/cv32a6_imafc_sv32_config_pkg.sv | 1 - .../cv64a6_imadfcv_sv39_polara_config_pkg.sv | 1 - core/include/cv64a6_imafdc_sv39_config_pkg.sv | 1 - .../cv64a6_imafdc_sv39_hpdcache_config_pkg.sv | 1 - ...cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 1 - .../cv64a6_imafdc_sv39_wb_config_pkg.sv | 1 - .../include/cv64a6_imafdch_sv39_config_pkg.sv | 1 - .../cv64a6_imafdch_sv39_wb_config_pkg.sv | 1 - .../include/cv64a6_imafdcv_sv39_config_pkg.sv | 1 - core/include/cv64a6_mmu_config_pkg.sv | 1 - core/include/riscv_pkg.sv | 1 + core/instr_realign.sv | 24 +++--- verif/regress/benchmark.sh | 14 ++-- verif/regress/coremark.sh | 16 ++-- verif/regress/cv32a6_tests.sh | 15 ++-- verif/regress/cv64a6_imafdc_tests.sh | 15 ++-- verif/regress/cvxif_verif_regression.sh | 18 +++-- verif/regress/dhrystone.sh | 14 ++-- verif/regress/dhrystone_smoke.sh | 19 +++-- verif/regress/dv-csr-embedded-tests.sh | 14 ++-- verif/regress/dv-generated-tests.sh | 7 +- verif/regress/dv-generated-xif-tests.sh | 7 +- verif/regress/dv-riscv-tests.sh | 12 ++- verif/regress/hwconfig_tests.sh | 47 ++---------- verif/regress/smoke-gen_tests.sh | 12 ++- verif/regress/smoke-tests-cv32a65x.sh | 48 ------------ verif/regress/smoke-tests-cv32a6_imac_sv32.sh | 56 -------------- .../regress/smoke-tests-cv64a6_imafdc_sv39.sh | 58 --------------- verif/regress/smoke-tests.sh | 73 +++++++++++++++++++ verif/sim/cva6.py | 13 +--- .../linker => verif/sim}/link.ld | 0 verif/tb/uvmt/cva6_tb_wrapper.sv | 2 +- .../tests/custom/common/test.ld | 13 ---- verif/tests/custom/return0/return0.c | 22 ------ verif/tests/testlist_csr_embedded.yaml | 2 +- verif/tests/testlist_cvxif.yaml | 4 +- verif/tests/testlist_isacov.yaml | 2 +- verif/tests/testlist_issues.yaml | 2 +- 48 files changed, 213 insertions(+), 416 deletions(-) delete mode 100644 verif/regress/smoke-tests-cv32a65x.sh delete mode 100644 verif/regress/smoke-tests-cv32a6_imac_sv32.sh delete mode 100644 verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh create mode 100644 verif/regress/smoke-tests.sh rename {config/gen_from_riscv_config/linker => verif/sim}/link.ld (100%) rename config/gen_from_riscv_config/cv32a65x/linker/link.ld => verif/tests/custom/common/test.ld (83%) delete mode 100644 verif/tests/custom/return0/return0.c diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c2697e0409..ba9980549e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -135,23 +135,7 @@ build_tools: - head -10000 verif/sim/logfile.log > artifacts/logs/logfile.log.head - if [ -n "$SPIKE_TANDEM" ]; then python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim; else python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log; fi -smoke-tests-cv32a65x: - extends: - - .fe_smoke_test - variables: - DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS" - DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations" - DASHBOARD_SORT_INDEX: 0 - DASHBOARD_JOB_CATEGORY: "Basic" - SPIKE_TANDEM: 1 - COLLECT_SIMU_LOGS: 1 - DV_SIMULATORS: "vcs-uvm" - script: - - bash verif/regress/smoke-tests-cv32a65x.sh - - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone - - !reference [.simu_after_script] - -smoke-tests-cv32a6_imac_sv32: +smoke: extends: - .fe_smoke_test variables: @@ -166,34 +150,14 @@ smoke-tests-cv32a6_imac_sv32: - DV_SIMULATORS: - "vcs-testharness" - "questa-testharness" + - "vcs-uvm" script: - source $QUESTA_BASHRC - - bash verif/regress/smoke-tests-cv32a6_imac_sv32.sh + - bash verif/regress/smoke-tests.sh - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone - !reference [.simu_after_script] -smoke-tests-cv64a6_imafdc_sv39: - extends: - - .fe_smoke_test - variables: - DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS" - DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations" - DASHBOARD_SORT_INDEX: 0 - DASHBOARD_JOB_CATEGORY: "Basic" - SPIKE_TANDEM: 1 - COLLECT_SIMU_LOGS: 1 - parallel: - matrix: - - DV_SIMULATORS: - - "vcs-testharness" - - "questa-testharness" - script: - - source $QUESTA_BASHRC - - bash verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh - - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone - - !reference [.simu_after_script] - -smoke-gen: +gen_smoke: extends: - .fe_smoke_test variables: @@ -217,12 +181,15 @@ smoke-bench: DASHBOARD_SORT_INDEX: 5 DASHBOARD_JOB_CATEGORY: "Performance" SPIKE_TANDEM: 1 - BENCH: "dhrystone" + parallel: + matrix: + - BENCH: "dhrystone" + DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=32768 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8"] script: - bash verif/regress/"$BENCH"_smoke.sh --no-print - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_cv32a65x verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log -smoke-hwconfig: +hwconfig: extends: - .fe_smoke_test variables: @@ -230,10 +197,8 @@ smoke-hwconfig: DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge target configurations" DASHBOARD_SORT_INDEX: 1 DASHBOARD_JOB_CATEGORY: "Basic" - DV_SIMULATORS: "vcs-uvm" - SPIKE_TANDEM: 1 - DV_TARGET: "hwconfig" - DV_HWCONFIG_OPTS: "cv32a65x" + DV_SIMULATORS: "veri-testharness,spike" + DV_HWCONFIG_OPTS: "cv32a6_imac_sv32" script: - source verif/regress/hwconfig_tests.sh - python3 .gitlab-ci/scripts/report_pass.py @@ -361,16 +326,16 @@ benchmarks: matrix: - BENCH: "dhrystone" ISSUE: "single" - DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=0 IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=0 IcacheByteSize=32768 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8"] - BENCH: "dhrystone" ISSUE: "dual" - DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=32768 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8"] - BENCH: "coremark" ISSUE: "single" - DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=0 IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=0 IcacheByteSize=32768 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8"] - BENCH: "coremark" ISSUE: "dual" - DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=32768 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8"] script: - bash verif/regress/"$BENCH".sh - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_"$ISSUE" verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py index c93e892cd1..64e12ccd9f 100644 --- a/.gitlab-ci/scripts/report_benchmark.py +++ b/.gitlab-ci/scripts/report_benchmark.py @@ -19,11 +19,11 @@ # Keep it up-to-date with compiler version and core performance improvements # Will fail if the number of cycles is different from this one valid_cycles = { - "dhrystone_dual": 20199, - "dhrystone_single": 25019, - "coremark_dual": 1017451, - "coremark_single": 1308656, - "dhrystone_cv32a65x": 32566, + "dhrystone_dual": 21530, + "dhrystone_single": 26392, + "coremark_dual": 530099, + "coremark_single": 673184, + "dhrystone_cv32a65x": 33736, } for arg in sys.argv[1:]: @@ -32,7 +32,7 @@ iterations = 50 else: if "--coremark" in arg: - iterations = 4 + iterations = 2 mode = arg.replace("-", "") else: path = arg diff --git a/README.md b/README.md index 63c6ae6205..7f47023df1 100644 --- a/README.md +++ b/README.md @@ -97,7 +97,7 @@ cd ./verif/sim python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml \ --c_tests ../tests/custom/hello_world/hello_world.c \ ---linker=../../config/gen_from_riscv_config/linker/link.ld \ +--linker=../tests/custom/common/test.ld \ --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib \ -nostartfiles -g ../tests/custom/common/syscalls.c \ ../tests/custom/common/crt.S -lgcc \ diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index 938473e264..56558f3668 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -369,7 +369,7 @@ module instr_queue end fetch_entry_o[NID].instruction = instr_data_out[i].instr; fetch_entry_o[NID].ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE; - fetch_entry_o[NID].ex.tval = {{64 - CVA6Cfg.VLEN{1'b0}}, instr_data_out[i].ex_vaddr}; + fetch_entry_o[NID].ex.tval = {{64 - riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr}; fetch_entry_o[NID].branch_predict.cf = instr_data_out[i].cf; // Cannot output two CF the same cycle. pop_instr[i] = fetch_entry_fire[NID]; diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index 629c96dc93..53ab116c6d 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -32,7 +32,7 @@ package build_config_pkg; config_pkg::cva6_cfg_t cfg; cfg.XLEN = CVA6Cfg.XLEN; - cfg.VLEN = CVA6Cfg.VLEN; + cfg.VLEN = (CVA6Cfg.XLEN == 32) ? 32 : 64; cfg.PLEN = (CVA6Cfg.XLEN == 32) ? 34 : 56; cfg.GPLEN = (CVA6Cfg.XLEN == 32) ? 34 : 41; cfg.IS_XLEN32 = IS_XLEN32; diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index f464f69542..30e071fd54 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -48,8 +48,6 @@ package config_pkg; typedef struct packed { // General Purpose Register Size (in bits) int unsigned XLEN; - // Virtual address Size (in bits) - int unsigned VLEN; // Atomic RISC-V extension bit RVA; // Bit manipulation RISC-V extension diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index c886cfbf4c..9047d2f134 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -20,7 +20,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(32), FpgaEn: bit'(0), TechnoCut: bit'(1), SuperscalarEn: bit'(1), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 25bf0290df..0e6510ba5c 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index eb91ac01e2..1fe4d3f551 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index d33e0bc681..27ad32d10c 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index 11eb14e9e4..e00ba727fd 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index 740fe251ea..96315e873d 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index 40feaac7a5..0f02d00657 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index d71531f498..32369a3ab8 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -81,7 +81,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 6785fefd20..ae6d9abd9c 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 99a886d9db..339a5803c7 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index efb9636bb1..560b0b8468 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index 4156235a0b..0fd26e48bb 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 5792767869..c31c2b3819 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -74,7 +74,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv index 3310f558c3..9f30c220ab 100644 --- a/core/include/cv64a6_mmu_config_pkg.sv +++ b/core/include/cv64a6_mmu_config_pkg.sv @@ -27,7 +27,6 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - VLEN: unsigned'(64), FpgaEn: bit'(0), TechnoCut: bit'(0), SuperscalarEn: bit'(0), diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv index 40499c6371..647ff4c7b8 100644 --- a/core/include/riscv_pkg.sv +++ b/core/include/riscv_pkg.sv @@ -23,6 +23,7 @@ package riscv; // FIXME stop using them from CoreV-Verif and HPDCache // Then remove them from this package localparam XLEN = cva6_config_pkg::CVA6ConfigXlen; + localparam VLEN = (XLEN == 32) ? 32 : 64; localparam PLEN = (XLEN == 32) ? 34 : 56; // -------------------- diff --git a/core/instr_realign.sv b/core/instr_realign.sv index 3aae6ff922..9191285b6e 100644 --- a/core/instr_realign.sv +++ b/core/instr_realign.sv @@ -127,7 +127,7 @@ module instr_realign instr_o[2] = '0; addr_o[2] = '0; instr_o[3] = {16'b0, data_i[63:48]}; - addr_o[3] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; + addr_o[3] = {address_i[riscv::VLEN-1:3], 3'b110}; case (address_i[2:1]) 2'b00: begin @@ -153,11 +153,11 @@ module instr_realign addr_o[0] = unaligned_address_q; instr_o[1] = data_i[47:16]; - addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b010}; + addr_o[1] = {address_i[riscv::VLEN-1:3], 3'b010}; if (instr_is_compressed[1]) begin instr_o[2] = data_i[63:32]; - addr_o[2] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; + addr_o[2] = {address_i[riscv::VLEN-1:3], 3'b100}; valid_o[2] = valid_i; if (instr_is_compressed[2]) begin @@ -189,7 +189,7 @@ module instr_realign if (instr_is_compressed[0]) begin instr_o[1] = data_i[47:16]; - addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b010}; + addr_o[1] = {address_i[riscv::VLEN-1:3], 3'b010}; // 64 48 32 16 0 // | 3 | 2 | 1 | 0 | <- instruction slot @@ -200,7 +200,7 @@ module instr_realign // | * | C | C | C | C | -> aligned if (instr_is_compressed[1]) begin instr_o[2] = data_i[63:32]; - addr_o[2] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; + addr_o[2] = {address_i[riscv::VLEN-1:3], 3'b100}; valid_o[2] = valid_i; if (instr_is_compressed[2]) begin @@ -231,7 +231,7 @@ module instr_realign // | * | C | C | I | // | * | I | I | instr_o[1] = data_i[63:32]; - addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; + addr_o[1] = {address_i[riscv::VLEN-1:3], 3'b100}; instr_o[2] = instr_o[3]; addr_o[2] = addr_o[3]; @@ -262,15 +262,15 @@ module instr_realign // 000 110 100 010 <- unaligned address instr_o[0] = data_i[31:0]; - addr_o[0] = {address_i[CVA6Cfg.VLEN-1:3], 3'b010}; + addr_o[0] = {address_i[riscv::VLEN-1:3], 3'b010}; valid_o[0] = valid_i; instr_o[2] = data_i[63:32]; - addr_o[2] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; + addr_o[2] = {address_i[riscv::VLEN-1:3], 3'b110}; if (instr_is_compressed[0]) begin instr_o[1] = data_i[47:16]; - addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; + addr_o[1] = {address_i[riscv::VLEN-1:3], 3'b100}; valid_o[1] = valid_i; if (instr_is_compressed[1]) begin @@ -304,11 +304,11 @@ module instr_realign // 1000 110 100 <- unaligned address instr_o[0] = data_i[31:0]; - addr_o[0] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; + addr_o[0] = {address_i[riscv::VLEN-1:3], 3'b100}; valid_o[0] = valid_i; instr_o[1] = data_i[47:16]; - addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; + addr_o[1] = {address_i[riscv::VLEN-1:3], 3'b110}; if (instr_is_compressed[0]) begin if (instr_is_compressed[1]) begin @@ -330,7 +330,7 @@ module instr_realign // 1000 110 <- unaligned address instr_o[0] = data_i[31:0]; - addr_o[0] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; + addr_o[0] = {address_i[riscv::VLEN-1:3], 3'b110}; if (instr_is_compressed[0]) begin valid_o[0] = valid_i; diff --git a/verif/regress/benchmark.sh b/verif/regress/benchmark.sh index 282bafdec9..3e5bf57e5d 100644 --- a/verif/regress/benchmark.sh +++ b/verif/regress/benchmark.sh @@ -13,18 +13,16 @@ if [ -z "$RISCV" ]; then return fi -if [ -z "$DV_SIMULATORS" ]; then - DV_SIMULATORS=veri-testharness,spike -fi - # install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh source ./verif/sim/setup-env.sh +if [ -z "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness,spike +fi + if [ -z "$DV_TARGET" ]; then DV_TARGET=cv64a6_imafdc_sv39 fi @@ -32,7 +30,7 @@ fi cd verif/sim/ BDIR=../tests/riscv-tests/benchmarks/ -CVA6_FLAGS="--target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml cva6.yaml --linker ../../config/gen_from_riscv_config/linker/link.ld" +CVA6_FLAGS="--target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml cva6.yaml --linker ../tests/custom/common/test.ld" GCC_COMMON_SRC=( ../tests/custom/common/syscalls.c diff --git a/verif/regress/coremark.sh b/verif/regress/coremark.sh index b21ec7e86b..466ee7db9b 100644 --- a/verif/regress/coremark.sh +++ b/verif/regress/coremark.sh @@ -18,18 +18,18 @@ if ! [ -n "$RISCV" ]; then return fi -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-uvm -fi - # install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh +source verif/regress/install-riscv-compliance.sh +source verif/regress/install-riscv-tests.sh source ./verif/sim/setup-env.sh +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm +fi + if ! [ -n "$DV_HWCONFIG_OPTS" ]; then DV_HWCONFIG_OPTS="cv32a65x" fi @@ -76,7 +76,7 @@ cflags_opt=( cflags=( "${cflags_opt[@]}" "-DCOMPILER_FLAGS='\"${cflags_opt[*]}\"'" - -DITERATIONS=4 + -DITERATIONS=2 -DPERFORMANCE_RUN -DSKIP_TIME_CHECK -I../tests/custom/env diff --git a/verif/regress/cv32a6_tests.sh b/verif/regress/cv32a6_tests.sh index 0af6cc0231..720c2734b6 100644 --- a/verif/regress/cv32a6_tests.sh +++ b/verif/regress/cv32a6_tests.sh @@ -14,24 +14,25 @@ if ! [ -n "$RISCV" ]; then return fi -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-testharness,spike -fi # install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh # install the required test suites +source ./verif/regress/install-riscv-compliance.sh source ./verif/regress/install-riscv-tests.sh +source ./verif/regress/install-riscv-arch-test.sh # setup sim env source ./verif/sim/setup-env.sh echo "$SPIKE_INSTALL_DIR$" +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-testharness,spike +fi + if ! [ -n "$DV_TARGET" ]; then DV_TARGET=cv32a65x fi @@ -59,7 +60,7 @@ for t in ${riscv_tests_list[@]} ; do [[ $? > 0 ]] && ((errors++)) done -python3 cva6.py --target ${DV_TARGET} --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c --linker=../../config/gen_from_riscv_config/linker/link.ld\ +python3 cva6.py --target ${DV_TARGET} --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c --linker=../tests/custom/common/test.ld\ --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common" $DV_OPTS [[ $? > 0 ]] && ((errors++)) diff --git a/verif/regress/cv64a6_imafdc_tests.sh b/verif/regress/cv64a6_imafdc_tests.sh index e5164f40e6..a24794b086 100644 --- a/verif/regress/cv64a6_imafdc_tests.sh +++ b/verif/regress/cv64a6_imafdc_tests.sh @@ -17,24 +17,25 @@ if ! [ -n "$RISCV" ]; then return fi -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-testharness,spike -fi # install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh # install the required test suites +source ./verif/regress/install-riscv-compliance.sh source ./verif/regress/install-riscv-tests.sh +source ./verif/regress/install-riscv-arch-test.sh # setup sim env source ./verif/sim/setup-env.sh echo "$SPIKE_INSTALL_DIR$" +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-testharness,spike +fi + if ! [ -n "$DV_TARGET" ]; then DV_TARGET=cv64a6_imafdc_sv39_hpdcache fi @@ -63,7 +64,7 @@ for t in ${riscv_tests_list[@]} ; do done python3 cva6.py --target ${DV_TARGET} --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c \ - --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../../config/gen_from_riscv_config/linker/link.ld" $DV_OPTS + --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" $DV_OPTS [[ $? > 0 ]] && ((errors++)) make -C ../.. clean diff --git a/verif/regress/cvxif_verif_regression.sh b/verif/regress/cvxif_verif_regression.sh index 4d7b9e6503..7661f7c2ad 100644 --- a/verif/regress/cvxif_verif_regression.sh +++ b/verif/regress/cvxif_verif_regression.sh @@ -14,21 +14,23 @@ if ! [ -n "$RISCV" ]; then return fi -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-testharness,spike -fi # install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh +# install the required test suites +source ./verif/regress/install-riscv-tests.sh + # setup sim env source ./verif/sim/setup-env.sh echo "$SPIKE_INSTALL_DIR$" +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-testharness,spike +fi + if ! [ -n "$UVM_VERBOSITY" ]; then export UVM_VERBOSITY=UVM_NONE fi @@ -40,10 +42,10 @@ export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBO cd verif/sim/ make -C ../.. clean make clean_all -python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld +python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS make -C ../.. clean make clean_all -python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld +python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS make -C ../.. clean make clean_all diff --git a/verif/regress/dhrystone.sh b/verif/regress/dhrystone.sh index 160608a290..23d1162497 100644 --- a/verif/regress/dhrystone.sh +++ b/verif/regress/dhrystone.sh @@ -13,18 +13,18 @@ if ! [ -n "$RISCV" ]; then return fi -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-uvm -fi - # install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh +source verif/regress/install-riscv-compliance.sh +source verif/regress/install-riscv-tests.sh source ./verif/sim/setup-env.sh +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm +fi + if ! [ -n "$DV_HWCONFIG_OPTS" ]; then DV_HWCONFIG_OPTS="cv32a65x" fi diff --git a/verif/regress/dhrystone_smoke.sh b/verif/regress/dhrystone_smoke.sh index f1238cb805..9d527204ab 100644 --- a/verif/regress/dhrystone_smoke.sh +++ b/verif/regress/dhrystone_smoke.sh @@ -13,17 +13,21 @@ if ! [ -n "$RISCV" ]; then return fi +# install the required tools +source ./verif/regress/install-verilator.sh +source ./verif/regress/install-spike.sh +source verif/regress/install-riscv-compliance.sh +source verif/regress/install-riscv-tests.sh + +source ./verif/sim/setup-env.sh + if ! [ -n "$DV_SIMULATORS" ]; then DV_SIMULATORS=vcs-uvm fi -# install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh +if ! [ -n "$DV_HWCONFIG_OPTS" ]; then + DV_HWCONFIG_OPTS="cv32a65x" fi -source ./verif/regress/install-spike.sh - -source ./verif/sim/setup-env.sh make clean make -C verif/sim clean_all @@ -54,7 +58,8 @@ cflags=( ) python3 cva6.py \ - --target cv32a65x \ + --target hwconfig \ + --hwconfig_opts="$DV_HWCONFIG_OPTS" \ --iss="$DV_SIMULATORS" \ --iss_yaml=cva6.yaml \ --c_tests "$src0" \ diff --git a/verif/regress/dv-csr-embedded-tests.sh b/verif/regress/dv-csr-embedded-tests.sh index 0e091230bd..13ee55b41c 100644 --- a/verif/regress/dv-csr-embedded-tests.sh +++ b/verif/regress/dv-csr-embedded-tests.sh @@ -13,14 +13,8 @@ if ! [ -n "$RISCV" ]; then return fi -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-uvm,spike -fi - # install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh source ./verif/sim/setup-env.sh @@ -32,7 +26,11 @@ if ! [ -n "$DV_TARGET" ]; then DV_TARGET=cv32a65x fi +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm,spike +fi + cd verif/sim/ -python3 cva6.py --testlist=../tests/testlist_csr_embedded.yaml --iss_yaml cva6.yaml --target $DV_TARGET --iss=$DV_SIMULATORS $DV_OPTS --priv=m --iss_timeout 600 --linker=../../config/gen_from_riscv_config/$DV_TARGET/linker/link.ld +python3 cva6.py --testlist=../tests/testlist_csr_embedded.yaml --iss_yaml cva6.yaml --target $DV_TARGET --iss=$DV_SIMULATORS $DV_OPTS --priv=m --iss_timeout 600 cd - diff --git a/verif/regress/dv-generated-tests.sh b/verif/regress/dv-generated-tests.sh index 36eff7eeeb..fd7946e042 100644 --- a/verif/regress/dv-generated-tests.sh +++ b/verif/regress/dv-generated-tests.sh @@ -18,6 +18,7 @@ if ! [ -n "$RISCV" ]; then fi # install the required tools +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh source ./verif/sim/setup-env.sh @@ -26,6 +27,10 @@ if ! [ -n "$DV_TARGET" ]; then DV_TARGET=cv32a65x fi +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm,spike +fi + if ! [ -n "$list_num" ]; then list_num=1 #default test list fi @@ -132,6 +137,6 @@ done j=0 elif [[ "$list_num" = 0 ]];then printf "==== Execute Directed tests to improve functional coverage of isa, by hitting corners !!! ====\n\n" - python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --isa_extension="zcb" --target $DV_TARGET --iss=vcs-uvm,spike --priv=m --linker=../../config/gen_from_riscv_config/$DV_TARGET/linker/link.ld + python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --isa_extension="zcb" --target $DV_TARGET --iss=vcs-uvm,spike --priv=m fi cd - diff --git a/verif/regress/dv-generated-xif-tests.sh b/verif/regress/dv-generated-xif-tests.sh index 0476e5b56d..cdff3e5d94 100644 --- a/verif/regress/dv-generated-xif-tests.sh +++ b/verif/regress/dv-generated-xif-tests.sh @@ -18,6 +18,7 @@ if ! [ -n "$RISCV" ]; then fi # install the required tools +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh source ./verif/sim/setup-env.sh @@ -26,6 +27,10 @@ if ! [ -n "$DV_TARGET" ]; then DV_TARGET=cv32a65x fi +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm,spike +fi + if ! [ -n "$list_num" ]; then list_num=1 #default test list fi @@ -98,6 +103,6 @@ done j=0 elif [[ "$list_num" = 0 ]];then printf "==== Execute Directed tests to improve functional coverage of isa, by hitting corners !!! ====\n\n" - python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --target $DV_TARGET --iss=vcs-uvm,spike --priv=m --linker=../../config/gen_from_riscv_config/$DV_TARGET/linker/link.ld + python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --target $DV_TARGET --iss=vcs-uvm,spike --priv=m fi cd - diff --git a/verif/regress/dv-riscv-tests.sh b/verif/regress/dv-riscv-tests.sh index 913244c9ca..4cf86d38ed 100755 --- a/verif/regress/dv-riscv-tests.sh +++ b/verif/regress/dv-riscv-tests.sh @@ -13,14 +13,8 @@ if ! [ -n "$RISCV" ]; then return fi -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=veri-testharness,spike -fi - # install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh source verif/regress/install-riscv-tests.sh @@ -30,6 +24,10 @@ if ! [ -n "$DV_TARGET" ]; then DV_TARGET=cv64a6_imafdc_sv39 fi +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness,spike +fi + if ! [ -n "$DV_TESTLISTS" ]; then DV_TESTLISTS="../tests/testlist_riscv-tests-$DV_TARGET-p.yaml \ ../tests/testlist_riscv-tests-$DV_TARGET-v.yaml" diff --git a/verif/regress/hwconfig_tests.sh b/verif/regress/hwconfig_tests.sh index 8fbf0cd8ae..e634501dfd 100644 --- a/verif/regress/hwconfig_tests.sh +++ b/verif/regress/hwconfig_tests.sh @@ -13,51 +13,20 @@ if ! [ -n "$RISCV" ]; then return fi -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-uvm -fi - # install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh +source verif/regress/install-riscv-tests.sh source ./verif/sim/setup-env.sh -if ! [ -n "$DV_TARGET" ]; then - DV_TARGET=cv32a65x +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness,spike fi -make clean -make -C verif/sim clean_all - -cd verif/sim - -srcA=( - ../tests/custom/common/syscalls.c - ../tests/custom/common/crt.S -) -cflags=( - -static - -mcmodel=medany - -fvisibility=hidden - -nostartfiles - -Oz -fno-inline - -Wno-implicit-function-declaration - -Wno-implicit-int - -I../tests/custom/env - -I../tests/custom/common - -I../tests/custom/dhrystone/ - -DNOPRINT -) - -python3 cva6.py \ - --target "$DV_TARGET" \ - --hwconfig_opts="$DV_HWCONFIG_OPTS" \ - --iss="$DV_SIMULATORS" \ - --iss_yaml=cva6.yaml \ - --c_tests "../tests/custom/return0/return0.c" \ - --gcc_opts "${srcA[*]} ${cflags[*]}" +cd verif/sim/ +python3 cva6.py --testlist=../tests/testlist_hwconfig.yaml --iss_yaml cva6.yaml --target hwconfig --isa=rv32imac --hwconfig_opts="$DV_HWCONFIG_OPTS" --iss=$DV_SIMULATORS +make -C ../.. clean +make clean_all cd - diff --git a/verif/regress/smoke-gen_tests.sh b/verif/regress/smoke-gen_tests.sh index 1895dd7fb9..6f820180a9 100644 --- a/verif/regress/smoke-gen_tests.sh +++ b/verif/regress/smoke-gen_tests.sh @@ -17,14 +17,8 @@ if ! [ -n "$RISCV" ]; then return fi -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-uvm -fi - # install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi +source ./verif/regress/install-verilator.sh source ./verif/regress/install-spike.sh source verif/sim/setup-env.sh @@ -33,6 +27,10 @@ if ! [ -n "$DV_TARGET" ]; then DV_TARGET=cv32a65x fi +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm +fi + cd verif/sim/ cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs,zcb" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS --priv=m -i 1 --iss_timeout 300 diff --git a/verif/regress/smoke-tests-cv32a65x.sh b/verif/regress/smoke-tests-cv32a65x.sh deleted file mode 100644 index cc1d8a37b7..0000000000 --- a/verif/regress/smoke-tests-cv32a65x.sh +++ /dev/null @@ -1,48 +0,0 @@ -# Copyright 2021 Thales DIS design services SAS -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# You may obtain a copy of the License at https://solderpad.org/licenses/ -# -# Original Author: Jean-Roch COULON - Thales - -# where are the tools -if ! [ -n "$RISCV" ]; then - echo "Error: RISCV variable undefined" - return -fi - -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-testharness,spike -fi - -# install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi -source ./verif/regress/install-spike.sh - -# setup sim env -source ./verif/sim/setup-env.sh - -echo "$SPIKE_INSTALL_DIR$" - -if ! [ -n "$UVM_VERBOSITY" ]; then - export UVM_VERBOSITY=UVM_NONE -fi - -export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY" - -CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc" - - -cd verif/sim/ - -make -C ../.. clean -make clean_all -python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS -make -C ../.. clean -make clean_all - -cd - diff --git a/verif/regress/smoke-tests-cv32a6_imac_sv32.sh b/verif/regress/smoke-tests-cv32a6_imac_sv32.sh deleted file mode 100644 index 6b6d4217d2..0000000000 --- a/verif/regress/smoke-tests-cv32a6_imac_sv32.sh +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 2021 Thales DIS design services SAS -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# You may obtain a copy of the License at https://solderpad.org/licenses/ -# -# Original Author: Jean-Roch COULON - Thales - -# where are the tools -if ! [ -n "$RISCV" ]; then - echo "Error: RISCV variable undefined" - return -fi - -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-testharness,spike -fi - -# install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi -source ./verif/regress/install-spike.sh - -# install the required test suites -source ./verif/regress/install-riscv-compliance.sh -source ./verif/regress/install-riscv-tests.sh -source ./verif/regress/install-riscv-arch-test.sh - -# setup sim env -source ./verif/sim/setup-env.sh - -echo "$SPIKE_INSTALL_DIR$" - -if ! [ -n "$UVM_VERBOSITY" ]; then - export UVM_VERBOSITY=UVM_NONE -fi - -export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY" - -CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc" - - -cd verif/sim/ - -make -C ../.. clean -make clean_all -python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS -python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS -python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld -python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/linker/link.ld --gcc_opts="$CC_OPTS -nostdlib -lgcc" $DV_OPTS -make -C ../.. clean -make clean_all - -cd - diff --git a/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh b/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh deleted file mode 100644 index d60ce010d2..0000000000 --- a/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh +++ /dev/null @@ -1,58 +0,0 @@ -# Copyright 2021 Thales DIS design services SAS -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# You may obtain a copy of the License at https://solderpad.org/licenses/ -# -# Original Author: Jean-Roch COULON - Thales - -# where are the tools -if ! [ -n "$RISCV" ]; then - echo "Error: RISCV variable undefined" - return -fi - -if ! [ -n "$DV_SIMULATORS" ]; then - DV_SIMULATORS=vcs-testharness,spike -fi - -# install the required tools -if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then - source ./verif/regress/install-verilator.sh -fi -source ./verif/regress/install-spike.sh - -# install the required test suites -source ./verif/regress/install-riscv-compliance.sh -source ./verif/regress/install-riscv-tests.sh -source ./verif/regress/install-riscv-arch-test.sh - -# setup sim env -source ./verif/sim/setup-env.sh - -echo "$SPIKE_INSTALL_DIR$" - -if ! [ -n "$UVM_VERBOSITY" ]; then - export UVM_VERBOSITY=UVM_NONE -fi - -export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY" - -CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc" - - -cd verif/sim/ - -make -C ../.. clean -make clean_all -python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS -python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS -python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS -python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld -python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS -python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --gcc_opts="$CC_OPTS -nostdlib -lgcc" $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld -make -C ../.. clean -make clean_all - -cd - diff --git a/verif/regress/smoke-tests.sh b/verif/regress/smoke-tests.sh new file mode 100644 index 0000000000..67b21fcc2a --- /dev/null +++ b/verif/regress/smoke-tests.sh @@ -0,0 +1,73 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + + +# install the required tools +source ./verif/regress/install-verilator.sh +source ./verif/regress/install-spike.sh + +# install the required test suites +source ./verif/regress/install-riscv-compliance.sh +source ./verif/regress/install-riscv-tests.sh +source ./verif/regress/install-riscv-arch-test.sh + +# setup sim env +source ./verif/sim/setup-env.sh + +echo "$SPIKE_INSTALL_DIR$" + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-testharness,spike +fi + +if ! [ -n "$UVM_VERBOSITY" ]; then + export UVM_VERBOSITY=UVM_NONE +fi + +export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY" + +CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc" + + +cd verif/sim/ + +if [[ "$DV_SIMULATORS" != *"uvm"* ]]; then + make -C ../.. clean + make clean_all + python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS + python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS + python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS + python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld + python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS + python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --gcc_opts="$CC_OPTS" $DV_OPTS --linker=../tests/custom/common/test.ld + make -C ../.. clean + make clean_all + python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS + python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS + python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld + python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS --linker=../tests/custom/common/test.ld --gcc_opts="$CC_OPTS" $DV_OPTS +fi +make -C ../.. clean +make clean_all +python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld +python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS --linker=../tests/custom/common/test.ld --gcc_opts="$CC_OPTS" $DV_OPTS +make -C ../.. clean +make clean_all + + + +cd - diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py index b874ff382f..6a94e64caa 100644 --- a/verif/sim/cva6.py +++ b/verif/sim/cva6.py @@ -33,7 +33,7 @@ from dv.scripts.whisper_log_trace_csv import * from dv.scripts.sail_log_to_trace_csv import * from dv.scripts.instr_trace_compare import * -from pathlib import Path + from types import SimpleNamespace LOGGER = logging.getLogger() @@ -1016,11 +1016,7 @@ def load_config(args, cwd): args.simulator_yaml = cwd + "/cva6-simulator.yaml" if not args.linker: - my_link = Path(cwd + f"/../../config/gen_from_riscv_config/{args.target}/linker/link.ld") - if my_link.is_file(): - args.linker = cwd + f"/../../config/gen_from_riscv_config/{args.target}/linker/link.ld" - else: - args.linker = cwd + f"/../../config/gen_from_riscv_config/linker/link.ld" + args.linker = cwd + "/link.ld" # Keep the core_setting_dir option to be backward compatible, suggest to use # --custom_target @@ -1030,7 +1026,6 @@ def load_config(args, cwd): else: args.core_setting_dir = args.custom_target - base = "" if not args.custom_target: if not args.testlist: args.testlist = cwd + "/target/"+ args.target +"/testlist.yaml" @@ -1040,10 +1035,6 @@ def load_config(args, cwd): output_file = "../../core/include/hwconfig_config_pkg.sv" user_config.derive_config(input_file, output_file, changes) args.hwconfig_opts = user_config.get_config(output_file) - os.system("mkdir -p ../../config/gen_from_riscv_config/hwconfig/spike") - os.system("mkdir -p ../../config/gen_from_riscv_config/hwconfig/linker") - os.system("cp ../../config/gen_from_riscv_config/%s/spike/spike.yaml ../../config/gen_from_riscv_config/hwconfig/spike/" % (base)) - os.system("cp ../../config/gen_from_riscv_config/%s/linker/*.ld ../../config/gen_from_riscv_config/hwconfig/linker/" % (base)) else: base = args.target if base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_wb"): diff --git a/config/gen_from_riscv_config/linker/link.ld b/verif/sim/link.ld similarity index 100% rename from config/gen_from_riscv_config/linker/link.ld rename to verif/sim/link.ld diff --git a/verif/tb/uvmt/cva6_tb_wrapper.sv b/verif/tb/uvmt/cva6_tb_wrapper.sv index 6a063ef844..9b010f51de 100644 --- a/verif/tb/uvmt/cva6_tb_wrapper.sv +++ b/verif/tb/uvmt/cva6_tb_wrapper.sv @@ -68,7 +68,7 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( ) ( input logic clk_i, input logic rst_ni, - input logic [CVA6Cfg.VLEN-1:0] boot_addr_i, + input logic [riscv::VLEN-1:0] boot_addr_i, output logic [31:0] tb_exit_o, output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o, output rvfi_csr_t rvfi_csr_o, diff --git a/config/gen_from_riscv_config/cv32a65x/linker/link.ld b/verif/tests/custom/common/test.ld similarity index 83% rename from config/gen_from_riscv_config/cv32a65x/linker/link.ld rename to verif/tests/custom/common/test.ld index a134ec289a..9c4c8efba7 100644 --- a/config/gen_from_riscv_config/cv32a65x/linker/link.ld +++ b/verif/tests/custom/common/test.ld @@ -23,7 +23,6 @@ SECTIONS /* text: test code section */ . = 0x80000000; - _start_text = .; .text.init : { *(.text.init) } . = ALIGN(0x1000); @@ -34,18 +33,6 @@ SECTIONS . = ALIGN(0x1000); .text : { *(.text) } - . = ALIGN(0x1000); - .text.startup : { *(.text.startup) } - . = ALIGN(0x1000); - _end_text = .; - . = ALIGN(0x1000); - .rodata : { *(.rodata*)} - . = ALIGN(0x8); - . = ALIGN(0x1000); - .page_table : { *(.page_table) } - .user_stack : { *(.user_stack) } - .kernel_data : { *(.kernel_data) } - .kernel_stack : { *(.kernel_stack) } /* data segment */ .data : { *(.data) } diff --git a/verif/tests/custom/return0/return0.c b/verif/tests/custom/return0/return0.c deleted file mode 100644 index 6b20abee28..0000000000 --- a/verif/tests/custom/return0/return0.c +++ /dev/null @@ -1,22 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -*/ - -int main() { - - return 0; -} diff --git a/verif/tests/testlist_csr_embedded.yaml b/verif/tests/testlist_csr_embedded.yaml index b790060a70..ab15da4ae6 100644 --- a/verif/tests/testlist_csr_embedded.yaml +++ b/verif/tests/testlist_csr_embedded.yaml @@ -28,7 +28,7 @@ common_test_config: &common_test_config path_var: TESTS_PATH - gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc" + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" testlist: - test: csr_test diff --git a/verif/tests/testlist_cvxif.yaml b/verif/tests/testlist_cvxif.yaml index 963a89ea44..1f6f45eb43 100644 --- a/verif/tests/testlist_cvxif.yaml +++ b/verif/tests/testlist_cvxif.yaml @@ -28,11 +28,11 @@ common_test_config: &common_test_config path_var: TESTS_PATH - gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common" + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" common_test_config_lgcc: &common_test_config_lgcc path_var: TESTS_PATH - gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc" + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" testlist: - test: cvxif_add_nop diff --git a/verif/tests/testlist_isacov.yaml b/verif/tests/testlist_isacov.yaml index 361ae97c7c..2a8b5b87f8 100644 --- a/verif/tests/testlist_isacov.yaml +++ b/verif/tests/testlist_isacov.yaml @@ -28,7 +28,7 @@ common_test_config: &common_test_config path_var: TESTS_PATH - gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc" + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" testlist: - test: branch_test diff --git a/verif/tests/testlist_issues.yaml b/verif/tests/testlist_issues.yaml index 92913456ce..4703854dea 100644 --- a/verif/tests/testlist_issues.yaml +++ b/verif/tests/testlist_issues.yaml @@ -32,7 +32,7 @@ # -------------------------------------------------------------------------------- common_test_config: &common_test_config path_var: TESTS_PATH - gcc_opts: "-static -misa-spec=2.2 -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../../config/gen_from_riscv_config/linker/link.ld -lgcc" + gcc_opts: "-static -misa-spec=2.2 -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" testlist: - test: compressed-fpreg-commits-rv64