diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.md b/docs/01_cva6_user/ip-xact/cva6_csr.md index 678d924bde..87fd36c732 100644 --- a/docs/01_cva6_user/ip-xact/cva6_csr.md +++ b/docs/01_cva6_user/ip-xact/cva6_csr.md @@ -62,12 +62,15 @@ The ``sstatus`` register is a subset of the ``mstatus`` register. The ``sie`` is the register containing supervisor interrupt enable bits. | BIT | NAME | displayName | RIGHT | Description | | --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- | +| 14:10 | Reserved_10 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 9 | SEIE | Supervisor-level external interrupt enable | read-write,WARL | SEIE is the interrupt\-enable bit for supervisor\-level external interrupts\.| -| 8 | UEIE | | read-write,WARL | User\-level external interrupts are disabled when the UEIE bit in the sie register is clear\.| +| 8 | UEIE | | read-write,WARL | User\-level external interrupts are disabled when the UEIE bit in the sie register is clear\.``Legal Values:``0\.| +| 7:6 | Reserved_6 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 5 | STIE | Supervisor-level timer interrupt enable | read-write,WARL | STIE is the interrupt\-enable bit for supervisor\-level timer interrupts\.| -| 4 | UTIE | | read-write,WARL | User\-level timer interrupts are disabled when the UTIE bit in the sie register is clear\.| +| 4 | UTIE | | read-write,WARL | User\-level timer interrupts are disabled when the UTIE bit in the sie register is clear\.``Legal Values:``0\.| +| 3:2 | Reserved_2 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 1 | SSIE | Supervisor-level software interrupt enable | read-write,WARL | SSIE is the interrupt\-enable bit for supervisor\-level software interrupts\.| -| 0 | USIE | | read-write,WARL | User\-level software interrupts are disabled when the USIE bit in the sie register is clear| +| 0 | USIE | | read-write,WARL | User\-level software interrupts are disabled when the USIE bit in the sie register is clear\.``Legal Values:``0\.| ## Supervisor Trap Vector Base Address Register ### *AddressOffset*: 'h105 @@ -160,12 +163,15 @@ When a trap is taken into S-mode, ``stval`` is written with exception-specific i The ``sip`` register contains information on pending interrupts. | BIT | NAME | displayName | RIGHT | Description | | --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- | +| 14:10 | Reserved_10 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 9 | SEIP | Supervisor-level external interrupt pending | read-only,WARL | SEIP is the interrupt\-pending bit for supervisor\-level external interrupts\.| -| 8 | UEIP | | read-write,WARL | UEIP may be written by S\-mode software to indicate to U\-mode that an external interrupt is pending\.| +| 8 | UEIP | | read-write,WARL | UEIP may be written by S\-mode software to indicate to U\-mode that an external interrupt is pending\.``Legal Values:``0\.| +| 7:6 | Reserved_6 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 5 | STIP | Supervisor-level timer interrupt pending | read-only,WARL | SEIP is the interrupt\-pending bit for supervisor\-level timer interrupts\.| -| 4 | UTIP | | read-write,WARL | A user\-level timer interrupt is pending if the UTIP bit in the sip register is set| +| 4 | UTIP | | read-write,WARL | A user\-level timer interrupt is pending if the UTIP bit in the sip register is set\.``Legal Values:``0\.| +| 3:2 | Reserved_2 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 1 | SSIP | Supervisor-level software interrupt pending | read-only,WARL | SSIP is the interrupt\-pending bit for supervisor\-level software interrupts\.| -| 0 | USIP | | read-write,WARL | A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit| +| 0 | USIP | | read-write,WARL | A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit\.``Legal Values:``0\.| ## Supervisor Address Translation and Protection Register ### *AddressOffset*: 'h180 @@ -241,15 +247,19 @@ Provides individual read/write bits to indicate that certain interrupts should b This register contains machine interrupt enable bits. | BIT | NAME | displayName | RIGHT | Description | | --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- | +| 15:12 | Reserved_12 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 11 | MEIE | M-mode external interrupt enable | read-write,WARL | Enables machine mode external interrupts\.| +| 10 | Reserved_10 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 9 | SEIE | S-mode external interrupt enable | read-write,WARL | Enables supervisor mode external interrupts\.| -| 8 | UEIE | | read-write,WARL | enables U\-mode external interrupts| +| 8 | UEIE | | read-write,WARL | enables U\-mode external interrupts\.``Legal Values:``0\.| | 7 | MTIE | M-mode timer interrupt enable | read-write,WARL | Enables machine mode timer interrupts\.| +| 6 | Reserved_6 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 5 | STIE | S-mode timer interrupt enable | read-write,WARL | Enables supervisor mode timer interrupts\.| -| 4 | UTIE | | read-write,WARL | timer interrupt\-enable bit for U\-mode| +| 4 | UTIE | | read-write,WARL | timer interrupt\-enable bit for U\-mode\.``Legal Values:``0\.| | 3 | MSIE | M-mode software interrupt enable | read-write | Enables machine mode software interrupts\.| +| 2 | Reserved_2 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 1 | SSIE | S-mode software interrupt enable | read-write,WARL | Enables supervisor mode software interrupts\.| -| 0 | USIE | | read-write,WARL | enable U\-mode software interrrupts| +| 0 | USIE | | read-write,WARL | enable U\-mode software interrrupts\.``Legal Values:``0\.| ## Machine Trap Vector Register ### *AddressOffset*: 'h305 @@ -350,15 +360,19 @@ When a trap is taken into M-mode, mtval is either set to zero or written with ex This register contains machine interrupt pending bits. | BIT | NAME | displayName | RIGHT | Description | | --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- | +| 15:12 | Reserved_12 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 11 | MEIP | M-mode external interrupt pending | read-only | The interrupt\-pending bit for machine\-level external interrupts\.| +| 10 | Reserved_10 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 9 | SEIP | S-mode external interrupt pending | read-write | The interrupt\-pending bit for supervisor\-level external interrupts\.| -| 8 | UEIP | | read-write | enables external interrupts| +| 8 | UEIP | | read-write | enables external interrupts\.``Legal Values:``0\.| | 7 | MTIP | M-mode timer interrupt pending | read-only | The interrupt\-pending bit for machine\-level timer interrupts\.| +| 6 | Reserved_6 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 5 | STIP | S-mode timer interrupt pending | read-write | The interrupt\-pending bit for supervisor\-level timer interrupts\.| -| 4 | UTIP | | read-write | Correspond to timer interrupt\-pending bits for user interrupt| +| 4 | UTIP | | read-write | Correspond to timer interrupt\-pending bits for user interrupt\.``Legal Values:``0\.| | 3 | MSIP | M-mode software interrupt pending | read-only | The interrupt\-pending bit for machine\-level software interrupts\.| +| 2 | Reserved_2 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 1 | SSIP | S-mode software interrupt pending | read-write | The interrupt\-pending bit for supervisor\-level software interrupts\.| -| 0 | USIP | | read-write | A hart to directly write its own USIP bits when running in the appropriate mode| +| 0 | USIP | | read-write | A hart to directly write its own USIP bits when running in the appropriate mode\.``Legal Values:``0\.| ## Physical Memory Protection Config 0 Register ### *AddressOffset*: 'h3A0 diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.rst b/docs/01_cva6_user/ip-xact/cva6_csr.rst index b2ebcaaf24..3e7a83396a 100644 --- a/docs/01_cva6_user/ip-xact/cva6_csr.rst +++ b/docs/01_cva6_user/ip-xact/cva6_csr.rst @@ -206,6 +206,11 @@ The ``sie`` is the register containing supervisor interrupt enable bits. - **displayName** - **RIGHT** - **Description** + * - 14:10 + - Reserved_10 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 9 - SEIE - Supervisor-level external interrupt enable @@ -215,7 +220,12 @@ The ``sie`` is the register containing supervisor interrupt enable bits. - UEIE - - read-write,WARL - - User\-level external interrupts are disabled when the UEIE bit in the sie register is clear\. + - User\-level external interrupts are disabled when the UEIE bit in the sie register is clear\.``Legal Values:``0\. + * - 7:6 + - Reserved_6 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 5 - STIE - Supervisor-level timer interrupt enable @@ -225,7 +235,12 @@ The ``sie`` is the register containing supervisor interrupt enable bits. - UTIE - - read-write,WARL - - User\-level timer interrupts are disabled when the UTIE bit in the sie register is clear\. + - User\-level timer interrupts are disabled when the UTIE bit in the sie register is clear\.``Legal Values:``0\. + * - 3:2 + - Reserved_2 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 1 - SSIE - Supervisor-level software interrupt enable @@ -235,7 +250,7 @@ The ``sie`` is the register containing supervisor interrupt enable bits. - USIE - - read-write,WARL - - User\-level software interrupts are disabled when the USIE bit in the sie register is clear + - User\-level software interrupts are disabled when the USIE bit in the sie register is clear\.``Legal Values:``0\. Supervisor Trap Vector Base Address Register -------------------------- @@ -511,6 +526,11 @@ The ``sip`` register contains information on pending interrupts. - **displayName** - **RIGHT** - **Description** + * - 14:10 + - Reserved_10 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 9 - SEIP - Supervisor-level external interrupt pending @@ -520,7 +540,12 @@ The ``sip`` register contains information on pending interrupts. - UEIP - - read-write,WARL - - UEIP may be written by S\-mode software to indicate to U\-mode that an external interrupt is pending\. + - UEIP may be written by S\-mode software to indicate to U\-mode that an external interrupt is pending\.``Legal Values:``0\. + * - 7:6 + - Reserved_6 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 5 - STIP - Supervisor-level timer interrupt pending @@ -530,7 +555,12 @@ The ``sip`` register contains information on pending interrupts. - UTIP - - read-write,WARL - - A user\-level timer interrupt is pending if the UTIP bit in the sip register is set + - A user\-level timer interrupt is pending if the UTIP bit in the sip register is set\.``Legal Values:``0\. + * - 3:2 + - Reserved_2 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 1 - SSIP - Supervisor-level software interrupt pending @@ -540,7 +570,7 @@ The ``sip`` register contains information on pending interrupts. - USIP - - read-write,WARL - - A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit + - A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit\.``Legal Values:``0\. Supervisor Address Translation and Protection Register -------------------------- @@ -794,11 +824,21 @@ This register contains machine interrupt enable bits. - **displayName** - **RIGHT** - **Description** + * - 15:12 + - Reserved_12 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 11 - MEIE - M-mode external interrupt enable - read-write,WARL - Enables machine mode external interrupts\. + * - 10 + - Reserved_10 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 9 - SEIE - S-mode external interrupt enable @@ -808,12 +848,17 @@ This register contains machine interrupt enable bits. - UEIE - - read-write,WARL - - enables U\-mode external interrupts + - enables U\-mode external interrupts\.``Legal Values:``0\. * - 7 - MTIE - M-mode timer interrupt enable - read-write,WARL - Enables machine mode timer interrupts\. + * - 6 + - Reserved_6 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 5 - STIE - S-mode timer interrupt enable @@ -823,12 +868,17 @@ This register contains machine interrupt enable bits. - UTIE - - read-write,WARL - - timer interrupt\-enable bit for U\-mode + - timer interrupt\-enable bit for U\-mode\.``Legal Values:``0\. * - 3 - MSIE - M-mode software interrupt enable - read-write - Enables machine mode software interrupts\. + * - 2 + - Reserved_2 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 1 - SSIE - S-mode software interrupt enable @@ -838,7 +888,7 @@ This register contains machine interrupt enable bits. - USIE - - read-write,WARL - - enable U\-mode software interrrupts + - enable U\-mode software interrrupts\.``Legal Values:``0\. Machine Trap Vector Register -------------------------- @@ -1137,11 +1187,21 @@ This register contains machine interrupt pending bits. - **displayName** - **RIGHT** - **Description** + * - 15:12 + - Reserved_12 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 11 - MEIP - M-mode external interrupt pending - read-only - The interrupt\-pending bit for machine\-level external interrupts\. + * - 10 + - Reserved_10 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 9 - SEIP - S-mode external interrupt pending @@ -1151,12 +1211,17 @@ This register contains machine interrupt pending bits. - UEIP - - read-write - - enables external interrupts + - enables external interrupts\.``Legal Values:``0\. * - 7 - MTIP - M-mode timer interrupt pending - read-only - The interrupt\-pending bit for machine\-level timer interrupts\. + * - 6 + - Reserved_6 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 5 - STIP - S-mode timer interrupt pending @@ -1166,12 +1231,17 @@ This register contains machine interrupt pending bits. - UTIP - - read-write - - Correspond to timer interrupt\-pending bits for user interrupt + - Correspond to timer interrupt\-pending bits for user interrupt\.``Legal Values:``0\. * - 3 - MSIP - M-mode software interrupt pending - read-only - The interrupt\-pending bit for machine\-level software interrupts\. + * - 2 + - Reserved_2 + - Reserved + - read-write,WARL + - Reserved\.``Legal Values:``0\. * - 1 - SSIP - S-mode software interrupt pending @@ -1181,7 +1251,7 @@ This register contains machine interrupt pending bits. - USIP - - read-write - - A hart to directly write its own USIP bits when running in the appropriate mode + - A hart to directly write its own USIP bits when running in the appropriate mode\.``Legal Values:``0\. Physical Memory Protection Config 0 Register -------------------------- diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.xml b/docs/01_cva6_user/ip-xact/cva6_csr.xml index 34a309e6e0..1370696bd4 100644 --- a/docs/01_cva6_user/ip-xact/cva6_csr.xml +++ b/docs/01_cva6_user/ip-xact/cva6_csr.xml @@ -531,6 +531,23 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.'h104 32 read-write + + Reserved_10 + Reserved + Reserved.``Legal Values:``0. + 10 + + + 0x0 + 0x1 + + + 5 + read-write + + WARL + + SEIE Supervisor-level External Interrupt Enable @@ -550,7 +567,7 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1. UEIE - User-level external interrupts are disabled when the UEIE bit in the sie register is clear. + User-level external interrupts are disabled when the UEIE bit in the sie register is clear.``Legal Values:``0. 8 @@ -564,6 +581,23 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.WARL + + Reserved_6 + Reserved + Reserved.``Legal Values:``0. + 6 + + + 0x0 + 0x1 + + + 2 + read-write + + WARL + + STIE Supervisor-level Timer Interrupt Enable @@ -583,7 +617,7 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1. UTIE - User-level timer interrupts are disabled when the UTIE bit in the sie register is clear. + User-level timer interrupts are disabled when the UTIE bit in the sie register is clear.``Legal Values:``0. 4 @@ -597,6 +631,23 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.WARL + + Reserved_2 + Reserved + Reserved.``Legal Values:``0. + 2 + + + 0x0 + 0x1 + + + 2 + read-write + + WARL + + SSIE Supervisor-level Software Interrupt Enable @@ -616,7 +667,7 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1. USIE - User-level software interrupts are disabled when the USIE bit in the sie register is clear + User-level software interrupts are disabled when the USIE bit in the sie register is clear.``Legal Values:``0. 0 @@ -940,6 +991,23 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus 32 true read-write + + Reserved_10 + Reserved + Reserved.``Legal Values:``0. + 10 + + + 0x0 + 0x1 + + + 5 + read-write + + WARL + + SEIP Supervisor-level External Interrupt Pending @@ -960,7 +1028,7 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus UEIP - UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending. + UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending.``Legal Values:``0. 8 @@ -974,6 +1042,23 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus WARL + + Reserved_6 + Reserved + Reserved.``Legal Values:``0. + 6 + + + 0x0 + 0x1 + + + 2 + read-write + + WARL + + STIP Supervisor-level Timer Interrupt Pending @@ -994,7 +1079,7 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus UTIP - A user-level timer interrupt is pending if the UTIP bit in the sip register is set + A user-level timer interrupt is pending if the UTIP bit in the sip register is set.``Legal Values:``0. 4 @@ -1008,6 +1093,23 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus WARL + + Reserved_2 + Reserved + Reserved.``Legal Values:``0. + 2 + + + 0x0 + 0x1 + + + 2 + read-write + + WARL + + SSIP Supervisor-level Software Interrupt Pending @@ -1028,7 +1130,7 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus USIP - A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit + A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit.``Legal Values:``0. 0 @@ -1763,6 +1865,23 @@ with the index of the bit position equal to the value returned in the ``mcause`` 'h304 32 read-write + + Reserved_12 + Reserved + Reserved.``Legal Values:``0. + 12 + + + 0x0 + 0x1 + + + 4 + read-write + + WARL + + MEIE M-mode External Interrupt Enable @@ -1780,6 +1899,23 @@ with the index of the bit position equal to the value returned in the ``mcause`` WARL + + Reserved_10 + Reserved + Reserved.``Legal Values:``0. + 10 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + SEIE S-mode External Interrupt Enable @@ -1799,7 +1935,7 @@ with the index of the bit position equal to the value returned in the ``mcause`` UEIE - enables U-mode external interrupts + enables U-mode external interrupts.``Legal Values:``0. 8 @@ -1830,6 +1966,23 @@ with the index of the bit position equal to the value returned in the ``mcause`` WARL + + Reserved_6 + Reserved + Reserved.``Legal Values:``0. + 6 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + STIE S-mode Timer Interrupt Enable @@ -1849,7 +2002,7 @@ with the index of the bit position equal to the value returned in the ``mcause`` UTIE - timer interrupt-enable bit for U-mode + timer interrupt-enable bit for U-mode.``Legal Values:``0. 4 @@ -1877,6 +2030,23 @@ with the index of the bit position equal to the value returned in the ``mcause`` 1 read-write + + Reserved_2 + Reserved + Reserved.``Legal Values:``0. + 2 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + SSIE S-mode Software Interrupt Enable @@ -1896,7 +2066,7 @@ with the index of the bit position equal to the value returned in the ``mcause`` USIE - enable U-mode software interrrupts + enable U-mode software interrrupts.``Legal Values:``0. 0 @@ -2243,6 +2413,23 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or 32 true read-write + + Reserved_12 + Reserved + Reserved.``Legal Values:``0. + 12 + + + 0x0 + 0x1 + + + 4 + read-write + + WARL + + MEIP M-mode External Interrupt Pending @@ -2258,6 +2445,23 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or true read-only + + Reserved_10 + Reserved + Reserved.``Legal Values:``0. + 10 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + SEIP S-mode External Interrupt Pending @@ -2274,7 +2478,7 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or UEIP - enables external interrupts + enables external interrupts.``Legal Values:``0. 8 @@ -2300,6 +2504,23 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or true read-only + + Reserved_6 + Reserved + Reserved.``Legal Values:``0. + 6 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + STIP S-mode Timer Interrupt Pending @@ -2316,7 +2537,7 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or UTIP - Correspond to timer interrupt-pending bits for user interrupt + Correspond to timer interrupt-pending bits for user interrupt.``Legal Values:``0. 4 @@ -2342,6 +2563,23 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or true read-only + + Reserved_2 + Reserved + Reserved.``Legal Values:``0. + 2 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + SSIP S-mode Software Interrupt Pending @@ -2358,7 +2596,7 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or USIP - A hart to directly write its own USIP bits when running in the appropriate mode + A hart to directly write its own USIP bits when running in the appropriate mode.``Legal Values:``0. 0 diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.yaml b/docs/01_cva6_user/ip-xact/cva6_csr.yaml index b9298bda63..911a861d87 100644 --- a/docs/01_cva6_user/ip-xact/cva6_csr.yaml +++ b/docs/01_cva6_user/ip-xact/cva6_csr.yaml @@ -399,6 +399,18 @@ component: size: '32' access: read-write field: + - name: Reserved_10 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '10' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '5' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: SEIE displayName: Supervisor-level External Interrupt Enable description: SEIE is the interrupt-enable bit for supervisor-level external interrupts. @@ -412,7 +424,7 @@ component: vendorExtensions: RISCV_behavior: WARL - name: UEIE - description: User-level external interrupts are disabled when the UEIE bit in the sie register is clear. + description: User-level external interrupts are disabled when the UEIE bit in the sie register is clear.``Legal Values:``0. bitOffset: '8' resets: reset: @@ -422,6 +434,18 @@ component: access: read-write vendorExtensions: RISCV_behavior: WARL + - name: Reserved_6 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '6' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '2' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: STIE displayName: Supervisor-level Timer Interrupt Enable description: STIE is the interrupt-enable bit for supervisor-level timer interrupts. @@ -435,7 +459,7 @@ component: vendorExtensions: RISCV_behavior: WARL - name: UTIE - description: User-level timer interrupts are disabled when the UTIE bit in the sie register is clear. + description: User-level timer interrupts are disabled when the UTIE bit in the sie register is clear.``Legal Values:``0. bitOffset: '4' resets: reset: @@ -445,6 +469,18 @@ component: access: read-write vendorExtensions: RISCV_behavior: WARL + - name: Reserved_2 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '2' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '2' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: SSIE displayName: Supervisor-level Software Interrupt Enable description: SSIE is the interrupt-enable bit for supervisor-level software interrupts. @@ -458,7 +494,7 @@ component: vendorExtensions: RISCV_behavior: WARL - name: USIE - description: User-level software interrupts are disabled when the USIE bit in the sie register is clear + description: User-level software interrupts are disabled when the USIE bit in the sie register is clear.``Legal Values:``0. bitOffset: '0' resets: reset: @@ -667,6 +703,18 @@ component: volatile: 'true' access: read-write field: + - name: Reserved_10 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '10' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '5' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: SEIP displayName: Supervisor-level External Interrupt Pending description: SEIP is the interrupt-pending bit for supervisor-level external interrupts. @@ -681,7 +729,7 @@ component: vendorExtensions: RISCV_behavior: WARL - name: UEIP - description: UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending. + description: UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending.``Legal Values:``0. bitOffset: '8' resets: reset: @@ -691,6 +739,18 @@ component: access: read-write vendorExtensions: RISCV_behavior: WARL + - name: Reserved_6 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '6' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '2' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: STIP displayName: Supervisor-level Timer Interrupt Pending description: SEIP is the interrupt-pending bit for supervisor-level timer interrupts. @@ -705,7 +765,7 @@ component: vendorExtensions: RISCV_behavior: WARL - name: UTIP - description: A user-level timer interrupt is pending if the UTIP bit in the sip register is set + description: A user-level timer interrupt is pending if the UTIP bit in the sip register is set.``Legal Values:``0. bitOffset: '4' resets: reset: @@ -715,6 +775,18 @@ component: access: read-write vendorExtensions: RISCV_behavior: WARL + - name: Reserved_2 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '2' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '2' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: SSIP displayName: Supervisor-level Software Interrupt Pending description: SSIP is the interrupt-pending bit for supervisor-level software interrupts. @@ -729,7 +801,7 @@ component: vendorExtensions: RISCV_behavior: WARL - name: USIP - description: A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit + description: A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit.``Legal Values:``0. bitOffset: '0' resets: reset: @@ -1267,6 +1339,18 @@ component: size: '32' access: read-write field: + - name: Reserved_12 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '12' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '4' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: MEIE displayName: M-mode External Interrupt Enable description: Enables machine mode external interrupts. @@ -1279,6 +1363,18 @@ component: access: read-write vendorExtensions: RISCV_behavior: WARL + - name: Reserved_10 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '10' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: SEIE displayName: S-mode External Interrupt Enable description: Enables supervisor mode external interrupts. @@ -1292,7 +1388,7 @@ component: vendorExtensions: RISCV_behavior: WARL - name: UEIE - description: enables U-mode external interrupts + description: enables U-mode external interrupts.``Legal Values:``0. bitOffset: '8' resets: reset: @@ -1314,6 +1410,18 @@ component: access: read-write vendorExtensions: RISCV_behavior: WARL + - name: Reserved_6 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '6' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: STIE displayName: S-mode Timer Interrupt Enable description: Enables supervisor mode timer interrupts. @@ -1327,7 +1435,7 @@ component: vendorExtensions: RISCV_behavior: WARL - name: UTIE - description: timer interrupt-enable bit for U-mode + description: timer interrupt-enable bit for U-mode.``Legal Values:``0. bitOffset: '4' resets: reset: @@ -1347,6 +1455,18 @@ component: mask: '0x1' bitWidth: '1' access: read-write + - name: Reserved_2 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '2' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: SSIE displayName: S-mode Software Interrupt Enable description: Enables supervisor mode software interrupts. @@ -1360,7 +1480,7 @@ component: vendorExtensions: RISCV_behavior: WARL - name: USIE - description: enable U-mode software interrrupts + description: enable U-mode software interrrupts.``Legal Values:``0. bitOffset: '0' resets: reset: @@ -1593,6 +1713,18 @@ component: volatile: 'true' access: read-write field: + - name: Reserved_12 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '12' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '4' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: MEIP displayName: M-mode External Interrupt Pending description: The interrupt-pending bit for machine-level external interrupts. @@ -1604,6 +1736,18 @@ component: bitWidth: '1' volatile: 'true' access: read-only + - name: Reserved_10 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '10' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: SEIP displayName: S-mode External Interrupt Pending description: The interrupt-pending bit for supervisor-level external interrupts. @@ -1615,7 +1759,7 @@ component: bitWidth: '1' access: read-write - name: UEIP - description: enables external interrupts + description: enables external interrupts.``Legal Values:``0. bitOffset: '8' resets: reset: @@ -1634,6 +1778,18 @@ component: bitWidth: '1' volatile: 'true' access: read-only + - name: Reserved_6 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '6' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: STIP displayName: S-mode Timer Interrupt Pending description: The interrupt-pending bit for supervisor-level timer interrupts. @@ -1645,7 +1801,7 @@ component: bitWidth: '1' access: read-write - name: UTIP - description: Correspond to timer interrupt-pending bits for user interrupt + description: Correspond to timer interrupt-pending bits for user interrupt.``Legal Values:``0. bitOffset: '4' resets: reset: @@ -1664,6 +1820,18 @@ component: bitWidth: '1' volatile: 'true' access: read-only + - name: Reserved_2 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '2' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL - name: SSIP displayName: S-mode Software Interrupt Pending description: The interrupt-pending bit for supervisor-level software interrupts. @@ -1675,7 +1843,7 @@ component: bitWidth: '1' access: read-write - name: USIP - description: A hart to directly write its own USIP bits when running in the appropriate mode + description: A hart to directly write its own USIP bits when running in the appropriate mode.``Legal Values:``0. bitOffset: '0' resets: reset: