diff --git a/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst b/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst index 18483fe754..f7f3805ff4 100644 --- a/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst +++ b/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst @@ -39,6 +39,9 @@ privileged specification. Reads or writes to a CSR that is not implemented will result in an illegal instruction exception. +Any illegal instruction exception raised by CSR access is precise. +For instance, reading and writing to a read-only CSR will not update the destination register. + .. tip:: This section was auto-generated by **Register Manager** from `Jade Design Automation `_. |logo|