diff --git a/config/gen_from_riscv_config/cv32a65x/csr/csr.rst b/config/gen_from_riscv_config/cv32a65x/csr/csr.rst index 9f02642f29..ad95398249 100644 --- a/config/gen_from_riscv_config/cv32a65x/csr/csr.rst +++ b/config/gen_from_riscv_config/cv32a65x/csr/csr.rst @@ -406,7 +406,7 @@ MIP PMPCFG[0-3] ~~~~~~~~~~~ -:Address: 0x3a0-0x3a3 +:Address: 0x3a0-0x3af :Reset Value: 0x00000000 :Privilege: MRW :Description: PMP configuration register @@ -428,7 +428,7 @@ PMPCFG[0-3] PMPADDR[0-15] ~~~~~~~~~~~~~ -:Address: 0x3b0-0x3bf +:Address: 0x3b0-0x3ef :Reset Value: 0x00000000 :Privilege: MRW :Description: Physical memory protection address register diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 327e527afe..4784564c84 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -65,8 +65,8 @@ module acc_dispatcher // Interface with the CSRs input priv_lvl_t ld_st_priv_lvl_i, input logic sum_i, - input pmpcfg_t [15:0] pmpcfg_i, - input logic [15:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input pmpcfg_t [CVA6Cfg.NrPMPEntries:0] pmpcfg_i, + input logic [CVA6Cfg.NrPMPEntries:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, input logic [2:0] fcsr_frm_i, output logic dirty_v_state_o, // Interface with the issue stage diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index c858d8532f..bce13e9f98 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -162,10 +162,10 @@ module csr_regfile input logic [CVA6Cfg.XLEN-1:0] perf_data_i, // TO_BE_COMPLETED - PERF_COUNTERS output logic perf_we_o, - // PMP configuration containing pmpcfg for max 16 PMPs - ACC_DISPATCHER - output riscv::pmpcfg_t [15:0] pmpcfg_o, + // PMP configuration containing pmpcfg for max 64 PMPs - ACC_DISPATCHER + output riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries:0] pmpcfg_o, // PMP addresses - ACC_DISPATCHER - output logic [15:0][CVA6Cfg.PLEN-3:0] pmpaddr_o, + output logic [CVA6Cfg.NrPMPEntries:0][CVA6Cfg.PLEN-3:0] pmpaddr_o, // TO_BE_COMPLETED - PERF_COUNTERS output logic [31:0] mcountinhibit_o, // RVFI @@ -274,10 +274,9 @@ module csr_regfile logic [63:0] cycle_q, cycle_d; logic [63:0] instret_q, instret_d; - riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d, pmpcfg_next; - logic [15:0][CVA6Cfg.PLEN-3:0] pmpaddr_q, pmpaddr_d, pmpaddr_next; + riscv::pmpcfg_t [63:0] pmpcfg_q, pmpcfg_d, pmpcfg_next; + logic [63:0][CVA6Cfg.PLEN-3:0] pmpaddr_q, pmpaddr_d, pmpaddr_next; logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q; - logic [3:0] index; localparam logic [CVA6Cfg.XLEN-1:0] IsaCode = (CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension | (CVA6Cfg.XLEN'(CVA6Cfg.RVB) << 1) // B - Bitmanip extension @@ -294,8 +293,8 @@ module csr_regfile | (CVA6Cfg.XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present | ((CVA6Cfg.XLEN == 64 ? 2 : 1) << CVA6Cfg.XLEN - 2); // MXL - assign pmpcfg_o = pmpcfg_q[15:0]; - assign pmpaddr_o = pmpaddr_q; + assign pmpcfg_o = pmpcfg_q[CVA6Cfg.NrPMPEntries:0]; + assign pmpaddr_o = pmpaddr_q[CVA6Cfg.NrPMPEntries:0]; riscv::fcsr_t fcsr_q, fcsr_d; // ---------------- @@ -329,7 +328,6 @@ module csr_regfile virtual_read_access_exception = 1'b0; csr_rdata = '0; perf_addr_o = csr_addr.address[11:0]; - index = '0; if (csr_read) begin unique case (conv_csr_addr.address) @@ -762,14 +760,31 @@ module csr_regfile end end // PMPs - riscv::CSR_PMPCFG0: csr_rdata = pmpcfg_q[CVA6Cfg.XLEN/8-1:0]; - riscv::CSR_PMPCFG1: - if (CVA6Cfg.XLEN == 32) csr_rdata = pmpcfg_q[7:4]; - else read_access_exception = 1'b1; - riscv::CSR_PMPCFG2: csr_rdata = pmpcfg_q[8+:CVA6Cfg.XLEN/8]; - riscv::CSR_PMPCFG3: - if (CVA6Cfg.XLEN == 32) csr_rdata = pmpcfg_q[15:12]; - else read_access_exception = 1'b1; + riscv::CSR_PMPCFG0, + riscv::CSR_PMPCFG1, + riscv::CSR_PMPCFG2, + riscv::CSR_PMPCFG3, + riscv::CSR_PMPCFG4, + riscv::CSR_PMPCFG5, + riscv::CSR_PMPCFG6, + riscv::CSR_PMPCFG7, + riscv::CSR_PMPCFG8, + riscv::CSR_PMPCFG9, + riscv::CSR_PMPCFG10, + riscv::CSR_PMPCFG11, + riscv::CSR_PMPCFG12, + riscv::CSR_PMPCFG13, + riscv::CSR_PMPCFG14, + riscv::CSR_PMPCFG15: begin + // index is calculated using PMPCFG0 as the offset + automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPCFG0; + + // if index is not even and XLEN==64, raise exception + if (CVA6Cfg.XLEN == 64 && index[0] == 1'b1) read_access_exception = 1'b1; + else begin + csr_rdata = pmpcfg_q[index*4+:CVA6Cfg.XLEN/8]; + end + end // PMPADDR riscv::CSR_PMPADDR0, riscv::CSR_PMPADDR1, @@ -786,9 +801,57 @@ module csr_regfile riscv::CSR_PMPADDR12, riscv::CSR_PMPADDR13, riscv::CSR_PMPADDR14, - riscv::CSR_PMPADDR15: begin - // index is specified by the last byte in the address - index = csr_addr.csr_decode.address[3:0]; + riscv::CSR_PMPADDR15, + riscv::CSR_PMPADDR16, + riscv::CSR_PMPADDR17, + riscv::CSR_PMPADDR18, + riscv::CSR_PMPADDR19, + riscv::CSR_PMPADDR20, + riscv::CSR_PMPADDR21, + riscv::CSR_PMPADDR22, + riscv::CSR_PMPADDR23, + riscv::CSR_PMPADDR24, + riscv::CSR_PMPADDR25, + riscv::CSR_PMPADDR26, + riscv::CSR_PMPADDR27, + riscv::CSR_PMPADDR28, + riscv::CSR_PMPADDR29, + riscv::CSR_PMPADDR30, + riscv::CSR_PMPADDR31, + riscv::CSR_PMPADDR32, + riscv::CSR_PMPADDR33, + riscv::CSR_PMPADDR34, + riscv::CSR_PMPADDR35, + riscv::CSR_PMPADDR36, + riscv::CSR_PMPADDR37, + riscv::CSR_PMPADDR38, + riscv::CSR_PMPADDR39, + riscv::CSR_PMPADDR40, + riscv::CSR_PMPADDR41, + riscv::CSR_PMPADDR42, + riscv::CSR_PMPADDR43, + riscv::CSR_PMPADDR44, + riscv::CSR_PMPADDR45, + riscv::CSR_PMPADDR46, + riscv::CSR_PMPADDR47, + riscv::CSR_PMPADDR48, + riscv::CSR_PMPADDR49, + riscv::CSR_PMPADDR50, + riscv::CSR_PMPADDR51, + riscv::CSR_PMPADDR52, + riscv::CSR_PMPADDR53, + riscv::CSR_PMPADDR54, + riscv::CSR_PMPADDR55, + riscv::CSR_PMPADDR56, + riscv::CSR_PMPADDR57, + riscv::CSR_PMPADDR58, + riscv::CSR_PMPADDR59, + riscv::CSR_PMPADDR60, + riscv::CSR_PMPADDR61, + riscv::CSR_PMPADDR62, + riscv::CSR_PMPADDR63: begin + // index is calculated using PMPADDR0 as the offset + automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPADDR0; // Important: we only support granularity 8 bytes (G=1) // -> last bit of pmpaddr must be set 0/1 based on the mode: // NA4, NAPOT: 1 @@ -1555,26 +1618,31 @@ module csr_regfile // 1. refuse to update any locked entry // 2. also refuse to update the entry below a locked TOR entry // Note that writes to pmpcfg below a locked TOR entry are valid - riscv::CSR_PMPCFG0: - for (int i = 0; i < (CVA6Cfg.XLEN / 8); i++) - if (!pmpcfg_q[i].locked) pmpcfg_d[i] = csr_wdata[i*8+:8]; - riscv::CSR_PMPCFG1: begin - if (CVA6Cfg.XLEN == 32) begin - for (int i = 0; i < 4; i++) - if (!pmpcfg_q[i+4].locked) pmpcfg_d[i+4] = csr_wdata[i*8+:8]; - end else begin - update_access_exception = 1'b1; - end - end - riscv::CSR_PMPCFG2: - for (int i = 0; i < (CVA6Cfg.XLEN / 8); i++) - if (!pmpcfg_q[i+8].locked) pmpcfg_d[i+8] = csr_wdata[i*8+:8]; - riscv::CSR_PMPCFG3: begin - if (CVA6Cfg.XLEN == 32) begin - for (int i = 0; i < 4; i++) - if (!pmpcfg_q[i+12].locked) pmpcfg_d[i+12] = csr_wdata[i*8+:8]; - end else begin - update_access_exception = 1'b1; + riscv::CSR_PMPCFG0, + riscv::CSR_PMPCFG1, + riscv::CSR_PMPCFG2, + riscv::CSR_PMPCFG3, + riscv::CSR_PMPCFG4, + riscv::CSR_PMPCFG5, + riscv::CSR_PMPCFG6, + riscv::CSR_PMPCFG7, + riscv::CSR_PMPCFG8, + riscv::CSR_PMPCFG9, + riscv::CSR_PMPCFG10, + riscv::CSR_PMPCFG11, + riscv::CSR_PMPCFG12, + riscv::CSR_PMPCFG13, + riscv::CSR_PMPCFG14, + riscv::CSR_PMPCFG15: begin + // index is calculated using PMPCFG0 as the offset + automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPCFG0; + + // if index is not even and XLEN==64, raise exception + if (CVA6Cfg.XLEN == 64 && index[0] == 1'b1) update_access_exception = 1'b1; + else begin + for (int i = 0; i < CVA6Cfg.XLEN / 8; i++) begin + if (!pmpcfg_q[index+i].locked) pmpcfg_d[index+i] = csr_wdata[i*8+:8]; + end end end riscv::CSR_PMPADDR0, @@ -1592,9 +1660,57 @@ module csr_regfile riscv::CSR_PMPADDR12, riscv::CSR_PMPADDR13, riscv::CSR_PMPADDR14, - riscv::CSR_PMPADDR15: begin - // index is specified by the last byte in the address - automatic logic [3:0] index = csr_addr.csr_decode.address[3:0]; + riscv::CSR_PMPADDR15, + riscv::CSR_PMPADDR16, + riscv::CSR_PMPADDR17, + riscv::CSR_PMPADDR18, + riscv::CSR_PMPADDR19, + riscv::CSR_PMPADDR20, + riscv::CSR_PMPADDR21, + riscv::CSR_PMPADDR22, + riscv::CSR_PMPADDR23, + riscv::CSR_PMPADDR24, + riscv::CSR_PMPADDR25, + riscv::CSR_PMPADDR26, + riscv::CSR_PMPADDR27, + riscv::CSR_PMPADDR28, + riscv::CSR_PMPADDR29, + riscv::CSR_PMPADDR30, + riscv::CSR_PMPADDR31, + riscv::CSR_PMPADDR32, + riscv::CSR_PMPADDR33, + riscv::CSR_PMPADDR34, + riscv::CSR_PMPADDR35, + riscv::CSR_PMPADDR36, + riscv::CSR_PMPADDR37, + riscv::CSR_PMPADDR38, + riscv::CSR_PMPADDR39, + riscv::CSR_PMPADDR40, + riscv::CSR_PMPADDR41, + riscv::CSR_PMPADDR42, + riscv::CSR_PMPADDR43, + riscv::CSR_PMPADDR44, + riscv::CSR_PMPADDR45, + riscv::CSR_PMPADDR46, + riscv::CSR_PMPADDR47, + riscv::CSR_PMPADDR48, + riscv::CSR_PMPADDR49, + riscv::CSR_PMPADDR50, + riscv::CSR_PMPADDR51, + riscv::CSR_PMPADDR52, + riscv::CSR_PMPADDR53, + riscv::CSR_PMPADDR54, + riscv::CSR_PMPADDR55, + riscv::CSR_PMPADDR56, + riscv::CSR_PMPADDR57, + riscv::CSR_PMPADDR58, + riscv::CSR_PMPADDR59, + riscv::CSR_PMPADDR60, + riscv::CSR_PMPADDR61, + riscv::CSR_PMPADDR62, + riscv::CSR_PMPADDR63: begin + // index is calculated using PMPADDR0 as the offset + automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPADDR0; // check if the entry or the entry above is locked if (!pmpcfg_q[index].locked && !(pmpcfg_q[index+1].locked && pmpcfg_q[index+1].addr_mode == riscv::TOR)) begin pmpaddr_d[index] = csr_wdata[CVA6Cfg.PLEN-3:0]; @@ -2448,7 +2564,7 @@ module csr_regfile // wait for interrupt wfi_q <= 1'b0; // pmp - for (int i = 0; i < 16; i++) begin + for (int i = 0; i < 64; i++) begin if (i < CVA6Cfg.NrPMPEntries) begin pmpcfg_q[i] <= riscv::pmpcfg_t'(CVA6Cfg.PMPCfgRstVal[i]); pmpaddr_q[i] <= CVA6Cfg.PMPAddrRstVal[i][CVA6Cfg.PLEN-3:0]; @@ -2535,7 +2651,7 @@ module csr_regfile // write logic pmp always_comb begin : write - for (int i = 0; i < 16; i++) begin + for (int i = 0; i < 64; i++) begin if (i < CVA6Cfg.NrPMPEntries) begin if (!CVA6Cfg.PMPEntryReadOnly[i]) begin // PMP locked logic is handled in the CSR write process above diff --git a/core/cva6.sv b/core/cva6.sv index 250858aa92..1d668e1d8d 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -518,8 +518,8 @@ module cva6 logic acc_cons_en_csr; logic debug_mode; logic single_step_csr_commit; - riscv::pmpcfg_t [15:0] pmpcfg; - logic [15:0][CVA6Cfg.PLEN-3:0] pmpaddr; + riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries:0] pmpcfg; + logic [CVA6Cfg.NrPMPEntries:0][CVA6Cfg.PLEN-3:0] pmpaddr; logic [31:0] mcountinhibit_csr_perf; // ---------------------------- // Performance Counters <-> * diff --git a/core/cva6_mmu/cva6_mmu.sv b/core/cva6_mmu/cva6_mmu.sv index 6b7f6e005e..39826da371 100644 --- a/core/cva6_mmu/cva6_mmu.sv +++ b/core/cva6_mmu/cva6_mmu.sv @@ -92,14 +92,15 @@ module cva6_mmu input logic flush_tlb_gvma_i, // Performance counters - output logic itlb_miss_o, - output logic dtlb_miss_o, + output logic itlb_miss_o, + output logic dtlb_miss_o, // PTW memory interface - input dcache_req_o_t req_port_i, - output dcache_req_i_t req_port_o, + input dcache_req_o_t req_port_i, + output dcache_req_i_t req_port_o, + // PMP - input riscv::pmpcfg_t [15:0] pmpcfg_i, - input logic [15:0][CVA6Cfg.PLEN-3:0] pmpaddr_i + input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries:0] pmpcfg_i, + input logic [CVA6Cfg.NrPMPEntries:0][CVA6Cfg.PLEN-3:0] pmpaddr_i ); // memory management, pte for cva6 diff --git a/core/cva6_mmu/cva6_ptw.sv b/core/cva6_mmu/cva6_ptw.sv index 0bd5ab4c5b..34c2cf1a19 100644 --- a/core/cva6_mmu/cva6_ptw.sv +++ b/core/cva6_mmu/cva6_ptw.sv @@ -84,8 +84,8 @@ module cva6_ptw // PMP - input riscv::pmpcfg_t [15:0] pmpcfg_i, - input logic [15:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries:0] pmpcfg_i, + input logic [CVA6Cfg.NrPMPEntries:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, output logic [CVA6Cfg.PLEN-1:0] bad_paddr_o, output logic [CVA6Cfg.GPLEN-1:0] bad_gpaddr_o diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 54d35e1ede..f94927676e 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -217,9 +217,9 @@ module ex_stage // To count the data TLB misses - PERF_COUNTERS output logic dtlb_miss_o, // Report the PMP configuration - CSR_REGFILE - input riscv::pmpcfg_t [15:0] pmpcfg_i, + input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries:0] pmpcfg_i, // Report the PMP addresses - CSR_REGFILE - input logic [15:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input logic [CVA6Cfg.NrPMPEntries:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, // Information dedicated to RVFI - RVFI output lsu_ctrl_t rvfi_lsu_ctrl_o, // Information dedicated to RVFI - RVFI diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index 2c4d37d41e..3ca1771698 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -103,11 +103,11 @@ package config_pkg; // PMP entries number int unsigned NrPMPEntries; // PMP CSR configuration reset values - logic [15:0][63:0] PMPCfgRstVal; + logic [63:0][63:0] PMPCfgRstVal; // PMP CSR address reset values - logic [15:0][63:0] PMPAddrRstVal; + logic [63:0][63:0] PMPAddrRstVal; // PMP CSR read-only bits - bit [15:0] PMPEntryReadOnly; + bit [63:0] PMPEntryReadOnly; // PMA non idempotent rules number int unsigned NrNonIdempotentRules; // PMA NonIdempotent region base address @@ -277,9 +277,9 @@ package config_pkg; bit TvalEn; bit DirectVecOnly; int unsigned NrPMPEntries; - logic [15:0][63:0] PMPCfgRstVal; - logic [15:0][63:0] PMPAddrRstVal; - bit [15:0] PMPEntryReadOnly; + logic [63:0][63:0] PMPCfgRstVal; + logic [63:0][63:0] PMPAddrRstVal; + bit [63:0] PMPEntryReadOnly; noc_type_e NOCType; int unsigned NrNonIdempotentRules; logic [NrMaxRules-1:0][63:0] NonIdempotentAddrBase; @@ -351,7 +351,7 @@ package config_pkg; assert (Cfg.NrNonIdempotentRules <= NrMaxRules); assert (Cfg.NrExecuteRegionRules <= NrMaxRules); assert (Cfg.NrCachedRegionRules <= NrMaxRules); - assert (Cfg.NrPMPEntries <= 16); + assert (Cfg.NrPMPEntries <= 64); `endif // pragma translate_on endfunction diff --git a/core/include/cv32a60x_config_pkg_deprecated.sv b/core/include/cv32a60x_config_pkg_deprecated.sv index bf06b965fb..c2637baf1e 100644 --- a/core/include/cv32a60x_config_pkg_deprecated.sv +++ b/core/include/cv32a60x_config_pkg_deprecated.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index c2b4a0ff08..3403daa092 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -64,9 +64,9 @@ package cva6_config_pkg; TvalEn: bit'(0), DirectVecOnly: bit'(1), NrPMPEntries: unsigned'(8), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv index 510c9da76e..b8990ae566 100644 --- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv +++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv @@ -115,9 +115,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 8dc68ccf1f..c6718e3717 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: unsigned'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 0509989bf9..c5a813243f 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: unsigned'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 24f0e33f4d..467bc57bfe 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index bce6e05f38..7028d2ad29 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index fbcca081e7..238f72dd4c 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index d59225bb54..cfe0ed8e0f 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index 3647583ea6..65ff07085a 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -123,9 +123,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 8ca1a8d342..a641d9bc39 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 50ed8c1133..b86e152a65 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index 62f4d3a520..36e77f1bcf 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index 786a68d3d3..95eb5046f4 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 5c95041ea3..48b2706fef 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -116,9 +116,9 @@ package cva6_config_pkg; TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv index d81a20985c..fbfc0f3adc 100644 --- a/core/include/cv64a6_mmu_config_pkg.sv +++ b/core/include/cv64a6_mmu_config_pkg.sv @@ -67,10 +67,10 @@ package cva6_config_pkg; DmBaseAddress: 64'h0, TvalEn: bit'(0), DirectVecOnly: bit'(1), - NrPMPEntries: unsigned'(16), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + NrPMPEntries: unsigned'(64), + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv index 42c9107f81..647ff4c7b8 100644 --- a/core/include/riscv_pkg.sv +++ b/core/include/riscv_pkg.sv @@ -487,6 +487,18 @@ package riscv; CSR_PMPCFG1 = 12'h3A1, CSR_PMPCFG2 = 12'h3A2, CSR_PMPCFG3 = 12'h3A3, + CSR_PMPCFG4 = 12'h3A4, + CSR_PMPCFG5 = 12'h3A5, + CSR_PMPCFG6 = 12'h3A6, + CSR_PMPCFG7 = 12'h3A7, + CSR_PMPCFG8 = 12'h3A8, + CSR_PMPCFG9 = 12'h3A9, + CSR_PMPCFG10 = 12'h3AA, + CSR_PMPCFG11 = 12'h3AB, + CSR_PMPCFG12 = 12'h3AC, + CSR_PMPCFG13 = 12'h3AD, + CSR_PMPCFG14 = 12'h3AE, + CSR_PMPCFG15 = 12'h3AF, CSR_PMPADDR0 = 12'h3B0, CSR_PMPADDR1 = 12'h3B1, CSR_PMPADDR2 = 12'h3B2, @@ -503,6 +515,54 @@ package riscv; CSR_PMPADDR13 = 12'h3BD, CSR_PMPADDR14 = 12'h3BE, CSR_PMPADDR15 = 12'h3BF, + CSR_PMPADDR16 = 12'h3C0, + CSR_PMPADDR17 = 12'h3C1, + CSR_PMPADDR18 = 12'h3C2, + CSR_PMPADDR19 = 12'h3C3, + CSR_PMPADDR20 = 12'h3C4, + CSR_PMPADDR21 = 12'h3C5, + CSR_PMPADDR22 = 12'h3C6, + CSR_PMPADDR23 = 12'h3C7, + CSR_PMPADDR24 = 12'h3C8, + CSR_PMPADDR25 = 12'h3C9, + CSR_PMPADDR26 = 12'h3CA, + CSR_PMPADDR27 = 12'h3CB, + CSR_PMPADDR28 = 12'h3CC, + CSR_PMPADDR29 = 12'h3CD, + CSR_PMPADDR30 = 12'h3CE, + CSR_PMPADDR31 = 12'h3CF, + CSR_PMPADDR32 = 12'h3D0, + CSR_PMPADDR33 = 12'h3D1, + CSR_PMPADDR34 = 12'h3D2, + CSR_PMPADDR35 = 12'h3D3, + CSR_PMPADDR36 = 12'h3D4, + CSR_PMPADDR37 = 12'h3D5, + CSR_PMPADDR38 = 12'h3D6, + CSR_PMPADDR39 = 12'h3D7, + CSR_PMPADDR40 = 12'h3D8, + CSR_PMPADDR41 = 12'h3D9, + CSR_PMPADDR42 = 12'h3DA, + CSR_PMPADDR43 = 12'h3DB, + CSR_PMPADDR44 = 12'h3DC, + CSR_PMPADDR45 = 12'h3DD, + CSR_PMPADDR46 = 12'h3DE, + CSR_PMPADDR47 = 12'h3DF, + CSR_PMPADDR48 = 12'h3E0, + CSR_PMPADDR49 = 12'h3E1, + CSR_PMPADDR50 = 12'h3E2, + CSR_PMPADDR51 = 12'h3E3, + CSR_PMPADDR52 = 12'h3E4, + CSR_PMPADDR53 = 12'h3E5, + CSR_PMPADDR54 = 12'h3E6, + CSR_PMPADDR55 = 12'h3E7, + CSR_PMPADDR56 = 12'h3E8, + CSR_PMPADDR57 = 12'h3E9, + CSR_PMPADDR58 = 12'h3EA, + CSR_PMPADDR59 = 12'h3EB, + CSR_PMPADDR60 = 12'h3EC, + CSR_PMPADDR61 = 12'h3ED, + CSR_PMPADDR62 = 12'h3EE, + CSR_PMPADDR63 = 12'h3EF, CSR_MVENDORID = 12'hF11, CSR_MARCHID = 12'hF12, CSR_MIMPID = 12'hF13, diff --git a/core/include/rvfi_types.svh b/core/include/rvfi_types.svh index 5fd98dce1b..c01bf0afb7 100644 --- a/core/include/rvfi_types.svh +++ b/core/include/rvfi_types.svh @@ -158,8 +158,8 @@ logic [Cfg.XLEN-1:0] dcache_q; \ logic [Cfg.XLEN-1:0] icache_q; \ logic [Cfg.XLEN-1:0] acc_cons_q; \ - riscv::pmpcfg_t [15:0] pmpcfg_q; \ - logic [15:0][Cfg.PLEN-3:0] pmpaddr_q; \ + riscv::pmpcfg_t [63:0] pmpcfg_q; \ + logic [63:0][Cfg.PLEN-3:0] pmpaddr_q; \ } `endif // RVFI_TYPES_SVH diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 5832ba85c6..e53292b5ea 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -146,10 +146,11 @@ module load_store_unit output amo_req_t amo_req_o, // AMO response - CACHE input amo_resp_t amo_resp_i, + // PMP configuration - CSR_REGFILE - input riscv::pmpcfg_t [15:0] pmpcfg_i, + input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries:0] pmpcfg_i, // PMP address - CSR_REGFILE - input logic [15:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input logic [CVA6Cfg.NrPMPEntries:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, // RVFI inforamtion - RVFI output lsu_ctrl_t rvfi_lsu_ctrl_o, diff --git a/core/pmp/src/pmp.sv b/core/pmp/src/pmp.sv index a3adbb903a..5d8264c9be 100644 --- a/core/pmp/src/pmp.sv +++ b/core/pmp/src/pmp.sv @@ -23,8 +23,8 @@ module pmp #( input riscv::pmp_access_t access_type_i, input riscv::priv_lvl_t priv_lvl_i, // Configuration - input logic [15:0][PMP_LEN-1:0] conf_addr_i, - input riscv::pmpcfg_t [15:0] conf_i, + input logic [NR_ENTRIES:0][PMP_LEN-1:0] conf_addr_i, + input riscv::pmpcfg_t [NR_ENTRIES:0] conf_i, // Output output logic allow_o ); diff --git a/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv b/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv index a06a6e418c..1b1aafcfaf 100644 --- a/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv +++ b/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv @@ -119,9 +119,9 @@ package cva6_config_pkg; DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), diff --git a/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv b/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv index 0633b97eb6..7ccfbfac87 100644 --- a/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv +++ b/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv @@ -119,9 +119,9 @@ package cva6_config_pkg; DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),