From 1db42ee8da0b10a96acdb2cd5f18b9d8761bc381 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Tue, 22 Aug 2023 14:04:06 +0200 Subject: [PATCH] Add variant into CVA6 parameter (#1320) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Variane as CVA6 parameter Signed-off-by: Jean-Roch Coulon * fix FPGA build Signed-off-by: Jean-Roch Coulon * Fix tipo in cva6.sv * fix lint warnings Signed-off-by: Jean-Roch Coulon * Fix is_*_fpr functions * remove blank lines * set IsRVFI out of CVA6Cfg * define config_pkg * Fix ariane_pkg comments * Fix Lint from André's feedbacks * Fix parameter transmission * Fix replace CVA6Cfg by CVA6ExtendCfg in cva6.sv * fix add CVA6Cfg in instr_queue, instr_scan and pmp parameters --------- Signed-off-by: Jean-Roch Coulon Co-authored-by: ALLART Come --- core/Flist.cva6 | 1 + core/Flist.cva6_gate | 1 + core/acc_dispatcher.sv | 2 +- core/alu.sv | 2 +- core/amo_buffer.sv | 2 +- core/ariane_regfile.sv | 2 +- core/ariane_regfile_ff.sv | 2 +- core/ariane_regfile_fpga.sv | 2 +- core/axi_shim.sv | 2 +- core/branch_unit.sv | 2 +- core/cache_subsystem/amo_alu.sv | 2 +- core/cache_subsystem/axi_adapter.sv | 2 +- core/cache_subsystem/cache_ctrl.sv | 2 +- core/cache_subsystem/cva6_icache.sv | 2 +- .../cva6_icache_axi_wrapper.sv | 2 +- core/cache_subsystem/miss_handler.sv | 2 +- core/cache_subsystem/std_cache_subsystem.sv | 2 +- core/cache_subsystem/std_nbdcache.sv | 2 +- core/cache_subsystem/tag_cmp.sv | 2 +- core/cache_subsystem/wt_axi_adapter.sv | 2 +- core/cache_subsystem/wt_cache_subsystem.sv | 2 +- core/cache_subsystem/wt_dcache.sv | 2 +- core/cache_subsystem/wt_dcache_ctrl.sv | 2 +- core/cache_subsystem/wt_dcache_mem.sv | 2 +- core/cache_subsystem/wt_dcache_missunit.sv | 2 +- core/cache_subsystem/wt_dcache_wbuffer.sv | 2 +- core/cache_subsystem/wt_l15_adapter.sv | 2 +- core/commit_stage.sv | 10 +- core/compressed_decoder.sv | 2 +- core/controller.sv | 2 +- core/csr_buffer.sv | 2 +- core/csr_regfile.sv | 40 ++-- core/cva6.sv | 185 +++++++++++------- core/cvxif_fu.sv | 2 +- core/decoder.sv | 128 ++++++------ core/ex_stage.sv | 10 +- core/fpu_wrap.sv | 44 ++--- core/frontend/bht.sv | 10 +- core/frontend/btb.sv | 8 +- core/frontend/frontend.sv | 17 +- core/frontend/instr_queue.sv | 2 +- core/frontend/instr_scan.sv | 2 +- core/frontend/ras.sv | 2 +- core/id_stage.sv | 4 +- core/include/ariane_pkg.sv | 132 ++++--------- core/include/config_pkg.sv | 109 +++++++++++ core/include/cv32a60x_config_pkg.sv | 30 +++ core/include/cv32a6_embedded_config_pkg.sv | 30 +++ .../cv32a6_ima_sv32_fpga_config_pkg.sv | 30 +++ core/include/cv32a6_imac_sv0_config_pkg.sv | 30 +++ core/include/cv32a6_imac_sv32_config_pkg.sv | 30 +++ core/include/cv32a6_imafc_sv32_config_pkg.sv | 30 +++ .../cv64a6_imadfcv_sv39_polara_config_pkg.sv | 30 +++ core/include/cv64a6_imafdc_sv39_config_pkg.sv | 30 +++ ...cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 30 +++ .../include/cv64a6_imafdcv_sv39_config_pkg.sv | 30 +++ core/instr_realign.sv | 2 +- core/issue_read_operands.sv | 69 +++---- core/issue_stage.sv | 28 +-- core/load_store_unit.sv | 2 +- core/load_unit.sv | 2 +- core/lsu_bypass.sv | 2 +- core/mmu_sv32/cva6_mmu_sv32.sv | 2 +- core/mmu_sv32/cva6_ptw_sv32.sv | 2 +- core/mmu_sv32/cva6_shared_tlb_sv32.sv | 2 +- core/mmu_sv32/cva6_tlb_sv32.sv | 2 +- core/mmu_sv39/mmu.sv | 2 +- core/mmu_sv39/ptw.sv | 2 +- core/mmu_sv39/tlb.sv | 2 +- core/mult.sv | 2 +- core/multiplier.sv | 2 +- core/perf_counters.sv | 2 +- core/pmp/src/pmp.sv | 3 +- core/pmp/src/pmp_entry.sv | 2 +- core/re_name.sv | 14 +- core/scoreboard.sv | 65 +++--- core/serdiv.sv | 2 +- core/store_buffer.sv | 2 +- core/store_unit.sv | 2 +- corev_apu/fpga/src/ariane_xilinx.sv | 13 +- corev_apu/src/ariane.sv | 8 +- corev_apu/tb/ariane_tb.sv | 57 +++--- corev_apu/tb/ariane_testharness.sv | 57 +++--- corev_apu/tb/rvfi_tracer.sv | 2 +- 84 files changed, 918 insertions(+), 497 deletions(-) create mode 100644 core/include/config_pkg.sv diff --git a/core/Flist.cva6 b/core/Flist.cva6 index a013ea705a..b05ec1a5d0 100644 --- a/core/Flist.cva6 +++ b/core/Flist.cva6 @@ -55,6 +55,7 @@ ${CVA6_REPO_DIR}/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt ${CVA6_REPO_DIR}/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv ${CVA6_REPO_DIR}/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv +${CVA6_REPO_DIR}/core/include/config_pkg.sv ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv ${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv diff --git a/core/Flist.cva6_gate b/core/Flist.cva6_gate index 490fb04f65..e51f2f3f14 100644 --- a/core/Flist.cva6_gate +++ b/core/Flist.cva6_gate @@ -8,6 +8,7 @@ # Original Author: Jean-Roch COULON - Thales # +${CVA6_REPO_DIR}/core/include/config_pkg.sv ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv ${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 8e965f4d01..6de6dd65ac 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -14,7 +14,7 @@ // Description: Functional unit that dispatches CVA6 instructions to accelerators. module acc_dispatcher import ariane_pkg::*; import riscv::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type acc_req_t = acc_pkg::accelerator_req_t, parameter type acc_resp_t = acc_pkg::accelerator_resp_t, parameter type acc_cfg_t = logic, diff --git a/core/alu.sv b/core/alu.sv index 0e0d3aa0db..90cdf9396d 100644 --- a/core/alu.sv +++ b/core/alu.sv @@ -19,7 +19,7 @@ module alu import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/core/amo_buffer.sv b/core/amo_buffer.sv index 5383827855..789ca41ad0 100644 --- a/core/amo_buffer.sv +++ b/core/amo_buffer.sv @@ -15,7 +15,7 @@ // Furthermore it handles interfacing with the commit stage module amo_buffer #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/core/ariane_regfile.sv b/core/ariane_regfile.sv index 512d231fb7..68d68eec96 100644 --- a/core/ariane_regfile.sv +++ b/core/ariane_regfile.sv @@ -24,7 +24,7 @@ // module ariane_regfile_lol #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned DATA_WIDTH = 32, parameter int unsigned NR_READ_PORTS = 2, parameter bit ZERO_REG_ZERO = 0 diff --git a/core/ariane_regfile_ff.sv b/core/ariane_regfile_ff.sv index 8d97945d52..293ce60acf 100644 --- a/core/ariane_regfile_ff.sv +++ b/core/ariane_regfile_ff.sv @@ -23,7 +23,7 @@ // module ariane_regfile #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned DATA_WIDTH = 32, parameter int unsigned NR_READ_PORTS = 2, parameter bit ZERO_REG_ZERO = 0 diff --git a/core/ariane_regfile_fpga.sv b/core/ariane_regfile_fpga.sv index fd8bd2a1bb..aa4bf986b6 100644 --- a/core/ariane_regfile_fpga.sv +++ b/core/ariane_regfile_fpga.sv @@ -26,7 +26,7 @@ // module ariane_regfile_fpga #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned DATA_WIDTH = 32, parameter int unsigned NR_READ_PORTS = 2, parameter bit ZERO_REG_ZERO = 0 diff --git a/core/axi_shim.sv b/core/axi_shim.sv index 09e0213c2d..9e8405051b 100644 --- a/core/axi_shim.sv +++ b/core/axi_shim.sv @@ -20,7 +20,7 @@ module axi_shim #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned AxiNumWords = 4, // data width in dwords, this is also the maximum burst length, must be >=2 parameter type axi_req_t = logic, parameter type axi_rsp_t = logic diff --git a/core/branch_unit.sv b/core/branch_unit.sv index 040a4aee9d..087b71807a 100644 --- a/core/branch_unit.sv +++ b/core/branch_unit.sv @@ -13,7 +13,7 @@ // Description: Branch target calculation and comparison module branch_unit #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, input logic rst_ni, diff --git a/core/cache_subsystem/amo_alu.sv b/core/cache_subsystem/amo_alu.sv index 8952037187..98a49d71f5 100644 --- a/core/cache_subsystem/amo_alu.sv +++ b/core/cache_subsystem/amo_alu.sv @@ -12,7 +12,7 @@ // Date: 15.09.2018 // Description: Combinatorial AMO unit module amo_alu #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( // AMO interface input ariane_pkg::amo_t amo_op_i, diff --git a/core/cache_subsystem/axi_adapter.sv b/core/cache_subsystem/axi_adapter.sv index 942cc64b97..d1e86e796c 100644 --- a/core/cache_subsystem/axi_adapter.sv +++ b/core/cache_subsystem/axi_adapter.sv @@ -17,7 +17,7 @@ //import std_cache_pkg::*; module axi_adapter #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned DATA_WIDTH = 256, parameter logic CRITICAL_WORD_FIRST = 0, // the AXI subsystem needs to support wrapping reads for this feature parameter int unsigned CACHELINE_BYTE_OFFSET = 8, diff --git a/core/cache_subsystem/cache_ctrl.sv b/core/cache_subsystem/cache_ctrl.sv index c00985f52d..39bc67d101 100644 --- a/core/cache_subsystem/cache_ctrl.sv +++ b/core/cache_subsystem/cache_ctrl.sv @@ -19,7 +19,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig // contains cacheable regions ) ( input logic clk_i, // Clock diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv index 63f869a2e0..8236ba11ed 100644 --- a/core/cache_subsystem/cva6_icache.sv +++ b/core/cache_subsystem/cva6_icache.sv @@ -26,7 +26,7 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, /// ID to be used for read transactions parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0, /// Contains cacheable regions diff --git a/core/cache_subsystem/cva6_icache_axi_wrapper.sv b/core/cache_subsystem/cva6_icache_axi_wrapper.sv index 6243edfde5..00561f33ca 100644 --- a/core/cache_subsystem/cva6_icache_axi_wrapper.sv +++ b/core/cache_subsystem/cva6_icache_axi_wrapper.sv @@ -14,7 +14,7 @@ // module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions parameter type axi_req_t = logic, parameter type axi_rsp_t = logic diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv index 701ba0f67f..7fe7cd6b1d 100644 --- a/core/cache_subsystem/miss_handler.sv +++ b/core/cache_subsystem/miss_handler.sv @@ -17,7 +17,7 @@ // -------------- module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned NR_PORTS = 3, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index 7ad78deb85..e404e920ca 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -16,7 +16,7 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions parameter type axi_ar_chan_t = logic, parameter type axi_aw_chan_t = logic, diff --git a/core/cache_subsystem/std_nbdcache.sv b/core/cache_subsystem/std_nbdcache.sv index a9fdf4115a..a2ab971b1f 100644 --- a/core/cache_subsystem/std_nbdcache.sv +++ b/core/cache_subsystem/std_nbdcache.sv @@ -14,7 +14,7 @@ module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions parameter type axi_req_t = logic, parameter type axi_rsp_t = logic diff --git a/core/cache_subsystem/tag_cmp.sv b/core/cache_subsystem/tag_cmp.sv index b55415e8b9..cfa2ebfcd2 100644 --- a/core/cache_subsystem/tag_cmp.sv +++ b/core/cache_subsystem/tag_cmp.sv @@ -16,7 +16,7 @@ // checks for hit or miss on cache // module tag_cmp #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned NR_PORTS = 3, parameter int unsigned ADDR_WIDTH = 64, parameter type l_data_t = std_cache_pkg::cache_line_t, diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index cc90d63d92..d53477bbd0 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -15,7 +15,7 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned ReqFifoDepth = 2, parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX, parameter type axi_req_t = logic, diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index 97fa20223b..efecfdcf3c 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -20,7 +20,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, // contains cacheable regions parameter int unsigned NumPorts = 3, parameter type noc_req_t = logic, diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index 9244817caf..bb192a41c9 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -14,7 +14,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned NumPorts = 3, // number of miss ports // ID to be used for read and AMO transactions. // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions diff --git a/core/cache_subsystem/wt_dcache_ctrl.sv b/core/cache_subsystem/wt_dcache_ctrl.sv index 204e2d720f..a6a14cd1b6 100644 --- a/core/cache_subsystem/wt_dcache_ctrl.sv +++ b/core/cache_subsystem/wt_dcache_ctrl.sv @@ -14,7 +14,7 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1, // ID to use for read transactions parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions ) ( diff --git a/core/cache_subsystem/wt_dcache_mem.sv b/core/cache_subsystem/wt_dcache_mem.sv index d25a590ade..62b99f1132 100644 --- a/core/cache_subsystem/wt_dcache_mem.sv +++ b/core/cache_subsystem/wt_dcache_mem.sv @@ -27,7 +27,7 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter parameter int unsigned NumPorts = 3 ) ( diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv index 4fa09c4e62..23b9df6c14 100644 --- a/core/cache_subsystem/wt_dcache_missunit.sv +++ b/core/cache_subsystem/wt_dcache_missunit.sv @@ -15,7 +15,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs parameter int unsigned NumPorts = 3 // number of miss ports diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv index 4334f06a3b..0090a33799 100644 --- a/core/cache_subsystem/wt_dcache_wbuffer.sv +++ b/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -50,7 +50,7 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions ) ( input logic clk_i, // Clock diff --git a/core/cache_subsystem/wt_l15_adapter.sv b/core/cache_subsystem/wt_l15_adapter.sv index b1a2860840..6dd3450d41 100644 --- a/core/cache_subsystem/wt_l15_adapter.sv +++ b/core/cache_subsystem/wt_l15_adapter.sv @@ -50,7 +50,7 @@ module wt_l15_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter bit SwapEndianess = 1 ) ( input logic clk_i, diff --git a/core/commit_stage.sv b/core/commit_stage.sv index 5ee099f54c..62018600c0 100644 --- a/core/commit_stage.sv +++ b/core/commit_stage.sv @@ -14,7 +14,7 @@ module commit_stage import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty )( input logic clk_i, input logic rst_ni, @@ -77,7 +77,7 @@ module commit_stage import ariane_pkg::*; #( always_comb begin : dirty_fp_state dirty_fp_state_o = 1'b0; for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin - dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || is_rd_fpr(commit_instr_i[i].op)); + dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || ariane_pkg::is_rd_fpr_cfg(commit_instr_i[i].op, CVA6Cfg.FpPresent)); // Check if we issued a vector floating-point instruction to the accellerator dirty_fp_state_o |= commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp; end @@ -117,7 +117,7 @@ module commit_stage import ariane_pkg::*; #( // we can definitely write the register file // if the instruction is not committing anything the destination commit_ack_o[0] = 1'b1; - if (is_rd_fpr(commit_instr_i[0].op)) begin + if (ariane_pkg::is_rd_fpr_cfg(commit_instr_i[0].op, CVA6Cfg.FpPresent)) begin we_fpr_o[0] = 1'b1; end else begin we_gpr_o[0] = 1'b1; @@ -197,7 +197,7 @@ module commit_stage import ariane_pkg::*; #( // ------------------ // AMO // ------------------ - if (RVA && instr_0_is_amo) begin + if (CVA6Cfg.RVA && instr_0_is_amo) begin // AMO finished commit_ack_o[0] = amo_resp_i.ack; // flush the pipeline @@ -229,7 +229,7 @@ module commit_stage import ariane_pkg::*; #( if (!exception_o.valid && !commit_instr_i[1].ex.valid && (commit_instr_i[1].fu inside {ALU, LOAD, CTRL_FLOW, MULT, FPU, FPU_VEC})) begin - if (is_rd_fpr(commit_instr_i[1].op)) + if (ariane_pkg::is_rd_fpr_cfg(commit_instr_i[1].op, CVA6Cfg.FpPresent)) we_fpr_o[1] = 1'b1; else we_gpr_o[1] = 1'b1; diff --git a/core/compressed_decoder.sv b/core/compressed_decoder.sv index b474dca680..2b4f4f46e3 100644 --- a/core/compressed_decoder.sv +++ b/core/compressed_decoder.sv @@ -20,7 +20,7 @@ module compressed_decoder #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic [31:0] instr_i, output logic [31:0] instr_o, diff --git a/core/controller.sv b/core/controller.sv index 5480286576..1596a4f4fb 100644 --- a/core/controller.sv +++ b/core/controller.sv @@ -14,7 +14,7 @@ module controller import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, input logic rst_ni, diff --git a/core/csr_buffer.sv b/core/csr_buffer.sv index 819df9f140..72db3196f9 100644 --- a/core/csr_buffer.sv +++ b/core/csr_buffer.sv @@ -15,7 +15,7 @@ module csr_buffer import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 71e217fccb..fe2022bcd1 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -14,7 +14,7 @@ module csr_regfile import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter logic [63:0] DmBaseAddress = 64'h0, // debug module base address parameter int AsidWidth = 1, parameter int unsigned NrPMPEntries = 8, @@ -155,6 +155,19 @@ module csr_regfile import ariane_pkg::*; #( logic [MHPMCounterNum+3-1:0] mcountinhibit_d,mcountinhibit_q; int index; + localparam riscv::xlen_t IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension + | (riscv::XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension + | (riscv::XLEN'(CVA6Cfg.RVD) << 3) // D - Double precsision floating-point extension + | (riscv::XLEN'(CVA6Cfg.RVF) << 5) // F - Single precsision floating-point extension + | (riscv::XLEN'(1 ) << 8) // I - RV32I/64I/128I base ISA + | (riscv::XLEN'(1 ) << 12) // M - Integer Multiply/Divide extension + | (riscv::XLEN'(0 ) << 13) // N - User level interrupts supported + | (riscv::XLEN'(1 ) << 18) // S - Supervisor mode implemented + | (riscv::XLEN'(1 ) << 20) // U - User mode implemented + | (riscv::XLEN'(CVA6Cfg.RVV) << 21) // V - Vector extension + | (riscv::XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present + | ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN-2); // MXL + assign pmpcfg_o = pmpcfg_q[15:0]; assign pmpaddr_o = pmpaddr_q; @@ -171,6 +184,7 @@ module csr_regfile import ariane_pkg::*; #( assign mstatus_extended = riscv::IS_XLEN64 ? mstatus_q[riscv::XLEN-1:0] : {mstatus_q.sd, mstatus_q.wpri3[7:0], mstatus_q[22:0]}; + always_comb begin : csr_read_process // a read access exception can only occur if we attempt to read a CSR which does not exist read_access_exception = 1'b0; @@ -242,7 +256,7 @@ module csr_regfile import ariane_pkg::*; #( // machine mode registers riscv::CSR_MSTATUS: csr_rdata = mstatus_extended; riscv::CSR_MSTATUSH: if (riscv::XLEN == 32) csr_rdata = '0; else read_access_exception = 1'b1; - riscv::CSR_MISA: csr_rdata = ISA_CODE; + riscv::CSR_MISA: csr_rdata = IsaCode; riscv::CSR_MEDELEG: csr_rdata = medeleg_q; riscv::CSR_MIDELEG: csr_rdata = mideleg_q; riscv::CSR_MIE: csr_rdata = mie_q; @@ -424,7 +438,7 @@ module csr_regfile import ariane_pkg::*; #( riscv::CSR_ICACHE: csr_rdata = icache_q; // custom (non RISC-V) accelerator memory consistency mode riscv::CSR_ACC_CONS: begin - if (ENABLE_ACCELERATOR) begin + if (CVA6Cfg.EnableAccelerator) begin csr_rdata = acc_cons_q; end else begin read_access_exception = 1'b1; @@ -622,11 +636,11 @@ module csr_regfile import ariane_pkg::*; #( mask = ariane_pkg::SMODE_STATUS_WRITE_MASK[riscv::XLEN-1:0]; mstatus_d = (mstatus_q & ~{{64-riscv::XLEN{1'b0}}, mask}) | {{64-riscv::XLEN{1'b0}}, (csr_wdata & mask)}; // hardwire to zero if floating point extension is not present - if (!FP_PRESENT) begin + if (!CVA6Cfg.FpPresent) begin mstatus_d.fs = riscv::Off; end // hardwire to zero if vector extension is not present - if (!RVV) begin + if (!CVA6Cfg.RVV) begin mstatus_d.vs = riscv::Off; end // this instruction has side-effects @@ -672,10 +686,10 @@ module csr_regfile import ariane_pkg::*; #( riscv::CSR_MSTATUS: begin mstatus_d = {{64-riscv::XLEN{1'b0}}, csr_wdata}; mstatus_d.xs = riscv::Off; - if (!FP_PRESENT) begin + if (!CVA6Cfg.FpPresent) begin mstatus_d.fs = riscv::Off; end - if (!RVV) begin + if (!CVA6Cfg.RVV) begin mstatus_d.vs = riscv::Off; end mstatus_d.wpri3 = 8'b0; @@ -827,7 +841,7 @@ module csr_regfile import ariane_pkg::*; #( riscv::CSR_DCACHE: dcache_d = {{riscv::XLEN-1{1'b0}}, csr_wdata[0]}; // enable bit riscv::CSR_ICACHE: icache_d = {{riscv::XLEN-1{1'b0}}, csr_wdata[0]}; // enable bit riscv::CSR_ACC_CONS: begin - if (ENABLE_ACCELERATOR) begin + if (CVA6Cfg.EnableAccelerator) begin acc_cons_d = {{riscv::XLEN-1{1'b0}}, csr_wdata[0]}; // enable bit end else begin update_access_exception = 1'b1; @@ -884,11 +898,11 @@ module csr_regfile import ariane_pkg::*; #( mstatus_d.uxl = riscv::XLEN_64; // mark the floating point extension register as dirty - if (FP_PRESENT && (dirty_fp_state_csr || dirty_fp_state_i)) begin + if (CVA6Cfg.FpPresent && (dirty_fp_state_csr || dirty_fp_state_i)) begin mstatus_d.fs = riscv::Dirty; end // mark the vector extension register as dirty - if (RVV && dirty_v_state_i) begin + if (CVA6Cfg.RVV && dirty_v_state_i) begin mstatus_d.vs = riscv::Dirty; end // hardwired extension registers @@ -905,7 +919,7 @@ module csr_regfile import ariane_pkg::*; #( // Update fflags as soon as a FP exception occurs in the accelerator // The exception is imprecise, and the fcsr.fflags update always happens immediately - if (ENABLE_ACCELERATOR) begin + if (CVA6Cfg.EnableAccelerator) begin fcsr_d.fflags |= acc_fflags_ex_valid_i ? acc_fflags_ex_i : 5'b0; end @@ -1323,7 +1337,7 @@ module csr_regfile import ariane_pkg::*; #( assign icache_en_o = icache_q[0] & (~debug_mode_q); `endif assign dcache_en_o = dcache_q[0]; - assign acc_cons_en_o = ENABLE_ACCELERATOR ? acc_cons_q[0] : 1'b0; + assign acc_cons_en_o = CVA6Cfg.EnableAccelerator ? acc_cons_q[0] : 1'b0; // determine if mprv needs to be considered if in debug mode assign mprv = (debug_mode_q && !dcsr_q.mprven) ? 1'b0 : mstatus_q.mprv; @@ -1362,7 +1376,7 @@ module csr_regfile import ariane_pkg::*; #( dcache_q <= {{riscv::XLEN-1{1'b0}}, 1'b1}; icache_q <= {{riscv::XLEN-1{1'b0}}, 1'b1}; mcountinhibit_q <= '0; - acc_cons_q <= {{riscv::XLEN-1{1'b0}}, ENABLE_ACCELERATOR}; + acc_cons_q <= {{riscv::XLEN-1{1'b0}}, CVA6Cfg.EnableAccelerator}; // supervisor mode registers sepc_q <= {riscv::XLEN{1'b0}}; scause_q <= {riscv::XLEN{1'b0}}; diff --git a/core/cva6.sv b/core/cva6.sv index 63cc33820c..2bfb09c795 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -14,38 +14,34 @@ module cva6 import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = { - unsigned'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts - unsigned'(cva6_config_pkg::CVA6ConfigRvfiTrace), // IsRVFI - unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth), // AxiAddrWidth - unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth), // AxiDataWidth - unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth), // AxiIdWidth - unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth) // AxiUserWidth - }, + // CVA6 config + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_default, + parameter bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace), + // RVFI parameter type rvfi_instr_t = struct packed { - logic [ariane_pkg::NRET-1:0] valid; - logic [ariane_pkg::NRET*64-1:0] order; - logic [ariane_pkg::NRET*ariane_pkg::ILEN-1:0] insn; - logic [ariane_pkg::NRET-1:0] trap; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] cause; - logic [ariane_pkg::NRET-1:0] halt; - logic [ariane_pkg::NRET-1:0] intr; - logic [ariane_pkg::NRET*2-1:0] mode; - logic [ariane_pkg::NRET*2-1:0] ixl; - logic [ariane_pkg::NRET*5-1:0] rs1_addr; - logic [ariane_pkg::NRET*5-1:0] rs2_addr; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs1_rdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs2_rdata; - logic [ariane_pkg::NRET*5-1:0] rd_addr; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] rd_wdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_rdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_wdata; - logic [ariane_pkg::NRET*riscv::VLEN-1:0] mem_addr; - logic [ariane_pkg::NRET*riscv::PLEN-1:0] mem_paddr; - logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask; - logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_rdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_wdata; + logic [config_pkg::NRET-1:0] valid; + logic [config_pkg::NRET*64-1:0] order; + logic [config_pkg::NRET*config_pkg::ILEN-1:0] insn; + logic [config_pkg::NRET-1:0] trap; + logic [config_pkg::NRET*riscv::XLEN-1:0] cause; + logic [config_pkg::NRET-1:0] halt; + logic [config_pkg::NRET-1:0] intr; + logic [config_pkg::NRET*2-1:0] mode; + logic [config_pkg::NRET*2-1:0] ixl; + logic [config_pkg::NRET*5-1:0] rs1_addr; + logic [config_pkg::NRET*5-1:0] rs2_addr; + logic [config_pkg::NRET*riscv::XLEN-1:0] rs1_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] rs2_rdata; + logic [config_pkg::NRET*5-1:0] rd_addr; + logic [config_pkg::NRET*riscv::XLEN-1:0] rd_wdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] pc_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] pc_wdata; + logic [config_pkg::NRET*riscv::VLEN-1:0] mem_addr; + logic [config_pkg::NRET*riscv::PLEN-1:0] mem_paddr; + logic [config_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask; + logic [config_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask; + logic [config_pkg::NRET*riscv::XLEN-1:0] mem_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] mem_wdata; }, // AXI types parameter type axi_ar_chan_t = struct packed { @@ -140,6 +136,63 @@ module cva6 import ariane_pkg::*; #( input noc_resp_t noc_resp_i ); + // ------------------------------------------ + // CVA6 configuration + // ------------------------------------------ + // Extended config + localparam bit RVF = (riscv::IS_XLEN64 | riscv::IS_XLEN32) & CVA6Cfg.FpuEn; + localparam bit RVD = (riscv::IS_XLEN64 ? 1:0) & CVA6Cfg.FpuEn; + localparam bit FpPresent = RVF | RVD | CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8; + localparam bit NSX = CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8 | CVA6Cfg.XFVec; // Are non-standard extensions present? + localparam int unsigned FLen = RVD ? 64 : // D ext. + RVF ? 32 : // F ext. + CVA6Cfg.XF16 ? 16 : // Xf16 ext. + CVA6Cfg.XF16ALT ? 16 : // Xf16alt ext. + CVA6Cfg.XF8 ? 8 : // Xf8 ext. + 1; // Unused in case of no FP + + // Transprecision floating-point extensions configuration + localparam bit RVFVec = RVF & CVA6Cfg.XFVec & FLen>32; // FP32 vectors available if vectors and larger fmt enabled + localparam bit XF16Vec = CVA6Cfg.XF16 & CVA6Cfg.XFVec & FLen>16; // FP16 vectors available if vectors and larger fmt enabled + localparam bit XF16ALTVec = CVA6Cfg.XF16ALT & CVA6Cfg.XFVec & FLen>16; // FP16ALT vectors available if vectors and larger fmt enabled + localparam bit XF8Vec = CVA6Cfg.XF8 & CVA6Cfg.XFVec & FLen>8; // FP8 vectors available if vectors and larger fmt enabled + + localparam bit EnableAccelerator = CVA6Cfg.RVV; // Currently only used by V extension (Ara) + localparam int unsigned NrWbPorts = (CVA6Cfg.CvxifEn || EnableAccelerator) ? 5 : 4; + + localparam NrRgprPorts = 2; + + localparam config_pkg::cva6_cfg_t CVA6ExtendCfg = { + CVA6Cfg.NrCommitPorts, + CVA6Cfg.AxiAddrWidth, + CVA6Cfg.AxiDataWidth, + CVA6Cfg.AxiIdWidth, + CVA6Cfg.AxiUserWidth, + CVA6Cfg.FpuEn, + CVA6Cfg.XF16, + CVA6Cfg.XF16ALT, + CVA6Cfg.XF8, + CVA6Cfg.RVA, + CVA6Cfg.RVV, + CVA6Cfg.RVC, + CVA6Cfg.XFVec, + CVA6Cfg.CvxifEn, + // Extended + bit'(RVF), + bit'(RVD), + bit'(FpPresent), + bit'(NSX), + unsigned'(FLen), + bit'(RVFVec), + bit'(XF16Vec), + bit'(XF16ALTVec), + bit'(XF8Vec), + unsigned'(NrRgprPorts), + unsigned'(NrWbPorts), + bit'(EnableAccelerator) + }; + + // ------------------------------------------ // Global Signals // Signals connecting more than one module @@ -149,7 +202,7 @@ module cva6 import ariane_pkg::*; #( bp_resolve_t resolved_branch; logic [riscv::VLEN-1:0] pc_commit; logic eret; - logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack; + logic [CVA6ExtendCfg.NrCommitPorts-1:0] commit_ack; localparam NumPorts = 3; cvxif_pkg::cvxif_req_t cvxif_req; @@ -263,14 +316,14 @@ module cva6 import ariane_pkg::*; #( // -------------- // ID <-> COMMIT // -------------- - scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_id_commit; + scoreboard_entry_t [CVA6ExtendCfg.NrCommitPorts-1:0] commit_instr_id_commit; // -------------- // COMMIT <-> ID // -------------- - logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_commit_id; - logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_commit_id; - logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_commit_id; - logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_commit_id; + logic [CVA6ExtendCfg.NrCommitPorts-1:0][4:0] waddr_commit_id; + logic [CVA6ExtendCfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_commit_id; + logic [CVA6ExtendCfg.NrCommitPorts-1:0] we_gpr_commit_id; + logic [CVA6ExtendCfg.NrCommitPorts-1:0] we_fpr_commit_id; // -------------- // CSR <-> * // -------------- @@ -372,7 +425,7 @@ module cva6 import ariane_pkg::*; #( // Frontend // -------------- frontend #( - .CVA6Cfg ( CVA6Cfg ), + .CVA6Cfg ( CVA6ExtendCfg ), .ArianeCfg ( ArianeCfg ) ) i_frontend ( .flush_i ( flush_ctrl_if ), // not entirely correct @@ -400,7 +453,7 @@ module cva6 import ariane_pkg::*; #( // ID // --------- id_stage #( - .CVA6Cfg ( CVA6Cfg ) + .CVA6Cfg ( CVA6ExtendCfg ) ) id_stage_i ( .clk_i, .rst_ni, @@ -428,17 +481,17 @@ module cva6 import ariane_pkg::*; #( .tsr_i ( tsr_csr_id ) ); - logic [NR_WB_PORTS-1:0][TRANS_ID_BITS-1:0] trans_id_ex_id; - logic [NR_WB_PORTS-1:0][riscv::XLEN-1:0] wbdata_ex_id; - exception_t [NR_WB_PORTS-1:0] ex_ex_ex_id; // exception from execute, ex_stage to id_stage - logic [NR_WB_PORTS-1:0] wt_valid_ex_id; + logic [NrWbPorts-1:0][TRANS_ID_BITS-1:0] trans_id_ex_id; + logic [NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_ex_id; + exception_t [NrWbPorts-1:0] ex_ex_ex_id; // exception from execute, ex_stage to id_stage + logic [NrWbPorts-1:0] wt_valid_ex_id; - if (CVXIF_PRESENT) begin + if (CVA6ExtendCfg.CvxifEn) begin assign trans_id_ex_id = {x_trans_id_ex_id, flu_trans_id_ex_id, load_trans_id_ex_id, store_trans_id_ex_id, fpu_trans_id_ex_id}; assign wbdata_ex_id = {x_result_ex_id, flu_result_ex_id, load_result_ex_id, store_result_ex_id, fpu_result_ex_id}; assign ex_ex_ex_id = {x_exception_ex_id, flu_exception_ex_id, load_exception_ex_id, store_exception_ex_id, fpu_exception_ex_id}; assign wt_valid_ex_id = {x_valid_ex_id, flu_valid_ex_id, load_valid_ex_id, store_valid_ex_id, fpu_valid_ex_id}; - end else if (ENABLE_ACCELERATOR) begin + end else if (CVA6ExtendCfg.EnableAccelerator) begin assign trans_id_ex_id = {flu_trans_id_ex_id, load_trans_id_ex_id, store_trans_id_ex_id, fpu_trans_id_ex_id, acc_trans_id_ex_id}; assign wbdata_ex_id = {flu_result_ex_id, load_result_ex_id, store_result_ex_id, fpu_result_ex_id, acc_result_ex_id}; assign ex_ex_ex_id = {flu_exception_ex_id, load_exception_ex_id, store_exception_ex_id, fpu_exception_ex_id, acc_exception_ex_id}; @@ -450,7 +503,7 @@ module cva6 import ariane_pkg::*; #( assign wt_valid_ex_id = {flu_valid_ex_id, load_valid_ex_id, store_valid_ex_id, fpu_valid_ex_id}; end - if (CVXIF_PRESENT && ENABLE_ACCELERATOR) begin : gen_err_xif_and_acc + if (CVA6ExtendCfg.CvxifEn && CVA6ExtendCfg.EnableAccelerator) begin : gen_err_xif_and_acc $error("X-interface and accelerator port cannot be enabled at the same time."); end @@ -458,9 +511,9 @@ module cva6 import ariane_pkg::*; #( // Issue // --------- issue_stage #( - .CVA6Cfg ( CVA6Cfg ), - .NR_ENTRIES ( NR_SB_ENTRIES ), - .NR_WB_PORTS ( NR_WB_PORTS ) + .CVA6Cfg ( CVA6ExtendCfg ), + .IsRVFI ( IsRVFI ), + .NR_ENTRIES ( NR_SB_ENTRIES ) ) issue_stage_i ( .clk_i, .rst_ni, @@ -534,7 +587,7 @@ module cva6 import ariane_pkg::*; #( // EX // --------- ex_stage #( - .CVA6Cfg ( CVA6Cfg ), + .CVA6Cfg ( CVA6ExtendCfg ), .ASID_WIDTH ( ASID_WIDTH ), .ArianeCfg ( ArianeCfg ) ) ex_stage_i ( @@ -652,7 +705,7 @@ module cva6 import ariane_pkg::*; #( assign no_st_pending_commit = no_st_pending_ex & dcache_commit_wbuffer_empty; commit_stage #( - .CVA6Cfg ( CVA6Cfg ) + .CVA6Cfg ( CVA6ExtendCfg ) ) commit_stage_i ( .clk_i, .rst_ni, @@ -691,7 +744,7 @@ module cva6 import ariane_pkg::*; #( // CSR // --------- csr_regfile #( - .CVA6Cfg ( CVA6Cfg ), + .CVA6Cfg ( CVA6ExtendCfg ), .AsidWidth ( ASID_WIDTH ), .DmBaseAddress ( ArianeCfg.DmBaseAddress ), .NrPMPEntries ( ArianeCfg.NrPMPEntries ), @@ -760,7 +813,7 @@ module cva6 import ariane_pkg::*; #( // ------------------------ if (PERF_COUNTER_EN) begin: gen_perf_counter perf_counters #( - .CVA6Cfg ( CVA6Cfg ), + .CVA6Cfg ( CVA6ExtendCfg ), .NumPorts ( NumPorts ) ) perf_counters_i ( .clk_i ( clk_i ), @@ -798,7 +851,7 @@ module cva6 import ariane_pkg::*; #( // Controller // ------------ controller #( - .CVA6Cfg ( CVA6Cfg ) + .CVA6Cfg ( CVA6ExtendCfg ) ) controller_i ( // flush ports .set_pc_commit_o ( set_pc_ctrl_pcgen ), @@ -837,7 +890,7 @@ module cva6 import ariane_pkg::*; #( if (DCACHE_TYPE == int'(cva6_config_pkg::WT)) begin : gen_cache_wt // this is a cache subsystem that is compatible with OpenPiton wt_cache_subsystem #( - .CVA6Cfg ( CVA6Cfg ), + .CVA6Cfg ( CVA6ExtendCfg ), .ArianeCfg ( ArianeCfg ), .NumPorts ( NumPorts ), .noc_req_t ( noc_req_t ), @@ -882,7 +935,7 @@ module cva6 import ariane_pkg::*; #( // note: this only works with one cacheable region // not as important since this cache subsystem is about to be // deprecated - .CVA6Cfg ( CVA6Cfg ), + .CVA6Cfg ( CVA6ExtendCfg ), .ArianeCfg ( ArianeCfg ), .axi_ar_chan_t ( axi_ar_chan_t ), .axi_aw_chan_t ( axi_aw_chan_t ), @@ -927,9 +980,9 @@ module cva6 import ariane_pkg::*; #( // Accelerator // ---------------- - if (ENABLE_ACCELERATOR) begin: gen_accelerator + if (CVA6ExtendCfg.EnableAccelerator) begin: gen_accelerator acc_dispatcher #( - .CVA6Cfg ( CVA6Cfg ), + .CVA6Cfg ( CVA6ExtendCfg), .acc_cfg_t ( acc_cfg_t ), .AccCfg ( AccCfg ), .acc_req_t ( cvxif_req_t ), @@ -1009,10 +1062,10 @@ module cva6 import ariane_pkg::*; #( logic piton_pc_vld; logic [riscv::VLEN-1:0] piton_pc; - logic [CVA6Cfg.NrCommitPorts-1:0][riscv::VLEN-1:0] pc_data; - logic [CVA6Cfg.NrCommitPorts-1:0] pc_pop, pc_empty; + logic [CVA6ExtendCfg.NrCommitPorts-1:0][riscv::VLEN-1:0] pc_data; + logic [CVA6ExtendCfg.NrCommitPorts-1:0] pc_pop, pc_empty; - for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_pc_fifo + for (genvar i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin : gen_pc_fifo fifo_v3 #( .DATA_WIDTH(64), .DEPTH(PC_QUEUE_DEPTH)) @@ -1032,7 +1085,7 @@ module cva6 import ariane_pkg::*; #( end rr_arb_tree #( - .NumIn(CVA6Cfg.NrCommitPorts), + .NumIn(CVA6ExtendCfg.NrCommitPorts), .DataWidth(64)) i_rr_arb_tree ( .clk_i ( clk_i ), @@ -1116,7 +1169,7 @@ module cva6 import ariane_pkg::*; #( default: ; // Do nothing endcase end - for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + for (int i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]); end else if (commit_ack[i] && commit_instr_id_commit[i].ex.valid) begin @@ -1141,9 +1194,9 @@ module cva6 import ariane_pkg::*; #( `endif // VERILATOR //pragma translate_on - if (CVA6Cfg.IsRVFI) begin + if (IsRVFI) begin always_comb begin - for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + for (int i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin logic exception, mem_exception; exception = commit_instr_id_commit[i].valid && ex_commit.valid; mem_exception = exception && @@ -1171,7 +1224,7 @@ module cva6 import ariane_pkg::*; #( rvfi_o[i].rs1_addr = commit_instr_id_commit[i].rs1[4:0]; rvfi_o[i].rs2_addr = commit_instr_id_commit[i].rs2[4:0]; rvfi_o[i].rd_addr = commit_instr_id_commit[i].rd[4:0]; - rvfi_o[i].rd_wdata = ariane_pkg::is_rd_fpr(commit_instr_id_commit[i].op) == 0 ? wdata_commit_id[i] : commit_instr_id_commit[i].result; + rvfi_o[i].rd_wdata = ariane_pkg::is_rd_fpr_cfg(commit_instr_id_commit[i].op, CVA6ExtendCfg.FpPresent) == 0 ? wdata_commit_id[i] : commit_instr_id_commit[i].result; rvfi_o[i].pc_rdata = commit_instr_id_commit[i].pc; rvfi_o[i].mem_addr = commit_instr_id_commit[i].lsu_addr; diff --git a/core/cvxif_fu.sv b/core/cvxif_fu.sv index 11d4838e5e..7896c0576d 100644 --- a/core/cvxif_fu.sv +++ b/core/cvxif_fu.sv @@ -11,7 +11,7 @@ module cvxif_fu import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, input logic rst_ni, diff --git a/core/decoder.sv b/core/decoder.sv index 86dd567e7f..96946124ce 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -20,7 +20,7 @@ // module decoder import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic debug_req_i, // external debug request input logic [riscv::VLEN-1:0] pc_i, // PC from IF @@ -77,7 +77,7 @@ module decoder import ariane_pkg::*; #( logic acc_illegal_instr; logic acc_is_control_flow_instr; - if (ENABLE_ACCELERATOR) begin: gen_accel_decoder + if (CVA6Cfg.EnableAccelerator) begin: gen_accel_decoder // This module is responsible for a light-weight decoding of accelerator instructions, // identifying them, but also whether they read/write scalar registers. // Accelerators are supposed to define this module. @@ -281,7 +281,7 @@ module decoder import ariane_pkg::*; #( // -------------------------------------------- if (instr.rvftype.funct2 == 2'b10) begin // Prefix 10 for all Xfvec ops // only generate decoder if FP extensions are enabled (static) - if (FP_PRESENT && XFVEC && fs_i != riscv::Off) begin + if (CVA6Cfg.FpPresent && CVA6Cfg.XFVec && fs_i != riscv::Off) begin automatic logic allow_replication; // control honoring of replication flag instruction_o.fu = FPU_VEC; // Same unit, but sets 'vectorial' signal @@ -352,10 +352,10 @@ module decoder import ariane_pkg::*; #( // determine source format unique case (instr.rvftype.rs2[21:20]) // Only process instruction if corresponding extension is active (static) - 2'b00: if (~RVFVEC) illegal_instr = 1'b1; - 2'b01: if (~XF16ALTVEC) illegal_instr = 1'b1; - 2'b10: if (~XF16VEC) illegal_instr = 1'b1; - 2'b11: if (~XF8VEC) illegal_instr = 1'b1; + 2'b00: if (~CVA6Cfg.RVFVec) illegal_instr = 1'b1; + 2'b01: if (~CVA6Cfg.XF16ALTVec) illegal_instr = 1'b1; + 2'b10: if (~CVA6Cfg.XF16Vec) illegal_instr = 1'b1; + 2'b11: if (~CVA6Cfg.XF8Vec) illegal_instr = 1'b1; default : illegal_instr = 1'b1; endcase end @@ -401,22 +401,22 @@ module decoder import ariane_pkg::*; #( 5'b11000 : begin instruction_o.op = ariane_pkg::VFCPKAB_S; // vfcpka/b.vfmt.s - Vectorial FP Cast-and-Pack from 2x FP32, lowest 4 entries imm_select = SIMM; // rd into result field (upper bits don't matter) - if (~RVF) illegal_instr = 1'b1; // if we don't support RVF, we can't cast from FP32 + if (~CVA6Cfg.RVF) illegal_instr = 1'b1; // if we don't support RVF, we can't cast from FP32 // check destination format unique case (instr.rvftype.vfmt) // Only process instruction if corresponding extension is active and FLEN suffices (static) 2'b00: begin - if (~RVFVEC) illegal_instr = 1'b1; // destination vector not supported + if (~CVA6Cfg.RVFVec) illegal_instr = 1'b1; // destination vector not supported if (instr.rvftype.repl) illegal_instr = 1'b1; // no entries 2/3 in vector of 2 fp32 end 2'b01: begin - if (~XF16ALTVEC) illegal_instr = 1'b1; // destination vector not supported + if (~CVA6Cfg.XF16ALTVec) illegal_instr = 1'b1; // destination vector not supported end 2'b10: begin - if (~XF16VEC) illegal_instr = 1'b1; // destination vector not supported + if (~CVA6Cfg.XF16Vec) illegal_instr = 1'b1; // destination vector not supported end 2'b11: begin - if (~XF8VEC) illegal_instr = 1'b1; // destination vector not supported + if (~CVA6Cfg.XF8Vec) illegal_instr = 1'b1; // destination vector not supported end default : illegal_instr = 1'b1; endcase @@ -424,7 +424,7 @@ module decoder import ariane_pkg::*; #( 5'b11001 : begin instruction_o.op = ariane_pkg::VFCPKCD_S; // vfcpkc/d.vfmt.s - Vectorial FP Cast-and-Pack from 2x FP32, second 4 entries imm_select = SIMM; // rd into result field (upper bits don't matter) - if (~RVF) illegal_instr = 1'b1; // if we don't support RVF, we can't cast from FP32 + if (~CVA6Cfg.RVF) illegal_instr = 1'b1; // if we don't support RVF, we can't cast from FP32 // check destination format unique case (instr.rvftype.vfmt) // Only process instruction if corresponding extension is active and FLEN suffices (static) @@ -432,7 +432,7 @@ module decoder import ariane_pkg::*; #( 2'b01: illegal_instr = 1'b1; // no entries 4-7 in vector of 4 FP16ALT 2'b10: illegal_instr = 1'b1; // no entries 4-7 in vector of 4 FP16 2'b11: begin - if (~XF8VEC) illegal_instr = 1'b1; // destination vector not supported + if (~CVA6Cfg.XF8Vec) illegal_instr = 1'b1; // destination vector not supported end default : illegal_instr = 1'b1; endcase @@ -440,22 +440,22 @@ module decoder import ariane_pkg::*; #( 5'b11010 : begin instruction_o.op = ariane_pkg::VFCPKAB_D; // vfcpka/b.vfmt.d - Vectorial FP Cast-and-Pack from 2x FP64, lowest 4 entries imm_select = SIMM; // rd into result field (upper bits don't matter) - if (~RVD) illegal_instr = 1'b1; // if we don't support RVD, we can't cast from FP64 + if (~CVA6Cfg.RVD) illegal_instr = 1'b1; // if we don't support RVD, we can't cast from FP64 // check destination format unique case (instr.rvftype.vfmt) // Only process instruction if corresponding extension is active and FLEN suffices (static) 2'b00: begin - if (~RVFVEC) illegal_instr = 1'b1; // destination vector not supported + if (~CVA6Cfg.RVFVec) illegal_instr = 1'b1; // destination vector not supported if (instr.rvftype.repl) illegal_instr = 1'b1; // no entries 2/3 in vector of 2 fp32 end 2'b01: begin - if (~XF16ALTVEC) illegal_instr = 1'b1; // destination vector not supported + if (~CVA6Cfg.XF16ALTVec) illegal_instr = 1'b1; // destination vector not supported end 2'b10: begin - if (~XF16VEC) illegal_instr = 1'b1; // destination vector not supported + if (~CVA6Cfg.XF16Vec) illegal_instr = 1'b1; // destination vector not supported end 2'b11: begin - if (~XF8VEC) illegal_instr = 1'b1; // destination vector not supported + if (~CVA6Cfg.XF8Vec) illegal_instr = 1'b1; // destination vector not supported end default : illegal_instr = 1'b1; endcase @@ -463,7 +463,7 @@ module decoder import ariane_pkg::*; #( 5'b11011 : begin instruction_o.op = ariane_pkg::VFCPKCD_D; // vfcpka/b.vfmt.d - Vectorial FP Cast-and-Pack from 2x FP64, second 4 entries imm_select = SIMM; // rd into result field (upper bits don't matter) - if (~RVD) illegal_instr = 1'b1; // if we don't support RVD, we can't cast from FP64 + if (~CVA6Cfg.RVD) illegal_instr = 1'b1; // if we don't support RVD, we can't cast from FP64 // check destination format unique case (instr.rvftype.vfmt) // Only process instruction if corresponding extension is active and FLEN suffices (static) @@ -471,7 +471,7 @@ module decoder import ariane_pkg::*; #( 2'b01: illegal_instr = 1'b1; // no entries 4-7 in vector of 4 FP16ALT 2'b10: illegal_instr = 1'b1; // no entries 4-7 in vector of 4 FP16 2'b11: begin - if (~XF8VEC) illegal_instr = 1'b1; // destination vector not supported + if (~CVA6Cfg.XF8Vec) illegal_instr = 1'b1; // destination vector not supported end default : illegal_instr = 1'b1; endcase @@ -482,10 +482,10 @@ module decoder import ariane_pkg::*; #( // check format unique case (instr.rvftype.vfmt) // Only process instruction if corresponding extension is active (static) - 2'b00: if (~RVFVEC) illegal_instr = 1'b1; - 2'b01: if (~XF16ALTVEC) illegal_instr = 1'b1; - 2'b10: if (~XF16VEC) illegal_instr = 1'b1; - 2'b11: if (~XF8VEC) illegal_instr = 1'b1; + 2'b00: if (~CVA6Cfg.RVFVec) illegal_instr = 1'b1; + 2'b01: if (~CVA6Cfg.XF16ALTVec) illegal_instr = 1'b1; + 2'b10: if (~CVA6Cfg.XF16Vec) illegal_instr = 1'b1; + 2'b11: if (~CVA6Cfg.XF8Vec) illegal_instr = 1'b1; default: illegal_instr = 1'b1; endcase @@ -810,7 +810,7 @@ module decoder import ariane_pkg::*; #( // Floating-Point Load/store // -------------------------------- riscv::OpcodeStoreFp: begin - if (FP_PRESENT && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static) + if (CVA6Cfg.FpPresent && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static) instruction_o.fu = STORE; imm_select = SIMM; instruction_o.rs1[4:0] = instr.stype.rs1; @@ -818,13 +818,13 @@ module decoder import ariane_pkg::*; #( // determine store size unique case (instr.stype.funct3) // Only process instruction if corresponding extension is active (static) - 3'b000: if (XF8) instruction_o.op = ariane_pkg::FSB; + 3'b000: if (CVA6Cfg.XF8) instruction_o.op = ariane_pkg::FSB; else illegal_instr = 1'b1; - 3'b001: if (XF16 | XF16ALT) instruction_o.op = ariane_pkg::FSH; + 3'b001: if (CVA6Cfg.XF16 | CVA6Cfg.XF16ALT) instruction_o.op = ariane_pkg::FSH; else illegal_instr = 1'b1; - 3'b010: if (RVF) instruction_o.op = ariane_pkg::FSW; + 3'b010: if (CVA6Cfg.RVF) instruction_o.op = ariane_pkg::FSW; else illegal_instr = 1'b1; - 3'b011: if (RVD) instruction_o.op = ariane_pkg::FSD; + 3'b011: if (CVA6Cfg.RVD) instruction_o.op = ariane_pkg::FSD; else illegal_instr = 1'b1; default: illegal_instr = 1'b1; endcase @@ -833,7 +833,7 @@ module decoder import ariane_pkg::*; #( end riscv::OpcodeLoadFp: begin - if (FP_PRESENT && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static) + if (CVA6Cfg.FpPresent && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static) instruction_o.fu = LOAD; imm_select = IIMM; instruction_o.rs1[4:0] = instr.itype.rs1; @@ -841,13 +841,13 @@ module decoder import ariane_pkg::*; #( // determine load size unique case (instr.itype.funct3) // Only process instruction if corresponding extension is active (static) - 3'b000: if (XF8) instruction_o.op = ariane_pkg::FLB; + 3'b000: if (CVA6Cfg.XF8) instruction_o.op = ariane_pkg::FLB; else illegal_instr = 1'b1; - 3'b001: if (XF16 | XF16ALT) instruction_o.op = ariane_pkg::FLH; + 3'b001: if (CVA6Cfg.XF16 | CVA6Cfg.XF16ALT) instruction_o.op = ariane_pkg::FLH; else illegal_instr = 1'b1; - 3'b010: if (RVF) instruction_o.op = ariane_pkg::FLW; + 3'b010: if (CVA6Cfg.RVF) instruction_o.op = ariane_pkg::FLW; else illegal_instr = 1'b1; - 3'b011: if (RVD) instruction_o.op = ariane_pkg::FLD; + 3'b011: if (CVA6Cfg.RVD) instruction_o.op = ariane_pkg::FLD; else illegal_instr = 1'b1; default: illegal_instr = 1'b1; endcase @@ -862,7 +862,7 @@ module decoder import ariane_pkg::*; #( riscv::OpcodeMsub, riscv::OpcodeNmsub, riscv::OpcodeNmadd: begin - if (FP_PRESENT && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static) + if (CVA6Cfg.FpPresent && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static) instruction_o.fu = FPU; instruction_o.rs1[4:0] = instr.r4type.rs1; instruction_o.rs2[4:0] = instr.r4type.rs2; @@ -880,10 +880,10 @@ module decoder import ariane_pkg::*; #( // determine fp format unique case (instr.r4type.funct2) // Only process instruction if corresponding extension is active (static) - 2'b00: if (~RVF) illegal_instr = 1'b1; - 2'b01: if (~RVD) illegal_instr = 1'b1; - 2'b10: if (~XF16 & ~XF16ALT) illegal_instr = 1'b1; - 2'b11: if (~XF8) illegal_instr = 1'b1; + 2'b00: if (~CVA6Cfg.RVF) illegal_instr = 1'b1; + 2'b01: if (~CVA6Cfg.RVD) illegal_instr = 1'b1; + 2'b10: if (~CVA6Cfg.XF16 & ~CVA6Cfg.XF16ALT) illegal_instr = 1'b1; + 2'b11: if (~CVA6Cfg.XF8) illegal_instr = 1'b1; default: illegal_instr = 1'b1; endcase @@ -892,7 +892,7 @@ module decoder import ariane_pkg::*; #( unique case (instr.rftype.rm) inside [3'b000:3'b100]: ; //legal rounding modes 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 - if (~XF16ALT || instr.rftype.fmt != 2'b10) + if (~CVA6Cfg.XF16ALT || instr.rftype.fmt != 2'b10) illegal_instr = 1'b1; unique case (frm_i) inside // actual rounding mode from frm csr [3'b000:3'b100]: ; //legal rounding modes @@ -915,7 +915,7 @@ module decoder import ariane_pkg::*; #( end riscv::OpcodeOpFp: begin - if (FP_PRESENT && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static) + if (CVA6Cfg.FpPresent && fs_i != riscv::Off) begin // only generate decoder if FP extensions are enabled (static) instruction_o.fu = FPU; instruction_o.rs1[4:0] = instr.rftype.rs1; instruction_o.rs2[4:0] = instr.rftype.rs2; @@ -945,7 +945,7 @@ module decoder import ariane_pkg::*; #( 5'b00100: begin instruction_o.op = ariane_pkg::FSGNJ; // fsgn{j[n]/jx}.fmt - FP Sign Injection check_fprm = 1'b0; // instruction encoded in rm, do the check here - if (XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) + if (CVA6Cfg.XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) if (!(instr.rftype.rm inside {[3'b000:3'b010], [3'b100:3'b110]})) illegal_instr = 1'b1; end else begin @@ -956,7 +956,7 @@ module decoder import ariane_pkg::*; #( 5'b00101: begin instruction_o.op = ariane_pkg::FMIN_MAX; // fmin/fmax.fmt - FP Minimum / Maximum check_fprm = 1'b0; // instruction encoded in rm, do the check here - if (XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) + if (CVA6Cfg.XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) if (!(instr.rftype.rm inside {[3'b000:3'b001], [3'b100:3'b101]})) illegal_instr = 1'b1; end else begin @@ -972,18 +972,18 @@ module decoder import ariane_pkg::*; #( // check source format unique case (instr.rftype.rs2[22:20]) // Only process instruction if corresponding extension is active (static) - 3'b000: if (~RVF) illegal_instr = 1'b1; - 3'b001: if (~RVD) illegal_instr = 1'b1; - 3'b010: if (~XF16) illegal_instr = 1'b1; - 3'b110: if (~XF16ALT) illegal_instr = 1'b1; - 3'b011: if (~XF8) illegal_instr = 1'b1; + 3'b000: if (~CVA6Cfg.RVF) illegal_instr = 1'b1; + 3'b001: if (~CVA6Cfg.RVD) illegal_instr = 1'b1; + 3'b010: if (~CVA6Cfg.XF16) illegal_instr = 1'b1; + 3'b110: if (~CVA6Cfg.XF16ALT) illegal_instr = 1'b1; + 3'b011: if (~CVA6Cfg.XF8) illegal_instr = 1'b1; default: illegal_instr = 1'b1; endcase end 5'b10100: begin instruction_o.op = ariane_pkg::FCMP; // feq/flt/fle.fmt - FP Comparisons check_fprm = 1'b0; // instruction encoded in rm, do the check here - if (XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) + if (CVA6Cfg.XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) if (!(instr.rftype.rm inside {[3'b000:3'b010], [3'b100:3'b110]})) illegal_instr = 1'b1; end else begin @@ -1004,9 +1004,9 @@ module decoder import ariane_pkg::*; #( 5'b11100: begin instruction_o.rs2[4:0] = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit check_fprm = 1'b0; // instruction encoded in rm, do the check here - if (instr.rftype.rm == 3'b000 || (XF16ALT && instr.rftype.rm == 3'b100)) // FP16ALT has separate encoding + if (instr.rftype.rm == 3'b000 || (CVA6Cfg.XF16ALT && instr.rftype.rm == 3'b100)) // FP16ALT has separate encoding instruction_o.op = ariane_pkg::FMV_F2X; // fmv.ifmt.fmt - FPR to GPR Move - else if (instr.rftype.rm == 3'b001 || (XF16ALT && instr.rftype.rm == 3'b101)) // FP16ALT has separate encoding + else if (instr.rftype.rm == 3'b001 || (CVA6Cfg.XF16ALT && instr.rftype.rm == 3'b101)) // FP16ALT has separate encoding instruction_o.op = ariane_pkg::FCLASS; // fclass.fmt - FP Classify else illegal_instr = 1'b1; // rs2 must be zero @@ -1016,7 +1016,7 @@ module decoder import ariane_pkg::*; #( instruction_o.op = ariane_pkg::FMV_X2F; // fmv.fmt.ifmt - GPR to FPR Move instruction_o.rs2[4:0] = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit check_fprm = 1'b0; // instruction encoded in rm, do the check here - if (!(instr.rftype.rm == 3'b000 || (XF16ALT && instr.rftype.rm == 3'b100))) + if (!(instr.rftype.rm == 3'b000 || (CVA6Cfg.XF16ALT && instr.rftype.rm == 3'b100))) illegal_instr = 1'b1; // rs2 must be zero if (instr.rftype.rs2 != 5'b00000) illegal_instr = 1'b1; @@ -1027,10 +1027,10 @@ module decoder import ariane_pkg::*; #( // check format unique case (instr.rftype.fmt) // Only process instruction if corresponding extension is active (static) - 2'b00: if (~RVF) illegal_instr = 1'b1; - 2'b01: if (~RVD) illegal_instr = 1'b1; - 2'b10: if (~XF16 & ~XF16ALT) illegal_instr = 1'b1; - 2'b11: if (~XF8) illegal_instr = 1'b1; + 2'b00: if (~CVA6Cfg.RVF) illegal_instr = 1'b1; + 2'b01: if (~CVA6Cfg.RVD) illegal_instr = 1'b1; + 2'b10: if (~CVA6Cfg.XF16 & ~CVA6Cfg.XF16ALT) illegal_instr = 1'b1; + 2'b11: if (~CVA6Cfg.XF8) illegal_instr = 1'b1; default: illegal_instr = 1'b1; endcase @@ -1039,7 +1039,7 @@ module decoder import ariane_pkg::*; #( unique case (instr.rftype.rm) inside [3'b000:3'b100]: ; //legal rounding modes 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 - if (~XF16ALT || instr.rftype.fmt != 2'b10) + if (~CVA6Cfg.XF16ALT || instr.rftype.fmt != 2'b10) illegal_instr = 1'b1; unique case (frm_i) inside // actual rounding mode from frm csr [3'b000:3'b100]: ; //legal rounding modes @@ -1072,7 +1072,7 @@ module decoder import ariane_pkg::*; #( instruction_o.rd[4:0] = instr.atype.rd; // TODO(zarubaf): Ordering // words - if (RVA && instr.stype.funct3 == 3'h2) begin + if (CVA6Cfg.RVA && instr.stype.funct3 == 3'h2) begin unique case (instr.instr[31:27]) 5'h0: instruction_o.op = ariane_pkg::AMO_ADDW; 5'h1: instruction_o.op = ariane_pkg::AMO_SWAPW; @@ -1091,7 +1091,7 @@ module decoder import ariane_pkg::*; #( default: illegal_instr = 1'b1; endcase // double words - end else if (RVA && instr.stype.funct3 == 3'h3) begin + end else if (CVA6Cfg.RVA && instr.stype.funct3 == 3'h3) begin unique case (instr.instr[31:27]) 5'h0: instruction_o.op = ariane_pkg::AMO_ADDD; 5'h1: instruction_o.op = ariane_pkg::AMO_SWAPD; @@ -1173,7 +1173,7 @@ module decoder import ariane_pkg::*; #( default: illegal_instr = 1'b1; endcase end - if (CVXIF_PRESENT) begin + if (CVA6Cfg.CvxifEn) begin if (is_illegal_i || illegal_instr) begin instruction_o.fu = CVXIF; instruction_o.rs1[4:0] = instr.r4type.rs1; @@ -1186,7 +1186,7 @@ module decoder import ariane_pkg::*; #( // Accelerator instructions. // These can overwrite the previous decoding entirely. - if (ENABLE_ACCELERATOR) begin // only generate decoder if accelerators are enabled (static) + if (CVA6Cfg.EnableAccelerator) begin // only generate decoder if accelerators are enabled (static) if (is_accel) begin instruction_o.fu = acc_instruction.fu; instruction_o.vfp = acc_instruction.vfp; @@ -1245,7 +1245,7 @@ module decoder import ariane_pkg::*; #( end endcase - if (ENABLE_ACCELERATOR) begin + if (CVA6Cfg.EnableAccelerator) begin if (is_accel) begin instruction_o.result = acc_instruction.result; instruction_o.use_imm = acc_instruction.use_imm; @@ -1275,7 +1275,7 @@ module decoder import ariane_pkg::*; #( // check here if we decoded an invalid instruction or if the compressed decoder already decoded // a invalid instruction if (illegal_instr || is_illegal_i) begin - if (!CVXIF_PRESENT) instruction_o.ex.valid = 1'b1; + if (!CVA6Cfg.CvxifEn) instruction_o.ex.valid = 1'b1; // we decoded an illegal exception here instruction_o.ex.cause = riscv::ILLEGAL_INSTR; // we got an ecall, set the correct cause depending on the current privilege level diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 59d542323e..05dda566e6 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -15,7 +15,7 @@ module ex_stage import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned ASID_WIDTH = 1, parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig ) ( @@ -264,11 +264,13 @@ module ex_stage import ariane_pkg::*; #( // FPU // ---------------- generate - if (FP_PRESENT) begin : fpu_gen + if (CVA6Cfg.FpPresent) begin : fpu_gen fu_data_t fpu_data; assign fpu_data = fpu_valid_i ? fu_data_i : '0; - fpu_wrap fpu_i ( + fpu_wrap #( + .CVA6Cfg ( CVA6Cfg ) + ) fpu_i ( .clk_i, .rst_ni, .flush_i, @@ -355,7 +357,7 @@ module ex_stage import ariane_pkg::*; #( .lsu_addr_trans_id_o ); - if (CVXIF_PRESENT) begin : gen_cvxif + if (CVA6Cfg.CvxifEn) begin : gen_cvxif fu_data_t cvxif_data; assign cvxif_data = x_valid_i ? fu_data_i : '0; cvxif_fu #( diff --git a/core/fpu_wrap.sv b/core/fpu_wrap.sv index 646d9e726e..3a586604d7 100644 --- a/core/fpu_wrap.sv +++ b/core/fpu_wrap.sv @@ -14,7 +14,7 @@ module fpu_wrap import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, input logic rst_ni, @@ -28,7 +28,7 @@ module fpu_wrap import ariane_pkg::*; #( input logic [2:0] fpu_frm_i, input logic [6:0] fpu_prec_i, output logic [TRANS_ID_BITS-1:0] fpu_trans_id_o, - output logic [FLEN-1:0] result_o, + output logic [CVA6Cfg.FLen-1:0] result_o, output logic fpu_valid_o, output exception_t fpu_exception_o ); @@ -36,13 +36,13 @@ module fpu_wrap import ariane_pkg::*; #( // this is a workaround // otherwise compilation might issue an error if FLEN=0 enum logic {READY, STALL} state_q, state_d; - if (FP_PRESENT) begin : fpu_gen - logic [FLEN-1:0] operand_a_i; - logic [FLEN-1:0] operand_b_i; - logic [FLEN-1:0] operand_c_i; - assign operand_a_i = fu_data_i.operand_a[FLEN-1:0]; - assign operand_b_i = fu_data_i.operand_b[FLEN-1:0]; - assign operand_c_i = fu_data_i.imm[FLEN-1:0]; + if (CVA6Cfg.FpPresent) begin : fpu_gen + logic [CVA6Cfg.FLen-1:0] operand_a_i; + logic [CVA6Cfg.FLen-1:0] operand_b_i; + logic [CVA6Cfg.FLen-1:0] operand_c_i; + assign operand_a_i = fu_data_i.operand_a[CVA6Cfg.FLen-1:0]; + assign operand_b_i = fu_data_i.operand_b[CVA6Cfg.FLen-1:0]; + assign operand_c_i = fu_data_i.imm[CVA6Cfg.FLen-1:0]; //----------------------------------- // FPnew config from FPnew package @@ -54,10 +54,10 @@ module fpu_wrap import ariane_pkg::*; #( // Features (enabled formats, vectors etc.) localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{ Width: unsigned'(riscv::XLEN), // parameterized using XLEN - EnableVectors: ariane_pkg::XFVEC, + EnableVectors: CVA6Cfg.XFVec, EnableNanBox: 1'b1, - FpFmtMask: {RVF, RVD, XF16, XF8, XF16ALT}, - IntFmtMask: {XFVEC && XF8, XFVEC && (XF16 || XF16ALT), 1'b1, 1'b1} + FpFmtMask: {CVA6Cfg.RVF, CVA6Cfg.RVD, CVA6Cfg.XF16, CVA6Cfg.XF8, CVA6Cfg.XF16ALT}, + IntFmtMask: {CVA6Cfg.XFVec && CVA6Cfg.XF8, CVA6Cfg.XFVec && (CVA6Cfg.XF16 || CVA6Cfg.XF16ALT), 1'b1, 1'b1} }; // Implementation (number of registers etc) @@ -81,9 +81,9 @@ module fpu_wrap import ariane_pkg::*; #( //------------------------------------------------- // Inputs to the FPU and protocol inversion buffer //------------------------------------------------- - logic [FLEN-1:0] operand_a_d, operand_a_q, operand_a; - logic [FLEN-1:0] operand_b_d, operand_b_q, operand_b; - logic [FLEN-1:0] operand_c_d, operand_c_q, operand_c; + logic [CVA6Cfg.FLen-1:0] operand_a_d, operand_a_q, operand_a; + logic [CVA6Cfg.FLen-1:0] operand_b_d, operand_b_q, operand_b; + logic [CVA6Cfg.FLen-1:0] operand_c_d, operand_c_q, operand_c; logic [OPBITS-1:0] fpu_op_d, fpu_op_q, fpu_op; logic fpu_op_mod_d, fpu_op_mod_q, fpu_op_mod; logic [FMTBITS-1:0] fpu_srcfmt_d, fpu_srcfmt_q, fpu_srcfmt; @@ -395,18 +395,18 @@ module fpu_wrap import ariane_pkg::*; #( if (fpu_vec_op_d && vec_replication) begin if (replicate_c) begin unique case (fpu_dstfmt_d) - fpnew_pkg::FP32: operand_c_d = RVD ? {2{operand_c_i[31:0]}} : operand_c_i; + fpnew_pkg::FP32: operand_c_d = CVA6Cfg.RVD ? {2{operand_c_i[31:0]}} : operand_c_i; fpnew_pkg::FP16, - fpnew_pkg::FP16ALT: operand_c_d = RVD ? {4{operand_c_i[15:0]}} : {2{operand_c_i[15:0]}}; - fpnew_pkg::FP8: operand_c_d = RVD ? {8{operand_c_i[7:0]}} : {4{operand_c_i[7:0]}}; + fpnew_pkg::FP16ALT: operand_c_d = CVA6Cfg.RVD ? {4{operand_c_i[15:0]}} : {2{operand_c_i[15:0]}}; + fpnew_pkg::FP8: operand_c_d = CVA6Cfg.RVD ? {8{operand_c_i[7:0]}} : {4{operand_c_i[7:0]}}; default: ; // Do nothing endcase // fpu_dstfmt_d end else begin unique case (fpu_dstfmt_d) - fpnew_pkg::FP32: operand_b_d = RVD ? {2{operand_b_i[31:0]}} : operand_b_i; + fpnew_pkg::FP32: operand_b_d = CVA6Cfg.RVD ? {2{operand_b_i[31:0]}} : operand_b_i; fpnew_pkg::FP16, - fpnew_pkg::FP16ALT: operand_b_d = RVD ? {4{operand_b_i[15:0]}} : {2{operand_b_i[15:0]}}; - fpnew_pkg::FP8: operand_b_d = RVD ? {8{operand_b_i[7:0]}} : {4{operand_b_i[7:0]}}; + fpnew_pkg::FP16ALT: operand_b_d = CVA6Cfg.RVD ? {4{operand_b_i[15:0]}} : {2{operand_b_i[15:0]}}; + fpnew_pkg::FP8: operand_b_d = CVA6Cfg.RVD ? {8{operand_b_i[7:0]}} : {4{operand_b_i[7:0]}}; default: ; // Do nothing endcase // fpu_dstfmt_d end @@ -508,7 +508,7 @@ module fpu_wrap import ariane_pkg::*; #( assign fpu_tag = use_hold ? fpu_tag_q : fpu_tag_d; // Consolidate operands - logic [2:0][FLEN-1:0] fpu_operands; + logic [2:0][CVA6Cfg.FLen-1:0] fpu_operands; assign fpu_operands[0] = operand_a; assign fpu_operands[1] = operand_b; diff --git a/core/frontend/bht.sv b/core/frontend/bht.sv index 0c4f1c1073..88bd9585ed 100644 --- a/core/frontend/bht.sv +++ b/core/frontend/bht.sv @@ -19,7 +19,7 @@ // branch history table - 2 bit saturation counter module bht #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned NR_ENTRIES = 1024 )( input logic clk_i, @@ -32,12 +32,12 @@ module bht #( output ariane_pkg::bht_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] bht_prediction_o ); // the last bit is always zero, we don't need it for indexing - localparam OFFSET = ariane_pkg::RVC == 1'b1 ? 1 : 2; + localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2; // re-shape the branch history table localparam NR_ROWS = NR_ENTRIES / ariane_pkg::INSTR_PER_FETCH; // number of bits needed to index the row localparam ROW_ADDR_BITS = $clog2(ariane_pkg::INSTR_PER_FETCH); - localparam ROW_INDEX_BITS = ariane_pkg::RVC == 1'b1 ? $clog2(ariane_pkg::INSTR_PER_FETCH) : 1; + localparam ROW_INDEX_BITS = CVA6Cfg.RVC == 1'b1 ? $clog2(ariane_pkg::INSTR_PER_FETCH) : 1; // number of bits we should use for prediction localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS; // we are not interested in all bits of the address @@ -53,7 +53,7 @@ module bht #( assign index = vpc_i[PREDICTION_BITS - 1:ROW_ADDR_BITS + OFFSET]; assign update_pc = bht_update_i.pc[PREDICTION_BITS - 1:ROW_ADDR_BITS + OFFSET]; - if (ariane_pkg::RVC) begin : gen_update_row_index + if (CVA6Cfg.RVC) begin : gen_update_row_index assign update_row_index = bht_update_i.pc[ROW_ADDR_BITS + OFFSET - 1:OFFSET]; end else begin assign update_row_index = '0; @@ -131,7 +131,7 @@ module bht #( ariane_pkg::bht_t [ariane_pkg::INSTR_PER_FETCH-1:0] bht; ariane_pkg::bht_t [ariane_pkg::INSTR_PER_FETCH-1:0] bht_updated; - if (ariane_pkg::RVC) begin : gen_row_index + if (CVA6Cfg.RVC) begin : gen_row_index assign row_index = vpc_i[ROW_ADDR_BITS + OFFSET - 1:OFFSET]; end else begin assign row_index = '0; diff --git a/core/frontend/btb.sv b/core/frontend/btb.sv index 8ca32753bb..54f458c73d 100644 --- a/core/frontend/btb.sv +++ b/core/frontend/btb.sv @@ -26,7 +26,7 @@ // // branch target buffer module btb #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int NR_ENTRIES = 8 )( input logic clk_i, // Clock @@ -39,12 +39,12 @@ module btb #( output ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] btb_prediction_o // prediction from btb ); // the last bit is always zero, we don't need it for indexing - localparam OFFSET = ariane_pkg::RVC == 1'b1 ? 1 : 2; + localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2; // re-shape the branch history table localparam NR_ROWS = NR_ENTRIES / ariane_pkg::INSTR_PER_FETCH; // number of bits needed to index the row localparam ROW_ADDR_BITS = $clog2(ariane_pkg::INSTR_PER_FETCH); - localparam ROW_INDEX_BITS = ariane_pkg::RVC == 1'b1 ? $clog2(ariane_pkg::INSTR_PER_FETCH) : 1; + localparam ROW_INDEX_BITS = CVA6Cfg.RVC == 1'b1 ? $clog2(ariane_pkg::INSTR_PER_FETCH) : 1; // number of bits we should use for prediction localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS; // prevent aliasing to degrade performance @@ -60,7 +60,7 @@ module btb #( assign index = vpc_i[PREDICTION_BITS - 1:ROW_ADDR_BITS + OFFSET]; assign update_pc = btb_update_i.pc[PREDICTION_BITS - 1:ROW_ADDR_BITS + OFFSET]; - if (ariane_pkg::RVC) begin : gen_update_row_index + if (CVA6Cfg.RVC) begin : gen_update_row_index assign update_row_index = btb_update_i.pc[ROW_ADDR_BITS + OFFSET - 1:OFFSET]; end else begin assign update_row_index = '0; diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 996219891d..399e271ad6 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -16,7 +16,7 @@ // change request from the back-end and does branch prediction. module frontend import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig ) ( input logic clk_i, // Clock @@ -70,7 +70,7 @@ module frontend import ariane_pkg::*; #( // shift amount logic [$clog2(ariane_pkg::INSTR_PER_FETCH)-1:0] shamt; // address will always be 16 bit aligned, make this explicit here - if (ariane_pkg::RVC) begin : gen_shamt + if (CVA6Cfg.RVC) begin : gen_shamt assign shamt = icache_dreq_i.vaddr[$clog2(ariane_pkg::INSTR_PER_FETCH):1]; end else begin assign shamt = 1'b0; @@ -133,7 +133,7 @@ module frontend import ariane_pkg::*; #( // select the right branch prediction result // in case we are serving an unaligned instruction in instr[0] we need to take // the prediction we saved from the previous fetch - if (ariane_pkg::RVC) begin : gen_btb_prediction_shifted + if (CVA6Cfg.RVC) begin : gen_btb_prediction_shifted assign bht_prediction_shifted[0] = (serving_unaligned) ? bht_q : bht_prediction[addr[0][$clog2(INSTR_PER_FETCH):1]]; assign btb_prediction_shifted[0] = (serving_unaligned) ? btb_q : btb_prediction[addr[0][$clog2(INSTR_PER_FETCH):1]]; @@ -400,6 +400,7 @@ module frontend import ariane_pkg::*; #( assign ras_predict = '0; end else begin : ras_gen ras #( + .CVA6Cfg ( CVA6Cfg ), .DEPTH ( ArianeCfg.RASDepth ) ) i_ras ( .clk_i, @@ -421,6 +422,7 @@ module frontend import ariane_pkg::*; #( assign btb_prediction = '0; end else begin : btb_gen btb #( + .CVA6Cfg ( CVA6Cfg ), .NR_ENTRIES ( ArianeCfg.BTBEntries ) ) i_btb ( .clk_i, @@ -437,6 +439,7 @@ module frontend import ariane_pkg::*; #( assign bht_prediction = '0; end else begin : bht_gen bht #( + .CVA6Cfg ( CVA6Cfg ), .NR_ENTRIES ( ArianeCfg.BHTEntries ) ) i_bht ( .clk_i, @@ -452,7 +455,9 @@ module frontend import ariane_pkg::*; #( // we need to inspect up to INSTR_PER_FETCH instructions for branches // and jumps for (genvar i = 0; i < INSTR_PER_FETCH; i++) begin : gen_instr_scan - instr_scan i_instr_scan ( + instr_scan #( + .CVA6Cfg ( CVA6Cfg ) + ) i_instr_scan ( .instr_i ( instr[i] ), .rvi_return_o ( rvi_return[i] ), .rvi_call_o ( rvi_call[i] ), @@ -470,7 +475,9 @@ module frontend import ariane_pkg::*; #( ); end - instr_queue i_instr_queue ( + instr_queue #( + .CVA6Cfg ( CVA6Cfg ) + ) i_instr_queue ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .flush_i ( flush_i ), diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index 7b1e6ea735..ae86e94068 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -44,7 +44,7 @@ // can not be pushed at once. module instr_queue import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, input logic rst_ni, diff --git a/core/frontend/instr_scan.sv b/core/frontend/instr_scan.sv index e24ba3b5d8..08ebb216cd 100644 --- a/core/frontend/instr_scan.sv +++ b/core/frontend/instr_scan.sv @@ -16,7 +16,7 @@ // Instruction Scanner // ------------------------------ module instr_scan #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic [31:0] instr_i, // expect aligned instruction, compressed or not output logic rvi_return_o, diff --git a/core/frontend/ras.sv b/core/frontend/ras.sv index b66ea1aae3..36c85dfef4 100644 --- a/core/frontend/ras.sv +++ b/core/frontend/ras.sv @@ -15,7 +15,7 @@ // return address stack module ras #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned DEPTH = 2 )( input logic clk_i, diff --git a/core/id_stage.sv b/core/id_stage.sv index 340930a3a1..456b244113 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -14,7 +14,7 @@ // issue and read operands. module id_stage #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, input logic rst_ni, @@ -57,7 +57,7 @@ module id_stage #( logic [31:0] instruction; logic is_compressed; - if (ariane_pkg::RVC) begin + if (CVA6Cfg.RVC) begin // --------------------------------------------------------- // 1. Check if they are compressed and expand in case they are // --------------------------------------------------------- diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index d1c127287d..d61d98cb6a 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -25,33 +25,6 @@ package ariane_pkg; - // --------------- - // Global Config - // --------------- - // This is the new user config interface system. If you need to parameterize something - // within Ariane add a field here and assign a default value to the config. Please make - // sure to add a propper parameter check to the `check_cfg` function. - localparam int unsigned ILEN = 32; - localparam int unsigned NRET = 1; - - typedef struct packed { - int unsigned NrCommitPorts; - int unsigned IsRVFI; - int unsigned AxiAddrWidth; - int unsigned AxiDataWidth; - int unsigned AxiIdWidth; - int unsigned AxiUserWidth; - } cva6_cfg_t; - - localparam cva6_cfg_t cva6_cfg_empty = { - unsigned'(0), // NrCommitPorts - unsigned'(0), // IsRVFI - unsigned'(0), // AxiAddrWidth - unsigned'(0), // AxiDataWidth - unsigned'(0), // AxiIdWidth - unsigned'(0) // AxiUserWidth - }; - localparam NrMaxRules = 16; typedef struct packed { int RASDepth; @@ -175,27 +148,6 @@ package ariane_pkg; localparam bit RVC = cva6_config_pkg::CVA6ConfigCExtEn; // Is C extension configuration -`ifdef PITON_ARIANE - // Floating-point extensions configuration - localparam bit RVF = riscv::IS_XLEN64; // Is F extension enabled - localparam bit RVD = riscv::IS_XLEN64; // Is D extension enabled -`else - // Floating-point extensions configuration - localparam bit RVF = (riscv::IS_XLEN64 | riscv::IS_XLEN32) & riscv::FPU_EN; // Is F extension enabled for both 32 Bit and 64 bit CPU - localparam bit RVD = (riscv::IS_XLEN64 ? 1:0) & riscv::FPU_EN; // Is D extension enabled for only 64 bit CPU -`endif - localparam bit RVA = cva6_config_pkg::CVA6ConfigAExtEn; // Is A extension enabled - localparam bit RVV = cva6_config_pkg::CVA6ConfigVExtEn; - - // Is the accelerator enabled? - localparam bit ENABLE_ACCELERATOR = RVV; // Currently only used by V extension (Ara) - - // Transprecision floating-point extensions configuration - localparam bit XF16 = cva6_config_pkg::CVA6ConfigF16En | RVV; // Is half-precision float extension (Xf16) enabled - localparam bit XF16ALT = cva6_config_pkg::CVA6ConfigF16AltEn; // Is alternative half-precision float extension (Xf16alt) enabled - localparam bit XF8 = cva6_config_pkg::CVA6ConfigF8En; // Is quarter-precision float extension (Xf8) enabled - localparam bit XFVEC = cva6_config_pkg::CVA6ConfigFVecEn; // Is vectorial float extension (Xfvec) enabled - // Transprecision float unit localparam int unsigned LAT_COMP_FP32 = 'd2; localparam int unsigned LAT_COMP_FP64 = 'd3; @@ -206,54 +158,14 @@ package ariane_pkg; localparam int unsigned LAT_NONCOMP = 'd1; localparam int unsigned LAT_CONV = 'd2; - // -------------------------------------- - // vvvv Don't change these by hand! vvvv - localparam bit FP_PRESENT = RVF | RVD | XF16 | XF16ALT | XF8; - - // Length of widest floating-point format - localparam FLEN = RVD ? 64 : // D ext. - RVF ? 32 : // F ext. - XF16 ? 16 : // Xf16 ext. - XF16ALT ? 16 : // Xf16alt ext. - XF8 ? 8 : // Xf8 ext. - 1; // Unused in case of no FP - - localparam bit NSX = XF16 | XF16ALT | XF8 | XFVEC; // Are non-standard extensions present? - - localparam bit RVFVEC = RVF & XFVEC & FLEN>32; // FP32 vectors available if vectors and larger fmt enabled - localparam bit XF16VEC = XF16 & XFVEC & FLEN>16; // FP16 vectors available if vectors and larger fmt enabled - localparam bit XF16ALTVEC = XF16ALT & XFVEC & FLEN>16; // FP16ALT vectors available if vectors and larger fmt enabled - localparam bit XF8VEC = XF8 & XFVEC & FLEN>8; // FP8 vectors available if vectors and larger fmt enabled - // ^^^^ until here ^^^^ - // --------------------- - localparam riscv::xlen_t OPENHWGROUP_MVENDORID = {{riscv::XLEN-32{1'b0}}, 32'h0602}; localparam riscv::xlen_t ARIANE_MARCHID = {{riscv::XLEN-32{1'b0}}, 32'd3}; - localparam riscv::xlen_t ISA_CODE = (riscv::XLEN'(RVA) << 0) // A - Atomic Instructions extension - | (riscv::XLEN'(RVC) << 2) // C - Compressed extension - | (riscv::XLEN'(RVD) << 3) // D - Double precsision floating-point extension - | (riscv::XLEN'(RVF) << 5) // F - Single precsision floating-point extension - | (riscv::XLEN'(1 ) << 8) // I - RV32I/64I/128I base ISA - | (riscv::XLEN'(1 ) << 12) // M - Integer Multiply/Divide extension - | (riscv::XLEN'(0 ) << 13) // N - User level interrupts supported - | (riscv::XLEN'(1 ) << 18) // S - Supervisor mode implemented - | (riscv::XLEN'(1 ) << 20) // U - User mode implemented - | (riscv::XLEN'(RVV) << 21) // V - Vector extension - | (riscv::XLEN'(NSX) << 23) // X - Non-standard extensions present - | ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN-2); // MXL - // 32 registers + 1 bit for re-naming = 6 localparam REG_ADDR_SIZE = 6; - localparam bit CVXIF_PRESENT = cva6_config_pkg::CVA6ConfigCvxifEn; - - // when cvx interface or the accelerator port is present, use an additional writeback port - localparam NR_WB_PORTS = (CVXIF_PRESENT || ENABLE_ACCELERATOR) ? 5 : 4; - // Read ports for general purpose register files localparam NR_RGPR_PORTS = 2; - typedef logic [(NR_RGPR_PORTS == 3 ? riscv::XLEN : FLEN)-1:0] rs3_len_t; // static debug hartinfo localparam ariane_dm_pkg::hartinfo_t DebugHartInfo = '{ @@ -595,8 +507,14 @@ package ariane_pkg; // ------------------------------- // Extract Src/Dst FP Reg from Op // ------------------------------- + // function used in instr_trace svh + // is_rs1_fpr function is kept to allow cva6 compilation with instr_trace feature function automatic logic is_rs1_fpr (input fu_op op); - if (FP_PRESENT) begin // makes function static for non-fp case + return is_rs1_fpr_cfg (op, 1); + endfunction + + function automatic logic is_rs1_fpr_cfg (input fu_op op, input bit FpPresent); + if (FpPresent) begin unique case (op) inside [FMUL:FNMADD], // Computational Operations (except ADD/SUB) FCVT_F2I, // Float-Int Casts @@ -609,12 +527,19 @@ package ariane_pkg; ACCEL_OP_FS1 : return 1'b1; // Accelerator instructions default : return 1'b0; // all other ops endcase - end else + end else begin return 1'b0; + end endfunction + // function used in instr_trace svh + // is_rs2_fpr function is kept to allow cva6 compilation with instr_trace feature function automatic logic is_rs2_fpr (input fu_op op); - if (FP_PRESENT) begin // makes function static for non-fp case + return is_rs2_fpr_cfg (op, 1); + endfunction + + function automatic logic is_rs2_fpr_cfg (input fu_op op, input bit FpPresent); + if (FpPresent) begin unique case (op) inside [FSD:FSB], // FP Stores [FADD:FMIN_MAX], // Computational Operations (no sqrt) @@ -625,25 +550,39 @@ package ariane_pkg; [VFMIN:VFCPKCD_D] : return 1'b1; // Additional Vectorial FP ops default : return 1'b0; // all other ops endcase - end else + end else begin return 1'b0; + end endfunction + // function used in instr_trace svh + // is_imm_fpr function is kept to allow cva6 compilation with instr_trace feature // ternary operations encode the rs3 address in the imm field, also add/sub function automatic logic is_imm_fpr (input fu_op op); - if (FP_PRESENT) begin // makes function static for non-fp case + return is_imm_fpr_cfg (op, 1); + endfunction + + function automatic logic is_imm_fpr_cfg (input fu_op op, input bit FpPresent); + if (FpPresent) begin unique case (op) inside [FADD:FSUB], // ADD/SUB need inputs as Operand B/C [FMADD:FNMADD], // Fused Computational Operations [VFCPKAB_S:VFCPKCD_D] : return 1'b1; // Vectorial FP cast and pack ops default : return 1'b0; // all other ops endcase - end else + end else begin return 1'b0; + end endfunction + // function used in instr_trace svh + // is_rd_fpr function is kept to allow cva6 compilation with instr_trace feature function automatic logic is_rd_fpr (input fu_op op); - if (FP_PRESENT) begin // makes function static for non-fp case + return is_rd_fpr_cfg (op, 1); + endfunction + + function automatic logic is_rd_fpr_cfg (input fu_op op, input bit FpPresent); + if (FpPresent) begin unique case (op) inside [FLD:FLB], // FP Loads [FADD:FNMADD], // Computational Operations @@ -656,8 +595,9 @@ package ariane_pkg; ACCEL_OP_FD : return 1'b1; // Accelerator instructions default : return 1'b0; // all other ops endcase - end else + end else begin return 1'b0; + end endfunction function automatic logic is_amo (fu_op op); diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv new file mode 100644 index 0000000000..5ae7e88d22 --- /dev/null +++ b/core/include/config_pkg.sv @@ -0,0 +1,109 @@ +// Copyright 2023 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + +package config_pkg; + + // --------------- + // Global Config + // --------------- + localparam int unsigned ILEN = 32; + localparam int unsigned NRET = 1; + + typedef struct packed { + int unsigned NrCommitPorts; + int unsigned AxiAddrWidth; + int unsigned AxiDataWidth; + int unsigned AxiIdWidth; + int unsigned AxiUserWidth; + bit FpuEn; + bit XF16; + bit XF16ALT; + bit XF8; + bit RVA; + bit RVV; + bit RVC; + bit XFVec; + bit CvxifEn; + // Calculated + bit RVF; + bit RVD; + bit FpPresent; + bit NSX; + int unsigned FLen; + bit RVFVec; + bit XF16Vec; + bit XF16ALTVec; + bit XF8Vec; + int unsigned NrRgprPorts; + int unsigned NrWbPorts; + bit EnableAccelerator; + } cva6_cfg_t; + + localparam cva6_cfg_t cva6_cfg_default = { + unsigned'(1), // NrCommitPorts + unsigned'(64), // AxiAddrWidth + unsigned'(64), // AxiDataWidth + unsigned'(4), // AxiIdWidth + unsigned'(32), // AxiUserWidth + bit'(0), // FpuEn + bit'(0), // XF16 + bit'(0), // XF16ALT + bit'(0), // XF8 + bit'(0), // RVA + bit'(0), // RVV + bit'(1), // RVC + bit'(0), // XFVec + bit'(1), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + + localparam cva6_cfg_t cva6_cfg_empty = { + unsigned'(0), // NrCommitPorts + unsigned'(0), // AxiAddrWidth + unsigned'(0), // AxiDataWidth + unsigned'(0), // AxiIdWidth + unsigned'(0), // AxiUserWidth + bit'(0), // FpuEn + bit'(0), // XF16 + bit'(0), // XF16ALT + bit'(0), // XF8 + bit'(0), // RVA + bit'(0), // RVV + bit'(0), // RVC + bit'(0), // XFVec + bit'(0), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + + +endpackage diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index b785557bf6..32645f90b7 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -76,4 +76,34 @@ package cva6_config_pkg; localparam CVA6ConfigRvfiTrace = 1; + localparam config_pkg::cva6_cfg_t cva6_cfg = { + unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth + bit'(CVA6ConfigFpuEn), // FpuEn + bit'(CVA6ConfigF16En), // XF16 + bit'(CVA6ConfigF16AltEn), // XF16ALT + bit'(CVA6ConfigF8En), // XF8 + bit'(CVA6ConfigAExtEn), // RVA + bit'(CVA6ConfigVExtEn), // RVV + bit'(CVA6ConfigCExtEn), // RVC + bit'(CVA6ConfigFVecEn), // XFVec + bit'(CVA6ConfigCvxifEn), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + endpackage diff --git a/core/include/cv32a6_embedded_config_pkg.sv b/core/include/cv32a6_embedded_config_pkg.sv index 6c6f52d254..d5066a1ad1 100644 --- a/core/include/cv32a6_embedded_config_pkg.sv +++ b/core/include/cv32a6_embedded_config_pkg.sv @@ -75,4 +75,34 @@ package cva6_config_pkg; localparam CVA6ConfigRvfiTrace = 1; + localparam config_pkg::cva6_cfg_t cva6_cfg = { + unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth + bit'(CVA6ConfigFpuEn), // FpuEn + bit'(CVA6ConfigF16En), // XF16 + bit'(CVA6ConfigF16AltEn), // XF16ALT + bit'(CVA6ConfigF8En), // XF8 + bit'(CVA6ConfigAExtEn), // RVA + bit'(CVA6ConfigVExtEn), // RVV + bit'(CVA6ConfigCExtEn), // RVC + bit'(CVA6ConfigFVecEn), // XFVec + bit'(CVA6ConfigCvxifEn), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + endpackage diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index a68f4434e2..7e85052e88 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -76,4 +76,34 @@ package cva6_config_pkg; localparam CVA6ConfigRvfiTrace = 1; + localparam config_pkg::cva6_cfg_t cva6_cfg = { + unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth + bit'(CVA6ConfigFpuEn), // FpuEn + bit'(CVA6ConfigF16En), // XF16 + bit'(CVA6ConfigF16AltEn), // XF16ALT + bit'(CVA6ConfigF8En), // XF8 + bit'(CVA6ConfigAExtEn), // RVA + bit'(CVA6ConfigVExtEn), // RVV + bit'(CVA6ConfigCExtEn), // RVC + bit'(CVA6ConfigFVecEn), // XFVec + bit'(CVA6ConfigCvxifEn), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + endpackage diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 665992f0d8..7da2cc3011 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -76,4 +76,34 @@ package cva6_config_pkg; localparam CVA6ConfigRvfiTrace = 1; + localparam config_pkg::cva6_cfg_t cva6_cfg = { + unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth + bit'(CVA6ConfigFpuEn), // FpuEn + bit'(CVA6ConfigF16En), // XF16 + bit'(CVA6ConfigF16AltEn), // XF16ALT + bit'(CVA6ConfigF8En), // XF8 + bit'(CVA6ConfigAExtEn), // RVA + bit'(CVA6ConfigVExtEn), // RVV + bit'(CVA6ConfigCExtEn), // RVC + bit'(CVA6ConfigFVecEn), // XFVec + bit'(CVA6ConfigCvxifEn), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + endpackage diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 08eddf066c..92a2a17dd9 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -76,4 +76,34 @@ package cva6_config_pkg; localparam CVA6ConfigRvfiTrace = 1; + localparam config_pkg::cva6_cfg_t cva6_cfg = { + unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth + bit'(CVA6ConfigFpuEn), // FpuEn + bit'(CVA6ConfigF16En), // XF16 + bit'(CVA6ConfigF16AltEn), // XF16ALT + bit'(CVA6ConfigF8En), // XF8 + bit'(CVA6ConfigAExtEn), // RVA + bit'(CVA6ConfigVExtEn), // RVV + bit'(CVA6ConfigCExtEn), // RVC + bit'(CVA6ConfigFVecEn), // XFVec + bit'(CVA6ConfigCvxifEn), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + endpackage diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index a1dda130ba..c9426ff0bb 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -76,4 +76,34 @@ package cva6_config_pkg; localparam CVA6ConfigRvfiTrace = 1; + localparam config_pkg::cva6_cfg_t cva6_cfg = { + unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth + bit'(CVA6ConfigFpuEn), // FpuEn + bit'(CVA6ConfigF16En), // XF16 + bit'(CVA6ConfigF16AltEn), // XF16ALT + bit'(CVA6ConfigF8En), // XF8 + bit'(CVA6ConfigAExtEn), // RVA + bit'(CVA6ConfigVExtEn), // RVV + bit'(CVA6ConfigCExtEn), // RVC + bit'(CVA6ConfigFVecEn), // XFVec + bit'(CVA6ConfigCvxifEn), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + endpackage diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index 58e0c640ff..e2237bd59d 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -76,4 +76,34 @@ package cva6_config_pkg; localparam CVA6ConfigRvfiTrace = 1; + localparam config_pkg::cva6_cfg_t cva6_cfg = { + unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth + bit'(CVA6ConfigFpuEn), // FpuEn + bit'(CVA6ConfigF16En), // XF16 + bit'(CVA6ConfigF16AltEn), // XF16ALT + bit'(CVA6ConfigF8En), // XF8 + bit'(CVA6ConfigAExtEn), // RVA + bit'(CVA6ConfigVExtEn), // RVV + bit'(CVA6ConfigCExtEn), // RVC + bit'(CVA6ConfigFVecEn), // XFVec + bit'(CVA6ConfigCvxifEn), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + endpackage diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index f7c7cdf218..2c31bd0e38 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -76,4 +76,34 @@ package cva6_config_pkg; localparam CVA6ConfigRvfiTrace = 1; + localparam config_pkg::cva6_cfg_t cva6_cfg = { + unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth + bit'(CVA6ConfigFpuEn), // FpuEn + bit'(CVA6ConfigF16En), // XF16 + bit'(CVA6ConfigF16AltEn), // XF16ALT + bit'(CVA6ConfigF8En), // XF8 + bit'(CVA6ConfigAExtEn), // RVA + bit'(CVA6ConfigVExtEn), // RVV + bit'(CVA6ConfigCExtEn), // RVC + bit'(CVA6ConfigFVecEn), // XFVec + bit'(CVA6ConfigCvxifEn), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + endpackage diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index f03e71be26..c3abdca58e 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -76,4 +76,34 @@ package cva6_config_pkg; localparam CVA6ConfigRvfiTrace = 1; + localparam config_pkg::cva6_cfg_t cva6_cfg = { + unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth + bit'(CVA6ConfigFpuEn), // FpuEn + bit'(CVA6ConfigF16En), // XF16 + bit'(CVA6ConfigF16AltEn), // XF16ALT + bit'(CVA6ConfigF8En), // XF8 + bit'(CVA6ConfigAExtEn), // RVA + bit'(CVA6ConfigVExtEn), // RVV + bit'(CVA6ConfigCExtEn), // RVC + bit'(CVA6ConfigFVecEn), // XFVec + bit'(CVA6ConfigCvxifEn), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + endpackage diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 2889a01890..e89904b546 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -76,4 +76,34 @@ package cva6_config_pkg; localparam CVA6ConfigRvfiTrace = 1; + localparam config_pkg::cva6_cfg_t cva6_cfg = { + unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth + bit'(CVA6ConfigFpuEn), // FpuEn + bit'(CVA6ConfigF16En), // XF16 + bit'(CVA6ConfigF16AltEn), // XF16ALT + bit'(CVA6ConfigF8En), // XF8 + bit'(CVA6ConfigAExtEn), // RVA + bit'(CVA6ConfigVExtEn), // RVV + bit'(CVA6ConfigCExtEn), // RVC + bit'(CVA6ConfigFVecEn), // XFVec + bit'(CVA6ConfigCvxifEn), // CvxifEn + // Extended + bit'(0), // RVF + bit'(0), // RVD + bit'(0), // FpPresent + bit'(0), // NSX + unsigned'(0), // FLen + bit'(0), // RVFVec + bit'(0), // XF16Vec + bit'(0), // XF16ALTVec + bit'(0), // XF8Vec + unsigned'(0), // NrRgprPorts + unsigned'(0), // NrWbPorts + bit'(0) // EnableAccelerator + } ; + endpackage diff --git a/core/instr_realign.sv b/core/instr_realign.sv index 58a7d210d5..72e5dfbfb3 100644 --- a/core/instr_realign.sv +++ b/core/instr_realign.sv @@ -21,7 +21,7 @@ module instr_realign import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, input logic rst_ni, diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index 8801dd284f..75a883ffd0 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -15,7 +15,8 @@ module issue_read_operands import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type rs3_len_t = logic )( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -130,8 +131,8 @@ module issue_read_operands import ariane_pkg::*; #( assign fpu_valid_o = fpu_valid_q; assign fpu_fmt_o = fpu_fmt_q; assign fpu_rm_o = fpu_rm_q; - assign cvxif_valid_o = CVXIF_PRESENT ? cvxif_valid_q : '0; - assign cvxif_off_instr_o = CVXIF_PRESENT ? cvxif_off_instr_q : '0; + assign cvxif_valid_o = CVA6Cfg.CvxifEn ? cvxif_valid_q : '0; + assign cvxif_off_instr_o = CVA6Cfg.CvxifEn ? cvxif_off_instr_q : '0; assign stall_issue_o = stall; // --------------- // Issue Stage @@ -176,22 +177,22 @@ module issue_read_operands import ariane_pkg::*; #( // as this is an immediate we do not have to wait on anything here // 1. check if the source registers are clobbered --> check appropriate clobber list (gpr/fpr) // 2. poll the scoreboard - if (!issue_instr_i.use_zimm && (is_rs1_fpr(issue_instr_i.op) ? rd_clobber_fpr_i[issue_instr_i.rs1] != NONE + if (!issue_instr_i.use_zimm && (is_rs1_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? rd_clobber_fpr_i[issue_instr_i.rs1] != NONE : rd_clobber_gpr_i[issue_instr_i.rs1] != NONE)) begin // check if the clobbering instruction is not a CSR instruction, CSR instructions can only // be fetched through the register file since they can't be forwarded // if the operand is available, forward it. CSRs don't write to/from FPR - if (rs1_valid_i && (is_rs1_fpr(issue_instr_i.op) ? 1'b1 : ((rd_clobber_gpr_i[issue_instr_i.rs1] != CSR) || (issue_instr_i.op == SFENCE_VMA)))) begin + if (rs1_valid_i && (is_rs1_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? 1'b1 : ((rd_clobber_gpr_i[issue_instr_i.rs1] != CSR) || (issue_instr_i.op == SFENCE_VMA)))) begin forward_rs1 = 1'b1; end else begin // the operand is not available -> stall stall = 1'b1; end end - if (is_rs2_fpr(issue_instr_i.op) ? rd_clobber_fpr_i[issue_instr_i.rs2] != NONE - : rd_clobber_gpr_i[issue_instr_i.rs2] != NONE) begin + if (is_rs2_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? rd_clobber_fpr_i[issue_instr_i.rs2] != NONE + : rd_clobber_gpr_i[issue_instr_i.rs2] != NONE) begin // if the operand is available, forward it. CSRs don't write to/from FPR - if (rs2_valid_i && (is_rs2_fpr(issue_instr_i.op) ? 1'b1 : ( (rd_clobber_gpr_i[issue_instr_i.rs2] != CSR) || (issue_instr_i.op == SFENCE_VMA)))) begin + if (rs2_valid_i && (is_rs2_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? 1'b1 : ( (rd_clobber_gpr_i[issue_instr_i.rs2] != CSR) || (issue_instr_i.op == SFENCE_VMA)))) begin forward_rs2 = 1'b1; end else begin // the operand is not available -> stall stall = 1'b1; @@ -199,8 +200,8 @@ module issue_read_operands import ariane_pkg::*; #( end // Only check clobbered gpr for OFFLOADED instruction - if (is_imm_fpr(issue_instr_i.op) ? rd_clobber_fpr_i[issue_instr_i.result[REG_ADDR_SIZE-1:0]] != NONE - : issue_instr_i.op == OFFLOAD && NR_RGPR_PORTS == 3 ? rd_clobber_gpr_i[issue_instr_i.result[REG_ADDR_SIZE-1:0]] != NONE : 0) begin + if (is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? rd_clobber_fpr_i[issue_instr_i.result[REG_ADDR_SIZE-1:0]] != NONE + : issue_instr_i.op == OFFLOAD && CVA6Cfg.NrRgprPorts == 3 ? rd_clobber_gpr_i[issue_instr_i.result[REG_ADDR_SIZE-1:0]] != NONE : 0) begin // if the operand is available, forward it. CSRs don't write to/from FPR so no need to check if (rs3_valid_i) begin forward_rs3 = 1'b1; @@ -217,11 +218,11 @@ module issue_read_operands import ariane_pkg::*; #( operand_b_n = operand_b_regfile; // immediates are the third operands in the store case // for FP operations, the imm field can also be the third operand from the regfile - if (NR_RGPR_PORTS == 3) begin - imm_n = is_imm_fpr(issue_instr_i.op) ? {{riscv::XLEN-FLEN{1'b0}}, operand_c_regfile} : + if (CVA6Cfg.NrRgprPorts == 3) begin + imm_n = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, operand_c_regfile} : issue_instr_i.op == OFFLOAD ? operand_c_regfile : issue_instr_i.result; end else begin - imm_n = is_imm_fpr(issue_instr_i.op) ? {{riscv::XLEN-FLEN{1'b0}}, operand_c_regfile} : issue_instr_i.result; + imm_n = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, operand_c_regfile} : issue_instr_i.result; end trans_id_n = issue_instr_i.trans_id; fu_n = issue_instr_i.fu; @@ -236,7 +237,7 @@ module issue_read_operands import ariane_pkg::*; #( end if (forward_rs3) begin - imm_n = NR_RGPR_PORTS == 3 ? rs3_i : {{riscv::XLEN-FLEN{1'b0}}, rs3_i};; + imm_n = CVA6Cfg.NrRgprPorts == 3 ? rs3_i : {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, rs3_i};; end // use the PC as operand a @@ -251,7 +252,7 @@ module issue_read_operands import ariane_pkg::*; #( end // or is it an immediate (including PC), this is not the case for a store, control flow, and accelerator instructions // also make sure operand B is not already used as an FP operand - if (issue_instr_i.use_imm && (issue_instr_i.fu != STORE) && (issue_instr_i.fu != CTRL_FLOW) && (issue_instr_i.fu != ACCEL) && !is_rs2_fpr(issue_instr_i.op)) begin + if (issue_instr_i.use_imm && (issue_instr_i.fu != STORE) && (issue_instr_i.fu != CTRL_FLOW) && (issue_instr_i.fu != ACCEL) && !is_rs2_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent)) begin operand_b_n = issue_instr_i.result; end end @@ -323,7 +324,7 @@ module issue_read_operands import ariane_pkg::*; #( end end - if (CVXIF_PRESENT) begin + if (CVA6Cfg.CvxifEn) begin always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin cvxif_valid_q <= 1'b0; @@ -363,15 +364,15 @@ module issue_read_operands import ariane_pkg::*; #( // WAW - Write After Write Dependency Check // ----------------------------------------- // no other instruction has the same destination register -> issue the instruction - if (is_rd_fpr(issue_instr_i.op) ? (rd_clobber_fpr_i[issue_instr_i.rd] == NONE) - : (rd_clobber_gpr_i[issue_instr_i.rd] == NONE)) begin + if (ariane_pkg::is_rd_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? (rd_clobber_fpr_i[issue_instr_i.rd] == NONE) + : (rd_clobber_gpr_i[issue_instr_i.rd] == NONE)) begin issue_ack_o = 1'b1; end // or check that the target destination register will be written in this cycle by the // commit stage for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++) - if (is_rd_fpr(issue_instr_i.op) ? (we_fpr_i[i] && waddr_i[i] == issue_instr_i.rd[4:0]) - : (we_gpr_i[i] && waddr_i[i] == issue_instr_i.rd[4:0])) begin + if (ariane_pkg::is_rd_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? (we_fpr_i[i] && waddr_i[i] == issue_instr_i.rd[4:0]) + : (we_gpr_i[i] && waddr_i[i] == issue_instr_i.rd[4:0])) begin issue_ack_o = 1'b1; end end @@ -398,14 +399,14 @@ module issue_read_operands import ariane_pkg::*; #( // ---------------------- // Integer Register File // ---------------------- - logic [NR_RGPR_PORTS-1:0][riscv::XLEN-1:0] rdata; - logic [NR_RGPR_PORTS-1:0][4:0] raddr_pack; + logic [CVA6Cfg.NrRgprPorts-1:0][riscv::XLEN-1:0] rdata; + logic [CVA6Cfg.NrRgprPorts-1:0][4:0] raddr_pack; // pack signals logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_pack; logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_pack; logic [CVA6Cfg.NrCommitPorts-1:0] we_pack; - assign raddr_pack = NR_RGPR_PORTS == 3 ? {issue_instr_i.result[4:0], issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]} + assign raddr_pack = CVA6Cfg.NrRgprPorts == 3 ? {issue_instr_i.result[4:0], issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]} : {issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]}; for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_write_back_port assign waddr_pack[i] = waddr_i[i]; @@ -416,7 +417,7 @@ module issue_read_operands import ariane_pkg::*; #( ariane_regfile_fpga #( .CVA6Cfg ( CVA6Cfg ), .DATA_WIDTH ( riscv::XLEN ), - .NR_READ_PORTS ( NR_RGPR_PORTS ), + .NR_READ_PORTS ( CVA6Cfg.NrRgprPorts ), .ZERO_REG_ZERO ( 1 ) ) i_ariane_regfile_fpga ( .test_en_i ( 1'b0 ), @@ -431,7 +432,7 @@ module issue_read_operands import ariane_pkg::*; #( ariane_regfile #( .CVA6Cfg ( CVA6Cfg ), .DATA_WIDTH ( riscv::XLEN ), - .NR_READ_PORTS ( NR_RGPR_PORTS ), + .NR_READ_PORTS ( CVA6Cfg.NrRgprPorts ), .ZERO_REG_ZERO ( 1 ) ) i_ariane_regfile ( .test_en_i ( 1'b0 ), @@ -447,22 +448,22 @@ module issue_read_operands import ariane_pkg::*; #( // ----------------------------- // Floating-Point Register File // ----------------------------- - logic [2:0][FLEN-1:0] fprdata; + logic [2:0][CVA6Cfg.FLen-1:0] fprdata; // pack signals logic [2:0][4:0] fp_raddr_pack; logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] fp_wdata_pack; generate - if (FP_PRESENT) begin : float_regfile_gen + if (CVA6Cfg.FpPresent) begin : float_regfile_gen assign fp_raddr_pack = {issue_instr_i.result[4:0], issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]}; for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_fp_wdata_pack - assign fp_wdata_pack[i] = {wdata_i[i][FLEN-1:0]}; + assign fp_wdata_pack[i] = {wdata_i[i][CVA6Cfg.FLen-1:0]}; end if (ariane_pkg::FPGA_EN) begin : gen_fpga_fp_regfile ariane_regfile_fpga #( .CVA6Cfg ( CVA6Cfg ), - .DATA_WIDTH ( FLEN ), + .DATA_WIDTH ( CVA6Cfg.FLen ), .NR_READ_PORTS ( 3 ), .ZERO_REG_ZERO ( 0 ) ) i_ariane_fp_regfile_fpga ( @@ -477,7 +478,7 @@ module issue_read_operands import ariane_pkg::*; #( end else begin : gen_asic_fp_regfile ariane_regfile #( .CVA6Cfg ( CVA6Cfg ), - .DATA_WIDTH ( FLEN ), + .DATA_WIDTH ( CVA6Cfg.FLen ), .NR_READ_PORTS ( 3 ), .ZERO_REG_ZERO ( 0 ) ) i_ariane_fp_regfile ( @@ -495,9 +496,9 @@ module issue_read_operands import ariane_pkg::*; #( end endgenerate - assign operand_a_regfile = is_rs1_fpr(issue_instr_i.op) ? {{riscv::XLEN-FLEN{1'b0}}, fprdata[0]} : rdata[0]; - assign operand_b_regfile = is_rs2_fpr(issue_instr_i.op) ? {{riscv::XLEN-FLEN{1'b0}}, fprdata[1]} : rdata[1]; - assign operand_c_regfile = NR_RGPR_PORTS == 3 ? (is_imm_fpr(issue_instr_i.op) ? {{riscv::XLEN-FLEN{1'b0}}, fprdata[2]} : rdata[2]) + assign operand_a_regfile = is_rs1_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[0]} : rdata[0]; + assign operand_b_regfile = is_rs2_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[1]} : rdata[1]; + assign operand_c_regfile = CVA6Cfg.NrRgprPorts == 3 ? (is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[2]} : rdata[2]) : fprdata[2]; // ---------------------- @@ -529,7 +530,7 @@ module issue_read_operands import ariane_pkg::*; #( //pragma translate_off initial begin - assert (NR_RGPR_PORTS == 2 || (NR_RGPR_PORTS == 3 && CVXIF_PRESENT)) + assert (CVA6Cfg.NrRgprPorts == 2 || (CVA6Cfg.NrRgprPorts == 3 && CVA6Cfg.CvxifEn)) else $fatal(1, "If CVXIF is enable, ariane regfile can have either 2 or 3 read ports. Else it has 2 read ports."); end diff --git a/core/issue_stage.sv b/core/issue_stage.sv index 00ddf92d7d..1aff2c20d8 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -15,9 +15,9 @@ module issue_stage import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, - parameter int unsigned NR_ENTRIES = 8, - parameter int unsigned NR_WB_PORTS = 4 + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter bit IsRVFI = bit'(0), + parameter int unsigned NR_ENTRIES = 8 )( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -68,12 +68,12 @@ module issue_stage import ariane_pkg::*; #( output logic issue_instr_hs_o, // write back port - input logic [NR_WB_PORTS-1:0][TRANS_ID_BITS-1:0] trans_id_i, - input bp_resolve_t resolved_branch_i, - input logic [NR_WB_PORTS-1:0][riscv::XLEN-1:0] wbdata_i, - input exception_t [NR_WB_PORTS-1:0] ex_ex_i, // exception from execute stage or CVXIF offloaded instruction - input logic [NR_WB_PORTS-1:0] wt_valid_i, - input logic x_we_i, + input logic [CVA6Cfg.NrWbPorts-1:0][TRANS_ID_BITS-1:0] trans_id_i, + input bp_resolve_t resolved_branch_i, + input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, + input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_ex_i, // exception from execute stage or CVXIF offloaded instruction + input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i, + input logic x_we_i, // commit port input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i, @@ -95,6 +95,8 @@ module issue_stage import ariane_pkg::*; #( // --------------------------------------------------- // Scoreboard (SB) <-> Issue and Read Operands (IRO) // --------------------------------------------------- + typedef logic [(CVA6Cfg.NrRgprPorts == 3 ? riscv::XLEN : CVA6Cfg.FLen)-1:0] rs3_len_t; + fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_gpr_sb_iro; fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_fpr_sb_iro; @@ -150,8 +152,9 @@ module issue_stage import ariane_pkg::*; #( // --------------------------------------------------------- scoreboard #( .CVA6Cfg ( CVA6Cfg ), - .NR_ENTRIES (NR_ENTRIES ), - .NR_WB_PORTS(NR_WB_PORTS) + .IsRVFI ( IsRVFI ), + .rs3_len_t ( rs3_len_t ), + .NR_ENTRIES (NR_ENTRIES ) ) i_scoreboard ( .sb_full_o ( sb_full_o ), .unresolved_branch_i ( 1'b0 ), @@ -191,7 +194,8 @@ module issue_stage import ariane_pkg::*; #( // 3. Issue instruction and read operand, also commit // --------------------------------------------------------- issue_read_operands #( - .CVA6Cfg ( CVA6Cfg ) + .CVA6Cfg ( CVA6Cfg ), + .rs3_len_t ( rs3_len_t ) )i_issue_read_operands ( .flush_i ( flush_unissued_instr_i ), .issue_instr_i ( issue_instr_sb_iro ), diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 73efd72b9e..d291c76f17 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -14,7 +14,7 @@ module load_store_unit import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned ASID_WIDTH = 1, parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig )( diff --git a/core/load_unit.sv b/core/load_unit.sv index 8ab3d2a365..6ad02fd05c 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -14,7 +14,7 @@ // Description: Load Unit, takes care of all load requests module load_unit import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig ) ( input logic clk_i, // Clock diff --git a/core/lsu_bypass.sv b/core/lsu_bypass.sv index 349916afee..217df7edfb 100644 --- a/core/lsu_bypass.sv +++ b/core/lsu_bypass.sv @@ -24,7 +24,7 @@ // two element FIFO. This is necessary as we only know very late in the cycle whether the load/store will succeed (address check, // TLB hit mainly). So we better unconditionally allow another request to arrive and store this request in case we need to. module lsu_bypass import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, input logic rst_ni, diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv index ba2bf9bd9c..162bc20bb4 100644 --- a/core/mmu_sv32/cva6_mmu_sv32.sv +++ b/core/mmu_sv32/cva6_mmu_sv32.sv @@ -27,7 +27,7 @@ // =========================================================================== // module cva6_mmu_sv32 import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned INSTR_TLB_ENTRIES = 2, parameter int unsigned DATA_TLB_ENTRIES = 2, parameter int unsigned ASID_WIDTH = 1, diff --git a/core/mmu_sv32/cva6_ptw_sv32.sv b/core/mmu_sv32/cva6_ptw_sv32.sv index 856f3c8b90..34fcb2f99a 100644 --- a/core/mmu_sv32/cva6_ptw_sv32.sv +++ b/core/mmu_sv32/cva6_ptw_sv32.sv @@ -27,7 +27,7 @@ /* verilator lint_off WIDTH */ module cva6_ptw_sv32 import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int ASID_WIDTH = 1, parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig ) ( diff --git a/core/mmu_sv32/cva6_shared_tlb_sv32.sv b/core/mmu_sv32/cva6_shared_tlb_sv32.sv index 8a13c2c9d6..496f065012 100644 --- a/core/mmu_sv32/cva6_shared_tlb_sv32.sv +++ b/core/mmu_sv32/cva6_shared_tlb_sv32.sv @@ -18,7 +18,7 @@ /* verilator lint_off WIDTH */ module cva6_shared_tlb_sv32 import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int SHARED_TLB_DEPTH = 64, parameter int SHARED_TLB_WAYS = 2, parameter int ASID_WIDTH = 1, diff --git a/core/mmu_sv32/cva6_tlb_sv32.sv b/core/mmu_sv32/cva6_tlb_sv32.sv index 404d77d5d7..0e79397c66 100644 --- a/core/mmu_sv32/cva6_tlb_sv32.sv +++ b/core/mmu_sv32/cva6_tlb_sv32.sv @@ -25,7 +25,7 @@ // =========================================================================== // module cva6_tlb_sv32 import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned TLB_ENTRIES = 4, parameter int unsigned ASID_WIDTH = 1 )( diff --git a/core/mmu_sv39/mmu.sv b/core/mmu_sv39/mmu.sv index efd82fe982..b0d77daa64 100644 --- a/core/mmu_sv39/mmu.sv +++ b/core/mmu_sv39/mmu.sv @@ -16,7 +16,7 @@ module mmu import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned INSTR_TLB_ENTRIES = 4, parameter int unsigned DATA_TLB_ENTRIES = 4, parameter int unsigned ASID_WIDTH = 1, diff --git a/core/mmu_sv39/ptw.sv b/core/mmu_sv39/ptw.sv index d309f6fcdf..e6c117155b 100644 --- a/core/mmu_sv39/ptw.sv +++ b/core/mmu_sv39/ptw.sv @@ -16,7 +16,7 @@ /* verilator lint_off WIDTH */ module ptw import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int ASID_WIDTH = 1, parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig ) ( diff --git a/core/mmu_sv39/tlb.sv b/core/mmu_sv39/tlb.sv index 5b718a2bd4..2aeb2dc618 100644 --- a/core/mmu_sv39/tlb.sv +++ b/core/mmu_sv39/tlb.sv @@ -16,7 +16,7 @@ module tlb import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned TLB_ENTRIES = 4, parameter int unsigned ASID_WIDTH = 1 )( diff --git a/core/mult.sv b/core/mult.sv index e09b73882a..69219a99f6 100644 --- a/core/mult.sv +++ b/core/mult.sv @@ -1,7 +1,7 @@ module mult import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, input logic rst_ni, diff --git a/core/multiplier.sv b/core/multiplier.sv index 7a765fea4a..1455799077 100644 --- a/core/multiplier.sv +++ b/core/multiplier.sv @@ -16,7 +16,7 @@ module multiplier import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, input logic rst_ni, diff --git a/core/perf_counters.sv b/core/perf_counters.sv index d299411bea..2987fe2d0a 100644 --- a/core/perf_counters.sv +++ b/core/perf_counters.sv @@ -14,7 +14,7 @@ module perf_counters import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned NumPorts = 3 // number of miss ports ) ( input logic clk_i, diff --git a/core/pmp/src/pmp.sv b/core/pmp/src/pmp.sv index 6470a10492..6c8171eac0 100644 --- a/core/pmp/src/pmp.sv +++ b/core/pmp/src/pmp.sv @@ -13,7 +13,7 @@ // Description: purely combinatorial PMP unit (with extraction for more complex configs such as NAPOT) module pmp #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned PLEN = 34, // rv64: 56 parameter int unsigned PMP_LEN = 32, // rv64: 54 parameter int unsigned NR_ENTRIES = 4 @@ -38,6 +38,7 @@ module pmp #( assign conf_addr_prev = (i == 0) ? '0 : conf_addr_i[i-1]; pmp_entry #( + .CVA6Cfg ( CVA6Cfg ), .PLEN ( PLEN ), .PMP_LEN ( PMP_LEN ) ) i_pmp_entry( diff --git a/core/pmp/src/pmp_entry.sv b/core/pmp/src/pmp_entry.sv index e3f75e81aa..6b4585e42f 100644 --- a/core/pmp/src/pmp_entry.sv +++ b/core/pmp/src/pmp_entry.sv @@ -13,7 +13,7 @@ // Description: single PMP entry module pmp_entry #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned PLEN = 56, parameter int unsigned PMP_LEN = 54 ) ( diff --git a/core/re_name.sv b/core/re_name.sv index 35941ab292..8fd88f3fd7 100644 --- a/core/re_name.sv +++ b/core/re_name.sv @@ -10,7 +10,7 @@ // Description: Re-name registers module re_name import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -48,30 +48,30 @@ module re_name import ariane_pkg::*; #( if (issue_ack_i && !flush_unissied_instr_i) begin // if we acknowledge the instruction tic the corresponding destination register - if (is_rd_fpr(issue_instr_i.op)) + if (ariane_pkg::is_rd_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent)) re_name_table_fpr_n[issue_instr_i.rd[4:0]] = re_name_table_fpr_q[issue_instr_i.rd[4:0]] ^ 1'b1; else re_name_table_gpr_n[issue_instr_i.rd[4:0]] = re_name_table_gpr_q[issue_instr_i.rd[4:0]] ^ 1'b1; end // select name bit according to the register file used for source operands - name_bit_rs1 = is_rs1_fpr(issue_instr_i.op) ? re_name_table_fpr_q[issue_instr_i.rs1[4:0]] + name_bit_rs1 = is_rs1_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? re_name_table_fpr_q[issue_instr_i.rs1[4:0]] : re_name_table_gpr_q[issue_instr_i.rs1[4:0]]; - name_bit_rs2 = is_rs2_fpr(issue_instr_i.op) ? re_name_table_fpr_q[issue_instr_i.rs2[4:0]] + name_bit_rs2 = is_rs2_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? re_name_table_fpr_q[issue_instr_i.rs2[4:0]] : re_name_table_gpr_q[issue_instr_i.rs2[4:0]]; // rs3 is only used in certain FP operations and held like an immediate name_bit_rs3 = re_name_table_fpr_q[issue_instr_i.result[4:0]]; // make sure only the addr bits are read // select name bit according to the state it will have after renaming - name_bit_rd = is_rd_fpr(issue_instr_i.op) ? re_name_table_fpr_q[issue_instr_i.rd[4:0]] ^ 1'b1 - : re_name_table_gpr_q[issue_instr_i.rd[4:0]] ^ (issue_instr_i.rd != '0); // don't rename x0 + name_bit_rd = ariane_pkg::is_rd_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? re_name_table_fpr_q[issue_instr_i.rd[4:0]] ^ 1'b1 + : re_name_table_gpr_q[issue_instr_i.rd[4:0]] ^ (issue_instr_i.rd != '0); // don't rename x0 // re-name the source registers issue_instr_o.rs1 = { ENABLE_RENAME & name_bit_rs1, issue_instr_i.rs1[4:0] }; issue_instr_o.rs2 = { ENABLE_RENAME & name_bit_rs2, issue_instr_i.rs2[4:0] }; // re-name the third operand in imm if it's actually an operand - if (is_imm_fpr(issue_instr_i.op) || (issue_instr_i.op == OFFLOAD && ariane_pkg::NR_RGPR_PORTS == 3)) begin + if (is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) || (issue_instr_i.op == OFFLOAD && CVA6Cfg.NrRgprPorts == 3)) begin issue_instr_o.result = { ENABLE_RENAME & name_bit_rs3, issue_instr_i.result[4:0]}; end // re-name the destination register diff --git a/core/scoreboard.sv b/core/scoreboard.sv index d954947add..0586cec683 100644 --- a/core/scoreboard.sv +++ b/core/scoreboard.sv @@ -13,9 +13,10 @@ // Description: Scoreboard - keeps track of all decoded, issued and committed instructions module scoreboard #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, - parameter int unsigned NR_ENTRIES = 8, // must be a power of 2 - parameter int unsigned NR_WB_PORTS = 1 + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter bit IsRVFI = bit'(0), + parameter type rs3_len_t = logic, + parameter int unsigned NR_ENTRIES = 8 // must be a power of 2 ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -37,7 +38,7 @@ module scoreboard #( output logic rs2_valid_o, input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs3_i, - output ariane_pkg::rs3_len_t rs3_o, + output rs3_len_t rs3_o, output logic rs3_valid_o, // advertise instruction to commit stage, if commit_ack_i is asserted advance the commit pointer @@ -57,10 +58,10 @@ module scoreboard #( // write-back port input ariane_pkg::bp_resolve_t resolved_branch_i, - input logic [NR_WB_PORTS-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i, // transaction ID at which to write the result back - input logic [NR_WB_PORTS-1:0][riscv::XLEN-1:0] wbdata_i, // write data in - input ariane_pkg::exception_t [NR_WB_PORTS-1:0] ex_i, // exception from a functional unit (e.g.: ld/st exception) - input logic [NR_WB_PORTS-1:0] wt_valid_i, // data in is valid + input logic [CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i, // transaction ID at which to write the result back + input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, // write data in + input ariane_pkg::exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i, // exception from a functional unit (e.g.: ld/st exception) + input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i, // data in is valid input logic x_we_i, // cvxif we for writeback // RVFI @@ -96,7 +97,7 @@ module scoreboard #( ariane_pkg::scoreboard_entry_t decoded_instr; always_comb begin decoded_instr = decoded_instr_i; - if (CVA6Cfg.IsRVFI) begin + if (IsRVFI) begin decoded_instr.rs1_rdata = rs1_forwarding_i; decoded_instr.rs2_rdata = rs2_forwarding_i; decoded_instr.lsu_addr = '0; @@ -138,7 +139,7 @@ module scoreboard #( // increase the issue counter and advance issue pointer issue_en = 1'b1; mem_n[issue_pointer_q] = {1'b1, // valid bit - ariane_pkg::is_rd_fpr(decoded_instr_i.op), // whether rd goes to the fpr + ariane_pkg::is_rd_fpr_cfg(decoded_instr_i.op, CVA6Cfg.FpPresent), // whether rd goes to the fpr decoded_instr // decoded instruction record }; end @@ -155,7 +156,7 @@ module scoreboard #( // ------------ // Write Back // ------------ - if (CVA6Cfg.IsRVFI) begin + if (IsRVFI) begin if (lsu_rmask_i != 0) begin mem_n[lsu_addr_trans_id_i].sbe.lsu_addr = lsu_addr_i; mem_n[lsu_addr_trans_id_i].sbe.lsu_rmask = lsu_rmask_i; @@ -166,7 +167,7 @@ module scoreboard #( end end - for (int unsigned i = 0; i < NR_WB_PORTS; i++) begin + for (int unsigned i = 0; i < CVA6Cfg.NrWbPorts; i++) begin // check if this instruction was issued (e.g.: it could happen after a flush that there is still // something in the pipeline e.g. an incomplete memory operation) if (wt_valid_i[i] && mem_q[trans_id_i[i]].issued) begin @@ -297,33 +298,33 @@ module scoreboard #( // Read Operands (a.k.a forwarding) // ---------------------------------- // read operand interface: same logic as register file - logic [NR_ENTRIES+NR_WB_PORTS-1:0] rs1_fwd_req, rs2_fwd_req, rs3_fwd_req; - logic [NR_ENTRIES+NR_WB_PORTS-1:0][riscv::XLEN-1:0] rs_data; + logic [NR_ENTRIES+CVA6Cfg.NrWbPorts-1:0] rs1_fwd_req, rs2_fwd_req, rs3_fwd_req; + logic [NR_ENTRIES+CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] rs_data; logic rs1_valid, rs2_valid, rs3_valid; // WB ports have higher prio than entries - for (genvar k = 0; unsigned'(k) < NR_WB_PORTS; k++) begin : gen_rs_wb - assign rs1_fwd_req[k] = (mem_q[trans_id_i[k]].sbe.rd == rs1_i) & wt_valid_i[k] & (~ex_i[k].valid) & (mem_q[trans_id_i[k]].is_rd_fpr_flag == ariane_pkg::is_rs1_fpr(issue_instr_o.op)); - assign rs2_fwd_req[k] = (mem_q[trans_id_i[k]].sbe.rd == rs2_i) & wt_valid_i[k] & (~ex_i[k].valid) & (mem_q[trans_id_i[k]].is_rd_fpr_flag == ariane_pkg::is_rs2_fpr(issue_instr_o.op)); - assign rs3_fwd_req[k] = (mem_q[trans_id_i[k]].sbe.rd == rs3_i) & wt_valid_i[k] & (~ex_i[k].valid) & (mem_q[trans_id_i[k]].is_rd_fpr_flag == ariane_pkg::is_imm_fpr(issue_instr_o.op)); + for (genvar k = 0; unsigned'(k) < CVA6Cfg.NrWbPorts; k++) begin : gen_rs_wb + assign rs1_fwd_req[k] = (mem_q[trans_id_i[k]].sbe.rd == rs1_i) & wt_valid_i[k] & (~ex_i[k].valid) & (mem_q[trans_id_i[k]].is_rd_fpr_flag == ariane_pkg::is_rs1_fpr_cfg(issue_instr_o.op, CVA6Cfg.FpPresent)); + assign rs2_fwd_req[k] = (mem_q[trans_id_i[k]].sbe.rd == rs2_i) & wt_valid_i[k] & (~ex_i[k].valid) & (mem_q[trans_id_i[k]].is_rd_fpr_flag == ariane_pkg::is_rs2_fpr_cfg(issue_instr_o.op, CVA6Cfg.FpPresent)); + assign rs3_fwd_req[k] = (mem_q[trans_id_i[k]].sbe.rd == rs3_i) & wt_valid_i[k] & (~ex_i[k].valid) & (mem_q[trans_id_i[k]].is_rd_fpr_flag == ariane_pkg::is_imm_fpr_cfg(issue_instr_o.op, CVA6Cfg.FpPresent)); assign rs_data[k] = wbdata_i[k]; end for (genvar k = 0; unsigned'(k) < NR_ENTRIES; k++) begin : gen_rs_entries - assign rs1_fwd_req[k+NR_WB_PORTS] = (mem_q[k].sbe.rd == rs1_i) & mem_q[k].issued & mem_q[k].sbe.valid & (mem_q[k].is_rd_fpr_flag == ariane_pkg::is_rs1_fpr(issue_instr_o.op)); - assign rs2_fwd_req[k+NR_WB_PORTS] = (mem_q[k].sbe.rd == rs2_i) & mem_q[k].issued & mem_q[k].sbe.valid & (mem_q[k].is_rd_fpr_flag == ariane_pkg::is_rs2_fpr(issue_instr_o.op)); - assign rs3_fwd_req[k+NR_WB_PORTS] = (mem_q[k].sbe.rd == rs3_i) & mem_q[k].issued & mem_q[k].sbe.valid & (mem_q[k].is_rd_fpr_flag == ariane_pkg::is_imm_fpr(issue_instr_o.op)); - assign rs_data[k+NR_WB_PORTS] = mem_q[k].sbe.result; + assign rs1_fwd_req[k+CVA6Cfg.NrWbPorts] = (mem_q[k].sbe.rd == rs1_i) & mem_q[k].issued & mem_q[k].sbe.valid & (mem_q[k].is_rd_fpr_flag == ariane_pkg::is_rs1_fpr_cfg(issue_instr_o.op, CVA6Cfg.FpPresent)); + assign rs2_fwd_req[k+CVA6Cfg.NrWbPorts] = (mem_q[k].sbe.rd == rs2_i) & mem_q[k].issued & mem_q[k].sbe.valid & (mem_q[k].is_rd_fpr_flag == ariane_pkg::is_rs2_fpr_cfg(issue_instr_o.op, CVA6Cfg.FpPresent)); + assign rs3_fwd_req[k+CVA6Cfg.NrWbPorts] = (mem_q[k].sbe.rd == rs3_i) & mem_q[k].issued & mem_q[k].sbe.valid & (mem_q[k].is_rd_fpr_flag == ariane_pkg::is_imm_fpr_cfg(issue_instr_o.op, CVA6Cfg.FpPresent)); + assign rs_data[k+CVA6Cfg.NrWbPorts] = mem_q[k].sbe.result; end // check whether we are accessing GPR[0] - assign rs1_valid_o = rs1_valid & ((|rs1_i) | ariane_pkg::is_rs1_fpr(issue_instr_o.op)); - assign rs2_valid_o = rs2_valid & ((|rs2_i) | ariane_pkg::is_rs2_fpr(issue_instr_o.op)); - assign rs3_valid_o = ariane_pkg::NR_RGPR_PORTS == 3 ? rs3_valid & ((|rs3_i) | ariane_pkg::is_imm_fpr(issue_instr_o.op)) : rs3_valid; + assign rs1_valid_o = rs1_valid & ((|rs1_i) | ariane_pkg::is_rs1_fpr_cfg(issue_instr_o.op, CVA6Cfg.FpPresent)); + assign rs2_valid_o = rs2_valid & ((|rs2_i) | ariane_pkg::is_rs2_fpr_cfg(issue_instr_o.op, CVA6Cfg.FpPresent)); + assign rs3_valid_o = CVA6Cfg.NrRgprPorts == 3 ? rs3_valid & ((|rs3_i) | ariane_pkg::is_imm_fpr_cfg(issue_instr_o.op, CVA6Cfg.FpPresent)) : rs3_valid; // use fixed prio here // this implicitly gives higher prio to WB ports rr_arb_tree #( - .NumIn(NR_ENTRIES+NR_WB_PORTS), + .NumIn(NR_ENTRIES+CVA6Cfg.NrWbPorts), .DataWidth(riscv::XLEN), .ExtPrio(1'b1), .AxiVldRdy(1'b1) @@ -342,7 +343,7 @@ module scoreboard #( ); rr_arb_tree #( - .NumIn(NR_ENTRIES+NR_WB_PORTS), + .NumIn(NR_ENTRIES+CVA6Cfg.NrWbPorts), .DataWidth(riscv::XLEN), .ExtPrio(1'b1), .AxiVldRdy(1'b1) @@ -363,7 +364,7 @@ module scoreboard #( riscv::xlen_t rs3; rr_arb_tree #( - .NumIn(NR_ENTRIES+NR_WB_PORTS), + .NumIn(NR_ENTRIES+CVA6Cfg.NrWbPorts), .DataWidth(riscv::XLEN), .ExtPrio(1'b1), .AxiVldRdy(1'b1) @@ -381,10 +382,10 @@ module scoreboard #( .idx_o ( ) ); - if (ariane_pkg::NR_RGPR_PORTS == 3) begin : gen_gp_three_port + if (CVA6Cfg.NrRgprPorts == 3) begin : gen_gp_three_port assign rs3_o = rs3[riscv::XLEN-1:0]; end else begin : gen_fp_three_port - assign rs3_o = rs3[ariane_pkg::FLEN-1:0]; + assign rs3_o = rs3[CVA6Cfg.FLen-1:0]; end @@ -428,8 +429,8 @@ module scoreboard #( // there should never be more than one instruction writing the same destination register (except x0) // check that no functional unit is retiring with the same transaction id - for (genvar i = 0; i < NR_WB_PORTS; i++) begin - for (genvar j = 0; j < NR_WB_PORTS; j++) begin + for (genvar i = 0; i < CVA6Cfg.NrWbPorts; i++) begin + for (genvar j = 0; j < CVA6Cfg.NrWbPorts; j++) begin assert property ( @(posedge clk_i) disable iff (!rst_ni) wt_valid_i[i] && wt_valid_i[j] && (i != j) |-> (trans_id_i[i] != trans_id_i[j])) else $fatal (1,"Two or more functional units are retiring instructions with the same transaction id!"); diff --git a/core/serdiv.sv b/core/serdiv.sv index 20386daf02..73704d9448 100644 --- a/core/serdiv.sv +++ b/core/serdiv.sv @@ -16,7 +16,7 @@ module serdiv import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter WIDTH = 64, parameter STABLE_HANDSHAKE = 0 // Guarantee a stable in_rdy_o during the input handshake. Keep it at 0 in CVA6 ) ( diff --git a/core/store_buffer.sv b/core/store_buffer.sv index 6a1163286a..772b051a0e 100644 --- a/core/store_buffer.sv +++ b/core/store_buffer.sv @@ -15,7 +15,7 @@ module store_buffer import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/core/store_unit.sv b/core/store_unit.sv index 27eb11aaa8..0dd90103aa 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -14,7 +14,7 @@ module store_unit import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index 405a56688a..575cbf9275 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -154,15 +154,9 @@ module ariane_xilinx ( output logic tx ); -// cva6 configuration -localparam ariane_pkg::cva6_cfg_t CVA6Cfg = { - unsigned'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts - unsigned'(0), // IsRVFI - unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth), // AxiAddrWidth - unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth), // AxiDataWidth - unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth), // AxiIdWidth - unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth) // DataUserWidth -}; +// CVA6 config +localparam bit IsRVFI = bit'(0); +localparam config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg; localparam type rvfi_instr_t = logic; @@ -710,6 +704,7 @@ ariane_axi::resp_t axi_ariane_resp; ariane #( .CVA6Cfg ( CVA6Cfg ), + .IsRVFI ( IsRVFI ), .rvfi_instr_t ( rvfi_instr_t ), .ArianeCfg ( ariane_soc::ArianeSocCfg ) ) i_ariane ( diff --git a/corev_apu/src/ariane.sv b/corev_apu/src/ariane.sv index 029a87a250..6a0327bf76 100644 --- a/corev_apu/src/ariane.sv +++ b/corev_apu/src/ariane.sv @@ -14,7 +14,8 @@ module ariane import ariane_pkg::*; #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter bit IsRVFI = bit'(0), parameter type rvfi_instr_t = logic, // parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, @@ -52,6 +53,7 @@ module ariane import ariane_pkg::*; #( cva6 #( .CVA6Cfg ( CVA6Cfg ), + .IsRVFI ( IsRVFI ), .rvfi_instr_t ( rvfi_instr_t ), // .ArianeCfg ( ArianeCfg ), @@ -76,7 +78,7 @@ module ariane import ariane_pkg::*; #( .noc_resp_i ( noc_resp_i ) ); - if (ariane_pkg::CVXIF_PRESENT) begin : gen_example_coprocessor + if (CVA6Cfg.CvxifEn) begin : gen_example_coprocessor cvxif_example_coprocessor i_cvxif_coprocessor ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -85,4 +87,4 @@ module ariane import ariane_pkg::*; #( ); end -endmodule // ariane \ No newline at end of file +endmodule // ariane diff --git a/corev_apu/tb/ariane_tb.sv b/corev_apu/tb/ariane_tb.sv index 23b515c673..67b7ea8580 100644 --- a/corev_apu/tb/ariane_tb.sv +++ b/corev_apu/tb/ariane_tb.sv @@ -29,38 +29,32 @@ import "DPI-C" context function void read_section(input longint address, inout b module ariane_tb; // cva6 configuration - localparam ariane_pkg::cva6_cfg_t CVA6Cfg = { - unsigned'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts - unsigned'(cva6_config_pkg::CVA6ConfigRvfiTrace), // IsRVFI - unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth), // AxiAddrWidth - unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth), // AxiDataWidth - unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth), // AxiIdWidth - unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth) // AxiUserWidth - }; + localparam config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg; + localparam bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace); localparam type rvfi_instr_t = struct packed { - logic [ariane_pkg::NRET-1:0] valid; - logic [ariane_pkg::NRET*64-1:0] order; - logic [ariane_pkg::NRET*ariane_pkg::ILEN-1:0] insn; - logic [ariane_pkg::NRET-1:0] trap; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] cause; - logic [ariane_pkg::NRET-1:0] halt; - logic [ariane_pkg::NRET-1:0] intr; - logic [ariane_pkg::NRET*2-1:0] mode; - logic [ariane_pkg::NRET*2-1:0] ixl; - logic [ariane_pkg::NRET*5-1:0] rs1_addr; - logic [ariane_pkg::NRET*5-1:0] rs2_addr; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs1_rdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs2_rdata; - logic [ariane_pkg::NRET*5-1:0] rd_addr; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] rd_wdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_rdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_wdata; - logic [ariane_pkg::NRET*riscv::VLEN-1:0] mem_addr; - logic [ariane_pkg::NRET*riscv::PLEN-1:0] mem_paddr; - logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask; - logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_rdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_wdata; + logic [config_pkg::NRET-1:0] valid; + logic [config_pkg::NRET*64-1:0] order; + logic [config_pkg::NRET*config_pkg::ILEN-1:0] insn; + logic [config_pkg::NRET-1:0] trap; + logic [config_pkg::NRET*riscv::XLEN-1:0] cause; + logic [config_pkg::NRET-1:0] halt; + logic [config_pkg::NRET-1:0] intr; + logic [config_pkg::NRET*2-1:0] mode; + logic [config_pkg::NRET*2-1:0] ixl; + logic [config_pkg::NRET*5-1:0] rs1_addr; + logic [config_pkg::NRET*5-1:0] rs2_addr; + logic [config_pkg::NRET*riscv::XLEN-1:0] rs1_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] rs2_rdata; + logic [config_pkg::NRET*5-1:0] rd_addr; + logic [config_pkg::NRET*riscv::XLEN-1:0] rd_wdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] pc_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] pc_wdata; + logic [config_pkg::NRET*riscv::VLEN-1:0] mem_addr; + logic [config_pkg::NRET*riscv::PLEN-1:0] mem_paddr; + logic [config_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask; + logic [config_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask; + logic [config_pkg::NRET*riscv::XLEN-1:0] mem_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] mem_wdata; }; static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); @@ -83,6 +77,7 @@ module ariane_tb; ariane_testharness #( .CVA6Cfg ( CVA6Cfg ), + .IsRVFI ( IsRVFI ), .rvfi_instr_t ( rvfi_instr_t ), // .NUM_WORDS ( NUM_WORDS ), diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv index bd74ac1e23..568d343345 100644 --- a/corev_apu/tb/ariane_testharness.sv +++ b/corev_apu/tb/ariane_testharness.sv @@ -16,38 +16,32 @@ `include "axi/assign.svh" module ariane_testharness #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = { - unsigned'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts - unsigned'(cva6_config_pkg::CVA6ConfigRvfiTrace), // IsRVFI - unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth), // AxiAddrWidth - unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth), // AxiDataWidth - unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth), // AxiIdWidth - unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth) // AxiUserWidth - }, + parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg, + parameter bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace), parameter type rvfi_instr_t = struct packed { - logic [ariane_pkg::NRET-1:0] valid; - logic [ariane_pkg::NRET*64-1:0] order; - logic [ariane_pkg::NRET*ariane_pkg::ILEN-1:0] insn; - logic [ariane_pkg::NRET-1:0] trap; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] cause; - logic [ariane_pkg::NRET-1:0] halt; - logic [ariane_pkg::NRET-1:0] intr; - logic [ariane_pkg::NRET*2-1:0] mode; - logic [ariane_pkg::NRET*2-1:0] ixl; - logic [ariane_pkg::NRET*5-1:0] rs1_addr; - logic [ariane_pkg::NRET*5-1:0] rs2_addr; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs1_rdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs2_rdata; - logic [ariane_pkg::NRET*5-1:0] rd_addr; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] rd_wdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_rdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_wdata; - logic [ariane_pkg::NRET*riscv::VLEN-1:0] mem_addr; - logic [ariane_pkg::NRET*riscv::PLEN-1:0] mem_paddr; - logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask; - logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_rdata; - logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_wdata; + logic [config_pkg::NRET-1:0] valid; + logic [config_pkg::NRET*64-1:0] order; + logic [config_pkg::NRET*config_pkg::ILEN-1:0] insn; + logic [config_pkg::NRET-1:0] trap; + logic [config_pkg::NRET*riscv::XLEN-1:0] cause; + logic [config_pkg::NRET-1:0] halt; + logic [config_pkg::NRET-1:0] intr; + logic [config_pkg::NRET*2-1:0] mode; + logic [config_pkg::NRET*2-1:0] ixl; + logic [config_pkg::NRET*5-1:0] rs1_addr; + logic [config_pkg::NRET*5-1:0] rs2_addr; + logic [config_pkg::NRET*riscv::XLEN-1:0] rs1_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] rs2_rdata; + logic [config_pkg::NRET*5-1:0] rd_addr; + logic [config_pkg::NRET*riscv::XLEN-1:0] rd_wdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] pc_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] pc_wdata; + logic [config_pkg::NRET*riscv::VLEN-1:0] mem_addr; + logic [config_pkg::NRET*riscv::PLEN-1:0] mem_paddr; + logic [config_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask; + logic [config_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask; + logic [config_pkg::NRET*riscv::XLEN-1:0] mem_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] mem_wdata; }, // parameter int unsigned AXI_USER_WIDTH = ariane_pkg::AXI_USER_WIDTH, @@ -640,6 +634,7 @@ module ariane_testharness #( ariane #( .CVA6Cfg ( CVA6Cfg ), + .IsRVFI ( IsRVFI ), .rvfi_instr_t ( rvfi_instr_t ), .ArianeCfg ( ariane_soc::ArianeSocCfg ), .noc_req_t ( ariane_axi::req_t ), diff --git a/corev_apu/tb/rvfi_tracer.sv b/corev_apu/tb/rvfi_tracer.sv index 962962fdea..75f68beb57 100644 --- a/corev_apu/tb/rvfi_tracer.sv +++ b/corev_apu/tb/rvfi_tracer.sv @@ -8,7 +8,7 @@ // Original Author: Jean-Roch COULON - Thales module rvfi_tracer #( - parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type rvfi_instr_t = logic, // parameter logic [7:0] HART_ID = '0,