From 17c16a64bb60be7b2c3e72cf552fdcd52086ab6e Mon Sep 17 00:00:00 2001 From: Arjan Bink Date: Tue, 18 Apr 2023 17:45:27 +0200 Subject: [PATCH 1/2] Updated RISC-V Debug specification to version 1.0-STABLE, fb702526127d0c8a4b343fc017e2c93137177df0, April 14 2023 Signed-off-by: Arjan Bink --- .../source/control_status_registers.rst | 81 ++++--------------- docs/user_manual/source/intro.rst | 4 +- 2 files changed, 16 insertions(+), 69 deletions(-) diff --git a/docs/user_manual/source/control_status_registers.rst b/docs/user_manual/source/control_status_registers.rst index ff9c52b9..feb35d4e 100644 --- a/docs/user_manual/source/control_status_registers.rst +++ b/docs/user_manual/source/control_status_registers.rst @@ -90,12 +90,8 @@ instruction exception. +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+ | 0x7A2 | ``tdata2`` | MRW | ``DBG_NUM_TRIGGERS`` > 0 | Trigger Data Register 2 | +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+ - | 0x7A3 | ``tdata3`` | MRW | ``DBG_NUM_TRIGGERS`` > 0 | Trigger Data Register 3 | - +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+ | 0x7A4 | ``tinfo`` | MRW | ``DBG_NUM_TRIGGERS`` > 0 | Trigger Info | +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+ - | 0x7A5 | ``tcontrol`` | MRW | ``DBG_NUM_TRIGGERS`` > 0 | Trigger Control | - +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+ | 0x7B0 | ``dcsr`` | DRW | ``DEBUG`` = 1 | Debug Control and Status | +---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+ | 0x7B1 | ``dpc`` | DRW | ``DEBUG`` = 1 | Debug PC | @@ -1556,20 +1552,21 @@ Reset Value: Not applicable +-------+-------------+----------------------------------------------------------------+ | 27 | WARL (0x1) | **DMODE**. Only debug mode can write ``tdata`` registers. | +-------+-------------+----------------------------------------------------------------+ - | 26:25 | WARL (0x0) | Hardwired to 0. | + | 26 | WARL (0x0) | **UNCERTAIN**. Hardwired to 0. | + +-------+-------------+----------------------------------------------------------------+ + | 25 | | **HIT1**. Forms 2-bit WARL (0x0, 0x1) bitfield with **HIT0**. | +-------+-------------+----------------------------------------------------------------+ | 24 | WARL (0x0) | **VS**. Hardwired to 0. | +-------+-------------+----------------------------------------------------------------+ | 23 | WARL (0x0) | **VU**. Hardwired to 0. | +-------+-------------+----------------------------------------------------------------+ - | 22 | WARL (0x0) | **HIT**. Hardwired to 0. | + | 22 | | **HIT0**. Forms 2-bit WARL (0x0, 0x1) bitfield with **HIT1**. | +-------+-------------+----------------------------------------------------------------+ | 21 | WARL (0x0) | **SELECT**. Only address matching is supported. | +-------+-------------+----------------------------------------------------------------+ - | 20 | WARL (0x0) | **TIMING**. Break before the instruction at the specified | - | | | address. | + | 20:19 | WARL (0x0) | Hardwired to 0. | +-------+-------------+----------------------------------------------------------------+ - | 19:16 | WARL (0x0) | **SIZE**. Match accesses of any size. | + | 18:16 | WARL (0x0) | **SIZE**. Match accesses of any size. | +-------+-------------+----------------------------------------------------------------+ | 15:12 | WARL (0x1) | **ACTION**. Enter debug mode on match. | +-------+-------------+----------------------------------------------------------------+ @@ -1580,7 +1577,7 @@ Reset Value: Not applicable +-------+-------------+----------------------------------------------------------------+ | 6 | WARL | **M**. Match in machine mode. | +-------+-------------+----------------------------------------------------------------+ - | 5 | WARL (0x0) | Hardwired to 0. | + | 5 | WARL (0x0) | **UNCERTAINEN**. Hardwired to 0. | +-------+-------------+----------------------------------------------------------------+ | 4 | WARL (0x0) | **S**. Hardwired to 0. | +-------+-------------+----------------------------------------------------------------+ @@ -1593,6 +1590,9 @@ Reset Value: Not applicable | 0 | WARL | **LOAD**. Enable matching on load address. | +-------+-------------+----------------------------------------------------------------+ +.. note:: + The ``hit1`` (MSB) and ``hit0`` (LSB) form a 2-bit bitfield together that has WARL (0x0, 0x1) behavior. + .. _csr-tdata1_disabled: Trigger Data 1 (``tdata1``) - ``disabled`` view @@ -1769,30 +1769,6 @@ Detailed: .. note:: Accessible in Debug Mode or M-Mode, depending on ``tdata1.DMODE``. -.. _csr-tdata3: - -Trigger Data Register 3 (``tdata3``) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -CSR Address: 0x7A3 - -Reset Value: 0x0000_0000 - -Detailed: - -.. table:: - :widths: 10 20 70 - :class: no-scrollbar-table - - +-------+------------+------------------------------------------------------------------+ - | Bit# | R/W | Description | - +=======+============+==================================================================+ - | 31:0 | WARL (0x0) | Hardwired to 0. | - +-------+------------+------------------------------------------------------------------+ - -Accessible in Debug Mode or M-Mode. -|corev| does not support the features requiring this register. CSR is hardwired to 0. - .. _csr-tinfo: Trigger Info (``tinfo``) @@ -1800,7 +1776,7 @@ Trigger Info (``tinfo``) CSR Address: 0x7A4 -Reset Value: 0x0000_8064 +Reset Value: 0x0100_8064 Detailed: @@ -1811,7 +1787,9 @@ Detailed: +-------+------------+------------------------------------------------------------------+ | Bit# | R/W | Description | +=======+============+==================================================================+ - | 31:16 | WARL (0x0) | Hardwired to 0. | + | 31:24 | R (0x1) | **VERSION**. Sdtrig version 1.0. | + +-------+------------+------------------------------------------------------------------+ + | 23:16 | WARL (0x0) | Hardwired to 0. | +-------+------------+------------------------------------------------------------------+ | 15:0 | R (0x8064) | **INFO**. Types 0x2, 0x5, 0x6 and 0xF are supported. | +-------+------------+------------------------------------------------------------------+ @@ -1823,37 +1801,6 @@ does not exist, this field contains 1. Accessible in Debug Mode or M-Mode. -.. _csr-tcontrol: - -Trigger Control (``tcontrol``) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -CSR Address: 0x7A5 - -Reset Value: 0x0000_0000 - -Detailed: - -.. table:: - :widths: 10 20 70 - :class: no-scrollbar-table - - +-------+-------------+------------------------------------------------------------------+ - | Bit# | R/W | Description | - +=======+=============+==================================================================+ - | 31:8 | WARL (0x0) | Hardwired to 0. | - +-------+-------------+------------------------------------------------------------------+ - | 7 | WARL (0x0) | **MPTE**. Hardwired to 0. | - +-------+-------------+------------------------------------------------------------------+ - | 6:4 | WARL (0x0) | Hardwired to 0. | - +-------+-------------+------------------------------------------------------------------+ - | 3 | WARL (0x0) | **MTE**. Hardwired to 0. | - +-------+-------------+------------------------------------------------------------------+ - | 2:0 | WARL (0x0) | Hardwired to 0. | - +-------+-------------+------------------------------------------------------------------+ - -|corev| does not support the features requiring this register. CSR is hardwired to 0. - .. _csr-dcsr: Debug Control and Status (``dcsr``) diff --git a/docs/user_manual/source/intro.rst b/docs/user_manual/source/intro.rst index 3cf1b595..a1f38b02 100644 --- a/docs/user_manual/source/intro.rst +++ b/docs/user_manual/source/intro.rst @@ -42,8 +42,8 @@ It follows these specifications: .. [RISC-V-RV32E] RISC-V Instruction Set Manual, Volume I: User-Level ISA, RV32E Base Integer Instruction Set, Document version 20191214-draft (January 31, 2023), https://github.com/riscv/riscv-isa-manual/releases/download/draft-20230131-c0b298a/riscv-spec.pdf -.. [RISC-V-DEBUG] RISC-V Debug Support, version 1.0-STABLE, 246028cd719426597269b3d717c866802c58bde7, - https://github.com/riscv/riscv-debug-spec/blob/05252da1575610e9605d882145da3f4e7f4f3cb1/riscv-debug-stable.pdf +.. [RISC-V-DEBUG] RISC-V Debug Support, version 1.0-STABLE, fb702526127d0c8a4b343fc017e2c93137177df0, April 14 2023, + https://github.com/riscv/riscv-debug-spec/blob/f4381fed042927d9d1fba774898ae2484e5cdc71/riscv-debug-stable.pdf .. [RISC-V-CLIC] Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extensions, version 0.9-draft, 3/14/2023, https://github.com/riscv/riscv-fast-interrupt/blob/550771f42b579776a37345894b9ca7e01e645555/clic.pdf From c91c4b2d0ffbfdac829a8731f2ee94699d4a8c06 Mon Sep 17 00:00:00 2001 From: Arjan Bink Date: Tue, 18 Apr 2023 17:50:50 +0200 Subject: [PATCH 2/2] Typo fix Signed-off-by: Arjan Bink --- docs/user_manual/source/control_status_registers.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/user_manual/source/control_status_registers.rst b/docs/user_manual/source/control_status_registers.rst index feb35d4e..66065b8b 100644 --- a/docs/user_manual/source/control_status_registers.rst +++ b/docs/user_manual/source/control_status_registers.rst @@ -1591,7 +1591,7 @@ Reset Value: Not applicable +-------+-------------+----------------------------------------------------------------+ .. note:: - The ``hit1`` (MSB) and ``hit0`` (LSB) form a 2-bit bitfield together that has WARL (0x0, 0x1) behavior. + The ``hit1`` (MSB) and ``hit0`` (LSB) bitfields form a 2-bit bitfield together that has WARL (0x0, 0x1) behavior. .. _csr-tdata1_disabled: