o1vm/riscv32i: define registers #2743
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Codecov ReportAttention: Patch coverage is
Additional details and impacted files@@ Coverage Diff @@
## master #2743 +/- ##
==========================================
- Coverage 73.70% 73.68% -0.03%
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Files 249 250 +1
Lines 57866 57889 +23
==========================================
+ Hits 42650 42654 +4
- Misses 15216 15235 +19 ☔ View full report in Codecov by Sentry. |
svv232
reviewed
Nov 14, 2024
Comment on lines
+38
to
+48
| if index < N_GP_REGISTERS { | ||
| &self.general_purpose[index] | ||
| } else if index == REGISTER_CURRENT_IP { | ||
| &self.current_instruction_pointer | ||
| } else if index == REGISTER_NEXT_IP { | ||
| &self.next_instruction_pointer | ||
| } else if index == REGISTER_HEAP_POINTER { | ||
| &self.heap_pointer | ||
| } else { | ||
| panic!("Index out of bounds"); | ||
| } |
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nbd since ip, nip, and the heap ptr are artificial, but it is a bit awkward that 32 isn't an index in the range.
svv232
approved these changes
Nov 14, 2024
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Import commits from #2727