Few questions about the source code

[alfa871212]

1. In ShiftAdd.cpp, the area is included with INV, NAND, DFF and Adder. But with respect to Power/Latency, I didn't see the INV Adder consideration. Is there any reason for that?

2. Cell width in the standard cell is CPP direction, but in SRAM definition cell width is in fin pitch direction, how can you divide SRAM cell width by standard cell width to determine the needed duplicate row for each module in SRAM array? Or if there is any reference demonstrating the fin direction will be rotated by 90 degree when it goes from SRAM cell to its periphery?