Naming here is compliant with the OpenTitan names and suffixes specification, with the following augmentations:
- Clock signals start with
clk_* - Inputs and outputs are marked with
*_i/o - Analog signals are marked with
*_a - Non-core level signals are marked with
*_h - Dual and negative polarity signals are marked with
*_p/n
| name | freq | description |
|---|---|---|
| sys | Up to 100MHz | jittery system clock. Mainly used for high performance and security modules. |
| usb | 48MHz | USB module source clock. |
| aon | 200kHz | Always-on domain clock. The only active clock while chip is in deep-sleep power states. |
| async | It does not matter what domain drives the signal |
- Input clocks: Each functional interface has a dedicated clock named after the interface.
| Signal Name / Affiliation |
I/O | Width/ Type/ Struct |
Clock Domain | Description |
|---|---|---|---|---|
| Power Supplies | ||||
| VCC | I | VCC is the main power supply. It is driven from an external source and is used to power the internal VCMAIN and VCAON power domains. VCC must always be present when the device is functioning; VCC is also used to power a number of pads that must be always on when the device is functioning. | ||
| AVCC | I | Analog blocks power supply. AVCC and AGND are analog supply and ground signals for the AST analog functions. They mainly serve for ADC and USB clock functionality. AVCC is expected to be driven by the same voltage regulator and have similar power availability as VCC. AVCC and AGND have dedicated package balls/pins. In the future, package pins sharing with VCC and GND may be considered based on post-silicon test results. | ||
| VCMAIN | O | Main core power, driven by internal capless voltage regulator | ||
| VCAON | O | Core voltage power for always-on domain (same voltage range as VCMAIN) | ||
| VIOA | I | IO supply, powering a set of pads. Unlike VCC, the IO supplies can be turned off by external components and the device will continue to function, the unpowered pads however, become inoperable. | ||
| VIOB | I | Same as VIOA, but for a different set of pads. | ||
| GND | I | Ground | ||
| AGND | I | Analog ground (see AVCC for further details) | ||
| Power Control and Reset | ||||
| otp_power_seq_i | I | 2 | async | Contains the power sequencing signals coming from the OTP macro. |
| otp_power_seq_h_o | O | 2 | async | Contains the power sequencing signals going to the OTP macro (VCC domain). |
| flash_power_down_h_o | O | 1 | async | Connected to flash (VCC domain). Used for flash power management. |
| flash_power_ready_h_o | O | 1 | async | Connected to flash (VCC domain). Used for flash power management. |
| vcmain_pok (aka vcmain_pok_o) | O | ast_pwst | async | Main core power-exist indication. Used by the OpenTitan power manager to determine the state of the main digital supply during power up and power down sequencing. |
| vcaon_pok (aka vcaon_pok_o) | O | ast_pwst | async | Always-on power-exist indication. Used by the OpenTitan power manager for power-on reset root. |
| vioa_pok (aka vioa_pok_o) | O | ast_pwst | async | VIOA power-exist indications. Used as a power-OK status signal. |
| viob_pok (aka viob_pok_o) | O | ast_pwst | async | VIOB power-exist indication. Used as a power-OK status signal. |
| por_ni | I | 1 | async | Power on reset input signal to AST. See Resets section for further details |
| main_pd_ni | I | 1 | aon | Power down enable for main core power. 0: main core power is down (deep-sleep state). 1: main core power is up. It may take up to 200 uS from this signal transition to power switching completion by AST (not including boot time and so). Note that flash must be prepared for power down before this signal is asserted. |
| main_env_iso_en_i | I | 1 | aon | Preliminary indication of VCMAIN isolation signal (main_iso_en) assertion. It is used by AST logic to latch interface signals which may no longer be valid after main_iso_en is active. This signal must be set at least 30ns before main_iso_en is active and must remain active at least 30ns after main_iso_en is no longer active. Note that main_iso_en itself asserts ahead of main_pd_ni. ie, the pwrmgr will set this signal to '1' before requesting the power be turned off. Similar, on power-on, the isolation is only released after power is restored and all powered off modules have been reset. |
| ast_init_done_o | O | mubi4 | tlul | When set, it indicates that the AST initialization was performed. Note that this signal may not be set while the chip is in TEST* or RMA lifecycle states. |
| Clock Outputs | ||||
| clk_src_sys_o | O | 1 | sys | 100 MHz clock with jitter (main clock domain). Used as the main system clock. |
| clk_src_sys_val_o | O | 1 | async | System clock valid. Used as "ack" signals for the power manager |
| clk_src_sys_en_i | I | 1 | aon | System clock enable. |
| clk_src_sys_jen_i | I | mubi4 | async | System clock jitter enable |
| clk_src_aon_o | O | 1 | aon | 200 KHz clock for always-on domain. |
| clk_src_aon_val_o | O | 1 | async | aon clock valid |
| clk_src_usb_o | O | 1 | usb | 48 MHz clock for USB. To comply with USB full speed clock specification, it supports frequency accuracy of +/-2500 ppm when usb_ref_pulse_i is available and +/-3% otherwise. It may take up to 50 ms for this clock to reach the accuracy target from the time 'usb_ref_pulse_i' is available. USB clock calibration interface is further detailed here. |
| clk_src_usb_val_o | O | 1 | async | USB clock valid |
| clk_src_usb_en_i | I | 1 | aon | USB clock enable |
| usb_ref_pulse_i | I | 1 | usb | USB reference pulse +/-500ppm. When valid, it is expected to pulse for one usb clock cycle every 1ms. |
| usb_ref_val_i | I | 1 | usb | USB reference valid. This bit serves as a valid signal for the usb_ref_pulse_i signal. It is set to 1 after the first valid usb_ref_pulse_i event is detected and remains high as long as usb_ref_pulse_i continues to behave as expected (per usb_ref_pulse description). Once usb_ref_pulse deviates from its expected behavior, usb_ref_val_i immediately negates to 0 and remains 0 until after the next valid usb_ref_val pulse. |
| clk_src_io_o | O | 1 | io | 96 MHz clock with +/-3% frequency accuracy. Used for peripherals that require a fixed frequency, for example SPI and UART |
| clk_src_io_val_o | O | 1 | async | I/O and timer clock valid. Used as "ack" signals for the Power manager. |
| clk_src_io_en_i | I | 1 | aon | I/O and timer clock enable |
| clk_src_io_48m_o | O | mubi4 | aon | Clock frequency indicator. When set, it indicates that the clk_src_io_o's frequency is 48 MHz; otherwise, it is 96 MHz. |
| Clock & Reset Inputs | ||||
| clk_ast_adc_i | I | 1 | adc | ADC interface clock input |
| clk_ast_rng_i | I | 1 | rng | RNG interface clock input |
| clk_ast_usb_i | I | 1 | usb | USB reference interface clock input |
| clk_ast_es_i | I | 1 | es | Entropy source interface clock input |
| clk_ast_alert_i | I | 1 | alert | Alert interface clock input |
| clk_ast_tlul_i | I | 1 | tlul | TLUL bus interface clock input |
| rst_ast_adc_ni | I | 1 | adc | ADC interface reset (active low) |
| rst_ast_rng_ni | I | 1 | rng | RNG interface reset (active low) |
| rst_ast_usb_ni | I | 1 | usb | USB reference interface reset (active low) |
| rst_ast_es_ni | I | 1 | es | Entropy source interface reset (active low) |
| rst_ast_alert_ni | I | 1 | alert | Alert interface interface reset (active low) |
| rst_ast_tlul_ni | I | 1 | tlul | TLUL bus reference interface reset (active low) |
| Register Access Interface | ||||
| tlul | I/O | tl_* | tlul | TLUL bus interface. Mainly used for configuration, calibration and trimming. At boot time, data is copied from non-volatile storage into AST registers by the SW boot entity. This interface has no further use beyond this point. Runtime interaction with AST is performed by other signals as described in this document. |
| Analog modules | ||||
| adc_a0_ai | I | awire | async | ADC analog input channels 0 to be measured. Signal type is awire (see ana_pkg.sv) |
| adc_a1_ai | I | awire | async | ADC analog input channels 1 to be measured. Signal type is awire (see ana_pkg.sv) |
| adc_d_o | O | 10 | adc | ADC digital data |
| adc_chnsel_i | I | 2 | adc | ADC input channel select (one hot). No more than one channel should be selected at a time. Any change in 'adc_chnsel_i' value must go through all '0'. Changing 'adc_chnsel_i' from '0' value to non-'0' value starts an ADC conversion. |
| adc_d_val_o | O | 1 | adc | ADC digital data valid |
| adc_pd_i | I | 1 | adc | ADC power down - for saving power during deep-sleep state between measurements. When this signal is high, ADC module is in off state, otherwise, it is in active state. For further description about adc_pd_i usage, see ADC module description below. |
| entropy_req_o | O | edn_req | es | Request entropy from EDN |
| entropy_rsp_i | I | edn_rsp | es | EDN entropy request acknowledgement and data. |
| rng_en_i | I | 1 | rng | Input from controller to enable RNG |
| rng_fips_i | I | 1 | rng | Indicates that the AST RNG module is requested to output FIPS SP-800-90B grade RNG bits. This may, but not necessarily affect bit-rate. This bit is a placeholder. The use of this signal inside AST is TBD. |
| rng_val_o | O | 1 | rng | RNG bit valid. This is a per-transaction valid. rng_b_o can be sampled whenever this bit is high. |
| rng_b_o | O | 4 | rng | RNG digital bit streams. The downstream controller of this signal should sample the rng_b_o whenever rng_val_o is high. |
| Countermeasures and Alerts | ||||
| alert_req_o | O | ast_alert_req | alert | Alert events. There are 11 such events. The alerts are associated with countermeasures like Active shield, clock glitch detector, voltage glitch detector, temperature sensor, and others. |
| alert_rsp_i | I | ast_alert_rsp | alert | This structure contains acknowledge signals and force-trigger by software signals for each alert event. The acknowledge signals are assumed to be synchronous pulses. |
| Trimming Test and Debug | ||||
| dft_scan_md_o | O | mubi4 | Scan mode indication signal. Controllable only when DFT features are enabled (Test and RMA states). Otherwise, these signals are grounded to 0. | |
| scan_shift_en_o | O | 1 | Scan shift enable | |
| scan_reset_no | O | 1 | Scan reset | |
| clk_ast_ext_i | I | 1 | async | External clock. While AST generates most of its clocks on-die, it still needs an external clock for clock calibration and first flash/OTP programming. Clock calibration: AST clock sources are inaccurate by default and must be calibrated prior to use. The results of the calibration are stored in OTP and reloaded by software upon system boot. First Flash / OTP programming: AST clock sources are inaccurate by default and may be out of range for initial flash and OTP programming. In this situation, an external clock may be required for initial programming such that a software image can be loaded to calibrate clocks and advance life cycle. |
| dft_strap_test_i | I | dft_strap_test_req | async | Strap inputs for DFT selection |
| flash_bist_en_o | O | mubi4 | Flash BIST enable | |
| vcc_supp_i | I | 1 | async | VCC Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant '1' and will be disconnected inside the AST. |
| vcmain_supp_i | I | 1 | async | VCMAIN Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant '1' and will be disconnected inside the AST. |
| vcaon_supp_i | I | 1 | async | VCAON Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant '1' and will be disconnected inside the AST. |
| vioa_supp_i | I | 1 | async | VIOA Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant '1' and will be disconnected inside the AST. |
| viob_supp_i | I | 1 | async | VIOB Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant '1' and will be disconnected inside the AST. |
| ast2pad_t0_ao, ast2pad_t1_ao | I/O | async | Analog debug signals. These signals should be connected directly to chip PADs. They can share PADs with functional signals but when they are used for their analog debug function, the functional I/O must be in tri-state. | |
| dpram_rmf_o, dpram_rml_o, spram_rm_o, sprgf_rm_o, sprom_rm_o |
O | dpm_rm | async | RAM/ROM Read-write Margin Trimming |
| padmux2ast_i | I | 6 | async | Digital debug input signals (routed to pin mux). These signals are controllable only when DFT features are enabled (Test and RMA states). Otherwise, these signals are grounded to 0. |
| ast2padmux_o | O | 9 | async | Digital debug output signals (routed to pin mux). These signals are only outputted when DFT features are enabled (Test and RMA states). Otherwise, these signals are grounded to 0. |
| usb_io_pu_cal_o | O | 20 | async | USB I/O calibration and trimming |
| io_clk_byp_req_i | I | mubi4 | async | External clock mux override request for OTP bootstrap purposes. AST responds to the request by setting io_clk_byp_ack_o to 'On'. When this bit is set and ack was received, clk_ast_ext_i serves as the io_clk clock root. Note: When 'On' (after ack), clk_src_io_o clock max frequency is limited to 50 MHz |
| io_clk_byp_ack_o | O | mubi4 | async | AST response to io_clk_byp_req_i. The ack is set to 'On' after clock switching function is performed. |
| all_clk_byp_req_i | I | mubi4 | async | External clock mux override request for OTP bootstrap purposes. AST responds to the request by setting io_clk_byp_ack_o to 'On'. When this bit is set and ack was received, clk_ast_ext_i serves as the io_clk clock root. Note: When 'On' (after ack), clk_src_io_o clock max frequency is limited to 50 MHz |
| all_clk_byp_ack_o | O | mubi4 | async | AST response to io_clk_byp_req_i. The ack is set to 'On' after clock switching function is performed. |
| ext_freq_is_96m_i | I | mubi4 | async | External clock frequency indication to AST. When set, it indicates that the external clock is 96MHz. |
| lc_dft_en_i | I | lc_tx | async | DFT enable |
| fla_obs_i | I | 8 | async | Flash observe bus for debug |
| otp_bos_i | I | 8 | async | OTP observe bus for debug |
| usb_obs_i | I | 1 | async | USB differential receiver output observe for debug |
| otm_obs_i | I | 8 | async | OpenTitan modules observe bus for debug (optional) |
| obs_ctrl_o | O | ast_obs_ctrl | async | Observability control structure. It contains observability module selection, signal group selection and enable logic. Open source modules may choose to use this infrastructure for selecting and gating observability signals to be driven into otm_obs_i bus. Whether to actually use this interface or not for open source modules observability is a project decision. |
| sns_clks_i | I | clkmgr_out | async | Clocks observability |
| sns_rst_i | I | rstmgr_out_t | async | Resets observability |
| sns_spi_ext_clk_i | I | 1 | async | SPI external clock observability |