clkmgr_testplan.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  name: "clkmgr"
  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson",
                     // ICEBOX: Top-level specific Hjson imported here. This will likely be resolved
                     // once we move to IPgen flow.
                     "hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr_sec_cm_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson"]
  testpoints: [
    {
      name: smoke
      desc: '''
            Smoke test disabling peripheral and transactional clocks.

            - Disables all peripheral clocks from their enabled reset state.
            - Transactional clocks gating depends on whether they are idle.
            - Initializes all units as busy (not idle).
            - Clears each unit's `clk_hints` bit, which has no effect until
              the unit becomes idle.
            - Sets the unit's `idle_i` bit, which should disable the clock.
            - Writes both values of the `jitter_enable` CSR.

            **Stimulus**:
            - CSR writes to `clk_enables` and `clk_hints`.
            - Setting `idle_i` clkmgr input.

            **Checks**:
            - SVA assertions for peripheral clocks enable and disable
              properties.
            - Transactional clocks check SVA properties as follows:
              - If the hint enables it, the clock becomes active.
              - If the hint disables it but the unit is busy, the clock remains
                active.
              - If the hint disables it and the unit is idle, the clock stops.
            - For transactional units the CSR `clk_hints_status` is checked
              to correspond to `clk_hints` once the units are idle.
            - Check in scoreboard the `jitter_en_o` output tracks updates of the
              `jitter_enable` CSR.
            '''
      stage: V1
      tests: ["clkmgr_smoke"]
    }
    {
      name: peri_enables
      desc: '''
            Peripheral clocks are disabled if its `clk_enables` bit is off,
            or the corresponding `pwr_i.*_ip_clk_en` is off, and `scanmode_i`
            is not `lc_ctrl_pkg::On`.

            This test runs multiple rounds which do the following:
            - Randomize `pwr_i.usb_ip_clk_en` and `scanmode_i`, and the initial
              setting of `clk_enables`.
            - Send a CSR write to `clk_enables` with its initial value.
            - Send a CSR write to `clk_enables` that flips all bits.

            It makes no sense to have `pwr_i.io_ip_clk_en` set to zero since
            that would prevent the CPU from running and sending CSR updates.

            **Checks**:
            - SVA assertions for peripheral clocks enable and disable
              properties.
            '''
      stage: V2
      tests: ["clkmgr_peri"]
    }
    {
      name: trans_enables
      desc: '''
            Transactional unit clocks are disabled if they are idle and
            their CSR `clk_hints` bit is off, or `pwr_i.main_ip_clk_en` is off,
            and `scanmode_i` is not `lc_ctrl_pkg::On`.
            This test randomizes the initial setting of `idle_i` and the
            desired value of `clk_hints`. Each round performs this sequence:
            - Writes the desired value to CSR `clk_hints` and checks that the
              CSR `clk_hints_status` reflects CSR `clk_hints` except for the
              units not-idle.
            - Marks all units as idle, and checks that `csr_hints_status`
              matches `clk_hints`.
            - Writes `clk_hints` to all ones and checks that `csr_hints_status`
              is all ones.
            - Writes `clk_hints` with its reset value.

            **Checks**:
            - SVA assertions for transactional unit clocks described in
              clkmgr_smoke.
            '''
      stage: V2
      tests: ["clkmgr_trans"]
    }
    {
      name: extclk
      desc: '''
            Tests the functionality of enabling external clocks.

            - External clock is enabled if the `lc_clk_byp_req_i` input from
              `lc_ctrl` is `lc_ctrl_pkg::On`.
            - External clock is also be enabled when CSR `extclk_ctrl.sel` is
              set to
              `lc_ctrl_pkg::On` and the `lc_dtl_en_i` input from `lc_ctrl` is
              `lc_ctrl_pkg::On`.
            - Notice writes to the `extclk_ctrl.sel` register are ignored unless
              the CSR `extclk_ctrl_regwen` is 1.
            - A successful switch to external clocks due to `lc_clk_byl_req_i`
              will cause the clkmgr to undo a divide by 2 for io_div4 and
              io_div2 clocks except when `(scanmode_i == prim_mubi_pkg::MuBi4True)`.
            - A software triggered switch to external clock will undo divides
              by 2 if `extclk_ctrl.hi_speed_sel` is set to `prim_mubi_pkg::MuBi4True`.

            **Stimulus**:
            - CSR writes to `extclk_ctrl` and `extclk_ctrl_regwen`.
            - Setting `lc_hw_debug_en_i`, `lc_clk_byp_req_i`, and the handshake to
              ast via `ast_clk_byp_req_o` and `ast_clk_byp_ack_i`.
            - Setting `scanmode_i`.

            **Checks**:
            Clock divider checks are done with SVA assertions.
            - When the external clock is selected (and not defeated by
              `scanmode_i` for scoreboard checks):
              - The `clk_io_div2_powerup` output matches the `clk_io_powerup`
                 output.
              - The `clk_io_div4_powerup` output matches the `clk_io_powerup`
                 output at half its frequency.
            - When the external clock is not selected or division is defeated:
              - The `clk_io_div2_powerup` output matches the `clk_io_powerup`
                output at half its frequency.
              - The `clk_io_div4_powerup` output matches the `clk_io_powerup`
                 output at a quarter of its frequency.
            LC / AST handshake:
            - When the external clock functionality is triggered the
              `ast_clk_byp_req_o` output pin is set to `lc_ctrl_pkg::On`.
            - When `ast_clk_byp_ack_i` is set to `lc_ctrl_pkg::On` in response
              to a corresponding request:
              - The clock dividers are stepped down, unless defeated by
                 `scanmode_i` being `lc_ctrl_pkg::On`.
             - If the initial request was due to the assertion of the
               `lc_clk_byp_req_i`, the `lc_clk_byp_ack_o` output is set to
               `lc_ctrl_pkg::On`.
            '''
      stage: V2
      tests: ["clkmgr_extclk"]
    }
    {
      name: clk_status
      desc: '''
            This tests the three `pwr_o.*_status` output ports, for the
            `io`, `main`, and `usb` clocks.

            The `pwr_o.*_status` output must track the correspponding
            `pwr_i.*_ip_clk_en` input.

            **Stimulus**:
            - Randomize the `pwr_i.*_ip_clk_en` setting for each clock.

            **Check**:
            - The checks are done in SVA at `clkmgr_pwrmgr_sva_if.sv`.
            '''
      stage: V2
      tests: ["clkmgr_clk_status"]
    }
    {
      name: jitter
      desc: '''
            This tests the jitter functionality.

            The jitter functionality is implemented by the AST block, but
            controlled by the `jitter_enable` CSR in this block. This CSR
            directly drives the `jitter_en_o` output pin.

            **Stimulus**:
            - CSR write to `jitter_enable`.

            **Check**:
            - The `jitter_en_o` output pin reflects the `jitter_enable` CSR.
              Test is implemented in the scoreboard, and is always running.
            '''
      stage: V2
      tests: ["clkmgr_smoke"]
    }
    {
      name: frequency
      desc: '''This tests the frequency counters measured count functionality.

            These counters compute the number of cycles of each clock relative
            to the aon timer, and compares it to the corresponding
            thresholds written into the `*_meas_ctrl_shadowed` CSR. Measurements
            beyond these thresholds trigger a recoverable alert and set a bit
            in the `recov_err_code` CSR. Also, if the counters reach their
            maximum value they don't wrap around.

            If clock calibration is lost, indicated by the `calib_rdy_i` input
            being `prim_mubi_pkg::MuBi4False`, the measurements stop, no
            error is triggered, and `measure_ctrl_regwen` is set to 1.

            **Stimulus**:
            - Randomly set slow, correct, and fast interval for each counter
              and test.
            - Randomly set the `calib_rdy_i` input.
            - Randomly trigger a clock saturation by forcing its cycle count
              to be near its maximum value while counting.

            **Check**:
            - Slow and fast intervals should cause a recoverable alert.
            - Coverage collected per clock.
            '''
      stage: V2
      tests: ["clkmgr_frequency"]
    }
    {
      name: frequency_timeout
      desc: '''This tests the frequency counters timeout functionality.

            These counters compute the number of cycles of some clock relative
            to the aon timer. It should trigger a recoverable alert when there
            is no valid measurement when enabled, leading to a timeout. This is
            separate from the `frequenty` testpoint to simplify the test checks.

            **Stimulus**:
            - Randomly stop measured clocks to trigger a timeout.

            **Check**:
            - Timeout should cause a recoverable alert.
            - Coverage collected per clock.
            '''
      stage: V2
      tests: ["clkmgr_frequency_timeout"]
    }
    {
      name: frequency_overflow
      desc: '''This tests the overflow feature in prim_clock_meas.

            This needs to modify the state of the counter to trigger the
            feature.

            **Stimulus**:
            - Program the counter. Whenever it hits the value of 1, set it to
              the range - 2.

            **Check**:
            - The internal cnt_ovfl flop is set.
            - The fast_o output should be set.
            '''
      stage: V2
      tests: ["clkmgr_frequency"]
    }
    {
      name: regwen
      desc: '''This tests the behavior of the regwen CSRs.

            When a regwen is clear, any write to CSRs it locks are ignored.
            Once a regwen is cleared, it will only be set again after a full
            reset.

            **Stimulus**:
            - Clear each regwen.
            - Write to the corresponding locked CSRs.

            **Check**:
            - The locked CSR value is not updated.
            '''
      stage: V3
      tests: ["clkmgr_regwen"]
    }
    {
      name: stress_all
      desc: '''This runs random sequences in succession.

            Randomly chooses from the following sequences:
            - clkmgr_extclk_vseq,
            - clkmgr_frequency_timeout_vseq,
            - clkmgr_frequency_vseq,
            - clkmgr_peri_vseq,
            - clkmgr_smoke_vseq,
            - clkmgr_trans_vseq
            '''
      stage: V2
      tests: ["clkmgr_stress_all"]
    }
  ]

  covergroups: [
    {
      name: peri_cg
      desc: '''
            Collects coverage for each peripheral clock.

            The peripheral clocks depend on a bit in the clk_enables CSR,
            the ip_clk_en input from pwrmgr, and the scanmode input.
            This collects the cross of them for each peripheral.

            FIXME This is collected in an array, one instance for each clock,
            but the dvsim coverage flow doesn't yet support arrays.
            '''
    }
    {
      name: trans_cg
      desc: '''
            Collects coverage for each transactional unit clock.

            The transactional unit clocks depend on a bit in the clk_hints CSR,
            the ip_clk_en input from pwrmgr, the respective idle input bit from
            the unit, and the scanmode input.
            This collects the cross of them for each transactional unit.

            FIXME This is collected in an array, one instance for each clock,
            but the dvsim coverage flow doesn't yet support arrays.
            '''
    }
    {
      name: extclk_cg
      desc: '''
            Collects coverage for the external clock selection.

            The external clock selection depends on the `extclk_ctrl` CSR
            fields `sel` and `hi_speed_sel`, and the `lc_hw_debug_en_i`,
            `lc_clk_byp_req_i`, and `scanmode_i` input pins. This covergroup
            collects their cross.
            '''
    }
    {
      name: freq_measure_cg
      desc: '''
            Collects coverage for the frequency measurement counters.

            The relevant information is whether it got an okay, slow, or
            fast measurement, or a timeout.
            '''
    }
  ]
}