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Hardware IP Blocks

HW Block Brief Summary
adc_ctrl Low-power controller for a dual-channel ADC with filtering and debouncing capability
aes AES encryption and decryption engine with SCA and FI countermeasures
aon_timer Wakeup and watchdog timers running on a low-power, always-on clock
clkmgr Derives and monitors on-chip clock signals, handles clock gating requests from power manager and software
csrng Takes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software
edn Distributes random numbers produced by CSRNG to hardware blocks
entropy_src Filters and checks raw entropy bits from a random noise source and forwards them to CSRNG
flash_ctrl Interfaces and manages integrated non-volatile flash memory; supports scrambling, integrity, and secure wipe
gpio General-purpose I/O pin control interface for software
hmac Accelerator for SHA-256-based keyed hash message authentication code and the SHA-256 hash function
i2c I2C interface for host and device mode, supporting up to 1 Mbaud data rates
keymgr Managing identities and root keys; shielding confidential assets from software; providing a key derivation interface for software
kmac Accelerator for Keccak-based keyed hash message authentication code and SHA-3 hash functions; with SCA and FI countermeasures
lc_ctrl Manages device life cycle states and transitions, and controls key manager, flash, OTP, and debug access
otbn Programmable coprocessor for asymmetric cryptography with SCA and FI countermeasures
otp_ctrl Interfaces integrated one-time programmable memory, supports scrambling, integrity and secure wipe
pattgen Transmission of short time-dependent data patterns on two clock-parallel output channels
pinmux Multiplexes between on-chip hardware blocks and pins; can be configured at runtime
pwm Transmission of pulse-width modulated output signals with adjustable duty cycle
rom_ctrl Interfaces scrambled boot ROM with system bus and KMAC for initial health check after reset
rstmgr Controls the on-chip reset signals, records reset cause and CPU crash dump for software
rv_core_ibex Dual-core lockstep 32-bit RISC-V processor running application and control software
rv_dm Enables debug support for Ibex, access protected by life cycle
rv_timer Memory-mapped timer unit implementing RISC-V mtime and mtimecmp registers
spi_device Serial peripheral interface supporting different device modes, suitable for bulk-load of data into and out of the chip
spi_host Serial peripheral interface for host mode, suitable for interfacing external serial NOR flash devices
sram_ctrl Interfacing on-chip SRAM blocks with system bus, supports lightweight scrambling, integrity and secure wipe
sysrst_ctrl Manages board-level reset sequencing, interfaces reset and power manager
uart Full duplex serial communication interface, supports bit rates of up to 1 Mbit/s
usbdev USB 2.0 Full Speed device interface (12 Mbit/s)