GSoC'23 Project Ideas List

Welcome to the project ideas list for GSoC'23. You are allowed to choose any given project to work on with us or you can suggest your own idea as well.

We encourage you to join our Gitter Chat Room (general) to discuss ideas. Please use the recommended Proposal Format for all projects and you can see the detailed timeline here.

Our active projects

1. NucleusRV: A 32-bit 5 staged pipelined RISC-V core designed in CHISEL.
2. OpenTCAM: An open-source Ternary Content Addressable Memory (TCAM) compiler.
3. Azadi-SoC: Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

Project 1: L1 cache controller with Nucleus RV core

Difficulty: Hard

Designation: 175 hours (medium)

Required Skills: CHISEL, Scala, RISC-V ISA, Compressed ISA of RISC-V

Mentors: Usman Zain, Farhan Ahmed

Chat channel: Join NucleusRV gitter channel

Overview:

NucleusRV is the 5-stage pipelined RISC-V based Core that currently supports I, M, and C extensions and is written in Chisel language. It is used along with the SoC-Now SoC Generator that takes a few parameters as input and generates an entire SoC consisting of a Core with selective extensions, and devices according to the given input parameters. The goal of this project is to add caches to the NRV-tile. Currently, our system looks like this:

Instruction and Data Cache will replace the ICCM and DCCM respectively. The scope of this project includes developing a cache controller, making it parameterizable such that we can configure the cache size, block size, etc.

Expected Outcomes:

• Parameterized L1 cache controller, written in CHISEL
• Integration of controller in NucleusRV core
• Documentation of the work done

Project 2: OpenTCAM - SRAM-based TCAM compiler

Difficulty: Hard

Designation: 350 hours (large)

Required Skills & Tools: Python, Verilog, OpenRAM Compiler, Verilator.

Mentors: Ali Ahmed, Sajjad Ahmed

Chat Channel: Join OpenTCAM Gitter Channel

Overview:

OpenTCAM is an open-source Python framework that can be used to create the design (RTL) and layouts (GDS-II) of a customizable SRAM-based TCAM memory to use in FPGA and ASIC designs. Currently, the compilers are using SRAMs generated from OpenRAM Compiler, but the idea is to make a generalized compiler for any SRAM-based TCAM. The idea is to utilize 36KB BRAM blocks of FPGAs and OpenRAM generated 1Kb SRAM blocks (using sky130 nm PDKs) for ASIC to mimic any size of TCAM.

The classical TCAM is really expensive, acquires a large area(16T cell) and has high power consumption, and is not openly available. Unlike SRAM which is cheap, power efficiency requires less area(6T cell) and has a mass production ratio.

OpenTCAM RTL-Gen is the extension of a broader TCAM compiler developed in GSoC’22. Which has TCAM to SRAM table mapping facility, but RTL generation support is very limited. This project is all about adding a wide range of configurable RTL generation to the existing compiler.

Table Mapping:

Block Diagram:

Expected Outcomes:

• Python-based TCAM compiler which can generate SystemVerilog RTL with different configurations of TCAM blocks for Single cycle search.
• Support for pipelined TCAM structure for multicycle search operations.
• Documentation of the work done

Reference: Ali Ahmed, Kyungbae Park. “Resource-Efficient SRAM-Based Ternary Content Addressable Memory”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( Volume: 25, Issue: 4, April 2017)

Project 3: TileLink Uncached Heavyweight (TL-UH) implementation in Azadi-SoC

Difficulty: Medium

Designation: 175 hours (medium)

Required Skills: SystemVerilog, Verilator, Understanding of basic Bus protocol.

Mentors: Zeeshan Rafique, Nameer Iqbal

Chat channel: Join Azadi-SoC gitter channel

Overview:

Azadi-SoC is a low-end embedded class System on Chip. It integrates an extended version of RISC-V based core. i.e. lowrisc/ibex and few peripherals using tilelink bus protocol. Currently, the SoC uses the TileLink Uncached Lightweight (TL-UL) to make communication possible with peripherals and external memories. The purpose of this project is to upgrade the TL-UL to TL-UH (Uncached Heavyweight) which comes with additional features including burst messages, hint operation, and atomic operations.

TileLink is a chip-scale interconnect standard providing multiple masters with coherent memory-mapped access to memory and other slave devices. TileLink is designed for use in a System-on-Chip (SoC) to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complex devices, using a fast scalable interconnect providing both low-latency and high-throughput transfers. The TileLink specification can be downloaded from here.

Expected Outcomes:

• Upgrade TL-UL to TL-UH for Azadi-SoC
• Testing at the SoC level
• Documentation of the work done

Project 4: Quad-SPI Flash Controller for Azadi-SoC

Difficulty: Medium

Designation: 175 hours (medium)

Required Skills & Tools: SystemVerilog, SPI and QSPI protocol, Memory interfacing, Verilator.

Mentors: Sajjad Ahmed, Zeeshan Rafique

Chat Channel: Join Azadi-SoC Gitter Channel

Overview:

Flash memories are widely used as off-chip storage for embedded processors. For an embedded processor to interact with different flash memory devices requires a well-structured flash memory controller which can communicate with the flash memory of different vendors. The project is aimed at designing a quad-spi flash memory controller for Azadi SoC (a 32bit SoC based on RISC-V ISA). The controller should have flexible configuration support to target various flash devices e.g, micron, spansion and winbond.

Block diagram:

Expected Outcomes:

• Single and Quad SPI interface modes.
• All Four operating modes (00, 01, 10, 11) of CPOL and CPHA.
• Flexible configuration support for targeting different flash memories.
• Documentation of the work done

Project 5: Verification of SRAM-based TCAM IP

Difficulty: Hard

Designation: 175 hours (medium)

Required Skills: Python, EDA tools, Verilog.

Mentors: Auringzaib Sabir, Ali Ahmed

Chat Channel: Join OpenTCAM Gitter Channel

Overview:

Build a verification environment for SRAM-based TCAM IP to test the behavior of the design. The project includes

1. Building a reference environment of a TCAM.
2. Comparator logic to compare the results from the reference model and the TCAM IP after a specific search query is stimulated to both the reference model and design under test.

TCAM

TCAM (ternary content-addressable memory) is a specialized type of high-speed memory that searches its entire contents in a single clock cycle. The term “ternary” refers to the memory's ability to store and query data using three different inputs: 0, 1, and X.

Expected Outcome:

• Build a python based verification environment for TCAM IP.
• Introduce multiple test scenarios to test generated RTL
• Documentation of the work done

Project 6: AES Block for Azadi-SoC

Difficulty: Hard

Designation: 175 hours (medium)

Required Skills: Python, EDA tools, Verilog.

Mentors: Ali Ahmed, Nouman Naseer

Chat Channel: Gitter Chat Room (general)

Overview:

The purpose of this project is to design a hardware accelerator for the AES encryption algorithm, which will improve the processing speed and efficiency of cryptographic operations in embedded systems. The accelerator will be designed using Verilog HDL and implemented on FPGA/ASIC technologies.

Design Overview:

There are three major functional blocks of the design.

1. System interface: for communication with CPU and memory.
2. Control unit: controls all operations of the AES block.
3. AES cipher block: performs encryption/decryption on targeted data. It is further divided into two blocks.

• A key expansion block that will generate the round keys needed for the AES cipher block. The key expansion block will take the input key and generate the required number of round keys based on the AES key schedule.
• An AES cipher block that will perform the encryption and decryption operations. The AES cipher block will implement the AES algorithm using the round keys generated by the key expansion block. The cipher block will be designed to operate in a pipelined fashion to achieve high throughput.

Block Diagram:

Expected Outcomes:

• Fully functional AES hardware accelerator that can perform efficient encryption and decryption operations.
• Should be capable of handling various key lengths and block sizes to meet the requirements of different applications.
• The design will be optimized for high performance, low latency, and low power consumption.